A test circuit, chip and test method for the logic of an auxiliary channel of a display interface

Abstract

The present application discloses a test circuit, a chip and a test method for a display interface auxiliary channel logic. The test circuit includes a processor, an output selection module, a clock adjustment module, an outputter, an inputter and an input selection module. The processor includes a test control module and a test pattern output module. The test control module is used to control the output selection module to select the test pattern output by the test pattern output module. The outputter is used to output the test pattern to the inputter according to the clock adjustment module. The inputter is used to input the parsed data obtained according to the test pattern to the input selection module. The test control module is further used to control the input selection module to select a test comparison module to determine the test result. This test circuit is integrated inside the chip, reducing the complexity of signal transmission. On the one hand, it can achieve automatic, efficient and comprehensive testing according to test cases; on the other hand, it can cover the data transmission rate in the protocol according to the clock adjustment module to ensure the comprehensiveness of testing.

Description

Technical Field

[0001] This application relates to the field of testing technologies, and particularly to a test circuit, a chip, and a test method for the logic of an auxiliary channel of a display interface. Background Art

[0002] An auxiliary channel (AUX) is an independent communication path used for auxiliary data transmission, link management, device control, and protocol management, and is a key functional module in a Display Port (DP). For example, during the DP link initialization phase, the AUX can negotiate the best transmission parameters (such as the number of channels, rate, etc.) through two-way communication to complete link training and ensure data transmission stability.

[0003] Therefore, before the electronic device (such as a chip) leaves the factory, it is very necessary to perform logic testing on the auxiliary channel. However, traditional test methods cannot balance high test efficiency and comprehensive test coverage. Summary of the Invention

[0004] In view of this, this application provides a test circuit, a chip, and a test method for the logic of an auxiliary channel of a display interface to balance high test efficiency and comprehensive test coverage.

[0005] In a first aspect, this application provides a test circuit for the logic of an auxiliary channel of a display interface. The test circuit is integrated inside the chip, and the test circuit includes a processor, an output selection module, a clock adjustment module, an outputter, an inputter, and an input selection module.

[0006] Specifically, the processor includes a test control module and a test pattern output module. The test pattern output module includes test cases that cover the specification requirements. The test cases include test patterns and theoretical results of auxiliary channel signals. The test control module is used to control the output selection module to select the test patterns output by the test pattern output module.

[0007] The outputter is used to output the test patterns to the inputter according to the clock adjustment module controlled by the test control module.

[0008] The inputter is used to input the parsed data obtained according to the test patterns to the input selection module.

[0009] The processor further includes a test comparison module.

[0010] The test control module is further used to control the input selection module to select the test comparison module to determine the test result of the logic of the auxiliary channel of the display interface according to the parsed data and the theoretical results.

[0011] In some possible implementations, the clock adjustment module is configured to control the rate of outputting the test pattern within a preset frequency range according to a preset step size.

[0012] In some possible implementations, the preset step size is 10 kHz, the lower limit of the preset frequency range is 830 kHz, and the upper limit of the preset frequency range is 1.25 MHz.

[0013] In some possible implementations, the test circuit further includes a transmission buffer module, and the output selection module outputs the test pattern to the output device through the transmission buffer module.

[0014] In some possible implementations, the test circuit further includes a reception buffer module, and the input device inputs the parsed data to the input selection module through the reception buffer module.

[0015] In some possible implementations, the processor further includes a conventional parsing module and a conventional output module. The conventional parsing module is configured to parse the auxiliary channel signal input by the external control through the input device, and the conventional output module is configured to output the auxiliary channel signal to the outside of the chip through the output device.

[0016] In some possible implementations, the test pattern is a pattern that conforms to the Manchester coding rule.

[0017] In a second aspect, the present application provides a chip, characterized in that the chip includes the test circuit as described in the first aspect or any one of the possible implementations of the first aspect.

[0018] In a third aspect, the present application provides a method for testing the logic of an auxiliary channel of a display interface. The method is implemented based on the test circuit as described in the first aspect or any one of the possible implementations of the first aspect. The method includes:

[0019] According to the test control module, control the output selection module to select the test pattern output by the test pattern output module. The test control module and the test pattern output module are included in the processor. The test pattern output module includes test cases that cover the specification requirements. The test cases include the test pattern of the auxiliary channel signal and the theoretical result;

[0020] Based on the output device, output the test pattern to the input device according to the clock adjustment module controlled by the test control module;

[0021] Based on the input device, input the parsed data obtained according to the test pattern to the input selection module;

[0022] The test control module controls the input selection module to select a test comparison module, so as to determine the test result of the display interface auxiliary channel logic according to the parsed data and the theoretical result, and the test comparison module is included in the processor.

[0023] In some possible implementation manners, determining the test result of the display interface auxiliary channel logic according to the parsed data and the theoretical result includes:

[0024] When the parsed data and the theoretical result match successfully, it is determined that the test of the display interface auxiliary channel logic passes;

[0025] Otherwise, it is determined that the test of the display interface auxiliary channel logic fails.

[0026] Based on the implementation manners provided in the above aspects of the present application, further combinations can be made to provide more implementation manners.

[0027] It can be seen from the above technical solutions that the present application has at least the following advantages:

[0028] The present application provides a test circuit for the display interface auxiliary channel logic. This test circuit is integrated inside the chip and directly performs tests using hardware, reducing the complexity of signal transmission. On the one hand, it can realize automatic, efficient, and comprehensive tests for the auxiliary channel logic according to preset test cases; on the other hand, this test circuit includes a clock adjustment module, which can cover tests of all data transmission rates in the protocol, ensuring the comprehensiveness of the tests. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic structural diagram of a test circuit for the display interface auxiliary channel logic disclosed in an embodiment of the present application;

[0030] Figure 2 It is a schematic structural diagram of another test circuit for the display interface auxiliary channel logic disclosed in an embodiment of the present application;

[0031] Figure 3 It is a schematic structural diagram of still another test circuit for the display interface auxiliary channel logic disclosed in an embodiment of the present application;

[0032] Figure 4 It is a schematic structural diagram of a chip disclosed in an embodiment of the present application;

[0033] Figure 5 It is a flowchart of a test method for the display interface auxiliary channel logic disclosed in an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] To make the above objects, features, and advantages of the present application more obvious and understandable, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to limit the present application. The terms "first" and "second" in the embodiments of the present application are only used for descriptive purposes and cannot be construed as indicating or implying relative importance, the order of operation time, or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features.

[0036] First, a detailed introduction to the background technology related to the embodiments of the present application will be provided.

[0037] The auxiliary channel (Auxiliary Channel, AUX) is an independent communication path for auxiliary data transmission, link management, device control, and protocol management, and is a key functional module in the Display Port (DP). For example, during the DP link initialization phase, the AUX can negotiate the best transmission parameters (such as the number of channels, rate, etc.) through two-way communication to complete link training and ensure data transmission stability. Therefore, before the electronic device (such as a chip) leaves the factory, it is very necessary to test the auxiliary channel.

[0038] The logical test of the circuit is a process of verifying whether the circuit design meets the expected function and timing requirements. By inputting specific signals and checking the output results of the circuit, the normal operation of the circuit can be ensured to prevent functional abnormalities and even economic losses caused by design defects in the electronic control products (especially chips) after leaving the factory.

[0039] Traditional logical tests of the auxiliary channel usually rely on external control to send a large amount of test data to the circuit, resulting in long test time and high test cost. Furthermore, on the one hand, traditional test methods require strict alignment of external signals with the internal clock of the chip circuit, which has high requirements for test data; on the other hand, precisely because external signals need to be strictly aligned with the internal clock of the chip circuit, and the internal clock is usually a fixed value, traditional test methods are difficult to cover all rate situations within the transmission rate range required by the protocol, resulting in a small test coverage rate.

[0040] In view of this, the embodiments of the present application provide a test circuit for the logic of the auxiliary channel of the display interface. The test circuit is integrated inside the chip and includes a processor, an output selection module, a clock adjustment module, an outputter, an inputter, and an input selection module.

[0041] Specifically, the processor includes a test control module and a test pattern output module. The test pattern output module includes test cases that meet the specification requirements, where the test cases include test patterns and theoretical results of the auxiliary channel signals. The test control module is used to control the output selection module to select the test patterns output by the test pattern output module. The output device is used to output the test patterns to the input device according to the clock adjustment module controlled by the test control module. The input device is used to input the parsed data obtained from the test patterns to the input selection module. The test control module is further used to control the input selection module to select the test comparison module in the processor to determine the test results of the auxiliary channel logic of the display interface according to the parsed data and the theoretical results.

[0042] This test circuit is integrated inside the chip and directly performs tests using hardware, reducing the complexity of signal transmission. On the one hand, it can achieve automatic, efficient, and comprehensive testing of the auxiliary channel logic according to the preset test cases. On the other hand, this test circuit includes a clock adjustment module, which can cover the tests of all data transmission rates in the protocol, ensuring the comprehensiveness of the tests.

[0043] To make the technical solution of this application clearer and easier to understand, the following introduces a test circuit for the auxiliary channel logic of a display interface provided by this application in combination with specific embodiments.

[0044] See Figure 1 It is a schematic structural diagram of a test circuit for the auxiliary channel logic of a display interface disclosed in an embodiment of this application.

[0045] The test circuit 1000 provided in the embodiment of this application is integrated inside the chip and includes a processor 100, an output selection module 200, a clock adjustment module 300, an output device 400, an input device 500, and an input selection module 600. The arrows in the figure indicate the transmission directions of signals / data.

[0046] The processor 100 in this application refers to a processing module used to control the input of test patterns and perform test comparisons. This application does not specifically limit the form of the processor 100. For example, the processor 100 can be a single-chip microcomputer, a microprocessor, etc.

[0047] Specifically, the processor 100 may include a test control module 10, a test pattern output module 11, and a test comparison module 12. Among them, the test control module 10 is used to output control signals during the test process and can be controlled by an external chip through a chip control port (commonly an IIC slave) to start the test at the beginning of the test. The test pattern output module 11 includes test cases that meet the coverage specifications (such as DP specifications). The test cases include test patterns and theoretical results of the auxiliary channel signals. The test cases can be stored in a pattern library. The test patterns used to display the logic test of the interface auxiliary channel should conform to the Manchester encoding rule. Manchester encoding divides each data bit (0 or 1) into two equal time periods, and there must be a level transition at the center of the bit, so as to transmit clock and data information through the level transition. For example, according to the IEEE802.3 standard, when the level jumps from low to high, it means the data is "1", and vice versa means "0". The test comparison module 12 is used to compare the test results obtained from the test with the theoretical results in the test cases. If the test results are the same as the theoretical results, it can be determined that the logic test passes; otherwise, it can be determined that the test fails.

[0048] In the initial stage of the test, the test control module 10 can output control signals to control the output selection module 200 to select the test pattern output by the test pattern output module 11. For example, the test control module 10 can output a control signal to the output selection module 200, instructing the output selection module 200 to send a data request to the test pattern output module 11, or the test control module 10 can control the test pattern output module 11 to send a test pattern to the output selection module 200 and instruct the output selection module 200 to receive the test pattern.

[0049] Then, the outputter 400 can output the test pattern to the inputter 500 according to the test pattern received by the output selection module 200 and the clock adjustment module 300 controlled by the test control module 10. Among them, the outputter 400 may include an analog output unit, which is controlled by the test control module 10 to turn on and output data. To test the performance of the test chip at different data transfer rates (bit rates), the test circuit may include a clock adjustment module 300 for simulating multiple data transfer rates (bit rates). Since the bit rate is positively correlated with the symbol rate (baud rate), and the symbol rate is directly determined by the clock frequency, it can be understood that the data transfer rate will be faster at a higher clock frequency.

[0050] In some possible implementations, the clock adjustment module 300 can control the rate of output test patterns within a preset frequency range according to a preset step size. According to relevant specification requirements, in the communication of the auxiliary channel signal of the chip, the clock frequency needs to cover the range from 830 kilohertz (kHz) to 1.25 megahertz (MHz), that is, the lower limit of the preset frequency range can be 830 kHz, and the upper limit of the preset frequency range can be 1.25 MHz. In some possible implementations, the clock adjustment module 300 can perform tests by covering the preset frequency range with a step size of 10 kHz. For example, after transmitting all test patterns at a clock frequency of 830 kHz, the test patterns are transmitted at a clock frequency of 840 kHz until all test patterns are transmitted at a clock frequency of 1.25 MHz.

[0051] Next, the inputter 500 can input the parsed data to the input selection module 600 according to the parsed data obtained by parsing the test pattern. Among them, the inputter 500 can include an analog input unit, which is controlled by the test control module 10 to be turned on and input data.

[0052] Finally, the test control module 10 can also control the input selection module 600 to select the test comparison module 12 to determine the test result of the display interface auxiliary channel logic according to the parsed data and the theoretical result. Among them, the test comparison module 12 includes test cases output by the test pattern output module 11, that is, the test comparison module 12 includes test patterns and corresponding theoretical results. Thus, the test comparison module 12 can compare the parsed data obtained by parsing by the inputter 500 with the theoretical result. When the parsed data matches the theoretical result successfully, it is determined that the logic test of the auxiliary channel passes. When the parsed data does not match the theoretical result, it is determined that the logic test fails.

[0053] Based on the above description, the present application provides a test circuit for the display interface auxiliary channel logic. This test circuit is integrated inside the chip and directly performs tests using hardware, reducing the complexity of signal transmission. On the one hand, it can achieve automatic, efficient, and comprehensive testing of the auxiliary channel logic according to preset test cases; on the other hand, this test circuit includes a clock adjustment module, which can cover tests of all data transmission rates in the protocol, ensuring the comprehensiveness of the test.

[0054] See Figure 2 which is a schematic structural diagram of another test circuit for the display interface auxiliary channel logic disclosed in the embodiments of the present application.

[0055] Compared with Figure 1 the disclosed test circuit, Figure 2The disclosed test circuit further includes a transmit buffer module 700 and a receive buffer module 800. After receiving the test pattern, the output selection module 200 first outputs the test pattern to the transmit buffer module 700, and the test pattern is output to the output device 400 through the transmit buffer module 700. After the input device 500 parses the parsed data, it first inputs the parsed data to the receive buffer module 800, and the parsed data is input to the input selection module 600 through the receive buffer module 800. Among them, the functions of the transmit buffer module 700 and the receive buffer module 800 are to temporarily store data and coordinate data transmission between different rates or different interfaces, so as to ensure stable and reliable data transmission. For example, a First-In-First-Out (FIFO) buffer memory can be selected.

[0056] See Figure 3 FIG. is a schematic structural diagram of another test circuit for the display interface auxiliary channel logic disclosed in the embodiment of the present application.

[0057] Compared with Figure 1 or Figure 2 the disclosed test circuit, Figure 3 In the disclosed test circuit, the processor further includes a conventional parsing module 14 and a conventional output module 15. The dashed lines indicate that the transmit buffer module and the receive buffer module are optional structures. The AUX signal usually has two polarities, positive and negative, which are represented by "+" and "-" in the figure. The conventional parsing module is used to parse the auxiliary channel signal input by the external control through the input device, and the conventional output module is used to output the auxiliary channel signal to the outside of the chip through the output device. That is, in a non-test scenario, when the chip communicates with the outside through the auxiliary channel, data reception and transmission will be performed separately.

[0058] Specifically, in the scenario of communicating with the outside, the input device 500, the input selection module 600, the conventional parsing module 14, and the possible receive buffer module 800 can form a receive module. The input device 500 receives the auxiliary channel signal from the outside and sends it to the conventional parsing module 14 via (the receive buffer module 800) and the input selection module 600; the output device 400, the output selection module 200, the conventional output module 15, and the possible transmit buffer module 700 can form a transmit module. The conventional output module 15 outputs the auxiliary channel signal to the outside through the output selection module 200, (the transmit buffer module 700), and the output device 400. Among them, the two processes of the chip receiving external signals and sending signals to the outside are independent.

[0059] Based on the above test circuit for the display interface auxiliary channel logic, the present application provides a chip, which will be introduced in detail below with reference to the accompanying drawings.

[0060] See Figure 4, This figure is a schematic structural diagram of a chip disclosed in an embodiment of the present application.

[0061] The chip 10000 provided in the embodiment of the present application includes the test circuit 100 introduced in the above embodiment. This chip can support auxiliary channel communication and has both a signal transmission function and a signal reception function. For example, it is a chip for audio signal transmission, such as a wireless audio chip, etc. The embodiment of the present application does not make any limitation on the specific type of the chip.

[0062] Based on the above content, the present application also provides a test method for the display interface auxiliary channel logic. Refer to Figure 5 the schematic diagram of a test method for the display interface auxiliary channel logic shown. This method is implemented based on the above test circuit and specifically includes:

[0063] S502: According to the test control module, control the output selection module to select the test pattern output by the test pattern output module. The test control module and the test pattern output module are included in the processor. The test pattern output module includes test cases that cover the specification requirements. The test cases include the test patterns of the auxiliary channel signals and the theoretical results.

[0064] S504: Based on the outputter, the clock adjustment module controlled by the test control module outputs the test pattern to the inputter.

[0065] S506: Based on the inputter, input the parsed data obtained according to the test pattern to the input selection module.

[0066] S508: According to the test control module, control the input selection module to select the test comparison module to determine the test result of the display interface auxiliary channel logic according to the parsed data and the theoretical results. The test comparison module is included in the processor.

[0067] Among them, when the parsed data and the theoretical results match successfully, it is determined that the test of the display interface auxiliary channel logic passes; otherwise, it is determined that the test of the display interface auxiliary channel logic fails.

[0068] The specific details of the above steps are similar to those corresponding in the previous text and will not be elaborated here.

[0069] It should be noted that the various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the system or device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method part.

[0070] It should be understood that in this application, "at least one (item)" means one or more, and "a plurality" means two or more. "And / or" is used to describe the association relationship of associated objects and indicates that there can be three relationships. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist simultaneously. Here, A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one (item) of the following" or its similar expressions refer to any combination of these items, including any combination of single items (items) or plural items (items). For example, at least one (item) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or plural.

[0071] It should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the said element.

[0072] The steps of the methods or algorithms described in connection with the embodiments disclosed herein can be implemented directly in hardware, software modules executed by a processor, or a combination of both. The software modules can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0073] The above description of the disclosed embodiments enables those skilled in the art to implement or use this application. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application will not be limited to these embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A test circuit for the logic of an auxiliary channel of a display interface, characterized in that, The test circuit is integrated inside the chip. The test circuit includes a processor, an output selection module, a clock adjustment module, an output device, an input device, and an input selection module; The processor includes a test control module and a test pattern output module. The test pattern output module includes test cases that cover the specification requirements. The test cases include test patterns and theoretical results of auxiliary channel signals. The test control module is used to control the output selection module to select the test patterns output by the test pattern output module; The output device is used to output the test patterns to the input device according to the clock adjustment module controlled by the test control module; The input device is used to input the parsed data obtained according to the test patterns to the input selection module; The processor further includes a test comparison module; The test control module is further used to control the input selection module to select the test comparison module, so as to determine the test result of the display interface auxiliary channel logic according to the parsed data and the theoretical results.

2. The test circuit according to claim 1, wherein The clock adjustment module is used to control the rate of outputting the test patterns within a preset frequency range according to a preset step size.

3. The test circuit according to claim 2, wherein The preset step size is 10 kHz, the lower limit of the preset frequency range is 830 kHz, and the upper limit of the preset frequency range is 1.25 MHz.

4. The test circuit according to claim 1, wherein The test circuit further includes a transmit buffer module. The output selection module outputs the test patterns to the output device through the transmit buffer module.

5. The test circuit according to claim 1, wherein The test circuit further includes a receive buffer module. The input device inputs the parsed data to the input selection module through the receive buffer module.

6. The test circuit according to claim 1, wherein The processor further includes a conventional parsing module and a conventional output module. The conventional parsing module is used to parse the auxiliary channel signals input by the external control through the input device, and the conventional output module is used to output the auxiliary channel signals to the outside of the chip through the output device.

7. The test circuit according to any one of claims 1 to 6, characterized in that, The test patterns are patterns that conform to the Manchester coding rule.

8. A chip, characterized in that, The chip includes the test circuit according to any one of claims 1 to 7.

9. A test method for the logic of an auxiliary channel of a display interface, characterized in that, Implemented based on the test circuit according to any one of claims 1 to 7, the method includes: According to the test control module, controlling the output selection module to select the test patterns output by the test pattern output module. The test control module and the test pattern output module are included in the processor. The test pattern output module includes test cases that cover the specification requirements. The test cases include the test patterns and theoretical results of the auxiliary channel signals; Based on the output device, outputting the test patterns to the input device according to the clock adjustment module controlled by the test control module; Based on the input device, inputting the parsed data obtained according to the test patterns to the input selection module; According to the test control module, controlling the input selection module to select the test comparison module, so as to determine the test result of the display interface auxiliary channel logic according to the parsed data and the theoretical results. The test comparison module is included in the processor.

10. The method according to claim 9, wherein Determining the test result of the display interface auxiliary channel logic according to the parsed data and the theoretical results includes: When the parsed data matches the theoretical result successfully, it is determined that the test of the display interface auxiliary channel logic passes; Otherwise, it is determined that the test of the display interface auxiliary channel logic fails.

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