Open drain repeater with edge accelerator for I2C applications

Abstract

An I2C relay unit includes an A-side terminal and a B-side terminal. The relay unit is operable in a first mode for receiving a signal at the A-side terminal and generating a signal at the B-side terminal based on an A-side signal, the relay unit further comprising a B-side rise time accelerator element and a controller unit, the controller unit is configured to control the B-side rise time accelerator element to pull up the voltage at the B-side terminal in the first mode when the voltage at the A-side terminal exceeds a first threshold voltage during a rising edge of the voltage, and to control the B-side rise time accelerator element to pull up the voltage at the B-side terminal in the second mode when the voltage at the A-side terminal exceeds the first threshold voltage during the rising edge of the voltage. And then when the voltage at the B-side terminal exceeds a second threshold voltage, the controller unit is configured to control the B-side rise time accelerator element to stop pulling up the voltage at the B-side terminal, and wherein the controller unit is further configured to disable the B-side rise time accelerator element when transmitting or receiving a handshake bit.

Description

Technical Field

[0001] The present disclosure generally relates to a repeater for open-drain bus communication and a system including the repeater. More specifically, the present disclosure relates to a repeater suitable for inter-integrated circuit (I2C) bus communication. Background Art

[0002] In the following, an open-drain bus refers to a bus that uses open-drain output drivers to connect devices to the bus.

[0003] Data communication between devices in a system can be performed using a bus connection. For example, a device can communicate with another device using an open-drain bus connection based on the I2C communication protocol.

[0004] 1 shows a known system 100, which includes a first communication unit 110 and a second communication unit 120 connected using a bus connection 101. The bus connection 101 includes a first segment 102 and a second segment 103, the first segment including a first bus line 102a, and the second segment including a second bus line 103a connected using an I2C bus repeater 130. The first bus line 102a and the second bus line 103a each have routing capacitances associated therewith, represented by C1 and C2, respectively. It should be noted that, typically, the first segment 102 and the second segment 103 each include multiple bus lines, such as a data bus line and a clock bus line.

[0005] The first segment 102 further includes a first pull-up resistor R1 connected between the first bus line 102a and the power supply voltage Vcc. Similarly, the second segment 103 further includes a second pull-up resistor R2 connected between the second bus line 103a and the power supply voltage Vcc.

[0006] The first communication unit 110 includes a first I2C controller 111 that controls a first pull-down transistor 112 connected between the first bus line 102a and ground. Similarly, the second communication unit 120 includes a second controller 121 that controls a second pull-down transistor 122 connected between the second bus line 103a and ground.

[0007] For each pair of bus lines 102a, 103a, the bus repeater 130 includes a relay unit 140. The relay unit 140 has an A-side terminal 141a and a B-side terminal 141b. Each relay unit 140 also includes an A-to-B buffer 142a, whose input is connected to the A-side terminal 141a, and whose output is connected to the control input of the B-side pull-down transistor 143b, which is arranged between the B-side terminal 141b and the ground. The relay unit 140 also includes a B-to-A buffer 142b, whose input is connected to the B-side terminal 141b, and whose output is connected to the control input of the A-side pull-down transistor 143a, which is arranged between the A-side terminal 141a and the ground.

[0008] Each relay unit 140 is configured to be operable in a first mode, wherein the relay unit 140 receives a signal at the A-side terminal 141a and generates a signal at the B-side terminal 141b based on the signal received at the A-side terminal 141a. However, the relay unit 140 may be bidirectional, as shown in FIG1. ​​In this case, the relay unit may also be configured to be operable in a second mode, wherein the relay unit 140 receives a signal at the B-side terminal 141b and generates a signal at the A-side terminal 141a based on the signal received at the B-side terminal 141b.

[0009] Hereinafter, it is assumed that a statement concerning pulling up a voltage is the same as a statement concerning pulling up a node that provides the voltage.

[0010] The bus connection 101 is an open drain type bus with a high idle state. Specifically, without the pull-down of the first pull-down transistor 112 and the A-side pull-down transistor 143a, the voltage on the first bus line 102a is pulled up by the first pull-up resistor R1. More specifically, the current through the pull-up resistor R1 charges the capacitor C1 until the voltage on the first bus line 102a is pulled up to the power supply voltage Vcc, which corresponds to a logical "high" voltage (VH). Similarly, without the pull-down of the second pull-down transistor 122 and the B-side pull-down transistor 143b, the voltage on the second bus line 103a is pulled up to the power supply voltage Vcc by the second pull-up resistor R2.

[0011] By changing the voltage on the first bus line 102a, the first communication unit 110 can transmit data to the second communication unit 120 through the bus connection 101. Specifically, if a logic "low" voltage (VL) signal is to be transmitted through the bus connection 101, the first communication unit 110 controls the first pull-down transistor 112 using the first I2C controller 111 to pull down the voltage on the first bus line 102a. On the other hand, if a VH signal is to be sent, the first I2C controller 111 first deactivates the pull-down transistor 112 to allow the voltage on the first bus line 102a to be pulled up by the first pull-up resistor R1.

[0012] If the first communication unit 110 is transmitting data to the second communication unit 120, the relay unit 140 operates in the first mode. The voltage on the first bus line 102a is received at the A-side terminal 141a by the relay unit 140. The A-to-B buffer 142a controls the B-side pull-down transistor 143b based on the voltage at the A-side terminal 141a to reproduce the signal received at the A-side terminal 141a. Specifically, if a VL signal is received at the A-side terminal 141a, the A-to-B buffer 142a activates the B-side pull-down transistor 143b so that the voltage at the B-side terminal 141b and the voltage on the second bus line 103a are pulled down. On the other hand, if a VH signal is received at the A-side terminal 141a, the A-to-B buffer 142a deactivates the B-side pull-down transistor 143b to allow the voltage at the B-side terminal 141b and the voltage on the second bus line 103a to be pulled up by the second pull-up resistor R2.

[0013] The operation of the system 100 is bidirectional. More specifically, in a manner similar to that described above, data communication from the second communication unit 120 to the first communication unit 110 is also possible. In this case, the relay unit 140 operates in the second mode.

[0014] The time required for the voltage on the bus line to change from VL to VH (ie, the "rise time") depends on the time constant formed by the capacitance of the bus line and the resistance of the corresponding pull-up resistor. Typically, the voltage transition from VL to VH will therefore occur in an exponentially rising manner.

[0015] In order to reduce the rise time of the voltage on the second bus line 103a, the relay unit 140 of the known system 100 comprises an accelerator element 144. The accelerator element comprises a current source connected to the B-side terminal 141b. The current source provides additional charging current, thereby reducing the time to charge the bus capacitance.

[0016] In the open-drain bus line communication system, when operating in the first mode, the second communication unit 120 can communicate with the first communication unit 110 by means of pulling down the voltage on the bus line 103a. When using a known bus repeater, the detection circuit designed to detect such a pull-down may be complicated, and the use of the bus repeater limits the overall system implementation. Summary of the invention

[0017] The following is an overview of the aspects of the specific examples disclosed herein. It should be understood that these aspects presented are only used to provide the reader with a brief overview of these specific embodiments, and these aspects are not intended to limit the scope of the present disclosure. In fact, the present disclosure may include a combination of multiple aspects and / or aspects that may not be described.

[0018] The present disclosure proposes improvements to known open-drain bus communication systems, such as the open-drain system 100 of Figure 1. Specifically, an improved open-drain repeater with an edge accelerator for I2C communication is proposed, which advantageously resolves potential bus jams during I2C communication, thereby ensuring higher load capacitance.

[0019] According to one aspect of the present disclosure, a relay unit for open-drain bus communication is proposed. The relay unit may include an A-side terminal configured to be electrically connected to an A-side open-drain bus line. The relay unit may also include a B-side terminal configured to be electrically connected to a B-side open-drain bus line. The relay unit may operate in a first mode, wherein the relay unit is configured to receive a signal at the A-side terminal and generate a signal at the B-side terminal based on the signal received at the A-side terminal. The relay unit may also include a B-side rise time accelerator element electrically connected to the B-side terminal. The relay unit may also include a controller unit. The controller unit may be configured to control the B-side rise time accelerator element to pull up the voltage at the B-side terminal when the voltage at the A-side terminal exceeds a first threshold voltage during the rising edge of the voltage when the relay unit operates in the first mode, and then when the voltage at the B-side terminal exceeds a second threshold voltage, the B-side rise time accelerator element is controlled to stop pulling up the voltage at the B-side terminal. The controller unit may also be configured to disable the B-side rise time accelerator element when transmitting or receiving a handshake bit (handshakebit).

[0020] In one embodiment, the relay unit is operable in a second mode, wherein the relay unit is configured to receive a signal at a B-side terminal and generate a signal at an A-side terminal based on the signal received at the B-side terminal. The relay unit may also include an A-side rise time accelerator element electrically connected to the A-side terminal. The controller unit may be configured to, when the relay unit is operating in the second mode, control the A-side rise time accelerator element to pull up the voltage at the A-side terminal when the voltage at the B-side terminal exceeds a third threshold voltage during the rising edge of the voltage, and then control the A-side rise time accelerator element to stop pulling up the voltage at the A-side terminal when the voltage at the A-side terminal exceeds a fourth threshold voltage. The controller unit may also be configured to disable the A-side rise time accelerator element when transmitting or receiving a handshake bit.

[0021] In one embodiment, the relay unit may further include a direction control element. The controller unit may be configured to determine whether the relay unit is operating in the first mode or in the second mode. The controller unit may be configured to control the direction control element to prevent communication from the B-side terminal to the A-side terminal in the first mode, and to prevent communication from the A-side terminal to the B-side terminal in the second mode.

[0022] In one embodiment, the relay unit may be an I2C relay unit.

[0023] According to one aspect of the present disclosure, a bus repeater is provided, which may include one or more relay units having one or more of the above-mentioned features.

[0024] According to one aspect of the present disclosure, a system is provided. The system may include a bus repeater as described above. The system may also include a first communication unit. The system may also include a second communication unit. The A-side terminal of the first relay unit may be connected to a data pin of the first communication unit via a first bus line. The B-side terminal of the first relay unit may be connected to a data pin of the second communication unit via a second bus line. The A-side terminal of the second relay unit may be connected to a clock pin of the first communication unit via a third bus line. The B-side terminal of the second relay unit may be connected to a clock pin of the second communication unit via a fourth bus line.

[0025] According to one aspect of the present disclosure, a method for sending a handshake in an I2C-based communication between integrated circuits in a relay unit is provided. The relay unit may include an A-side terminal acting as a host and a B-side terminal acting as a slave. The method may include determining to perform a handshake from the host to the slave. The method may also include, if this has been determined, blocking communication from the host to the slave, and blocking edge acceleration of signals on the A-side terminal and the B-side terminal of the relay unit.

[0026] In one embodiment, the method may further include: after preventing edge acceleration, monitoring the state of the B-side terminal and enabling slave-to-master propagation. If the B-side terminal is not driven from the slave, a high signal may be transmitted on the A-side terminal. If the B-side terminal is driven from the slave, a low signal may be transmitted to the A-side terminal and confirmation is determined to be detected from the slave.

[0027] In one embodiment, the method may further include determining that a handshake is to be performed from the slave to the master. The method may further include, if this has been determined, blocking communication from the slave to the master, and blocking edge acceleration of signals on the A-side terminal and the B-side terminal of the relay unit.

[0028] In one embodiment, the method may further include: after preventing edge acceleration, monitoring the state of the A-side terminal and enabling host-to-slave propagation. If the A-side terminal is not driven from the host, a high signal may be transmitted on the B-side terminal. If the A-side terminal is driven from the host, a low signal may be transmitted to the B-side terminal.

[0029] In one embodiment, the method may further include, after preventing edge acceleration, expiring a delay timer before monitoring the state of the A-side terminal or the B-side terminal. The delay timer is set to 160ns, for example. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Embodiments of the present disclosure will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference numerals indicate corresponding parts and in which:

[0031] FIG1 is a schematic diagram of an open-drain communication system known in the art;

[0032] Figure 2 is a schematic diagram of a relay unit of a repeater according to an embodiment of the present disclosure;

[0033] Figure 3 and Figure 6-Figure 9 a graph showing voltage levels of various signals;

[0034] Figure 4 An example I2C bit transfer is shown;

[0035] Figure 5A and Figure 5B shows the data field in I2C bit transfer;

[0036] Fig.10 is a flowchart of an example method of the present disclosure; and

[0037] Fig.11 is a schematic diagram of a system using I2C bus communication according to an embodiment of the present disclosure.

[0038] The drawings are for illustrative purposes only and are not intended to limit the scope of protection defined by the claims. DETAILED DESCRIPTION

[0039] It will be readily appreciated that the components of the embodiments generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following more detailed description of the various embodiments as illustrated in the accompanying drawings is not intended to limit the scope of the present disclosure, but is merely representative of the various embodiments. Although various aspects of the embodiments are presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0040] The described embodiments are to be considered in all respects as illustrative only and not restrictive. Therefore, the scope of the present disclosure is indicated by the appended claims rather than by this detailed description. All changes within the meaning and scope of the equivalents of the claims are included within the scope of the claims.

[0041] References to features, advantages, or similar language throughout the specification do not mean that all features and advantages that can be achieved by the present disclosure should be or should be in any single example of the present disclosure. Instead, language referring to features and advantages is understood to mean that a particular feature, advantage, or characteristic described in conjunction with an embodiment is included in at least one embodiment of the present disclosure. Therefore, throughout the specification, discussions of features and advantages and similar language may, but do not necessarily, refer to the same example.

[0042] In addition, the features, advantages and characteristics of the present disclosure can be combined in one or more embodiments in any suitable manner. According to the description herein, those skilled in the relevant art will recognize that the present disclosure can be implemented without one or more specific features or advantages of a particular embodiment. In other cases, it can be recognized that additional features and advantages that may not be present in all embodiments of the present disclosure in certain embodiments. Throughout the specification, reference to "one embodiment", "embodiment" or similar language means that the specific features, structures or characteristics described in conjunction with the indicated embodiment are included in at least one embodiment of the present disclosure. Therefore, the phrases "one embodiment", "embodiment" and similar language throughout the specification may but do not necessarily all refer to the same embodiment.

[0043] I2C relay units typically use open-drain drivers to speed up the signal using pull-up resistors. Therefore, the communication of the signal can be improved by trading off power consumption, so high performance with low power consumption can be a challenging design feature. This is even more challenging in higher load capacitance applications.

[0044] In I2C communication, the acknowledgement (ACK) interface bit includes the ACK bit and the first bit of the new byte. The I2C protocol ends each transmitted byte with an ACK bit from the receiver end. As will be further explained, the rise time accelerator may compete with the open drain driver from the master or slave, which may cause the bus to get stuck, resulting in a breakdown current from the power supply (VCC) to the ground. The present disclosure focuses on solving the bus stuck during I2C communication, thereby enabling higher load capacitance.

[0045] The present disclosure proposes a controller unit of a relay unit, which enables intelligent acceleration of input signal edges when necessary and disables acceleration of output signal edges to avoid bus jams. This achieves signal integrity on input and output signals.

[0046] Here, the controller unit of the present disclosure can detect the handshake bit and disable edge acceleration during the handshake bit. The controller unit may include a clock pulse counter and a start-stop detection for counting clock pulses from the clock input signal 290 after the start condition on the serial data (SDA) signal. The clock input signal 290 may be a serial clock signal (SCL) of the host, which may also be referred to as SCLA. The controller unit may also detect the propagation direction so that the controller unit can control the rise time accelerator depending on the signal propagation direction from the host to the slave or from the slave to the host. The controller unit may include an optional timer to further control the propagation direction during the ACK interface bit. The solution of the present disclosure will be further explained below.

[0047] exist Figure 2 , a relay unit 200 of a repeater for open-drain bus communication according to the present disclosure is shown. The repeater may include at least one Figure 2 The relay unit 200 is shown.

[0048] The relay unit 200 includes an A-side terminal 201 and a B-side terminal 211. The A-side terminal 201 is configured to be electrically connected to the first communication unit using a first bus line (e.g., an A-side open drain bus). Similarly, the B-side terminal 211 is configured to be electrically connected to the second communication unit using a second bus line (e.g., a B-side open drain bus). The first communication unit can communicate with the second communication unit via a bus connection formed by the first bus line, the relay unit 200, and the second bus line. Specifically, the first communication unit can transmit data to the second communication unit by providing a voltage signal, such as a logic "high" voltage signal (VH) or a logic "low" voltage signal (VL) to the A-side terminal 201 of the relay unit 200 via the first bus line. The voltage signal is then relayed by the relay unit 200 at the B-side terminal 211. Then, the second communication unit can receive the voltage signal provided by the first communication unit from the B-side terminal 211 of the relay unit 200 via the second bus line.

[0049] The relay unit 200 includes an A-to-B buffer 202, a B-side pull-down control unit 215, and a B-side pull-down element 213 disposed between a B-side terminal 211 and a B-side ground reference terminal. The A-to-B buffer 202 receives a voltage signal at the A-side terminal 201 and generates a first buffered voltage signal. The first buffered voltage signal may then be provided to the B-side pull-down control unit 215. However, in some embodiments, the first buffered voltage signal may be provided to the controller unit 220 for direction (DIR) detection and / or ACK detection, which will be further described below.

[0050] The B-side pull-down control unit 215 is configured to control the B-side pull-down element 213 based on the received buffered signal. For example, if the received buffered voltage signal indicates a VH signal received at the A-side terminal 201, the B-side pull-down control unit 215 does not activate the B-side pull-down element 213, so that the voltage at the B-side terminal 211 is pulled up to or maintained at VH. On the other hand, if the received buffered voltage signal indicates a VL signal at the A-side terminal 201, the B-side pull-down control unit 215 generates a first control signal to control the B-side pull-down element 213 to pull down the voltage at the B-side terminal 211. For example, the B-side pull-down element 213 is a pull-down transistor configured to pull down the voltage at the B-side terminal 211 by absorbing the charge of the B-side bus line capacitance based on its gate or base voltage. The gate or base voltage is controlled by the first control signal generated by the B-side pull-down control unit 215. The B-side pull-down element 213 is, for example, an n-type metal oxide semiconductor (NMOS) transistor.

[0051] In the absence of pull-down, the voltage at the B-side terminal 211 is pulled up to the B-side power supply voltage VCCB by a pull-up resistor, such as the B-side pull-up resistor R2 and / or another pull-up resistor connected to the second bus line outside the relay unit 200. On the other hand, if, for example, the voltage at the A-side terminal 201 is pulled down by the first communication unit, in order to relay the signal at the B-side terminal 211, the B-side pull-down element 213 is controlled by the B-side pull-down control unit 215 to pull down the voltage at the B-side terminal 211 to VL.

[0052] For example, the B-side pull-down element 213 may be connected to a B-side reference voltage, such as ground, and may thus pull down the voltage at the B-side terminal 211 toward the B-side reference voltage. However, since the (possibly external) pull-up resistor continuously pulls up the voltage at the B-side terminal 211, VL may be greater than the B-side reference voltage. In other words, the logical "low" voltage level VL depends on the pull-down strength of the B-side pull-down element 213 and the pull-up strength of the (external) pull-up resistor. The B-side pull-down control unit 215 controls the pull-down strength of the B-side pull-down element 213 using a first control signal.

[0053] During the transition from VL to VH at the B-side terminal 211, the voltage at the B-side terminal 211 will increase in an exponentially increasing manner based on the time constant of the capacitance of the second bus line combined with the resistance of the corresponding pull-up resistor. Specifically, the current through the pull-up resistor will decrease as the voltage at the B-side terminal 211 increases, which current charges the capacitor. In other words, the rise time at the B-side terminal 211 and therefore the maximum reliable communication rate is generally dictated by the time constant.

[0054] The rise time can be improved by reducing the resistance of the pull-up resistor. However, if the same VL level is required, this will inherently require the B-side pull-down element 213 to have a greater pull-down strength, resulting in increased power consumption of the relay unit 200. Therefore, there is a trade-off between the maximum communication rate and the power consumption of the repeater.

[0055] In order to further improve the rise and fall time performance regardless of the selected pull-up resistor, the relay unit 200 further includes a B-side accelerator element 214 electrically connected to the B-side terminal 211, and a first control unit configured to control the B-side accelerator element 214 to pull up the voltage at the B-side terminal 211. Figure 2In the example of , the first control unit is integrated with the B-side accelerator element 214, but it may be outside the B-side accelerator element 214. For example, when the relay unit 200 is operated in the first mode, the first control unit of the B-side accelerator element 214 determines whether a transition from VL to VH occurs at the A-side terminal 201, and activates the B-side accelerator element 214 during at least a portion of the transition from VL to VH at the B-side terminal 211.

[0056] The B-side slew rate control unit 216 may further improve the slew rate of the signal, as will be further explained below.

[0057] like Figure 2 The relay unit 200 shown is bidirectional. That is, the relay unit 200 can operate in a first mode and a second mode, wherein the relay unit 200 receives a voltage signal at the B-side terminal 211 and relays the voltage signal at the A-side terminal 201. To this end, the relay unit 200 includes a B-to-A buffer 212, an A-side pull-down control unit 205, and an A-side pull-down element 203, which are sequentially arranged between the B-side terminal 211 and the A-side terminal 201. The operations of the B-to-A buffer 212, the A-side pull-down control unit 205, and the A-side pull-down element 203 may be similar to or equivalent to the operations of the A-to-B buffer 202, the B-side pull-down control unit 215, and the B-side pull-down element 213. Therefore, a detailed description thereof is omitted.

[0058] In addition, the relay unit 200 may include an A-side pull-up resistor R1 connected between the A-side power supply voltage VCCA and the A-side terminal 201. Alternatively or alternatively, an external pull-up resistor may be connected to the first bus line. The voltage at the A-side terminal 201 is pulled up by the pull-up resistor.

[0059] The relay unit 200 also includes direction detection to determine whether the relay unit 200 is operating in the first mode or the second mode, and controls the A-side pull-down control unit 205 and / or the B-side pull-down control unit 215 accordingly. For direction detection and according to the I2C specification, one of the A-side and the B-side can be operated in the master mode, and the other of the A-side and the B-side can be operated in the slave mode. In the following example, the A-side is operated in the master mode, and the B-side is operated in the slave mode.

[0060] For example, in the case of operating the A side in the host mode, the controller unit 220 may receive an input signal 291 similar or identical to a signal at the A side terminal 201, or an input signal similar or identical to a first buffered signal from the A to B buffer 202, and determine whether to operate the relay unit 200 in the first mode or in the second mode based on the input signal 291. Depending on the determined operating mode, the direction control (DIR_CTRL) signals 298, 299 may trigger the A side direction control element 207 and the B side direction control element 217, respectively. The direction control elements 207, 217 may be implemented as anti-self-locking triggers.

[0061] For example, if a voltage conversion occurs at the A-side terminal 201, it can be determined based on the input signal 291 that the relay unit 200 is operated in the first mode. Therefore, the DIR_CTRL signal 299 signals the B-side direction control element 217 to enable the B-side pull-down control unit 215. In addition, because the voltage at the A-side terminal 201 should be controlled by the first communication unit instead of the relay unit 200, the DIR_CTRL signal 298 signals the A-side direction control element 207 to disable the A-side pull-down control unit 205. In other words, the A-side pull-down control unit 205 and the A-side pull-down element 203 are disabled in the first mode, and the B-side pull-down control unit 215 and the B-side pull-down element 213 are disabled in the second mode.

[0062] The first power supply voltage VCCA and the second power supply voltage VCCB may be the same DC voltage, or may be different DC voltages. The latter may be required when the first communication unit operates based on a different voltage range compared to the second communication unit. For example, the first communication unit may require a VL level of 0.1V and a VH level of 1V, while the second communication unit may require a VL level of 0.3V and a VH level of 3.3V. In this case, for example, the VH signal provided by the first communication unit may not be recognized as a VH signal by the first communication unit. In order to correct this, the A-side terminal 201 may have an A-side logic "high" voltage level VHa based on the power supply voltage VCCA, and the B-side terminal 211 may have a B-side logic "high" voltage level VHb based on the power supply voltage VCCB. The logic "low" voltage levels VLa, VLb at the A-side terminal 201 and the B-side terminal 211 may depend on the pull-up strength of the corresponding pull-up resistor and the pull-down strength of the corresponding pull-down element, respectively.

[0063] If the first power supply voltage VCCA is different from the second power supply voltage VCCB, the relay unit 200 may further include an A to B level converter 208 and a B to A level converter 218. The A to B level converter 208 receives the first buffer signal from the A to B buffer 202 and outputs a voltage signal having a different voltage range relative to the received first buffer signal. Similarly, the B to A level converter 218 receives the second buffer signal from the B to A buffer 212 and outputs a signal having a different voltage range relative to the received second buffer signal.

[0064] For example, the first buffered signal is a voltage signal between the A-side ground reference voltage received at the A-side ground reference terminal and the A-side power supply voltage VCCA, and the voltage signal output by the A-to-B level converter 208 is a voltage between the B-side ground reference voltage received at the B-side ground reference terminal and the B-side power supply voltage VCCB. Similarly, the second buffered signal may be a voltage signal between the B-side ground reference voltage received at the B-side ground reference terminal and the B-side power supply voltage VCCB, and the voltage signal output by the B-to-A level converter 218 may be a voltage between the A-side ground reference voltage received at the A-side ground reference terminal and the A-side power supply voltage VCCA.

[0065] according to Figure 2 The relay unit 200 further includes an A-side accelerator element 204 electrically connected to the A-side terminal 201, wherein the second control unit is configured to control the A-side accelerator element 204 to pull up the voltage at the A-side terminal 201. The A-side accelerator element 204 may be the same as or similar to the B-side accelerator element 214, and may include a second control unit that is the same as or similar to the first control unit of the B-side accelerator element 214.

[0066] Relay unit 200 may also include an A-side slew rate control unit 206 similar to B-side slew rate control unit 216 .

[0067] A side accelerator element 204 and B side accelerator element 214 can each include a voltage controlled current source. For example, B side accelerator element 214 can include a p-type MOS (PMOS) transistor connected between the second power supply voltage VCCB and the B side terminal 211, and the first control unit of B side accelerator element 214 can control its gate voltage. Similarly, A side accelerator element 204 can include a PMOS transistor connected between the first power supply voltage VCCA and the A side terminal 201, and the PMOS transistor has a second control unit for controlling its gate voltage. Therefore, each of A side accelerator element 204 and B side accelerator element 214 can generate a substantially constant current when activated, for charging bus line capacitance when saturated operation.

[0068] In addition, the current generated by the A-side accelerator element 204 and the B-side accelerator element 214 can greatly exceed the current through the pull-up resistor connected to the same bus line, especially when the voltage on the bus line increases. Therefore, the rise time at the A-side terminal 201 and / or the B-side terminal 211 can be significantly reduced.

[0069] Figure 2 The block diagram may describe an I2C relay unit 200 of a repeater system, which includes two channels, a forward channel for converting and buffering signals from an A-side terminal 201 to a B-side terminal 211, and a backward channel for converting and buffering signals from a B-side terminal 211 to an A-side terminal 201.

[0070] As described above, the forward channel may include an A-side input buffer 202, an A-side level shifter 208, a B-side anti-locking trigger 217, a B-side pull-down element 213, and a B-side slew rate control unit 216. The A-side input buffer 202 may include a Schmitt trigger that converts a slowly rising signal into a buffered signal at the input and provides the input to the A-side level shifter 208. The A-side level shifter 208 converts the signal in the VCCA domain to the VCCB domain. The output of the A-side level shifter 208 may be fed to the B-side anti-locking trigger 217 to prevent self-locking. The output of the B-side anti-locking trigger 217 may be an input to a B-side pull-down network including a B-side pull-down control unit 215 and a B-side pull-down element 213. The pull-down network, together with the B-side slew rate control unit 216, controls the fall time on the output to ensure that the minimum fall time meets the I2C specification.

[0071] The reverse channel is symmetrical to the forward channel and is responsible for converting the signal from the B-side terminal 211 to the A-side terminal 201 .

[0072] The I2C relay unit 200 may include two rise time accelerator elements 204, 214, one on the A side terminal 201 and the other on the B side terminal 211. The rise time accelerator elements 204, 214 may be configured to be turned on only during a low to high transition and to boost the signal until they reach a second threshold voltage, such as 80% of VCCA or VCCB, respectively. The rise time accelerator elements 204, 214 may be configured to be turned on after being triggered. In a first example, it may be triggered by a terminal voltage that rises from low to high and crosses a first threshold voltage, such as 42.5% of VCCA or VCCB. In a second example, it may be triggered by detecting a relative port between the A side and the B side that rises from low to high and crosses a first threshold voltage.

[0073] Figure 3An example of signal propagation for a low to high transition on the forward channel is shown. Five signal graphs are shown where the x-axis is aligned and represents time in any time unit and the y-axis represents signal strength in volts. The A-side terminal 201 can be released and pulled up with resistor R1. Once the signal at the A-side terminal 201 (at Figure 3 201) across Figure 3 The A-side rise time accelerator element 204 may be configured to provide a first threshold voltage as “Vtp” in FIG. Figure 2 and Figure 3 The A-side rise time accelerator element 204, which operates as an input accelerator in this example, accelerates the signal on the A-side terminal 201 from the first threshold voltage Vtp to the Figure 3 The second threshold voltage depicted as "Vstop" in FIG. 1 is, for example, from Vtp = 42.5% of VCCA to Vstop = 80% of VCCA. Because the Output_acc_A2B signal (in Figure 2 and Figure 3 295) becomes high, so the B-side rise time accelerator 214, which now operates as an output accelerator, can Figure 3 The signal on VCCB (depicted as "211") is accelerated from the VL level to a second threshold level, for example, from VL to Vstop = 80% of VCCB.

[0074] A relay unit with an edge accelerator, such as the relay unit 200 with the rise time accelerator elements 204, 214, may encounter a problem of the bus getting stuck during an acknowledgement. This may occur when the master releases and the slave transmits an acknowledgement, which typically includes one bit represented by the VH signal. This Figure 3 , where at the confirmation bit, the master releases the line. At t1, the voltage on the A-side terminal 201 crosses the first threshold voltage Vtp, and the input edge acceleration on the A-side terminal 201 and the output edge acceleration on the B-side terminal 211 begin. At t2, the slave transmits a confirmation by pulling the signal at the B-side terminal 211 low. Figure 3 Here, the B-side rise time accelerator 214 attempts to pull the signal on the B-side terminal 211 high, while the slave attempts to pull the signal on the B-side terminal 211 low. Since both the rise time accelerator 214 and the slave are very strong, the signal at the B-side terminal 211 may settle at any voltage between VCCB and ground, causing the bus to get stuck and potentially dissipate a lot of current. Figure 3 , an example of a bus stuck voltage “ 304 ” is depicted.

[0075] Bus jams may be prevented by including an ACK detection mechanism in the controller unit 220, as described in further detail below.

[0076] I2C bit transmission usually includes handshake bits and non-handshake bits. Non-handshake bits are used when communication is in one direction and the other end is in receiving mode. Handshake bits are used when one end of the relay unit 200 releases and the other end responds. Figure 4 An example of an I2C bit transfer 400 is shown, in which the most significant bit (MSB) and the ACK bit of a data byte are handshake bits, while the other bits (depicted as “bits”) including the least significant bit (LSB) are non-handshake bits. Figure 4 , SCL is the serial clock (SCL) signal and SDA is the serial data (SDA) signal. In the illustrated cycle 402, the SDA line is stable (i.e., has a logic "1" or logic "0" value) and the SCL line is high (i.e., has a logic "1" value). Figure 4 In the example of , the I2C bit transfer includes byte 404 of data representing a value of 10101010 (0xAAh) followed by an ACK bit.

[0077] Figure 5A An example portion of an I2C communication 500A is shown in which a master transmitter addresses a slave receiver with 7-bit addressing and a write operation. The timing of the handshake bits is depicted as P1, P2, P3, P4, P5, and P6. The I2C communication 500A generally includes a start condition 502, a slave address 504, a read / write bit 506, first ACK 508 (e.g., SDA low), first data 510, second ACK 512 (e.g., SDA low), second data 514, ACK (e.g., SDA low) or non-ACK (NACK, e.g., SDA high) 516, and stop condition 518. For a write operation, The value 520 of bit 506 is generally "0". The payload of the transmitted data, including the ACK, is depicted as 522. Figure 5A , the shaded portions (ie, 502, 504, 506, 510, 514, and 518) represent data from the master to the slaves, and the unshaded portions (ie, 508, 512, and 516) represent data from the slaves to the master.

[0078] For non-handshake bits in a master to slave data transfer, the voltage levels 600 at the various data lines SCLA, SDAA, SCLB, and SDAB may be as follows: Figure 6 Here, SCLA represents the SCL for the host (e.g., for Figure 2 communication from side A to side B in the communication), SCLB represents the SCL for the slave (for example, for Figure 2 ), SDAA represents the signal on the A-side terminal 201, and SDAB represents the signal on the B-side terminal 211. The Vstop and Vtp levels may be similar to Figure 3 , for example, 80% of VCC and 42.5% of VCC respectively. Figure 6 In the case of a low state of SCLA and SCLB, the data changes from low to high. Figure 6 As shown, two edge accelerators enhance the edges of all signals.

[0079] For the handshake bits, consider Figure 5A The situation at P1 shown in FIG. ACK detection by the controller unit 220 may be started after SCLB receives a transition from high to low. SDAB is released by the relay unit 200 at t1. Figure 7 In the example of FIG. 7 , the voltage levels 700 of the data lines SCLA, SDAA, SCLB, SDAB are shown for a slave to transmit a NACK to a host. Since the slave does not transmit an ACK, the host releases SDAA, and therefore both SDAA and SDAB see a high state before the next rising edge of SCLA and SCLB. Here, the relay unit 200 makes the decision to expect a NACK from the slave so that the rising edge on SDAB relies only on a pull-up element, such as a pull-up resistor. The setup time at the host and slave interface is easy to achieve because it does not depend on the slave to respond or the host to release, SDAB can use the full low state of SCLB and see a high state before the next rising edge.

[0080] exist Figure 8 In the example of , the voltage levels 800 of the data lines SCLA, SDAA, SCLB, SDAB are shown for the slave to transmit an ACK to the master. If the slave transmits an ACK on SDAB at t2, it is pulled low from the outside. SDAA follows SDAB and the master sees the ACK. At the P1 interface, the controller unit 220 can control the rise time accelerator elements 204, 214 on SDAA and SDAB to be disabled to avoid conflicts between the external pull drivers and the rise time accelerators. Here, the disable signals 292, 293 can be sent from the controller unit 220 to the corresponding rise time accelerator elements 204, 214. Therefore, the bus can be prevented from getting stuck because the open drain driver from the slave does not conflict with the edge acceleration.

[0081] At P2, assuming there is an ACK from the slave, during the ACK bit, the direction of propagation is from the slave to the master. If the master wants to send Low (i.e., VL), the relay unit 200 can do as follows Fig. 9 The reaction was carried out as shown. Fig. 9In the example of FIG. 1 , the voltage levels 900 of the data lines SCLA, SDAA, SCLB, SDAB are shown for a host transmitting a Low (i.e., VL) to a slave after an ACK bit. First, when the controller unit 220 starts by predicting that the host wants to transmit a High (i.e., VH) during the first bit, the relay unit 200 may release SDAA at t1. If the host transmits a Low at t3, SDAB may follow the host at t4. According to the I2C protocol, the slave releases the line at t2, and the slave receives data from the master.

[0082] Figure 5B FIG. 5 shows an example portion of an I2C communication 500B, where a master transmitter addresses a slave receiver using 7-bit addressing and a read operation. Figure 5A As shown, the shaded part (in Figure 5B 502, 504, 506, 512, 516 and 518) represent data from the master to the slave, and the non-shaded portion (in Figure 5B 508, 510 and 514) represent data from the slave to the master. For a read operation, The value 520 of bit 506 is usually "1". Figure 5B In the example, field 516 includes a NACK bit. Figure 5B The read operation shown is similar to Figure 5A The write operation shown is slightly different. After the slave is addressed, the slave immediately transmits data to the master, so there is no handshake after ACK 508. Therefore, there are only handshake bits P1, P3, P4, P5 and P6 in I2C communication 500B. After receiving the first byte of data, there is an ACK from the master to the slave at P3. Here, the handshake is from the slave to the master, and at P4, the handshake is from the master to the slave.

[0083] Fig.10 An example process flow 1000 of a process performed by a controller unit, such as the controller unit 220, for preventing a bus jam during a handshake is shown. The process flow 1000 enables smart acceleration (i.e., rise time acceleration only when necessary and avoiding bus jams) and direction control. For smart acceleration, the controller unit 220 can generate disable signals 292, 293 for disabling the rise time accelerator 204, 214 during a handshake. For direction control, the controller unit 220 can generate DIR_CTRL signals 298, 299 for controlling the direction control elements 207, 217.

[0084] In step 1002, a controller unit, such as controller unit 220, may determine a Figure 5A I2C communication 500A or Figure 5BWhether the I2C communication 500B of the I2C communication is to perform a handshake from the A side of the relay unit such as the relay unit 200 to the B side, or vice versa. The A side can be defined as the host, and the B side can be defined as the slave. The controller unit 220 can receive an input signal 291 representing a signal at the host (e.g., a signal at the A side terminal 201) and a clock input signal 290 to determine when to perform a handshake.

[0085] exist Figure 5A During the write operation of the example of , handshaking is performed from the master to the slave at P1, P3, and P5, i.e., handshaking is performed during the ACK bit 508, ACK bit 512, and ACK / NACK bit 516 from the slave to the master. Figure 5B During the read operation of the example of , handshaking is performed from the master to the slave at P1 and P4, that is, handshaking is performed during the ACK bit 508 from the slave to the master and during the first bit of the read operation at data 514.

[0086] exist Figure 5A During the write operation of the example of , a handshake is performed from the slave to the master at P2 and P4, i.e., the first bit of the write operation at data 510 and data 514. Figure 5B During the read operation of the example of , a handshake is performed from the slave to the master at P3 and P5, ie, during the ACK bit 512 and the ACK / NACK bit 516 from the master to the slave.

[0087] Depending on the direction of the handshake, steps 1010-1016 or steps 1020-1026 may be performed. Fig.10 In the example of , if it is determined that a handshake is to be performed from the master to the slave, steps 1010-1016 are performed. On the other hand, if it is determined that a handshake is to be performed from the slave to the master, steps 1020-1026 are performed.

[0088] In step 1010, when handshaking from the master to the slave (i.e., during the ACK bit 508, ACK bit 512, and ACK / NACK bit 516 of 500A, and during the ACK bit 508 of 500B and the first bit of the read operation at the data 514), the controller unit 220 blocks the communication from the A-side terminal 201 to the B-side terminal 211, for example, by transmitting a DIR_CTRL signal to the B-side anti-locking flip-flop 217. The relay unit 200 may release the B-side terminal 211 after the falling edge of the clock signal at the B-side terminal 211.

[0089] In step 1010 , for handshaking, the controller unit 220 further inhibits edge acceleration on the rise time accelerator elements 204 , 214 by transmitting a disable signal 292 , 293 to the rise time accelerator elements 204 , 214 .

[0090] Optionally, the relay unit may implement a delay timer at the end of step 1010 to avoid potential malfunction on the B-side terminal 211. The delay timer is set to, for example, 160 ns, or any other suitable time value between 100 ns and 300 ns.

[0091] In step 1012, the state of the signal on the B-side terminal 211 is monitored and the propagation from the slave to the master is enabled. If the B-side terminal 211 is not driven from the slave (the signal is high), then in step 1014, the relay unit 200 transmits a high signal on the A-side terminal 201. If the B-side terminal 211 is driven from the slave (the signal is low), then in step 1016, the confirmation from the slave is detected and a low signal is transmitted to the A-side terminal 201.

[0092] In step 1020, when handshaking from the slave to the master (i.e., during the ACK bit 512 and the NACK bit 516 of 500B, and between the first bit periods of the write operation at the data 510 and the data 514 of 500A), the controller unit 220 blocks the communication from the B-side terminal 211 to the A-side terminal 201, for example, by transmitting a DIR_CTRL signal to the A-side direction control element 207. The relay unit 200 may release the A-side terminal 201 after the falling edge of the clock signal at the A-side terminal 201.

[0093] In step 1020 , for handshaking, the controller unit 220 further inhibits edge acceleration on the rise time accelerator elements 204 , 214 by transmitting a disable signal 292 , 293 to the rise time accelerator elements 204 , 214 .

[0094] Optionally, the relay unit may implement a delay timer at the end of step 1020 to avoid potential malfunction on the A-side terminal 201. The delay timer is set to 160ns, for example, or any other suitable time value between 100ns and 300ns.

[0095] In step 1022, the state of the signal on the A-side terminal 201 is monitored, and the propagation from the host to the slave is enabled. If the A-side terminal 201 is not driven from the host (the signal is high), then in step 1024, the relay unit 200 transmits a high signal on the B-side terminal 211. Input acceleration on the B-side terminal 211 can be enabled to accelerate the edge. If the A-side terminal 201 is driven from the host (the signal is low), then in step 1026, a low signal is transmitted to the B-side terminal 211.

[0096] The controller unit 220 may be configured to execute the following algorithm.

[0097] For the handshake from the master to the slave (this occurs during the first bit of an acknowledge or read operation from the slave):

[0098] -Relay units block the master to slave direction;

[0099] -The repeater releases SDAB after the falling edge of SCLB;

[0100] - Repeater blocks edge accelerator on SDAA and SDAB;

[0101] - Wait 160ns to avoid glitches on SDAB (optional);

[0102] - Monitor the status of SDAB and enable slave to master propagation;

[0103] - If SDAB is not driven from the slave, a high signal is transmitted on SDAA;

[0104] - If SDAB is driven from the slave, then an ACK from the slave is detected and a low signal is transmitted to SDAB.

[0105] For the handshake from slave to master (this happens during the acknowledgement of the first bit of a write byte from the master or write):

[0106] -Repeaters block slaves from reaching the master;

[0107] -Repeater releases SDAA on falling edge of SCLA;

[0108] - Repeater blocks edge accelerator on SDAA and SDAB;

[0109] - Wait 160ns to avoid glitches on SDAA (optional);

[0110] - Monitor the status of SDAA and enable master to slave propagation;

[0111] - If SDAA is not driven from the host, a high signal is sent on SDAB, which can enable input acceleration on SDAB to accelerate the edge;

[0112] - If driving SDAA from the slave host, send a low signal to SDAB.

[0113] Fig.11 A system 1100 is shown that employs a bus repeater 1102. The bus repeater 1102 may include one or more repeater units, such as the repeater unit 200. Fig.11In the example of FIG. 1 , the bus repeater 1102 includes two repeater units 200A and 200B. The system 1100 may further include a first communication unit 110 and a second communication unit 120 .

[0114] The A-side terminal 201 of the first relay unit 200A may be connected to the data pin of the first communication unit 110 via a corresponding bus line, and the B-side terminal 211 of the first relay unit 200A may be connected to the data pin of the second communication unit 120 via a corresponding bus line. Similarly, the A-side terminal 201 of the second relay unit 200B may be connected to the clock pin of the first communication unit 110 via a corresponding bus line, and the B-side terminal 211 of the second relay unit 200B may be connected to the clock pin of the second communication unit 120 via a corresponding bus line. In the system 1100, communication between the first communication unit 110 and the second communication unit 120 may be performed based on the I2C protocol.

Claims

1. A relay unit (200) for open-drain bus line communication, the relay unit (200) comprising: A-side terminal (201), the A-side terminal being configured to be electrically connected to an A-side open-drain bus line; and a B-side terminal (211), the B-side terminal being configured to be electrically connected to a B-side open-drain bus line, wherein the relay unit (200) is operable in a first mode, wherein the relay unit (200) is configured to receive a signal at the A-side terminal (201), and to generate a signal at the B-side terminal (211) based on the signal received at the A-side terminal (201), The relay unit (200) further comprises: A B-side rise time accelerator element (214), the B-side rise time accelerator element being electrically connected to the B-side terminal (211); and a controller unit (220), wherein the controller unit (220) is configured to, when the relay unit (200) operates in the first mode, control the B-side rise time accelerator element (214) to pull up the voltage at the B-side terminal (211) when the voltage at the A-side terminal (201) exceeds a first threshold voltage during a rising edge of the voltage, and then control the B-side rise time accelerator element (214) to stop pulling up the voltage at the B-side terminal (211) when the voltage at the B-side terminal (211) exceeds a second threshold voltage, And wherein the controller unit (220) is further configured to disable the B-side rise time accelerator element (214) when transmitting or receiving a handshake bit.

2. The relay unit (200) according to claim 1, wherein the relay unit (200) is operable in a second mode, wherein the relay unit (200) is configured to receive a signal at the B-side terminal (211), and to generate a signal at the A-side terminal (201) based on the signal received at the B-side terminal (211), The relay unit (200) further includes an A-side rise time accelerator element (204) electrically connected to the A-side terminal (201), wherein the controller unit (220) is configured to, when the relay unit (200) operates in the second mode, control the A-side rise time accelerator element (204) to pull up the voltage at the A-side terminal (201) when the voltage at the B-side terminal (211) exceeds a third threshold voltage during a rising edge of the voltage, and then control the A-side rise time accelerator element (204) to stop pulling up the voltage at the A-side terminal (201) when the voltage at the A-side terminal (201) exceeds a fourth threshold voltage, And wherein the controller unit (220) is further configured to disable the A-side rise time accelerator element (204) when transmitting or receiving a handshake bit.

3. The relay unit (200) according to claim 2, The relay unit further comprises a direction control element (207, 217), wherein the controller unit (220) is configured to determine whether the relay unit (200) is operating in the first mode or in the second mode, And wherein the controller unit (220) is configured to control the direction control element (207, 217) to prevent communication from the B-side terminal (201) to the A-side terminal (211) in the first mode, and to prevent communication from the A-side terminal (211) to the B-side terminal (201) in the second mode.

4. The relay unit (200) according to any one of the preceding claims, wherein the relay unit (200) is an Inter-Integrated Circuit (I2C) relay unit.

5. A bus repeater (1102), comprising one or more relay units (200, 200A, 200B) according to any one of claims 1-4.

6. A system (1100), comprising: The bus repeater (1102) according to claim 5; A first communication unit (110); as well as a second communication unit (120), The A-side terminal (201) of the first relay unit (200A) is connected to the data pin of the first communication unit (110) via a first bus line, wherein the B-side terminal (211) of the first relay unit (200A) is connected to the data pin of the second communication unit (120) via a second bus line, wherein the A-side terminal (201) of the second relay unit (200B) is connected to the clock pin of the first communication unit (110) via a third bus line, And wherein the B-side terminal (211) of the second relay unit (200B) is connected to the clock pin of the second communication unit (120) via a fourth bus line.

7. A method (1000) for sending a handshake in an inter-IC I2C based communication in a relay unit, the relay unit comprising an A-side terminal acting as a master and a B-side terminal acting as a slave, the method comprising: Determine that a handshake is to be performed from the master to the slave, and if this has been determined: Block communication from the master to the slave; as well as The edge acceleration of the signal on the A-side terminal and the B-side terminal of the relay unit is prevented.

8. The method according to claim 7, further comprising: After preventing the edge from accelerating, monitoring the state of the B-side terminal and enabling slave-to-master propagation; If the B-side terminal is not driven from the slave, a high signal is transmitted on the A-side terminal; And if the B-side terminal is driven from the slave, a low signal is transmitted to the A-side terminal, and it is determined that confirmation is detected from the slave.

9. The method according to claim 7 or claim 8, further comprising: Determine that a handshake is to be performed from the slave to the master, and if this has been determined: Block communication from slaves to the master; as well as The edge acceleration of the signal on the A-side terminal and the B-side terminal of the relay unit is prevented.

10. The method according to claim 9, further comprising: After preventing the edge acceleration, monitoring the state of the A-side terminal and enabling master to slave propagation; If the A-side terminal is not driven from the host, a high signal is transmitted on the B-side terminal; And if the A-side terminal is driven from the host, a low signal is transmitted to the B-side terminal.

11. The method according to any one of claims 8 to 10, further comprising: After preventing the edge from accelerating, a delay timer is expired before monitoring the state of the A-side terminal or the B-side terminal.

12. The method according to claim 11, wherein the delay timer is set to 160ns.

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