FPGA-Based High-Definition Image Rotation System and Method

Abstract

The present invention provides an FPGA-based high-definition image rotation system and method, including a receiving module, a display module, and a control module; the receiving module receives and stores image data in YUV422 format, and parses the image data to obtain a write instruction and image coordinate information; the display module generates a read instruction according to the display information and the image coordinate information, and outputs rotated image data in YUV422 format; the control module reads the image data stored in the receiving module according to the write instruction and stores it in the DDR particles in a preset storage manner, and reads the image data stored in the DDR particles to the display module in a preset reading manner according to the read instruction. By using low-speed image data in YUV422 format and caching it in the DDR, not only is the input image data significantly reduced, but also the image data can correspond to the bit width of the DDR particles, maximizing the use of DDR space and improving the processing efficiency of image rotation, solving the problem of how to improve the image rotation display efficiency without occupying too many resources.

Description

Technical Field

[0001] The present invention relates to the technical fields of image processing and data storage, and particularly to a high-definition image rotation system and method based on FPGA. Background Art

[0002] With the continuous development and improvement of information technology, higher requirements are put forward for the resolution of image display, such as high-definition resolutions of 1080P, 2160p, 3840p, etc.; at the same time, the display methods are not all conventional landscape displays, and many portrait displays are added to meet the diverse display needs of people.

[0003] In order to achieve 90-degree rotation of an image, currently, a static random access memory (SRAM) is usually used. Although this device has no delay waiting for reading and writing data, its price is too high and it is not suitable for large-scale applications. Or, DDR3 is adopted, and its BURST burst technology is utilized, that is, each time an address is read / written, 8 data are output / input. However, since various data alignments and clock alignments need to be performed inside the DDR3 particles, each time data is read and written in a DDR BANK, a read / write command is generated, resulting in low efficiency and affecting the resolution of image display.

[0004] In addition, for images with a large size, the prior art also needs to divide the image into regions, rotate the image separately based on each region, and then write it into the DDR, and realize the rotation of the image by recalculating the image coordinates and then reading them out. This method will undoubtedly use a large number of calculation processes and occupy more hardware resources. Summary of the Invention

[0005] The purpose of the present invention is to provide a high-definition image rotation system and method based on FPGA, so as to at least solve the problem of how to improve the image rotation display efficiency without occupying too many resources.

[0006] To solve the above technical problems, the present invention provides a high-definition image rotation system based on FPGA, including a receiving module, a display module, and a control module;

[0007] The receiving module is used to receive and store image data in YUV422 format, and parse the image data to obtain a write instruction and image coordinate information; the display module is used to generate a read instruction according to the display information and the image coordinate information, and output the rotated image data in YUV422 format; the control module is used to read the image data stored in the receiving module according to the write instruction, and store the image data into the DDR particles in a preset storage manner, and is also used to read the image data stored in the DDR particles into the display module in a preset reading manner according to the read instruction;

[0008] The DDR particles include multiple storage areas, and each storage area has multiple storage blocks; when image data is stored in the DDR particles, the image data of the same row is sequentially stored in different storage blocks of different storage areas in units of rows, and the storage start position of the image data of the subsequent row is one storage area behind the storage start position of the image data of the previous row.

[0009] Optionally, in the FPGA-based high-definition image rotation system, the receiving module includes an image acquisition unit, a write FIFO unit, and an input storage unit;

[0010] The image acquisition unit is used to receive image data in YUV422 format and parse the image data to obtain a write instruction and image coordinate information; the write FIFO unit is used to store the write instruction; the input storage unit is used to store image data in YUV422 format.

[0011] Optionally, in the FPGA-based high-definition image rotation system, the image acquisition unit includes an IDDR sub-unit, a splicing sub-unit, a write storage address generation sub-unit, a coordinate generation sub-unit, and a frame start sub-unit;

[0012] The IDDR sub-unit is used to receive image data in YUV422 format and convert the image data from dual-edge image data into two single-edge sub-image data; the splicing sub-unit is used to splice the two-way single-edge sub-image data output by the IDDR sub-unit to obtain one-way single-edge image data; the write storage address generation sub-unit is used to receive a line synchronization signal and generate a write enable signal and a write address signal; the coordinate generation sub-unit is used to receive a line start signal and generate image coordinate information, and the image coordinate information includes image line coordinate information and image column coordinate information; the frame start sub-unit is used to receive a frame start signal and generate frame information; the write instruction includes a write enable signal, a write address signal, image line coordinate information, and frame information.

[0013] Optionally, in the FPGA-based high-definition image rotation system, the storage space of the input storage unit is 2 times the width of the maximum input image; the image data is stored in the input storage unit in a ping-pong manner and read out from the input storage unit in a ping-pong manner.

[0014] Optionally, in the FPGA-based high-definition image rotation system, the display module includes an output storage unit, a read FIFO unit, and an image output unit;

[0015] The output storage unit is used to store the image data read from the DDR particles; the image output unit is used to obtain the display information and image coordinate information, generate a read instruction according to the display information and image coordinate information, and is also used to output the image data stored in the output storage unit and generate a synchronization code to output the rotated image data in YUV422 format; the read FIFO unit is used to store the read instruction.

[0016] Optionally, in the above-mentioned FPGA-based high-definition image rotation system, the image output unit includes a read instruction generation subunit, a synchronization code generation subunit, and an ODDR subunit;

[0017] The read instruction generation subunit is used to generate a read instruction according to the display information and image coordinate information; the synchronization code generation subunit is used to generate a synchronization code according to the image coordinate information; the ODDR subunit is used to restore the image data stored in the output storage unit from single-edge image data to double-edge image data to output the rotated image data in YUV422 format.

[0018] Optionally, in the above-mentioned FPGA-based high-definition image rotation system, the control module includes a read-write arbitration unit, a status controller, a control signal generation unit, a command address generation unit, and a DDR physical layer;

[0019] The read-write arbitration unit is used to receive a write instruction and a read instruction, and start the status controller according to the write instruction or read instruction in a first-in-first-out arbitration manner; the status controller is used to generate an address signal and a read-write command for controlling the DDR physical layer according to the write instruction or read instruction; the control signal generation unit is used to generate a read address signal according to the write instruction; and is also used to generate a write address signal according to the read instruction;

[0020] The command address generation unit is used to send the image data stored in the receiving module to the DDR particles through the DDR physical layer by using the address signal, the read-write command, and the read address signal; and is also used to read the image data from the DDR particles through the DDR physical layer by using the address signal, the read-write command, and the write address signal and write it into the display module.

[0021] To solve the above technical problems, the present invention also provides an FPGA-based high-definition image rotation method, which is applied to the FPGA-based high-definition image rotation system described in any one of the above, and the high-definition image rotation method includes:

[0022] Receive and store the image data in YUV422 format;

[0023] Analyze the image data to obtain a write instruction and image coordinate information;

[0024] Read the image data stored in the receiving module according to the write instruction, and store the image data in the DDR particles according to the preset storage method;

[0025] Generate a read instruction according to the display information and the image coordinate information;

[0026] Read the image data stored in the DDR particles according to the read instruction in the preset reading method, so as to output the rotated image data in YUV422 format.

[0027] Optionally, in the above-mentioned high-definition image rotation method based on FPGA, the method for parsing the image data to obtain the write instruction and the image coordinate information includes:

[0028] Convert the received image data in YUV422 format from the double-edge image data format to two single-edge sub-image data;

[0029] Stitch the two single-edge sub-image data to obtain one single-edge image data;

[0030] Receive the line synchronization signal and generate a write enable signal and a write address signal;

[0031] Receive the line start signal and generate image coordinate information, where the image coordinate information includes image line coordinate information and image column coordinate information;

[0032] Receive the frame start signal and generate frame information;

[0033] Among them, the write instruction includes a write enable signal, a write address signal, image line coordinate information, and frame information.

[0034] Optionally, in the above-mentioned high-definition image rotation method based on FPGA, the method for reading the image data stored in the receiving module according to the write instruction and storing the image data in the DDR particles according to the preset storage method includes:

[0035] Receive the write instruction;

[0036] According to the arbitration method of first in first out, generate a read address signal, an address signal, and a read / write command according to the write instruction;

[0037] According to the read address signal, read the image data from the receiving module, and according to the address signal and the read / write command, send the read image data to the DDR particles through the DDR physical layer.

[0038] Optionally, in the above-mentioned high-definition image rotation method based on FPGA, the method for generating a read instruction according to the display information and the image coordinate information includes:

[0039] Generate a read instruction according to the display information and the image coordinate information;

[0040] Generate a synchronization code according to the image coordinate information.

[0041] Optionally, in the above-mentioned high-definition image rotation method based on FPGA, the method of reading out the image data stored in the DDR particles according to the read instruction in a preset reading manner to output rotated image data in YUV422 format includes:

[0042] Receive a read instruction;

[0043] According to the first-in-first-out arbitration method, generate a write address signal, an address signal, and a read / write command according to the read instruction;

[0044] According to the address signal and the read / write command, read the image data from the DDR particles through the DDR physical layer, and write the read image data into the display module according to the write address signal;

[0045] Restore the image data from the single-edge image data format to the double-edge image data format, and output the rotated image data in YUV422 format.

[0046] The high-definition image rotation system and method based on FPGA provided by the present invention include a receiving module, a display module, and a control module; the receiving module is used to receive and store image data in YUV422 format, and parse the image data to obtain a write instruction and image coordinate information; the display module is used to generate a read instruction according to the display information and the image coordinate information, and output the rotated image data in YUV422 format; the control module is used to read the image data stored in the receiving module according to the write instruction, and store the image data in the DDR particles in a preset storage manner, and is also used to read the image data stored in the DDR particles to the display module in a preset reading manner according to the read instruction. By using the low-speed image data in YUV422 format and caching it in the DDR, not only can the input image data be greatly reduced, but also the image data can correspond to the bit width of the DDR particles, maximizing the use of the DDR space, improving the processing efficiency of image rotation, and solving the problem of how to improve the image rotation display efficiency without occupying too many resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a structural block diagram of the high-definition image rotation system based on FPGA provided in this embodiment;

[0048] Figure 2 It is a structural schematic diagram of the receiving module provided in this embodiment;

[0049] Figure 3 It is a structural schematic diagram of the image acquisition unit provided in this embodiment;

[0050] Figure 4Schematic diagram of the display module provided in this embodiment;

[0051] Figure 5 Schematic diagram of the image output unit provided in this embodiment;

[0052] Figure 6 Schematic diagram of the control module provided in this embodiment;

[0053] Figure 7 Flowchart of the high-definition image rotation method based on FPGA provided in this embodiment;

[0054] Figure 8 Schematic diagram of the connection of each module unit in the high-definition image rotation system based on FPGA provided in this embodiment;

[0055] Figure 9 Schematic diagram of the writing format of image data in the DDR particles provided in this embodiment;

[0056] Figure 10 Schematic diagram of the reading format of image data in the DDR particles provided in this embodiment;

[0057] Figure 11 Schematic diagram of the structure of writing 8 columns of data into one RAM provided in this embodiment;

[0058] Figure 12 Schematic diagram of the storage method of image data in the output storage unit provided in this embodiment. Detailed implementation manners

[0059] The following further elaborates on the high-definition image rotation system and method based on FPGA proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the accompanying drawings need to show different focuses and sometimes use different scales.

[0060] It should be noted that the "first", "second", etc. in the description, claims and drawings of the present invention are used to distinguish similar objects, so as to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that such structures can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any of their variations are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0061] To clearly illustrate the implementation scheme of the transceiver delay calibration system and method provided in this embodiment, the technical terms involved in this embodiment are explained as follows:

[0062] ASIC: Application Specific Integrated Circuit, an application-specific integrated circuit;

[0063] FPGA: Field Programmable Gate Array, a field-programmable gate array;

[0064] DDR SDRAM: Double Data Rate Synchronous Dynamic Random Access Memory, double data rate synchronous dynamic random access memory, abbreviated as DDR;

[0065] IDDR: input double-data-rate, input double data rate;

[0066] ODDR: output double-data-rate, output double data rate;

[0067] MC: Memory Controller, a memory controller;

[0068] PHY: Physical Layer, the physical layer;

[0069] FIFO: First Input First Output, first in first out;

[0070] RAM: Random Access Memory, random access memory;

[0071] SRAM: Static Random-Access Memory, static random access memory;

[0072] RGB: Read Green Blue, red, green, and blue primary colors;

[0073] YUV: YCbCr, a color encoding based on luminance and chrominance;

[0074] CMD: Command, a command;

[0075] BANK: a block in DDR;

[0076] TTL: Transistor Transistor Logic, a level standard;

[0077] HDMI: High Definition Multimedia Interface, a high-definition multimedia interface;

[0078] DE: A single-bit synchronization signal for image display, indicating the valid display part of the image;

[0079] HS: A single-bit synchronization signal for image display, indicating the starting point of each line of the image;

[0080] VS: A single-bit synchronization signal for image display, indicating the starting flag of each frame of the image.

[0081] This embodiment provides a high-definition image rotation system based on FPGA, as Figure 1 shown, including a receiving module, a display module, and a control module;

[0082] The receiving module is used to receive and store image data in YUV422 format, and parse the image data to obtain a write instruction and image coordinate information; the display module is used to generate a read instruction according to the display information and image coordinate information, and output the rotated image data in YUV422 format; the control module is used to read the image data stored in the receiving module according to the write instruction, and store the image data in the DDR particles in a preset storage manner, and is also used to read the image data stored in the DDR particles in a preset reading manner to the display module.

[0083] The high-definition image rotation system based on FPGA provided by this embodiment, by using low-speed image data in YUV422 format and caching it in DDR, compared with the conventionally used YUV444 format image data, the input image data is greatly reduced, and it can also make the image data correspond to the bit width of the DDR particles, maximizing the use of DDR space and improving the processing efficiency of image rotation; designed based on FPGA, it can flexibly set the implementation of each functional unit, replace the existing SRAM solution, effectively reduce the cost, and solve the problem of how to improve the image rotation display efficiency without occupying too many resources.

[0084] Further, in this embodiment, as Figure 2 shown, the receiving module includes an image acquisition unit, a write FIFO unit, and an input storage unit. The image acquisition unit is used to receive image data in YUV422 format and parse the image data to obtain a write instruction and image coordinate information; the write FIFO unit is used to store the write instruction; the input storage unit is used to store image data in YUV422 format.

[0085] Specifically, in this embodiment, the image acquisition unit includes an IDDR sub-unit, a splicing sub-unit, a write storage address generation sub-unit, a coordinate generation sub-unit, and a frame start sub-unit.

[0086] Among them, as Figure 3 shown, the IDDR sub-unit is used to receive the image data rx_ttl[31:0] in YUV422 format. This image data is dual-edge image data. The IDDR sub-unit converts the dual-edge image data rx_ttl[31:0] into two single-edge image data p[31:0] and n[31:0]; the splicing sub-unit is used to splice the two-way single-edge sub-image data output by the IDDR sub-unit to obtain single-edge image data rx_data[63:0]; the write storage address generation sub-unit is used to receive the line synchronization signal rx_rtl_de and generate a write enable signal rx_en and a write address signal rx_waddr; the coordinate generation sub-unit is used to receive the line start signal rx_rtl_hs and generate image coordinate information, and the image coordinate information includes image row coordinate information cnt_x and image column coordinate information cnt_y; the frame start sub-unit is used to receive the frame start signal rx_rtl_vs and generate a frame information frame; the write instruction includes a write enable signal, a write address signal, image row coordinate information, and frame information.

[0087] In practical applications, considering that the externally input image data is usually dual-edge image data, therefore, through the IDDR core, the dual-edge image data can be converted into two-way single-edge image data, and then spliced to realize the conversion of the input dual-edge clock 32-bit data into single-edge clock 64-bit data.

[0088] The write storage address generation sub-unit uses the line synchronization signal rx_rtl_de to generate a write enable signal rx_en and a write address signal rx_waddr, and accumulates the write address signal rx_waddr according to the rising edge of the input clock, so as to realize the sequential storage of image data in the input storage unit; at the same time, the write storage address generation sub-unit also generates a line synchronization flag signal de_flag and provides the line synchronization flag signal de_flag to the coordinate generation sub-unit.

[0089] The frame start sub-unit samples the input frame start signal rx_rtl_vs through a clock to obtain a frame start flag signal vs_flag, and controls the frame signal frame to increment by 1 after each frame start flag signal vs_flag; at the same time, the frame start flag signal vs_flag is also provided to the coordinate generation sub-unit.

[0090] The coordinate generation subunit receives the row start signal rx_rtl_hs, and relocates the coordinate starting point by using the frame start flag signal vs_flag and the line synchronization flag signal de_flag, and generates the image coordinate information cnt_x and cnt_y.

[0091] Furthermore, in order to ensure that the image data can be effectively stored and enable the subsequent control module to read it in a certain order, in this embodiment, the storage space of the input storage unit is 2 times the width of the maximum input image.

[0092] In a specific embodiment, the input storage unit can be a RAM, and its storage length is 8192. In this way, it can be compatible with the caching of image data of 4K@60Hz and below, meeting the existing image display requirements.

[0093] Moreover, the image data is stored in the input storage unit in a ping-pong manner and read from the input storage unit in a ping-pong manner to maximize the data read / write efficiency.

[0094] Furthermore, in this embodiment, the write FIFO unit stores the write instructions and image coordinate information output by the image acquisition unit, specifically including frame information, row coordinate information, etc. The write FIFO unit can also output a write empty signal rx_empty to inform the control module that there is new image data to be read.

[0095] Furthermore, in this embodiment, as Figure 4 shown, the display module includes an output storage unit, a read FIFO unit, and an image output unit. The output storage unit is used to store the image data read from the DDR particles; the image output unit is used to obtain the display information and image coordinate information, generate read instructions according to the display information and image coordinate information, and is also used to output the image data stored in the output storage unit and generate a synchronization code to output the rotated image data in YUV422 format; the read FIFO unit is used to store the read instructions.

[0096] Specifically, in this embodiment, the image output unit includes a read instruction generation subunit, a synchronization code generation subunit, and an ODDR subunit.

[0097] Among them, as Figure 5As shown, the read instruction generation subunit is used to generate a read instruction according to the display information and the image coordinate information, where the read instruction includes a FIFO enable signal fifo_en and a FIFO data signal fifo_data; the synchronization code generation subunit is used to generate a synchronization code according to the image coordinate information, where the synchronization code includes a line synchronization signal de, a line start signal hs, and a frame start signal vs; the ODDR subunit is used to restore the image data (including p[31:0] and n[31:0]) stored in the output storage unit from single-edge image data to double-edge image data, so as to output high-definition rotated image data HDMI in the YUV422 format.

[0098] In practical applications, considering that during the image rotation process, the reading and writing of image data are both performed with single-edge image data. Therefore, in order to output double-edge image data, an ODDR core can be used to restore the single-edge image data to double-edge image data.

[0099] Furthermore, in order to rotate the output image compared to the original input image and be able to efficiently read out the image data for display, in this embodiment, the image data read from the DDR particles is sequentially stored in the output storage unit.

[0100] In a specific embodiment, the output storage unit can be a RAM, and it can be divided into multiple storage spaces for correspondingly storing the corresponding image data, thereby improving the image display efficiency.

[0101] Furthermore, in this embodiment, the read FIFO unit stores the read instruction output by the image output unit. The read FIFO unit can also output a read empty signal tx_empty, which is used to inform the control module that the display module is in an idle state and new image data can be read.

[0102] Furthermore, in this embodiment, as Figure 6 shown, the control module includes a read-write arbitration unit, a status controller, a control signal generation unit, a command address generation unit, and a DDR physical layer.

[0103] Among them, the read-write arbitration unit is used to receive a write instruction and a read instruction, and start the status controller according to the write instruction or the read instruction in a first-in-first-out arbitration manner. Specifically, the write instruction is obtained through the write FIFO unit of the receiving module, and the read instruction is obtained through the read FIFO unit of the display module.

[0104] And, the status controller is used to generate an address signal and a read-write command for controlling the DDR physical layer according to the write instruction or the read instruction.

[0105] Moreover, the control signal generation unit is configured to generate a read address signal according to a write instruction and generate a write address signal according to a read instruction. Specifically, the control signal generation unit includes a read signal generation unit and a write signal generation unit. The read signal generation unit is configured to generate a read address signal, and the write signal generation unit is configured to generate a write address signal.

[0106] Moreover, the command address generation unit is configured to send the image data stored in the receiving module to the DDR chip through the DDR physical layer by using the address signal, the read / write command, and the read address signal; and is further configured to read the image data from the DDR chip through the DDR physical layer according to the address signal, the read / write command, and the write address signal and write the image data into the display module.

[0107] The overall write process of the control module is generally as follows: The read / write arbitration unit controls the state controller to start according to the write instruction; the state controller correspondingly generates the address signal and the write command necessary for controlling the DDR physical layer. The read signal generation unit generates a read address signal and issues it to the input storage unit in the receiving module, so as to read the image data in the input storage unit and transfer it to the command address generation unit; the command address generation unit writes the obtained image data into the DDR chip through the DDR physical layer according to the address signal and the write command.

[0108] The overall read process of the storage control unit is generally as follows: The read / write arbitration unit controls the state controller to start according to the read instruction; the state controller correspondingly generates the address signal and the read command necessary for controlling the DDR physical layer. The command address generation unit reads the image data in the DDR chip through the DDR physical layer according to the address signal and the read command and provides it to the write signal generation unit; the write signal generation unit generates a write address signal, and the command address generation unit writes the read data into the output storage unit in the display module according to the write address signal.

[0109] The high-definition image rotation system based on FPGA provided in this embodiment converts the signal input through HDMI into a low-speed TTL signal in YUV422 format by using an external dedicated chip and then caches it in the DDR, so that the image data input to the FPGA is reduced by 1 / 3 compared with the original YUV444 format; moreover, the common bit width of the DDR chip is 16 bits, which exactly corresponds to the 16-bit data in the YUV422 format, making the most of the space of the DDR itself; in addition, by writing the input image data into the DDR in sequence each time and then storing the read image data to be rotated in the output storage unit in sequence, not only the read and write operations on the DDR are achieved with the highest efficiency, but also the efficient display of the rotated image is realized, thus replacing the original high-cost SRAM solution and solving the problem of high-efficiency read and write required for image rotation.

[0110] This embodiment also provides an FPGA-based high-definition image rotation method, which is applied to the FPGA-based high-definition image rotation system described above, as Figure 7 shown. The high-definition image rotation method includes:

[0111] S1. Receive and store image data in YUV422 format;

[0112] S2. Analyze the image data to obtain a write instruction and image coordinate information;

[0113] S3. Read the image data stored in the receiving module according to the write instruction, and store the image data in the DDR particles in a preset storage manner;

[0114] S4. Generate a read instruction according to the display information and the image coordinate information;

[0115] S5. Read out the image data stored in the DDR particles in a preset reading manner according to the read instruction, so as to output rotated image data in YUV422 format.

[0116] The FPGA-based high-definition image rotation method provided by this embodiment uses image data in low-speed YUV422 format and caches it in the DDR. This not only greatly reduces the input image data, but also enables the image data to correspond to the bit width of the DDR particles, making the most of the DDR space and improving the processing efficiency of image rotation. By reading and writing the image data in sequence, the efficient rotation display of the image data is realized, and the problem of how to improve the image rotation display efficiency without occupying too many resources is solved.

[0117] Next, refer to Figure 8 to describe in detail the implementation process of the FPGA-based high-definition image rotation method provided by this embodiment.

[0118] Specifically, in this embodiment, in step S1, receive and store image data in YUV422 format.

[0119] In practical applications, the input image data can be image video streams of specifications such as 1k@60Hz, 2k@60Hz, 4K@60Hz, etc. In addition, an external dedicated chip can be used to convert the original image video data signal in other formats into a TTL signal in YUV422 format, and the converted TTL signal is used as the image data and input into the receiving module of the FPGA-based high-definition image rotation system provided by this embodiment. Specifically, the image acquisition unit of the receiving module receives the image data in YUV422 format, and the input storage unit stores the image data in YUV422 format.

[0120] Further, in this embodiment, the method for parsing the image data to obtain the write instruction and the image coordinate information in step S2 includes:

[0121] S21, converting the received image data in YUV422 format from the double-edge image data format to two single-edge sub-image data. Specifically, in this embodiment, the IDDR sub-unit in the image acquisition unit converts the image data from the double-edge image data format to two single-edge sub-image data.

[0122] S22, splicing the two single-edge sub-image data to obtain one single-edge image data. Specifically, in this embodiment, the splicing sub-unit in the image acquisition unit splices the image data and outputs the single-edge image data rx_data.

[0123] At this time, the single-edge image data rx_data and its input storage address information rx_waddr are stored in the input storage unit together.

[0124] S23, receiving the line synchronization signal and generating a write address signal. Specifically, in this embodiment, the write storage address generation sub-unit in the image acquisition unit receives the line synchronization signal rx_rtl_de and generates a write enable signal rx_en and a write address signal rx_waddr.

[0125] S24, receiving the line start signal and generating the image coordinate information, where the image coordinate information includes the image row coordinate information and the image column coordinate information. Specifically, in this embodiment, the coordinate generation sub-unit in the image acquisition unit receives the line start signal rx_rtl_hs and generates the image coordinate information, where the image coordinate information includes the image row coordinate information cnt_x and the image column coordinate information cnt_y.

[0126] S25, receiving the frame start signal and generating the frame information. Specifically, in this embodiment, the frame start sub-unit in the image acquisition unit receives the frame start signal rx_rtl_vs and generates the frame information frame.

[0127] At this time, the write enable signal rx_en, the write address signal rx_waddr, the image row coordinate information cnt_x, the image column coordinate information cnt_y, the frame information frame, etc. are stored in the write FIFO unit.

[0128] Further, in this embodiment, the method for reading the image data stored in the receiving module according to the write instruction and storing the image data in the DDR particles in a preset storage manner in step S3 includes:

[0129] S31. Receive a write command. Specifically, first, a write FIFO unit generates a write-empty signal rx_empty and inputs it into the read-write arbitration unit of the control module, so that the read-write arbitration unit knows that there is new image data to be read. At the same time, the write FIFO unit also inputs the first-in-first-out write data signal fifo_wdata into the read-write arbitration unit, causing the read-write arbitration unit to control the status controller to start.

[0130] S32. According to the first-in-first-out arbitration method, generate a read address signal, an address signal, and a read-write command based on the write command. Specifically, after the status controller starts, it generates the address signal and the read-write command necessary to control the DDR physical layer according to the write command. At this time, the read-write command is specifically a write command. In addition, the read signal generation unit generates a read address signal raddr according to the write command.

[0131] S33. Read the image data from the receiving module according to the read address signal, and send the read image data to the DDR particle through the DDR physical layer according to the address signal and the read-write command. Specifically, read the corresponding image data wdata[127:0] from the input storage unit according to the read address signal raddr and send it to the command address generation unit. Then, the command address generation unit writes the obtained image data into the DDR particle through the DDR physical layer according to the address signal and the write command.

[0132] The DDR particle includes a plurality of storage areas, and each of the storage areas has a plurality of storage blocks. During the process of writing image data into the DDR particle, the command address generation unit controls the image data to store the image data of the same row in different storage blocks of different storage areas in units of rows, and the storage start position of the image data of the latter row is one storage area after the storage start position of the image data of the previous row, that is, Figure 9 Stored in the DDR in the shown format. Specifically, to meet the display format of 4K images, in this embodiment, the DDR particle includes 8 storage areas (banks), and each storage area has 4096 storage blocks (blocks). The data is stored in each storage block in units of rows.

[0133] In practical applications, since DDR3 mostly stores data in bursts of 8 pixels per command, that is, with a 128-bit width, the storage of the first row of data of a landscape image is as Figure 9The flow direction of the left arrow in the figure. Among them, block1-1 means storing the first 8 data of the first row of the input image as the first group, and continuously storing 8 pixel values in burst mode at this address; similarly, block1-2 means storing the second group of 8 data of the first row, that is, the data of pixels 9 to 16; until after storing block1-8, the data storage returns to the space of block1-1, and continues after the address of the first storage, and stores the image data of the subsequent row. In this way, each time a group of data is sent, it is stored between different memory banks (banks), achieving the highest efficiency in the DDR write direction.

[0134] After writing a row of image data, write the image data of the second row. The storage method is different from the previous row, and the starting point needs to be delayed by one memory bank (bank) compared to the previous row. As shown by the data storage flow direction of the right arrow in 9 in the figure, the starting point is block2-1 in bank2, which means storing the first group of data of the second row of the image. Then, block2-2 in bank3 stores the second group of data of the second row of the image, and so on, storing up to 4K, that is, 4096 rows of data.

[0135] Further, in this embodiment, step S4, the method for generating a read instruction according to the display information and the image coordinate information includes:

[0136] S41, generating a read instruction according to the display information and the image coordinate information. Specifically, in this embodiment, the read instruction is generated by the read instruction generation subunit in the image output unit of the display module, where the read instruction includes the FIFO enable signal fifo_en and the FIFO data signal fifo_data.

[0137] S42, generating a synchronization code according to the image coordinate information. Specifically, in this embodiment, the synchronization code is generated by the synchronization code generation subunit in the image output unit of the display module according to the image coordinate information, where the synchronization code includes the line synchronization signal de, the line start signal hs, and the frame start signal vs.

[0138] Further, in this embodiment, step S5, the method for reading out the image data stored in the DDR chip according to the read instruction in a preset reading manner to output the rotated image data in YUV422 format includes:

[0139] S51, receiving the read instruction. Specifically, first, the read FIFO unit generates a read empty signal tx_empty and inputs it to the read-write arbitration unit of the control module, so that the read-write arbitration unit can know that new image data can be read; at the same time, the read FIFO unit also inputs the first-in-first-out read data signal fifo_rdata to the read-write arbitration unit, so that the read-write arbitration unit controls the state controller to start.

[0140] S52, according to the first-in-first-out arbitration method, generate a write address signal, an address signal, and a read / write command according to the read instruction. Specifically, after the status controller is started, generate the necessary address signal and read / write command for controlling the DDR physical layer according to the read instruction. At this time, the read / write command is specifically a read command; and, the write signal generation unit generates a write address signal waddr according to the read instruction.

[0141] S53, according to the address signal and the read / write command, read the image data from the DDR particles through the DDR physical layer, and write the read image data into the display module according to the write address signal. Specifically, according to the address signal and the read command, read the corresponding image data rdata[127:0] from the DDR particles through the DDR physical layer, and then the command address generation unit writes the obtained image data into the output storage unit of the display module according to the write address signal waddr.

[0142] During the process of reading the image data from the DDR particles, in order to realize the 90-degree rotation display of the input image, it is necessary to read the horizontally stored data vertically, that is, the first row of data read is the first column of data written. Since in this embodiment, considering the low read efficiency of the DDR in the same bank during the writing process, the image data is written into different banks each time. Therefore, when reading the image data, it is also necessary to read different banks each time to improve the read efficiency; at the same time, since the frame jump signal is used to store the image data, the maximum of 2 frames of image data can be stored. When reading, it is necessary to have a frame of image data cached in the DDR3 before the read operation can be executed.

[0143] In practical applications, as Figure 10 shown, the first 9 rows of data (block9) in a frame of image stored horizontally in the DDR particles are displayed. In order to maximize the efficiency of the DDR read / write operation, the starting data of the first row of the vertical screen display is in the first block of bank1, that is, block1-1, and then the second block of bank2, that is, block2-1. The first 8 columns of data of the horizontal screen are read in sequence to obtain the first 8 rows of data after rotation. The read bank sequence is as shown by the arrow in the figure, block1-1, block2-1, block3-1, block4-1, block5-1, block6-1, block7-1, block8-1, block9-1..., after reading 8 banks, it returns to bank1 and continues to read the address data of the next row. The read data is written into the RAM group in the output storage unit according to the indication signal of the write signal generation unit.

[0144] Corresponding to the readout method, considering that at least 8 columns of data before the horizontal stored data need to be read for the rotated longitudinal data to be read out, if 8 columns and the maximum 4k row data are read at one time and all the data is written into a group of RAMs, the difficulty of timing convergence will increase. Therefore, in this embodiment, there are 8 groups of RAMs in the output storage unit to store 8 columns of data respectively, thus effectively avoiding the timing problem caused by too large RAM.

[0145] As Figure 11 shown, it is a schematic structural diagram of writing 8 columns of data into one RAM. The RAM is divided into high and low address bits, each accounting for half of the entire RAM. This method can conveniently implement the ping-pong operation. For the 8 columns of data before rotation read out, through the write signal generation unit, they are stored into the RAM in units of columns respectively. As Figure 12 shown, the data stored in the first RAM1 are the first column data of the landscape image in sequence, and the data stored in the second RAM2 are the second column data of the landscape image in sequence. The ping-pong storage method is adopted to realize the alternate storage of data. When the data is stored in the low addresses of 8 groups of RAMs, the loop jumps to the high address of the first group of RAM1 to continue caching until the last row of data for vertical display is cached.

[0146] S54, restore the image data from the single-edge image data format to the double-edge image data format, and output the rotated image data in YUV422 format. Specifically, in this embodiment, the ODDR sub-unit in the image output unit restores the image data (including p[31:0] and n[31:0]) from the single-edge image data to the double-edge image data to output the high-definition rotated image data HDMI in YUV422 format.

[0147] The high-definition image rotation method based on FPGA provided in this embodiment effectively improves the read and write efficiency of the DDR particles by improving the write and read methods of the image data in the DDR particles, writing the image data into different banks and correspondingly reading from different banks, meeting the high frame rate requirements of image rotation display.

[0148] The high-definition image rotation method based on FPGA provided in this embodiment makes full use of the burst characteristics of the DDR, transmits 8 data together, and improves the data transmission efficiency; at the same time, correspondingly adopts 8 groups of output RAMs to store the 8 columns of data before rotation output respectively, which not only reduces the cache pressure, but also makes the timing of the entire system easier to converge.

[0149] In practical applications, if the FPGA system only implements the rotation of image data, the DDR particle refresh function in the microcontroller MC can be not used, and only the DFI interface of the DDR physical layer is used to implement the read and write of image data, thus saving the reaction time of the entire system and accelerating the read and write efficiency.

[0150] It should be noted that the embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. In addition, the different parts among the embodiments can also be combined and used. The present invention does not make any limitations in this regard.

[0151] The high-definition image rotation system and method based on FPGA provided in this embodiment include a receiving module, a display module, and a control module; the receiving module is used to receive and store image data in the YUV422 format, and parse the image data to obtain a write instruction and image coordinate information; the display module is used to generate a read instruction according to the display information and the image coordinate information, and output the rotated image data in the YUV422 format; the control module is used to read the image data stored in the receiving module according to the write instruction, and store the image data in the DDR particles in a preset storage manner, and is also used to read the image data stored in the DDR particles in a preset reading manner to the display module according to the read instruction. By using the image data in the low-speed YUV422 format and caching it in the DDR, not only is the input image data greatly reduced, but also the image data can correspond to the bit width of the DDR particles, maximizing the use of the DDR space and improving the processing efficiency of image rotation, and solving the problem of how to improve the image rotation display efficiency without occupying too many resources.

[0152] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure are within the protection scope of the claims.

Claims

1. A high-definition image rotation system based on FPGA, characterized in that, It includes a receiving module, a display module, and a control module; The receiving module is used to receive and store image data in YUV422 format, and parse the image data to obtain a write instruction and image coordinate information; the display module is used to generate a read instruction according to the display information and the image coordinate information, and output the rotated image data in YUV422 format; the control module is used to read the image data stored in the receiving module according to the write instruction, and store the image data in the DDR particles in a preset storage mode, and is also used to read the image data stored in the DDR particles in a preset reading mode to the display module according to the read instruction; the control module includes a read-write arbitration unit, a status controller, a control signal generation unit, a command address generation unit, and a DDR physical layer; the read-write arbitration unit is used to receive the write instruction and the read instruction, and start the status controller according to the write instruction or the read instruction in a first-in-first-out arbitration manner; the status controller is used to generate an address signal and a read-write command for controlling the DDR physical layer according to the write instruction or the read instruction; the control signal generation unit is used to generate a read address signal according to the write instruction; and is also used to generate a write address signal according to the read instruction; the command address generation unit is used to send the image data stored in the receiving module to the DDR particles through the DDR physical layer by using the address signal, the read-write command, and the read address signal; and is also used to read the image data from the DDR particles and write it into the display module through the DDR physical layer by using the address signal, the read-write command, and the write address signal; The DDR particles include multiple storage areas, and each storage area has multiple storage blocks; when the image data is stored in the DDR particles, the image data of the same row is sequentially stored in different storage blocks of different storage areas in units of rows, and the storage start position of the image data of the next row is one storage area behind the storage start position of the image data of the previous row.

2. The high-definition image rotation system based on FPGA according to claim 1, characterized in that The receiving module includes an image acquisition unit, a write FIFO unit, and an input storage unit; The image acquisition unit is used to receive the image data in YUV422 format, and parse the image data to obtain a write instruction and image coordinate information; the write FIFO unit is used to store the write instruction; the input storage unit is used to store the image data in YUV422 format.

3. The high-definition image rotation system based on FPGA according to claim 2, wherein, The image acquisition unit includes an IDDR subunit, a splicing subunit, a write storage address generation subunit, a coordinate generation subunit, and a frame start subunit; The IDDR sub-unit is used to receive image data in YUV422 format and convert the image data from double-edge image data into two single-edge sub-image data; the splicing sub-unit is used to splice the two-way single-edge sub-image data output by the IDDR sub-unit to obtain one-way single-edge image data; the write storage address generation sub-unit is used to receive a line synchronization signal and generate a write enable signal and a write address signal; the coordinate generation sub-unit is used to receive a line start signal and generate image coordinate information, and the image coordinate information includes image line coordinate information and image column coordinate information; the frame start sub-unit is used to receive a frame start signal and generate frame information; the write instruction includes a write enable signal, a write address signal, image line coordinate information, and frame information.

4. The high-definition image rotation system based on FPGA according to claim 2, characterized in that The storage space of the input storage unit is 2 times the width of the maximum input image; the image data is stored in the input storage unit in a ping-pong manner and read out from the input storage unit in a ping-pong manner.

5. The high-definition image rotation system based on FPGA according to claim 1, wherein, The display module includes an output storage unit, a read FIFO unit, and an image output unit; The output storage unit is used to store the image data read from the DDR particle; the image output unit is used to obtain display information and image coordinate information, generate a read instruction according to the display information and the image coordinate information, and is also used to output the image data stored in the output storage unit and generate a synchronization code to output rotated image data in YUV422 format; the read FIFO unit is used to store the read instruction.

6. The high-definition image rotation system based on FPGA according to claim 5, characterized in that, The image output unit includes a read instruction generation sub-unit, a synchronization code generation sub-unit, and an ODDR sub-unit; The read instruction generation sub-unit is used to generate a read instruction according to the display information and the image coordinate information; the synchronization code generation sub-unit is used to generate a synchronization code according to the image coordinate information; the ODDR sub-unit is used to restore the image data stored in the output storage unit from single-edge image data to double-edge image data to output rotated image data in YUV422 format.

7. A high-definition image rotation method based on FPGA, which is applied to the high-definition image rotation system based on FPGA according to any one of claims 1 to 6, and is characterized in that, The high-definition image rotation method includes: Receiving and storing image data in YUV422 format; Parsing the image data to obtain a write instruction and image coordinate information; Reading the image data stored in the receiving module according to the write instruction and storing the image data into the DDR particle in a preset storage mode; Generating a read instruction according to the display information and the image coordinate information; Reading out the image data stored in the DDR particle according to the read instruction in a preset reading mode to output rotated image data in YUV422 format.

8. The FPGA-based high-definition image rotation method according to claim 7, characterized in that, The method for parsing the image data to obtain a write instruction and image coordinate information includes: Converting the received YUV422 format image data from double-edge image data format into two-way single-edge sub-image data; Splicing the two-way single-edge sub-image data to obtain one-way single-edge image data; Receiving a line synchronization signal and generating a write enable signal and a write address signal; Receiving a line start signal and generating image coordinate information, and the image coordinate information includes image line coordinate information and image column coordinate information; Receiving a frame start signal and generating frame information; Among them, the write instruction includes a write enable signal, a write address signal, image line coordinate information, and frame information.

9. The method for rotating high-definition images based on FPGA according to claim 7, characterized in that, The method for reading the image data stored in the receiving module according to the write instruction and storing the image data in the DDR particles in a preset storage manner includes: Receiving a write instruction; According to the first-in-first-out arbitration method, generating a read address signal, an address signal, and a read / write command according to the write instruction; According to the read address signal, reading the image data from the receiving module, and according to the address signal and the read / write command, sending the read image data to the DDR particles through the DDR physical layer.

10. The high-definition image rotation method based on FPGA according to claim 7, characterized in that The method for generating a read instruction according to the display information and the image coordinate information includes: Generating a read instruction according to the display information and the image coordinate information; Generating a synchronization code according to the image coordinate information.

11. The high-definition image rotation method based on FPGA according to claim 7, characterized in that, The method for reading the image data stored in the DDR particles in a preset reading manner according to the read instruction to output rotated image data in the YUV422 format includes: Receiving a read instruction; According to the first-in-first-out arbitration method, generating a write address signal, an address signal, and a read / write command according to the read instruction; According to the address signal and the read / write command, reading the image data from the DDR particles through the DDR physical layer, and according to the write address signal, writing the read image data into the display module; Restoring the image data from the single-edge image data format to the double-edge image data format, and outputting the rotated image data in the YUV422 format.

Images