Short wave array signal phase control synchronization method based on pulse programming

Abstract

The invention discloses a short wave array signal phase control synchronization method based on pulse programming, which can eliminate errors caused by layout and wiring delay, clock skew and clock jitter through pulse programming and realize accurate array signal synchronization. The main implementation process comprises the following steps: 1) synchronous clock generation: obtaining N + 1 paths of stable and synchronous main clocks through input clock processing, main clock distribution, main clock deviation elimination, driving and buffering, and then generating N + 1 paths of synchronous sub-clocks with different frequencies through clock derivation; 2) programmable pulse generation: after receiving an external signal generation instruction, generating one path of pulse according to a synchronous main clock, and then generating pulses of other main clocks and sub-clocks through pulse programming for synchronous triggering of array signal generation; (3) array signal generation: under the trigger of the sub-clock pulse, the baseband signal is acquired and processed through a modulation source, and a low-rate baseband signal is generated; under the triggering of a main clock pulse, a high-rate baseband signal is obtained through baseband signal processing on a low-rate baseband signal, a carrier signal corresponding to an initial phase is generated according to an array output phase requirement, and quadrature modulation, amplitude adjustment and digital-to-analog conversion are carried out to obtain an array signal for transmission.

Description

Technical Field

[0001] The invention relates to the technical field of shortwave signal processing, and in particular to a shortwave array signal phase-controlled synchronization method based on pulse programming. Background Art

[0002] Shortwave communication occupies an irreplaceable position in communication technology with its wide coverage, long transmission distance, low communication cost and strong anti-interference ability. It is even the only effective communication method in harsh environments and is widely used in aviation, navigation, meteorology, emergency rescue and other fields.

[0003] In shortwave communications, some scenarios have long communication distances and huge power requirements. Relying on a single power amplifier and antenna radiation is not only difficult and costly to achieve, but also difficult to achieve good results. Therefore, a more economical and practical shortwave phased antenna array synthesis technology was born, that is, multiple power amplifiers and antenna arrays achieve spatial power synthesis of transmitted energy in a specific direction by changing the phase of adjacent array elements, thereby achieving a higher equivalent radiated power in the target area. In order to achieve efficient power synthesis, it is necessary to provide the shortwave array system with multi-channel array signals whose amplitude and phase can be precisely controlled according to the requirements of array synthesis. The precise synchronization of multi-channel array signals is the basis for precise control of phase.

[0004] Traditional signal sources are mostly single-channel outputs, and the signals between multiple signal sources are unrelated, making it impossible to achieve signal synchronization. Therefore, the array synthesis system needs to use a dedicated array synthesis excitation signal generation device. In the process of generating array synthesis excitation signals, the direct method or feedback method is currently mainly used to achieve synchronization between multiple array signals. The former has the advantage of being able to quickly generate synchronized array signals, but the disadvantage is that it is susceptible to layout and wiring, clock offset, clock jitter and other factors, resulting in low synchronization accuracy; the latter has the advantage of being able to continuously update the iterative array signal phase through continuous feedback sampling to achieve high-precision synchronization signal generation, but the disadvantage is that it takes a long time to achieve synchronization between array signals.

[0005] How to provide the shortwave array system with multi-channel array signals whose amplitude and phase can be precisely controlled according to the requirements of array synthesis, and eliminate the problem of low array signal synchronization accuracy caused by adverse factors such as clock jitter, is a problem that needs to be solved at present. Summary of the invention

[0006] The purpose of the present invention is to provide a short-wave array signal phase-controlled synchronization method based on pulse programming, which can eliminate the errors caused by layout and wiring delay, clock offset and clock jitter through pulse programming when generating multi-channel array signals by direct method, so as to achieve accurate array signal synchronization.

[0007] In a first aspect of an embodiment of the present invention, a shortwave array signal phase-controlled synchronization method based on pulse programming is disclosed, which is implemented by using a synchronization signal FPGA and an array signal FPGA, and includes:

[0008] S1, using the synchronization signal FPGA to generate N+1 first master clock signals; N is the number of array signal FPGAs;

[0009] S2, using the array signal FPGA, processing the N+1 first master clock signals to obtain a synchronous master clock signal and a sub-clock signal group corresponding to each synchronous master clock signal;

[0010] S3, based on the synchronous master clock signal and the sub-clock signal group corresponding to each synchronous master clock signal, using the synchronous signal FPGA, generating a pulse group for array signal triggering operation;

[0011] S4, using the pulse group as an operation trigger signal, and using the array signal FPGA to process the modulation source signal, the carrier signal frequency information, and the carrier signal phase information to obtain the digital radio frequency signal required by each shortwave array of the shortwave array system;

[0012] S5, performing digital-to-analog conversion processing on the digital radio frequency signal required by the shortwave array system to obtain a signal to be transmitted by the shortwave array system.

[0013] The method of using the synchronization signal FPGA to generate N+1 master clock signals includes:

[0014] S11, using a preset dedicated global clock pin of the synchronization signal FPGA to receive an original clock signal;

[0015] S12, buffering the original clock signal, and processing the buffered original clock signal using the global high-speed network of the synchronization signal FPGA to obtain a master clock signal;

[0016] S13, using the clock distribution network of the synchronization signal FPGA, fan out the master clock signal into N+1 first master clock signals, input N of the first master clock signals into N array signal FPGAs respectively, and input the remaining first master clock signal into the programmable pulse generation module of the synchronization signal FPGA.

[0017] The method of using the array signal FPGA to process the N+1 first master clock signals to obtain a synchronous master clock signal and a sub-clock signal group corresponding to each synchronous master clock signal includes:

[0018] Using the phase-locked loop of the array signal FPGA, the phase of the N+1 first master clock signals is fine-tuned to obtain N+1 destination FPGA-side master clocks;

[0019] Using the array signal FPGA, the master clock of each destination FPGA end is input into the global clock buffer resource of the array signal FPGA, and a synchronous master clock signal is output;

[0020] By utilizing the clock manager module resources of the array signal FPGA, each synchronous main clock signal is divided and processed to obtain a corresponding sub-clock signal group.

[0021] Each of the synchronous main clock signals corresponds to a sub-clock signal group; each sub-clock signal group includes a first sub-clock signal, a second sub-clock signal, a third sub-clock signal, and a fourth sub-clock signal.

[0022] The method of generating a pulse group for array signal triggering operation based on a synchronous master clock signal and a sub-clock signal group corresponding to each synchronous master clock signal by using a synchronous signal FPGA comprises:

[0023] In the master clock domain, the pulse generator of the synchronization signal FPGA generates the initial pulse;

[0024] Using the synchronization signal FPGA, the initial pulse is processed by combinatorial logic programming to obtain a sub-pulse signal of a sub-clock domain corresponding to each sub-clock signal of the sub-clock signal group; the sub-pulse signal includes a first sub-pulse signal belonging to the first sub-clock domain, a second sub-pulse signal belonging to the second sub-clock domain, a third sub-pulse signal belonging to the third sub-clock domain, and a fourth sub-pulse signal belonging to the fourth sub-clock domain; the first to fourth sub-clock domains are respectively determined by the first to fourth sub-clock signals;

[0025] The initial pulse is subjected to derivative processing to obtain N main pulse signals; the clock domain of the main pulse signal is the main clock domain;

[0026] Performing derivative processing on the sub-pulse signals of each sub-clock domain respectively to obtain N pulse communication signals of each sub-clock domain;

[0027] Using the N main pulse signals and the N pulse communication signals of each sub-clock domain, a pulse group for array signal triggering operation is constructed;

[0028] According to the relative transmission delay between the synchronization signal FPGA and the array signal FPGA, the pulse group used for the array signal trigger operation is pre-programmed with a time delay, and the pulse group after the time delay pre-programming is sent to N array signal FPGAs.

[0029] The combinational logic programming process includes register latching operation, multi-stage D flip-flop operation, and inversion and AND operation.

[0030] The pulse group is used as an operation trigger signal, and the array signal FPGA is used to process the modulation source signal, the carrier signal frequency information and the carrier signal phase information to obtain the digital radio frequency signal required by each shortwave array of the shortwave array system, including:

[0031] S41, using the pulse group as an operation trigger signal, and using the array signal FPGA to process the modulation source signal to obtain a high-rate baseband signal;

[0032] S42, using the pulse group as an operation trigger signal, and using the array signal FPGA to process the carrier signal frequency information and the carrier signal phase information to obtain a carrier signal;

[0033] S43, using the pulse group as an operation trigger signal, modulating the high-rate baseband signal and the carrier signal to obtain a digital radio frequency signal required by each shortwave array of the shortwave array system.

[0034] The pulse group is used as an operation trigger signal, and the array signal FPGA is used to process the modulation source signal to obtain a high-rate baseband signal, including:

[0035] S411, making the array signal FPGA work in the first sub-clock domain, capturing the pulse communication signal of the first sub-clock domain, using the pulse communication signal of the first sub-clock domain to trigger the acquisition, selection, filtering and automatic gain control of the modulation source signal, and obtaining the modulation source data;

[0036] S412, enabling the array signal FPGA to operate in the second sub-clock domain, capturing the pulse communication signal in the second sub-clock domain, and using the pulse communication signal in the second sub-clock domain to trigger the interpolation, filtering and baseband modulation operations of the modulation source data to generate a low-rate baseband signal;

[0037] S413, making the array signal FPGA work in the third sub-clock domain, capturing the pulse communication signal of the third sub-clock domain, and using the pulse communication signal of the third sub-clock domain to trigger the integrated transmission and split extraction processing of multiple baseband signals;

[0038] S414, enables the array signal FPGA to work in the fourth sub-clock domain and the main clock domain, and respectively captures the pulse communication signal and the main pulse signal of the fourth sub-clock domain; utilizes the pulse communication signal and the main pulse signal of the fourth sub-clock domain to respectively trigger the first-level interpolation filtering processing and the second-level interpolation filtering processing of the multi-channel baseband signals, and obtains a high-speed baseband signal.

[0039] The method uses the pulse group as an operation trigger signal, and uses the array signal FPGA to process the carrier signal frequency information and the carrier signal phase information to obtain the carrier signal, including:

[0040] The array signal FPGA is made to work in the main clock domain to capture the main clock domain pulse; the initial phase of the signal required for each shortwave array is determined according to the required carrier signal frequency information and carrier signal phase information; the main clock domain pulse is used to trigger the phase accumulator, so that the phase accumulator generates a carrier signal according to the frequency information and initial phase of the carrier signal.

[0041] The method uses the pulse group as an operation trigger signal to modulate the high-rate baseband signal and the carrier signal to obtain a digital radio frequency signal required by each shortwave array of the shortwave array system, including:

[0042] S431, making the array signal FPGA work in the main clock domain, capturing the main clock domain pulse; using the main clock domain pulse to trigger the orthogonal modulation converter, completing the orthogonal modulation conversion of the high-speed baseband signal and the carrier signal, and generating a digital RF signal with consistent amplitude;

[0043] S432, make the array signal FPGA work in the main clock domain, capture the main clock domain pulse; use the main clock domain pulse to trigger the multiplier, complete the amplitude adjustment of the digital RF signal, and generate the digital RF signal required by each shortwave array of the shortwave array system.

[0044] According to a second aspect of the present invention, a short wave array signal phase control synchronization device based on pulse programming is disclosed, the device comprising:

[0045] A memory storing executable program code;

[0046] a processor coupled to the memory;

[0047] The processor calls the executable program code stored in the memory to execute the shortwave array signal phase-controlled synchronization method based on pulse programming.

[0048] The third aspect of the present invention discloses a computer storable medium storing computer instructions, which, when called by a computer, are used to execute the shortwave array signal phase-controlled synchronization method based on pulse programming.

[0049] According to a fourth aspect of the present invention, an information data processing terminal is disclosed. The information data processing terminal is used to implement the shortwave array signal phase-controlled synchronization method based on pulse programming.

[0050] The beneficial effects of the present invention are:

[0051] The present invention adopts a pulse programming method to realize stable and reliable multi-channel array synchronization signal generation, which can eliminate the influence caused by factors such as wiring delay, clock jitter, clock offset, etc., achieve higher synchronization accuracy, and ensure the synthesis effect of array phase-controlled synthesis. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 It is a principle block diagram of the short wave array signal phase control synchronization method based on pulse programming of the present invention;

[0053] Figure 2 Generates block diagram for synchronous clock;

[0054] Figure 3 It is the principle block diagram of programmable pulse generation;

[0055] Figure 4 This is the error signal diagram that may be caused by factors such as clock jitter;

[0056] Figure 5 This is the error signal diagram after the pulse programming is introduced. DETAILED DESCRIPTION

[0057] In order to better understand the content of the present invention, an embodiment is given here.

[0058] Figure 1 It is a principle block diagram of the short wave array signal phase control synchronization method based on pulse programming of the present invention; Figure 2 Generates block diagram for synchronous clock; Figure 3 It is the principle block diagram of programmable pulse generation; Figure 4 This is the error signal diagram that may be caused by factors such as clock jitter; Figure 5 This is the error signal diagram after the pulse programming is introduced.

[0059] In a first aspect of an embodiment of the present invention, a shortwave array signal phase-controlled synchronization method based on pulse programming is disclosed, which is implemented by using a synchronization signal FPGA and an array signal FPGA, and includes:

[0060] S1, using the synchronization signal FPGA to generate N+1 first master clock signals; N is the number of array signal FPGAs;

[0061] S2, using the array signal FPGA, processing the N+1 first master clock signals to obtain a synchronous master clock signal and a sub-clock signal group corresponding to each synchronous master clock signal;

[0062] S3, based on the synchronous master clock signal and the sub-clock signal group corresponding to each synchronous master clock signal, using the synchronous signal FPGA, generating a pulse group for array signal triggering operation;

[0063] S4, using the pulse group as an operation trigger signal, and using the array signal FPGA to process the modulation source signal, the carrier signal frequency information, and the carrier signal phase information to obtain the digital radio frequency signal required by each shortwave array of the shortwave array system;

[0064] S5, performing digital-to-analog conversion processing on the digital radio frequency signal required by the shortwave array system to obtain a signal to be transmitted by the shortwave array system.

[0065] The synchronization signal FPGA and the array signal FPGA are connected;

[0066] The method of using the synchronization signal FPGA to generate N+1 master clock signals includes:

[0067] Using the preset dedicated global clock pin of the synchronization signal FPGA, the original clock signal is received;

[0068] Buffering the original clock signal, and processing the buffered original clock signal using an H-type all-copper global high-speed network of a synchronization signal FPGA to obtain a master clock signal;

[0069] The master clock signal is fanned out into N+1 first master clock signals by using the clock distribution network of the synchronization signal FPGA, N of the first master clock signals are respectively input into N array signal FPGAs, and the remaining first master clock signal is input into the programmable pulse generation module of the synchronization signal FPGA;

[0070] The method of using the array signal FPGA to process the N+1 first master clock signals to obtain a synchronous master clock signal and a sub-clock signal group corresponding to each synchronous master clock signal includes:

[0071] Using the phase-locked loop of the array signal FPGA, the phase of the N+1 first master clock signals is fine-tuned to obtain N+1 destination FPGA-side master clocks;

[0072] Using the array signal FPGA, the master clock of each destination FPGA end is input into the built-in global clock buffer resource, and the synchronous master clock signal is output;

[0073] Using the clock manager module resources of the array signal FPGA, each synchronous main clock signal is divided and processed to obtain the corresponding sub-clock signal group;

[0074] Each of the synchronous master clock signals corresponds to a sub-clock signal group; each sub-clock signal group includes a first sub-clock signal, a second sub-clock signal, a third sub-clock signal, and a fourth sub-clock signal;

[0075] The method of generating a pulse group for array signal triggering operation based on a synchronous master clock signal and a sub-clock signal group corresponding to each synchronous master clock signal by using a synchronous signal FPGA comprises:

[0076] In the master clock domain, the pulse generator of the synchronization signal FPGA generates the initial pulse;

[0077] Using the synchronization signal FPGA, the initial pulse is processed by combinatorial logic programming to obtain a sub-pulse signal of a sub-clock domain corresponding to each sub-clock signal of the sub-clock signal group; the sub-pulse signal includes a first sub-pulse signal belonging to the first sub-clock domain, a second sub-pulse signal belonging to the second sub-clock domain, a third sub-pulse signal belonging to the third sub-clock domain, and a fourth sub-pulse signal belonging to the fourth sub-clock domain; the first to fourth sub-clock domains are respectively determined by the first to fourth sub-clock signals;

[0078] The initial pulse is subjected to derivative processing to obtain N main pulse signals; the clock domain of the main pulse signal is the main clock domain;

[0079] Performing derivative processing on the sub-pulse signals of each sub-clock domain respectively to obtain N pulse communication signals of each sub-clock domain;

[0080] Using the N main pulse signals and the N pulse communication signals of each sub-clock domain, a pulse group for array signal triggering operation is constructed;

[0081] According to the relative transmission delay between the synchronization signal FPGA and the array signal FPGA, the pulse group used for the array signal trigger operation is subjected to time delay pre-programming processing, and the pulse group subjected to the time delay pre-programming processing is sent to N array signal FPGAs;

[0082] The combinational logic programming process includes register latching operation, multi-stage D flip-flop operation, and negation and operation;

[0083] The pulse group is used as an operation trigger signal, and the array signal FPGA is used to process the modulation source signal, the carrier signal frequency information and the carrier signal phase information to obtain the digital radio frequency signal required by each shortwave array of the shortwave array system, including:

[0084] S41, using the pulse group as an operation trigger signal, and using the array signal FPGA to process the modulation source signal to obtain a high-rate baseband signal;

[0085] S42, using the pulse group as an operation trigger signal, and using the array signal FPGA to process the carrier signal frequency information and the carrier signal phase information to obtain a carrier signal;

[0086] S43, using the pulse group as an operation trigger signal, modulating the high-rate baseband signal and the carrier signal to obtain a digital radio frequency signal required by each shortwave array of the shortwave array system.

[0087] The pulse group is used as an operation trigger signal, and the array signal FPGA is used to process the modulation source signal to obtain a high-rate baseband signal, including:

[0088] S411, making the array signal FPGA work in the first sub-clock domain, capturing the pulse communication signal of the first sub-clock domain, using the pulse communication signal of the first sub-clock domain to trigger the acquisition, selection, filtering and automatic gain control of the modulation source signal, and obtaining the modulation source data;

[0089] S412, enabling the array signal FPGA to operate in the second sub-clock domain, capturing the pulse communication signal in the second sub-clock domain, and using the pulse communication signal in the second sub-clock domain to trigger the interpolation, filtering and baseband modulation operations of the modulation source data to generate a low-rate baseband signal;

[0090] S413, making the array signal FPGA work in the third sub-clock domain, capturing the pulse communication signal of the third sub-clock domain, and using the pulse communication signal of the third sub-clock domain to trigger the integrated transmission and split extraction processing of multiple baseband signals;

[0091] S414, making the array signal FPGA work in the fourth sub-clock domain and the main clock domain, respectively capturing the pulse communication signal and the main pulse signal of the fourth sub-clock domain; using the pulse communication signal and the main pulse signal of the fourth sub-clock domain, respectively triggering the first-level interpolation filtering processing and the second-level interpolation filtering processing of the multi-channel baseband signals, to obtain a high-rate baseband signal;

[0092] The method uses the pulse group as an operation trigger signal, and uses the array signal FPGA to process the carrier signal frequency information and the carrier signal phase information to obtain the carrier signal, including:

[0093] Make the array signal FPGA work in the main clock domain and capture the main clock domain pulse; determine the signal initial phase required by each short wave array according to the required frequency and phase of the carrier signal; use the main clock domain pulse to trigger the phase accumulator, so that the phase accumulator generates a carrier signal according to the frequency and initial phase of the carrier signal;

[0094] The method uses the pulse group as an operation trigger signal to modulate the high-rate baseband signal and the carrier signal to obtain a digital radio frequency signal required by each shortwave array of the shortwave array system, including:

[0095] S431, making the array signal FPGA work in the main clock domain, capturing the main clock domain pulse; using the main clock domain pulse to trigger the orthogonal modulation converter, completing the orthogonal modulation conversion of the high-speed baseband signal and the carrier signal, and generating a digital RF signal with consistent amplitude;

[0096] S432, make the array signal FPGA work in the main clock domain, capture the main clock domain pulse; use the main clock domain pulse to trigger the multiplier, complete the amplitude adjustment of the digital RF signal, and generate the digital RF signal required by each shortwave array of the shortwave array system.

[0097] According to the required frequency and phase of the carrier signal, the initial phase of the signal required by each shortwave array is determined, and the initial phase of the signal can be determined according to a lookup table; the lookup table is determined according to the DDS method.

[0098] The sending of the pulse group after time delay pre-programming processing to N array signal FPGAs is to send a main pulse signal and the pulse communication signals of four sub-clock domains to one array signal FPGA, and so on, to send N main pulse signals and N pulse communication signals of each sub-clock domain to N array signal FPGAs respectively.

[0099] The branching and frequency division processing is to realize the branching, synchronization, phase shifting, frequency division, frequency multiplication and de-jittering of the clock according to the frequency of the sub-clock signal group to be generated, and derive the signal for each main clock to generate the required sub-clocks of different frequencies;

[0100] The frequencies of the first sub-clock signal, the second sub-clock signal, the third sub-clock signal, and the fourth sub-clock signal increase in sequence.

[0101] The method utilizes the phase-locked loop of the array signal FPGA to fine-tune the phase of N+1 first master clocks to obtain N+1 destination FPGA end master clocks, which is to obtain 1 first master clock from the programmable pulse generation module of the synchronization signal FPGA, fine-tune the phase of the N+1 first master clocks, and then send 1 destination FPGA end master clock to the programmable pulse generation module of the synchronization signal FPGA;

[0102] The method of dividing and frequency-dividing each synchronous master clock signal to obtain a corresponding sub-clock signal group includes utilizing the built-in clock manager module resources to realize clock division, synchronization, phase shifting, frequency division, frequency multiplication and de-jittering, generating sub-clocks of different frequencies required for each master clock derived signal, and synchronizing sub-clocks of the same frequency derived from different master clocks.

[0103] The original clock is generated by a high-precision crystal oscillator.

[0104] The synchronization signal FPGA is used to generate a clock signal and a pulse signal;

[0105] The array signal FPGA is used to generate the digital radio frequency signal required by each shortwave array;

[0106] The method of pre-programming the time delay of the pulse group used for the array signal triggering operation according to the relative transmission delay between the synchronization signal FPGA and the array signal FPGA includes:

[0107] The relative transmission delay between the synchronization signal FPGA and the N array signal FPGAs is measured, and the jth measurement result of the relative transmission delay between the synchronization signal FPGA and the i-th array signal FPGA is expressed as α ij ;

[0108] All α ij Represented as matrix A; the element in the i-th row and j-th column of matrix A is α ij ;

[0109] For each row vector of the matrix A, the corresponding mean is calculated;

[0110] For each row vector of the matrix A, the difference between the row vector and the corresponding mean is calculated to obtain a difference vector;

[0111] For each difference vector, find the element with the maximum value, and determine the sequence number of the element as the sequence number of the difference vector;

[0112] The sequence number value of the difference vector is used to perform fusion calculation processing on the mean value of each row vector of the matrix A to obtain the relative transmission delay between the synchronization signal FPGA and each array signal FPGA.

[0113] According to the relative transmission delay, the pulse group used for array signal triggering operation is pre-programmed with time delay.

[0114] The expression of the fusion calculation process is:

[0115] t i =T in (q i ),

[0116] Among them, in is the serial number value of the i-th difference vector, q i is the mean of the i-th row vector of matrix A, T in () represents the inth order polynomial of the first kind Chebyshev polynomial, t i is the relative transmission delay between the synchronization signal FPGA and the i-th array signal FPGA.

[0117] According to a second aspect of the present invention, a short wave array signal phase control synchronization device based on pulse programming is disclosed, the device comprising:

[0118] A memory storing executable program code;

[0119] a processor coupled to the memory;

[0120] The processor calls the executable program code stored in the memory to execute the shortwave array signal phase-controlled synchronization method based on pulse programming.

[0121] The third aspect of the present invention discloses a computer storable medium storing computer instructions, which, when called by a computer, are used to execute the shortwave array signal phase-controlled synchronization method based on pulse programming.

[0122] According to a fourth aspect of the present invention, an information data processing terminal is disclosed. The information data processing terminal is used to implement the shortwave array signal phase-controlled synchronization method based on pulse programming.

[0123] The fifth aspect of the present invention discloses a short wave array signal phase control synchronization method based on pulse programming, and the specific implementation steps are as follows:

[0124] S1) Synchronous clock generation: Through input clock processing, master clock distribution, master clock deviation elimination, driving and buffering, N+1 stable and synchronized master clocks are obtained, and then N+1 sub-clocks with different frequency synchronization are generated through clock derivation, where N is a natural number, which is equal to the number of array elements in the array synthesis system.

[0125] S2) Programmable pulse generation: After receiving the external signal generation instruction, a pulse is generated according to the synchronous master clock, and then pulses of other master clocks and sub-clocks are generated through pulse programming for synchronous triggering of array signal generation.

[0126] S3) Array signal generation: Under the triggering of the sub-clock pulse, a low-rate baseband signal is obtained through modulation source acquisition processing and baseband signal generation; under the triggering of the main clock pulse, the low-rate baseband signal is processed by baseband signal processing to obtain a high-rate baseband signal, and a carrier signal corresponding to the initial phase is generated according to the array output phase requirement, and orthogonal modulation, amplitude adjustment, and digital-to-analog conversion are performed to obtain an array signal for transmission.

[0127] Furthermore, in the generation of the synchronous clock, the original clock is provided by a high-precision crystal oscillator and sent to the FPGA chip. The FPGA global clock resources are used to generate the working clock required for programmable pulse generation and the working clocks of various levels required for N groups of array signals after fanning out and derivation. The clock signals generated by different groups of array signals are kept synchronized, which specifically includes the following steps:

[0128] S11) Input clock processing: The clock is input from a dedicated global clock pin, and is output from an H-type all-copper global high-speed network after being buffered, achieving a first-level global buffer drive with minimum time jitter and minimum delay difference to obtain a master clock;

[0129] S12) Master clock distribution: Through the clock distribution network, the master clock is fanned out to N+1 paths, and respectively sent to the FPGA chips where the programmable pulse generation and N groups of array signal generation are located. Through resource scheduling, layout and routing, and clock constraints, the fanned-out N+1 master clocks are guaranteed to remain synchronized;

[0130] S13) Eliminating master clock deviation: Although N+1 master clocks are synchronized, due to the existence of PCB wiring and clock offset factors, the master clocks may still have deviations when reaching different FPGA clock input pins. Therefore, the clock phase is fine-tuned using a phase-locked loop to achieve compensation, so that the offset between different master clocks is reduced to a reasonable range, and N+1 destination FPGA-side master clocks are obtained;

[0131] S14) Driving and buffering: The master clock has a large fan-out number at the destination FPGA. The clock is driven by input global buffer and global buffer resources to increase clock stability. At this time, the clock signal is connected to the global routing resource, the clock signal offset is minimized, and a more stable and synchronized master clock is obtained.

[0132] S15) Clock derivation: Utilize the resources of the clock manager module to implement clock branching, synchronization, phase shifting, frequency division, frequency multiplication and de-jittering, derive signals for each master clock to generate the required sub-clocks of different frequencies, and synchronize the sub-clocks of the same frequency derived from different master clocks.

[0133] Furthermore, the generation of the programmable pulse specifically comprises the following steps:

[0134] S21) Initial pulse generation: In the main clock domain, the pulse generator responds to the external signal generation instruction under the control of logic programming, obtains the initial pulse through the pulse counter counting, and processes the setup time and hold time of the pulse signal through programming to meet the signal clock domain conversion and signal capture requirements;

[0135] S22) Pulse generation in each clock domain: To avoid the difference in pulse capture due to clock jitter, clock offset, pulse signal establishment time and other factors, which may cause the array signal to be asynchronous, the generation timing and holding time of each pulse signal need to be programmed. The initial pulse is programmed through combinational logic such as register latch, multi-stage D flip-flop, inversion and handshake mechanism to generate corresponding pulse signals in each sub-clock domain, and pulse signals are generated in both the main clock domain and the sub-clock domain;

[0136] S23) Pulse signal derivation: Each clock domain pulse signal is derivatized, and each clock domain pulse signal is derived into N pulse signals for array signal generation of N channels. The relative delay of each pulse signal is pre-programmed to eliminate the influence of layout and routing delay to ensure the synchronization when the pulse is captured.

[0137] Furthermore, the array signal generation, a total of N (N is a natural number, equal to the number of array elements of the array synthesis system), signal generation 1 to signal generation N respectively correspond to array elements 1 to array elements N of the array synthesis system, specifically includes the following steps:

[0138] S31) Modulation source acquisition and processing: Working in the low-rate sub-clock domain, the modulation source signal (such as audio signal, etc.) is captured by the clock domain pulse to trigger acquisition, selection, filtering, automatic gain control and other processing to generate modulation source data;

[0139] S32) Baseband signal generation: working in the low-rate sub-clock domain, capturing the clock domain pulse to trigger the interpolation, filtering, and baseband modulation (such as FM, etc.) of the modulation source data to generate a low-rate baseband signal;

[0140] S33) baseband signal processing: first, in the lower sub-clock domain, by capturing the corresponding clock domain pulse to trigger the baseband signal integration and splitting processing, and then in the low clock domain and the main clock domain, by capturing the corresponding clock domain pulse to trigger the two-stage signal interpolation filtering processing, a high-rate baseband signal is generated;

[0141] S34) Carrier signal generation: in the master clock domain, by capturing the master clock domain pulse triggering the phase accumulator, according to the required carrier signal frequency and phase, determining the initial phase of the signal required by the array element of the array synthesis system, and using the phase accumulator to generate the carrier signal;

[0142] S35) Quadrature modulation: in the master clock domain, by capturing the master clock domain pulse to trigger the quadrature modulation converter, the quadrature modulation conversion of the high-speed baseband signal and the carrier signal is completed to generate a digital RF signal with the same amplitude;

[0143] S36) Amplitude adjustment: In the main clock domain, the amplitude adjustment of the digital RF signal is completed by capturing the main clock domain pulse to trigger the multiplier, thereby generating a digital RF signal with the amplitude required by the array element of the array synthesis system.

[0144] S37) Digital-to-analog conversion: The digital RF signal is sent to the DAC chip for digital-to-analog conversion, that is, the array signal required by the array element of the array synthesis system is generated for transmission.

[0145] The present invention provides a short wave array signal phase control synchronization method based on pulse programming, and the specific implementation steps are as follows:

[0146] S1) Synchronous clock generation: Through input clock processing, master clock distribution, master clock deviation elimination, driving and buffering, N+1 stable and synchronized master clocks are obtained, and then N+1 sub-clocks with different frequency synchronization are generated through clock derivation, where N is a natural number, which is equal to the number of array elements in the array synthesis system.

[0147] S2) Programmable pulse generation: After receiving the external signal generation instruction, a pulse is generated according to the synchronous master clock, and then pulses of other master clocks and sub-clocks are generated through pulse programming for synchronous triggering of array signal generation.

[0148] S3) Array signal generation: Under the triggering of the sub-clock pulse, a low-rate baseband signal is obtained through modulation source acquisition processing and baseband signal generation; under the triggering of the main clock pulse, the low-rate baseband signal is processed by baseband signal processing to obtain a high-rate baseband signal, and a carrier signal corresponding to the initial phase is generated according to the array output phase requirement, and orthogonal modulation, amplitude adjustment, and digital-to-analog conversion are performed to obtain an array signal for transmission.

[0149] Furthermore, in the generation of the synchronous clock, the original clock is provided by a high-precision crystal oscillator and sent to the FPGA chip. The FPGA global clock resources are used to generate the working clock for programmable pulse generation and the working clocks of various levels required for the generation of N groups of array signals through fan-out and derivation. The clock signals generated by different groups of array signals are kept synchronized, which specifically includes the following steps:

[0150] S11) Input clock processing: The clock is input from a dedicated global clock pin, and is output from an H-type all-copper global high-speed network after being buffered, achieving a first-level global buffer drive with minimum time jitter and minimum delay difference to obtain the main clock clk_in;

[0151] S12) Master clock distribution: Through the clock distribution network, the master clock clk_in is fanned out to N+1 paths (clk_in_pul, clk_in_1~clk_in_N), and sent to the FPGA chips where the programmable pulse generation and N groups of array signal generation are located. Through resource scheduling, layout and routing, and clock constraints, the fanned-out N+1 master clocks (clk_in_pul, clk_in_1~clk_in_N) are guaranteed to remain synchronized;

[0152] S13) Eliminate master clock deviation: Although the clocks clk_in_pul, clk_in_1~clk_in_N are synchronized, due to the presence of layout and routing delay and clock offset factors, the master clock may still have deviations when it reaches different FPGA clock input pins. Therefore, the clock phase is fine-tuned using a phase-locked loop (PLL) to achieve compensation, so that the skew between different master clocks is reduced to a reasonable range, and N+1 destination FPGA-side master clocks clk_dst_pul, clk_dst_1~clk_dst_N are obtained;

[0153] S14) Driving and buffering: The number of fan-outs of the main clocks clk_dst_pul, clk_dst_1~clk_dst_N at the destination FPGA is large. The clock is driven by the input global buffer and global buffer resources to increase clock stability. At this time, the clock signal is connected to the global routing resource, the clock signal skew is minimal, and the synchronous clocks clk_pul, clk_1~clk_N are obtained;

[0154] S15) Clock derivation: Use the clock manager module resources to implement clock branching, synchronization, phase shifting, frequency division, frequency multiplication and de-jittering, and derive the synchronous working sub-clocks of each level required for signal generation: the clock clk_pul derives the clocks clk_pul_a, clk_pul_b, clk_pul_c, clk_pul_d, the clock clk_1 derives the clocks clk_1_a, clk_1_b, clk_1_c, clk_1_d, ..., the clock clk_N derives the clocks clk_N_a, clk_N_b, clk_N_c, clk_N_d. The clocks clk_pul_a, clk_1_a, ..., clk_N_a are of the same frequency and are synchronized; the clocks clk_pul_b, clk_1_b, ..., clk_N_b are of the same frequency and are synchronized; the clocks clk_pul_c, clk_1_c, ..., clk_N_c are of the same frequency and are synchronized; the clocks clk_pul_d, clk_1_d, ..., clk_N_d are of the same frequency and are synchronized.

[0155] Furthermore, the generation of the programmable pulse works in the clk_pul clock domain and specifically includes the following steps:

[0156] S21) Initial pulse generation: In the main clock domain, the pulse generator responds to the input signal (command signal, trigger signal, etc.) under the control of logic programming, and obtains the initial pulse pulse_start through the pulse counter counting, and the setup time and hold time of the pulse signal are processed by programming to meet the signal clock domain conversion and signal capture requirements;

[0157] S22) Generation of pulses in each clock domain: In order to avoid the difference in pulse capture caused by clock jitter, clock offset, pulse signal establishment time and other factors, which may lead to asynchrony in array signals, it is necessary to program the generation timing and holding time of each pulse signal. The initial pulse is processed through combinational logic programming such as register latch, multi-level D flip-flop, negation and handshake mechanism, and the corresponding pulse signal is generated in each sub-clock domain, and pulse signals are generated in both the main clock domain and the sub-clock domain; the initial pulse pulse_start is processed through combinational logic programming such as register latch, multi-level D flip-flop, negation and handshake mechanism, and generates clk_pul clock domain pulse signal pulse_pul, clk_pul_a clock domain pulse signal pulse_a, clk_pul_b clock domain pulse signal pulse_b, clk_pul_c clock domain pulse signal pulse_c, clk_pul_d clock domain pulse signal pulse_d;

[0158] S23) Pulse signal derivation: derive each clock domain pulse signal, pulse_pul derives pulse signals pulse_pul1~pulse_pulN, pulse_a derives pulse signals pulse_a1~pulse_aN, pulse_b derives pulse signals pulse_b1~pulse_bN, pulse_c derives pulse signals pulse_c1~pulse_cN, pulse_d derives pulse signals pulse_d1~pulse_dN, and the relative delay of each pulse signal is pre-programmed to eliminate the influence of layout and routing delay to ensure the synchronization when the pulse is captured. Pulse signals pulse_pul1, pulse_a1, pulse_b1, pulse_c1, and pulse_d1 are sent to the FPGA chip where signal generation 1 is located, ..., and pulse signals pulse_pulN, pulse_aN, pulse_bN, pulse_cN, and pulse_dN are sent to the FPGA chip where signal generation N is located.

[0159] Further, the array signal generation, a total of N (N is a natural number, equal to the number of array elements of the array synthesis system), signal generation 1 to signal generation N respectively correspond to array elements 1 to array elements N of the array synthesis system, and the working master clocks are clk_1 to clk_N respectively, and specifically include the following steps:

[0160] S31) Modulation source acquisition processing: working in the clk_a (clk_1_a, ..., clk_N_a) clock domain, triggering the acquisition, selection, filtering, automatic gain control and other processing of the modulation source signal (such as audio signal, etc.) by capturing the pulse pulse_a (pulse_a1~pulse_aN), and generating the modulation source data;

[0161] S32) Baseband signal generation: working in the clk_b (clk_1_b, ..., clk_N_b) clock domain, triggering interpolation, filtering, and baseband modulation (such as FM, etc.) of the modulation source data by capturing pulses pulse_b (pulse_b1 to pulse_bN), and generating a baseband signal in the clk_b clock domain;

[0162] S33) Baseband signal processing: first, in the clk_c (clk_1_c, ..., clk_N_c) clock domain, by capturing pulse pulse_c (pulse_c1 ~ pulse_cN), triggering baseband signal integration and splitting processing, and then in the clk_d (clk_1_d, ..., clk_N_d) clock domain and the main clock clk (clk_1, ..., clk_N) clock domain, by capturing pulse pulse_c (pulse_c1 ~ pulse_cN) and programmable pulse pulse_pul (pulse_pul1 ~ pulse_pulN), triggering two-stage signal interpolation filtering processing, generating the baseband signal of the main clock clk (clk_1, ..., clk_N) clock domain;

[0163] S34) Carrier signal generation: in the clock domain of the master clock clk (clk_1, ..., clk_N), the phase accumulator is triggered by capturing the pulse pulse_pul (pulse_pul1 to pulse_pulN), and the carrier signal is generated according to the required signal frequency and the initial phase of the signal required by the array element of the array synthesis system;

[0164] S35) Quadrature modulation: in the clock domain of the master clock clk (clk_1, ..., clk_N), the quadrature modulation converter is triggered by capturing pulses pulse_pul (pulse_pul1 to pulse_pulN), so as to complete the quadrature modulation conversion of the baseband signal and the carrier signal in the master clock domain, and generate a digital RF signal with the same amplitude;

[0165] S36) Amplitude adjustment: In the clock domain of the main clock clk (clk_1, ..., clk_N), the multiplier is triggered by capturing the pulse pulse_pul (pulse_pul1 ~ pulse_pulN), so as to complete the amplitude adjustment of the digital RF signal and generate a digital RF signal of the amplitude required by the array element of the array synthesis system.

[0166] S37) Digital-to-analog conversion: The digital RF signal is sent to the DAC chip for digital-to-analog conversion, that is, the array signal required by the array element of the array synthesis system is generated for transmission.

[0167] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A shortwave array signal phase-controlled synchronization method based on pulse programming, characterized in that: This is achieved using the synchronization signal FPGA and array signal FPGA, including: S1, using the synchronization signal FPGA to generate N+1 first master clock signals; N is the number of array signal FPGAs; S2, using the array signal FPGA, processing the N+1 first master clock signals to obtain a synchronous master clock signal and a sub-clock signal group corresponding to each synchronous master clock signal; S3, based on the synchronous master clock signal and the sub-clock signal group corresponding to each synchronous master clock signal, using the synchronous signal FPGA, generating a pulse group for array signal triggering operation; S4, using the pulse group as an operation trigger signal, and using the array signal FPGA to process the modulation source signal, the carrier signal frequency information, and the carrier signal phase information to obtain the digital radio frequency signal required by each shortwave array of the shortwave array system; S5, performing digital-to-analog conversion processing on the digital radio frequency signal required by the shortwave array system to obtain a signal to be transmitted by the shortwave array system.

2. The shortwave array signal phase-controlled synchronization method based on pulse programming as claimed in claim 1, characterized in that: The method of using the synchronization signal FPGA to generate N+1 master clock signals includes: S11, using a preset dedicated global clock pin of the synchronization signal FPGA to receive an original clock signal; S12, buffering the original clock signal, and processing the buffered original clock signal using the global high-speed network of the synchronization signal FPGA to obtain a master clock signal; S13, using the clock distribution network of the synchronization signal FPGA, fan out the master clock signal into N+1 first master clock signals, input N of the first master clock signals into N array signal FPGAs respectively, and input the remaining first master clock signal into the programmable pulse generation module of the synchronization signal FPGA.

3. The shortwave array signal phase-controlled synchronization method based on pulse programming as claimed in claim 1, characterized in that: The method of using the array signal FPGA to process the N+1 first master clock signals to obtain a synchronous master clock signal and a sub-clock signal group corresponding to each synchronous master clock signal includes: Using the phase-locked loop of the array signal FPGA, the phase of the N+1 first master clock signals is finely adjusted to obtain N+1 destination FPGA end master clocks; Using the array signal FPGA, the master clock of each destination FPGA is input into the global clock buffer resource of the array signal FPGA, and a synchronous master clock signal is output; By utilizing the clock manager module resources of the array signal FPGA, each synchronous main clock signal is divided and processed to obtain a corresponding sub-clock signal group.

4. The shortwave array signal phase-controlled synchronization method based on pulse programming as claimed in claim 3, characterized in that: Each of the synchronous main clock signals corresponds to a sub-clock signal group; each sub-clock signal group includes a first sub-clock signal, a second sub-clock signal, a third sub-clock signal, and a fourth sub-clock signal.

5. The shortwave array signal phase-controlled synchronization method based on pulse programming as claimed in claim 1, characterized in that: The method of generating a pulse group for array signal triggering operation based on a synchronous master clock signal and a sub-clock signal group corresponding to each synchronous master clock signal by using a synchronous signal FPGA comprises: In the master clock domain, the pulse generator of the synchronization signal FPGA generates the initial pulse; Using the synchronization signal FPGA, the initial pulse is processed by combinatorial logic programming to obtain a sub-pulse signal of a sub-clock domain corresponding to each sub-clock signal of the sub-clock signal group; the sub-pulse signal includes a first sub-pulse signal belonging to the first sub-clock domain, a second sub-pulse signal belonging to the second sub-clock domain, a third sub-pulse signal belonging to the third sub-clock domain, and a fourth sub-pulse signal belonging to the fourth sub-clock domain; the first to fourth sub-clock domains are respectively determined by the first to fourth sub-clock signals; The initial pulse is subjected to derivative processing to obtain N main pulse signals; the clock domain of the main pulse signal is the main clock domain; Performing derivative processing on the sub-pulse signals of each sub-clock domain respectively to obtain N pulse communication signals of each sub-clock domain; Using the N main pulse signals and the N pulse communication signals of each sub-clock domain, a pulse group for array signal triggering operation is constructed; According to the relative transmission delay between the synchronization signal FPGA and the array signal FPGA, the pulse group used for the array signal trigger operation is pre-programmed with a time delay, and the pulse group after the time delay pre-programming is sent to N array signal FPGAs.

6. The shortwave array signal phase-controlled synchronization method based on pulse programming as claimed in claim 5, characterized in that: The combinational logic programming process includes register latching operation, multi-stage D flip-flop operation, and inversion and AND operation.

7. The shortwave array signal phase-controlled synchronization method based on pulse programming as claimed in claim 5, characterized in that: The pulse group is used as an operation trigger signal, and the array signal FPGA is used to process the modulation source signal, the carrier signal frequency information and the carrier signal phase information to obtain the digital radio frequency signal required by each shortwave array of the shortwave array system, including: S41, using the pulse group as an operation trigger signal, and using the array signal FPGA to process the modulation source signal to obtain a high-rate baseband signal; S42, using the pulse group as an operation trigger signal, and using the array signal FPGA to process the carrier signal frequency information and the carrier signal phase information to obtain a carrier signal; S43, using the pulse group as an operation trigger signal, modulating the high-rate baseband signal and the carrier signal to obtain a digital radio frequency signal required by each shortwave array of the shortwave array system.

8. The shortwave array signal phase-controlled synchronization method based on pulse programming as claimed in claim 7, characterized in that: The pulse group is used as an operation trigger signal, and the array signal FPGA is used to process the modulation source signal to obtain a high-rate baseband signal, including: S411, making the array signal FPGA work in the first sub-clock domain, capturing the pulse communication signal of the first sub-clock domain, using the pulse communication signal of the first sub-clock domain to trigger the acquisition, selection, filtering and automatic gain control of the modulation source signal, and obtaining the modulation source data; S412, enabling the array signal FPGA to operate in the second sub-clock domain, capturing the pulse communication signal in the second sub-clock domain, and using the pulse communication signal in the second sub-clock domain to trigger the interpolation, filtering and baseband modulation operations of the modulation source data to generate a low-rate baseband signal; S413, making the array signal FPGA work in the third sub-clock domain, capturing the pulse communication signal of the third sub-clock domain, and using the pulse communication signal of the third sub-clock domain to trigger the integrated transmission and split extraction processing of multiple baseband signals; S414, enables the array signal FPGA to work in the fourth sub-clock domain and the main clock domain, and respectively captures the pulse communication signal and the main pulse signal of the fourth sub-clock domain; utilizes the pulse communication signal and the main pulse signal of the fourth sub-clock domain to respectively trigger the first-level interpolation filtering processing and the second-level interpolation filtering processing of the multi-channel baseband signals, and obtains a high-speed baseband signal.

9. The shortwave array signal phase-controlled synchronization method based on pulse programming as claimed in claim 7, characterized in that: The method uses the pulse group as an operation trigger signal, and uses the array signal FPGA to process the carrier signal frequency information and the carrier signal phase information to obtain the carrier signal, including: The array signal FPGA is made to work in the main clock domain to capture the main clock domain pulse; the initial phase of the signal required for each shortwave array is determined according to the required carrier signal frequency information and carrier signal phase information; the main clock domain pulse is used to trigger the phase accumulator, so that the phase accumulator generates a carrier signal according to the frequency information and initial phase of the carrier signal.

10. The shortwave array signal phase-controlled synchronization method based on pulse programming as claimed in claim 7, characterized in that: The method uses the pulse group as an operation trigger signal to modulate the high-rate baseband signal and the carrier signal to obtain a digital radio frequency signal required by each shortwave array of the shortwave array system, including: S431, making the array signal FPGA work in the main clock domain, capturing the main clock domain pulse; using the main clock domain pulse to trigger the orthogonal modulation converter, completing the orthogonal modulation conversion of the high-speed baseband signal and the carrier signal, and generating a digital RF signal with consistent amplitude; S432, make the array signal FPGA work in the main clock domain, capture the main clock domain pulse; use the main clock domain pulse to trigger the multiplier, complete the amplitude adjustment of the digital RF signal, and generate the digital RF signal required by each shortwave array of the shortwave array system.

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