Printed circuit board and method for manufacturing printed circuit board

Abstract

The present invention provides a circuit connection substrate and the like capable of suppressing a decrease in connection reliability by reducing a fragile portion of a terminal portion. A printed circuit board includes: a first insulating layer; a conductor layer disposed on the first insulating layer; and a second insulating layer disposed on the conductor layer and having an opening, the wired circuit board having a terminal portion located between the first insulating layer and the second insulating layer and exposed to the outside through the opening. The terminal portion includes a connection layer that is a part of the conductor layer, a barrier layer disposed on the connection layer, and an external connection layer disposed on the barrier layer, the external connection layer including copper.

Description

Technical Field

[0001] The present invention relates to a wiring circuit substrate and a method for manufacturing the wiring circuit substrate, and a semiconductor package and electronic equipment including the wiring circuit substrate. Background Art

[0002] The wired circuit board is manufactured by laminating conductors such as wiring and various insulating layers on a base material. The conductors and insulating layers are patterned by, for example, photolithography.

[0003] As a wiring circuit substrate, for example, a wiring circuit substrate is proposed, comprising: a first insulating layer; a terminal; a second insulating layer, which is arranged on one side of the terminal in the thickness direction; and a wiring, which is continuous with the terminal in a direction intersecting the thickness direction, the first insulating layer having an opening portion, which passes through the opening portion in the thickness direction, and the cross-sectional area of ​​the opening increases toward one side in the thickness direction, the terminal having a peripheral portion and a solid portion, the peripheral portion being in contact with the inner side surface of the first insulating layer forming the opening portion, the solid portion being integrally arranged with the peripheral portion on the inner side of the peripheral portion, and the peripheral portion and the solid portion filling the entire opening portion (see patent document 1). Prior art literature Patent Literature

[0004] Patent Document 1: Japanese Patent Application Publication No. 2018-190950 Summary of the invention Problems to be solved by the invention

[0005] The wiring circuit substrate is connected to a BGA (ball grid array) or the like, for example. At this time, the terminal portion of the wiring circuit substrate is connected to the solder ball. The connection between the terminal portion of the wiring circuit substrate and the solder ball has the problem of the terminal portion becoming brittle due to the connection of dissimilar metals. If the terminal portion becomes brittle, the connection reliability is reduced.

[0006] An object of the present invention is to provide a circuit connection substrate capable of suppressing a decrease in connection reliability by reducing a brittle portion of a terminal portion, and a semiconductor package and an electronic device including the wiring circuit substrate. Technical solutions to solve problems

[0007] The inventors of the present invention have conducted intensive studies to solve the above-mentioned problems, and as a result, have found that the above-mentioned problems can be solved, thereby completing the present invention having the following gist. That is, the present invention includes the following contents.

[0008] [1] A wired circuit board comprising: a first insulating layer; a conductive layer disposed on the first insulating layer; and a second insulating layer disposed on the conductive layer and having an opening. The wiring circuit substrate has a terminal portion, the terminal portion is located between the first insulating layer and the second insulating layer and is exposed to the outside through the opening portion. The terminal portion includes a connection layer as a part of the conductor layer, a barrier layer arranged on the connection layer, and an external connection layer arranged on the barrier layer. The external connection layer includes copper. [2] The wired circuit board according to [1], wherein the barrier layer contains at least any one of chromium, titanium, and tungsten. [3] The wired circuit board according to [1] or [2], wherein the conductor layer is a wiring layer having wiring in a portion other than the connection layer. [4] The wiring circuit board according to any one of [1] to [3], further comprising a metal core layer on a surface of the first insulating layer opposite to the conductor layer side. [5] The wired circuit board according to [4], further comprising a third insulating layer on a surface of the metal core layer opposite to the first insulating layer. [6] The wired circuit board according to any one of [1] to [5], wherein the thickness of the external connection layer is 10 μm or less. [7] The wired circuit board according to any one of [1] to [6], wherein the barrier layer has a thickness of 1 μm or less. [8] A semiconductor package including the wiring circuit substrate according to any one of [1] to [7]. [9] An electronic device comprising the semiconductor package described in [8].

[10] A method for manufacturing a wiring circuit substrate, for manufacturing the wiring circuit substrate described in any one of [1] to [7], comprising: forming a barrier layer precursor on the conductor layer formed on the first insulating layer; A process of forming an external connection layer on a portion of the barrier layer precursor by electrolytic plating using the barrier layer precursor as a seed layer, the portion of the barrier layer precursor being located on the connection layer which is a portion of the conductor layer and corresponding to the barrier layer; and A step of removing the barrier layer precursor except for a portion to be the barrier layer.

[11] The method for manufacturing a wired circuit board according to

[10] , further comprising the step of forming a third insulating layer having the opening so that the external connection layer is exposed from the opening. Effects of the Invention

[0009] According to the present invention, it is possible to provide a circuit connection substrate that suppresses a decrease in connection reliability by reducing the brittle portion of a terminal portion, and a semiconductor package and an electronic device including the wired circuit substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a schematic diagram of one embodiment of a wired circuit board. Figure 2 This is a schematic diagram of another embodiment of a wired circuit board. Figure 3A This is a schematic diagram for explaining one embodiment of a method for manufacturing a wired circuit board (part 1). Figure 3B This is a schematic diagram for explaining one embodiment of a method for manufacturing a wired circuit board (part 2). Figure 3C This is a schematic diagram (part 3) for explaining one embodiment of a method for manufacturing a wired circuit board. Figure 3D This is a schematic diagram (part 4) for explaining one embodiment of a method for manufacturing a wired circuit board. Figure 3E This is a schematic diagram (part 5) for explaining one embodiment of a method for manufacturing a wired circuit board. Figure 3F This is a schematic diagram (part 6) for explaining one embodiment of a method for manufacturing a wired circuit board. Figure 3G This is a schematic diagram for explaining one embodiment of a method for manufacturing a wired circuit board (part 7). Figure 3H This is a schematic diagram (part 8) for explaining one embodiment of a method for manufacturing a wired circuit board. Fig. 3I This is a schematic diagram (part 9) for explaining one embodiment of a method for manufacturing a printed circuit board. Figure 4 This is a schematic diagram of another embodiment of a wired circuit board. Figure 5A This is a schematic diagram (part 1) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 5B This is a schematic diagram (part 2) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 5CThis is a schematic diagram (part 3) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 5D This is a schematic diagram (part 4) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 5E This is a schematic diagram (part 5) for explaining another embodiment of the method for manufacturing a printed circuit board. Fig. 5F This is a schematic diagram (part 6) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 5G This is a schematic diagram (part 7) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 5H This is a schematic diagram (part 8) for explaining another embodiment of the method for manufacturing a printed circuit board. Fig.5I This is a schematic diagram (No. 9) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 5J This is a schematic diagram (No. 10 ) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 5K This is a schematic diagram (No. 11) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 6 This is a schematic diagram of another embodiment of a wired circuit board. Fig. 7A This is a schematic diagram (part 1) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 7B This is a schematic diagram (part 2) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 7C This is a schematic diagram (part 3) for explaining another embodiment of the method for manufacturing a printed circuit board. Fig.7D This is a schematic diagram (part 4) for explaining another embodiment of the method for manufacturing a printed circuit board. Fig. 7E This is a schematic diagram (part 5) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 7F This is a schematic diagram (part 6) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 7G This is a schematic diagram (part 7) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 7HThis is a schematic diagram (part 8) for explaining another embodiment of the method for manufacturing a printed circuit board. Figure 8 This is a schematic diagram of another embodiment of a wired circuit board. DETAILED DESCRIPTION

[0011] (Wired Circuit Board, and Method for Manufacturing the Wired Circuit Board) The wired circuit board of the present invention includes at least a first insulating layer, a conductive layer disposed on the first insulating layer, and a second insulating layer disposed on the conductive layer and having an opening, and may further include other members as necessary. The wiring circuit substrate has a terminal portion. The terminal portion is located between the first insulating layer and the second insulating layer. The terminal portion is exposed to the outside through the opening portion. The terminal portion includes a connection layer which is a part of the conductor layer, a barrier layer arranged on the connection layer, and an external connection layer arranged on the barrier layer. The external connection layer contains copper.

[0012] The terminal portion connected to the external terminal such as the solder ball has a barrier layer between the connection layer and the external connection layer. Thus, even if the terminal portion becomes brittle due to alloying caused by the connection of the metal (such as Sn) in the external terminal and the dissimilar metal of copper in the external connection layer, the barrier layer prevents the brittleness from reaching the connection layer below the barrier layer. Therefore, the brittle portion of the terminal portion can be reduced. As a result, the reduction in connection reliability can be suppressed. It should be noted that as a method of suppressing the reduction in connection reliability due to the embrittlement of the terminal portion, the direction of increasing the thickness of the terminal portion can be considered. However, in this case, forming a thick terminal portion will cause new problems such as difficulty in controlling the thickness and reduced flatness of the wiring circuit substrate. In addition, in the case where a part of the conductor layer plays the role of the terminal portion, if a thick conductor layer is formed, the aspect ratio of the wiring constituting the conductor layer becomes larger, which is prone to wiring pattern defects (for example, pattern distortion).

[0013] Below, use Figure 1 An example of the wired circuit board of the present invention will be described. Figure 1 The illustrated wired circuit board includes a first insulating layer 1 , a conductive layer 2 , and a second insulating layer 3 . The conductor layer 2 is disposed on the first insulating layer 1. The conductor layer 2 is located between the first insulating layer 1 and the second insulating layer 3. The conductor layer 2 has wiring in a portion other than the connection layer 2x described later. Therefore, the conductor layer 2 can be called a wiring layer. By providing the conductor layer 2 with wiring, a wiring circuit substrate with various wiring designs can be obtained, thereby increasing the degree of freedom in design. The second insulating layer 3 is disposed on the conductive layer 2. The second insulating layer 3 is not only located on the conductive layer 2, but also fills in spaces between the wirings of the conductive layer 2. The second insulating layer 3 has an opening 3a. The opening 3a is a through hole that penetrates the second insulating layer 3 in the thickness direction. The wired circuit board has a terminal portion 51. The terminal portion 51 is located between the first insulating layer 1 and the second insulating layer 3, and is exposed to the outside through the opening portion 3a. The terminal portion 51 does not fill the opening portion 3a. The terminal portion 51 includes a connection layer 2x as a part of the conductor layer 2, a barrier layer 4 disposed on the connection layer 2x, and an external connection layer 5 disposed on the barrier layer 4. In the terminal portion 51, the connection layer 2x, the barrier layer 4, and the external connection layer 5 are arranged in the thickness direction. In the terminal portion 51, the connection layer 2x is located on the first insulating layer 1 side relative to the barrier layer 4, and the external connection layer 5 is located on the opposite side of the barrier layer 4 relative to the first insulating layer 1 side. The connection layer 2x is in contact with the barrier layer 4. The connection layer 2x is electrically connected to the external connection layer 5, but is not in physical contact. The external connection layer 5 contains copper. The terminal portion 51 is a terminal for connection to an external terminal such as a solder ball.

[0014] use Figure 2 Another example of the wired circuit board of the present invention will be described. Figure 2 The illustrated wired circuit board includes a metal core layer 10 , a first insulating layer 1 , a conductor layer 2 , and a second insulating layer 3 . The metal core layer 10 is located on the surface of the first insulating layer 1 on the opposite side to the conductive layer 2. From another perspective, the first insulating layer 1 is located between the metal core layer 10 and the conductive layer 2. The conductor layer 2 is disposed on the first insulating layer 1. The conductor layer 2 is located between the first insulating layer 1 and the second insulating layer 3. The conductor layer 2 has wiring (not shown) in a portion other than a connection layer 2x described later. Therefore, the conductor layer 2 can be called a wiring layer. The second insulating layer 3 is disposed on the conductive layer 2. The second insulating layer 3 is not only located on the conductive layer 2, but also fills in spaces between the wirings of the conductive layer 2. The second insulating layer 3 has an opening 3a. The opening 3a is a through hole that penetrates the second insulating layer 3 in the thickness direction. The wired circuit board has a terminal portion 51. The terminal portion 51 is located between the first insulating layer 1 and the second insulating layer 3, and is exposed to the outside through the opening portion 3a. The terminal portion 51 does not fill the opening portion 3a. The terminal portion 51 includes a connection layer 2x as a part of the conductor layer 2, a barrier layer 4 disposed on the connection layer 2x, and an external connection layer 5 disposed on the barrier layer 4. In the terminal portion 51, the connection layer 2x, the barrier layer 4, and the external connection layer 5 are arranged in the thickness direction. In the terminal portion 51, the connection layer 2x is located on the first insulating layer 1 side relative to the barrier layer 4, and the external connection layer 5 is located on the opposite side of the barrier layer 4 relative to the first insulating layer 1 side. The connection layer 2x is in contact with the barrier layer 4. The connection layer 2x is electrically connected to the external connection layer 5, but is not in physical contact. The external connection layer 5 contains copper. The terminal portion 51 is a terminal for connection to an external terminal such as a solder ball.

[0015] The metal core layer is, for example, an element for ensuring the rigidity of the printed circuit board. The material of the metal core layer is not particularly limited, and examples thereof include Cu, Cu alloys, Al, stainless steel, FeNi alloys such as 42 alloy, and combinations thereof. Among them, Cu and Cu alloys are preferred from the viewpoint of thermal conductivity and electrical conductivity. In addition, stainless steel and 42 alloy are preferred from the viewpoint of suppressing warpage, and 42 alloy is more preferred. The thickness of the metal core layer is not particularly limited, and is, for example, 10 μm or more, preferably 15 μm or more, and, for example, 500 μm or less, preferably 300 μm or less. In the present invention, "thickness" refers to the length in the thickness direction of the metal core layer. The thickness direction of the metal core layer refers to the direction perpendicular to the surface direction of the metal core layer.

[0016] When the metal core layer has a through hole, the shape of the through hole in the metal core layer is not particularly limited.

[0017] When the metal core layer has a through hole, there is no particular limitation on the side surface shape of the through hole in the metal core layer. The side surface shape of the through hole in the metal core layer may be an arc shape or a linear shape in a cross section parallel to the thickness direction of the metal core layer. The arc shape here refers to a shape that is recessed from the through-hole side toward the metal core layer side. If the shape is an arc, the adhesion between the insulating portion located between the metal core layer and the conductor present in the through hole and the metal core layer can be improved. The insulating portion realizes electrical insulation between the metal core layer and the conductor. If the shape is a linear shape, it becomes easy to form a seed layer when forming an interlayer connection portion when manufacturing a wired circuit board.

[0018] The material of the insulating layer (e.g., the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer) in the wiring circuit substrate is not particularly limited, and examples thereof include synthetic resins. Examples of synthetic resins include polyimide, polyamide-imide, polyarylethernitrile, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, polyvinyl chloride, epoxy resin, phenolic resin, acrylic resin, and liquid crystal polymer. The insulating layer may contain particles (fillers). As particles, inorganic particles and organic particles may be mentioned. As particles, inorganic particles are preferred. As inorganic particles, for example, particles containing silicon dioxide such as aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, aluminum oxide, aluminum nitride, boron nitride, crystalline silicon dioxide, and amorphous silicon dioxide may be mentioned. In addition, as the material of the inorganic particles, metal single substances, alloys, etc. such as aluminum, gold, silver, copper, and nickel may be mentioned. It may also be particles such as aluminum borate whiskers, amorphous carbon, and graphite. The shape of the particles may be various shapes such as spherical, needle-shaped, and flaky. As particles, only one of the above-mentioned particles may be used, or two or more may be used. The resin used to form the insulating layer may be a thermosetting resin or a thermoplastic resin. In addition, the resin used to form the insulating layer may be a photosensitive resin or a non-photosensitive resin. The insulating layer can be formed by, for example, the following method. (I): Lamination and hot pressing of thermosetting insulating resin film (e.g., Class B insulating resin film) (II): Application and drying of liquid resin composition When the insulating layer has an opening, examples of a method for forming the opening in the insulating layer include the following methods. (III): When the insulating layer is formed using a thermosetting resin or a thermoplastic resin, laser irradiation is performed. (IV): When the insulating layer is formed using a photosensitive resin, the photosensitive resin film is selectively exposed and developed. The thickness of the insulating layer is not particularly limited, and is, for example, 1 μm or more, preferably 3 μm or more, and, for example, 35 μm or less, preferably 20 μm or less.

[0019] The conductor layer (e.g., conductor layer 2, second conductor layer 22 described later, third conductor layer 24 described later) in the wiring circuit board may be made of metal materials, such as copper, nickel, gold, solder, and alloys thereof. The thickness of the conductor layer is not particularly limited, and is, for example, 3 μm or more, preferably 5 μm or more, and, for example, 50 μm or less, preferably 30 μm or less. The connection layer is a part of the conductor layer, so the material of the connection layer is the same as that of the conductor layer. The thickness of the connection layer is, for example, the same as the thickness of the conductor layer. However, when the connection layer is located on the interlayer connection portion, the thickness of the connection layer may be thicker than the thickness of other portions of the conductor layer (eg, wiring).

[0020] The barrier layer is preferably a layer that does not form an alloy with a metal (eg, Sn) in an external terminal such as a solder ball, or a layer that is unlikely to become brittle even if an alloy is formed. The material of the barrier layer is not particularly limited, and may be a single metal, an alloy, or a metal oxide. Such a barrier layer is not particularly limited, but preferably contains at least one of chromium, titanium, nickel, and tungsten. This can also serve as a seed layer when forming an external connection layer by electrolytic plating, thereby improving the productivity of the wiring circuit board. The barrier layer can be a single layer or multiple layers. The thickness of the barrier layer is not particularly limited, and is, for example, 2 μm or less, preferably 1 μm or less, and, for example, 0.01 μm or more, preferably 0.03 μm or more. The thinner the barrier layer is, the thinner the printed circuit board can be. In this regard, the barrier layer is preferably 1 μm or less in thickness. The thickness of the barrier layer is, for example, 1 / 1000 to 1 / 3, preferably 1 / 500 to 1 / 10 of the thickness of the external connection layer.

[0021] The external connection layer includes copper. Even when the external connection layer includes copper that is easily embrittled by forming an alloy, the wired circuit board of the present invention includes the barrier layer as a lower layer of the external connection layer, and thus can prevent the entire terminal portion from becoming embrittled. The external connection layer may contain components other than copper. The thickness of the external connection layer is not particularly limited, and is, for example, 20 μm or less, preferably 10 μm or less, and, for example, 1 μm or more, preferably 3 μm or more. The thinner the thickness of the external connection layer is, the thinner the printed circuit board can be. In this regard, the thickness of the external connection layer is preferably 10 μm or less.

[0022] The main component of the interlayer connection portion described below is not particularly limited, and examples thereof include metal materials. Examples of the metal material include copper, nickel, gold, silver, solder, and alloys thereof. There is no particular limitation on the shape of the interlayer connecting portion. The cross-sectional shape of the interlayer connection portion is not particularly limited, and may be, for example, a rectangular shape or a trapezoidal shape in a cross section parallel to the thickness direction of the metal core layer.

[0023] The wired circuit board may include a seed layer (not shown). The seed layer is used as a conductive layer for electrolytic plating. Examples of the material of the seed layer include copper, chromium, titanium, nickel, tungsten, and alloys thereof. The seed layer may be a single layer or a multi-layered layer. In the case of a multi-layered layer, the material of each layer may be copper, chromium, titanium, nickel, tungsten, and alloys thereof.

[0024] The method for producing a wired circuit board of the present invention includes the following steps. A step of forming a barrier layer precursor on the conductor layer formed on the first insulating layer A step of forming an external connection layer by electrolytic plating on a portion of the barrier layer precursor located on a portion of the conductor layer, i.e., the connection layer, and corresponding to the barrier layer, using the barrier layer precursor as a seed layer. · Step of removing the barrier layer precursor except for the portion to be the barrier layer The method for producing the wired circuit board of the present invention is a method for producing the wired circuit board of the present invention.

[0025] use Figure 3A to Figure 3I right Figure 2 An embodiment of a method for manufacturing a wired circuit board shown in FIG. 1 will be described. First, a first insulating layer 1 ( Figure 3A ) The first insulating layer 1 can be formed by, for example, laminating a B-class insulating resin film and forming an insulating layer by heat pressing.

[0026] Next, a patterned conductor layer 2 (wiring layer) is formed on the first insulating layer 1. The patterned conductor layer 2 is formed, for example, by the following method. Formation of a seed layer (not shown) on the first insulating layer 1 ·Formation of photoresist film on seed layer · Formation of the resist pattern 15 by selective exposure and development of the photoresist film (partial exposure of the seed layer) ( Figure 3B ) · Formation of the conductor layer 2 by electrolytic plating of the exposed seed layer ( Figure 3C ) · Removal of the resist pattern 15 and removal of the unnecessary seed layer ( Figure 3D ) The formed patterned electrolytic plating layer serves as the conductor layer 2 .

[0027] Next, a barrier layer precursor 4x ( Figure 3E ). The barrier layer precursor 4x is formed to cover the patterned conductor layer 2. Therefore, a portion of the barrier layer precursor 4x is also formed on the first insulating layer 1 exposed between the patterned conductor layers 2. It should be noted that the barrier layer precursor 4x on the portion that becomes a portion of the conductor layer 2, i.e., the connection layer 2x, becomes the barrier layer 4. The barrier layer precursor 4x also serves as a seed layer when forming the external connection layer 5 by electrolytic plating. The barrier layer precursor 4x may be a single layer or a multilayer. The barrier layer precursor 4x can be formed by a method commonly used as a method for forming a seed layer, for example. Examples of the barrier layer precursor 4x include a vapor deposition method and a sputtering method.

[0028] Next, a photoresist film is formed on the barrier layer precursor 4x. Then, the photoresist film is selectively exposed and developed to form a resist pattern 16 ( Figure 3F ). The exposed barrier layer precursor 4x is the barrier layer precursor 4x at a portion that will become a part of the conductor layer 2, that is, the connection layer 2x.

[0029] Next, the exposed barrier layer precursor 4x is used as a seed layer, and the barrier layer precursor 4x is electrolytically plated. Thus, an external connection layer 5 ( Figure 3G ).

[0030] Next, the resist pattern 16 is removed, and unnecessary barrier layer precursor 4x is removed ( Figure 3H ). Through the above, the terminal portion 51 including the connection layer 2x, the barrier layer 4 disposed on the connection layer 2x, and the external connection layer 5 disposed on the barrier layer 4 is formed. It should be noted that Figure 3H In the examples above, the barrier layer 4 and the external connection layer 5 are arranged on a part of the surface of the connection layer 2 x , but the barrier layer 4 and the external connection layer 5 may be arranged on the entire surface of the connection layer 2 x .

[0031] Next, the second insulating layer 3 is formed on the conductor layer 2. Furthermore, an opening 3a ( Fig. 3I ) The second insulating layer 3 having the opening 3 a can be formed, for example, as follows. ·B-class insulating resin film bonding and hot pressing Formation of the opening 3a by laser irradiation on the insulating layer or the like Through the above steps, we can get Figure 2 ( Fig. 3I ) shown in the wiring circuit substrate.

[0032] Figure 4 This is a schematic diagram of another embodiment of a wired circuit board. Figure 4 The wiring circuit substrate shown in FIG. Figure 2 The wired circuit board shown in the figure also has the following structure. Figure 4 The illustrated wired circuit board includes a metal core layer 10 , a first insulating layer 1 , a conductor layer 2 , and a second insulating layer 3 . The metal core layer 10 is located on the surface of the first insulating layer 1 on the opposite side to the conductive layer 2. From another perspective, the first insulating layer 1 is located between the metal core layer 10 and the conductive layer 2. The conductor layer 2 is disposed on the first insulating layer 1. The conductor layer 2 is located between the first insulating layer 1 and the second insulating layer 3. The conductor layer 2 has wiring in a portion other than a connection layer 2x described later. Therefore, the conductor layer 2 can be referred to as a wiring layer. The second insulating layer 3 is disposed on the conductive layer 2. The second insulating layer 3 is not only located on the conductive layer 2, but also fills in spaces between the wirings of the conductive layer 2. The second insulating layer 3 has an opening 3a. The opening 3a is a through hole that penetrates the second insulating layer 3 in the thickness direction. The wired circuit board has a terminal portion 51a. The terminal portion 51a is located between the first insulating layer 1 and the second insulating layer 3, and is exposed to the outside through the opening portion 3a. The terminal portion 51a does not fill the opening portion 3a. The terminal portion 51a includes a connection layer 2x as a part of the conductor layer 2, a barrier layer 4 disposed on the connection layer 2x, and an external connection layer 5 disposed on the barrier layer 4. In the terminal portion 51a, the connection layer 2x, the barrier layer 4, and the external connection layer 5 are arranged in the thickness direction. In the terminal portion 51a, the connection layer 2x is located on the first insulating layer 1 side relative to the barrier layer 4, and the external connection layer 5 is located on the opposite side of the barrier layer 4 relative to the first insulating layer 1 side. The connection layer 2x is in contact with the barrier layer 4. The connection layer 2x is electrically connected to the external connection layer 5, but is not in physical contact. The external connection layer 5 contains copper.

[0033] Figure 4 The illustrated wired circuit board further includes a third insulating layer 21 , a second conductive layer 22 , a fourth insulating layer 23 , a third conductive layer 24 , a fifth insulating layer 25 , an interlayer connecting portion 27 , and a second terminal portion 51 b . The third insulating layer 21 is located on the surface of the metal core layer 10 opposite to the first insulating layer 1 side. The second conductive layer 22 is disposed on the third insulating layer 21 . The fourth insulating layer 23 covers the second conductive layer 22 . The third conductive layer 24 is disposed on the fourth insulating layer 23 . The fifth insulating layer 25 covers the third conductive layer 24 . The interlayer connection portion 27 passes through the through hole of the metal core layer 10 . The second terminal portion 51b is located between the first insulating layer 1 and the second insulating layer 3, and is exposed to the outside through the opening portion 3a. The second terminal portion 51b does not fill the opening portion 3a. The second terminal portion 51b includes a connection layer 2x as a part of the conductor layer 2, a barrier layer 4 disposed on the connection layer 2x, and an external connection layer 5 disposed on the barrier layer 4. In the second terminal portion 51b, the connection layer 2x, the barrier layer 4, and the external connection layer 5 are arranged in the thickness direction. In the second terminal portion 51b, the connection layer 2x is located on the first insulating layer 1 side relative to the barrier layer 4, and the external connection layer 5 is located on the opposite side of the barrier layer 4 relative to the first insulating layer 1 side. The connection layer 2x is in contact with the barrier layer 4. The connection layer 2x is electrically connected to the external connection layer 5, but is not in physical contact. The external connection layer 5 contains copper. The interlayer connection portion 27 electrically connects a portion of the second conductor layer 22 and the second terminal portion 51 b . The interlayer connection portion 27 is not electrically connected to the metal core layer 10 . A portion of the third conductor layer 24 is electrically connected to the interlayer connection portion 27 via a portion of the second conductor layer 22. The portion of the third conductor layer 24 electrically connected to the interlayer connection portion 27 functions as a terminal for external connection. Therefore, the fifth insulating layer 25 is provided with an opening 25a to expose a portion of the third conductor layer 24. A portion of the third conductor layer 24 electrically connected to the interlayer connection portion 27 is connected to, for example, a printed wiring board.

[0034] use Figure 5A to Figure 5K right Figure 4 An example of a method for manufacturing a wiring circuit substrate shown in FIG. Figure 4 The manufacturing method of the area indicated by the dotted line X in FIG.

[0035] First, a third insulating layer 21 ( Figure 5A The third insulating layer 21 can be formed by laminating a B-class insulating resin film and forming the insulating layer by heat pressing. The opening 21a can be formed by irradiating the formed insulating layer with laser light, for example.

[0036] Next, a patterned second conductor layer 22 ( Figure 5B ) The second conductor layer 22 can be formed, for example, as follows. Formation of a seed layer (not shown) on the third insulating layer 21 Formation of a photoresist film (not shown) on the seed layer · Formation of a resist pattern by selective exposure and development of a photoresist film (partial exposure of the seed layer) Electrolytic plating of the exposed seed layer ·Removal of photoresist film and unnecessary seed layer The formed patterned electrolytic plating layer becomes the second conductor layer 22. A part of the second conductor layer 22 fills the opening 21a.

[0037] Next, a fourth insulating layer 23 ( 23a ) having an opening 23a is formed so as to cover the second conductive layer 22 and expose a portion of the second conductive layer 22. Figure 5C The fourth insulating layer 23 can be formed by laminating a B-class insulating resin film and forming the insulating layer by heat pressing. The opening 23a can be formed by irradiating the formed insulating layer with laser light, for example.

[0038] Next, a patterned third conductor layer 24 ( Figure 5D ) The third conductor layer 24 can be formed, for example, as follows. Formation of a seed layer (not shown) on the fourth insulating layer 23 Formation of a photoresist film (not shown) on the seed layer · Formation of a resist pattern by selective exposure and development of a photoresist film (partial exposure of the seed layer) Electrolytic plating of the exposed seed layer ·Removal of photoresist film and unnecessary seed layer The formed patterned electrolytic plating layer becomes the third conductor layer 24. A part of the third conductor layer 24 fills the opening 23a and is electrically connected to the second conductor layer 22.

[0039] Next, a fifth insulating layer 25 ( 25 ) having an opening 25 a is formed so as to cover the third conductive layer 24 and expose a portion of the third conductive layer 24 . Figure 5E The fifth insulating layer 25 can be formed by laminating a B-class insulating resin film and forming the insulating layer by heat pressing. The opening 25a can be formed by irradiating the formed insulating layer with laser light, for example.

[0040] Next, a through hole 10a is formed in the metal core layer 10 so that the entire surface of the second conductor layer 22 on the metal core layer 10 side that fills the opening 21a of the third insulating layer 21 is exposed. Fig. 5F) The through hole 10a can be formed, for example, as follows. Formation of a photoresist film (not shown) on the metal core layer 10 · Formation of a resist pattern by selective exposure and development of the photoresist film (partial exposure of the metal core layer 10) Wet etching of the exposed metal core layer 10 (for example, wet etching using ferric chloride) Removal of photoresist film Through the above steps, the through hole 10 a is formed.

[0041] Next, a seed layer (not shown) is formed on the surface of the metal core layer 10 and the surface inside the through hole 10 a . Furthermore, a photoresist film 26 is formed on the surface of the metal core layer 10 on which the seed layer is formed. At this time, the photoresist film 26 is temporarily formed to fill the through hole 10a, and then, by selective exposure and development, the photoresist film ( Figure 5G ).

[0042] Next, an interlayer connection portion 27 ( Figure 5H The interlayer connection portion 27 can be formed by, for example, electrolytic plating on a seed layer (not shown).

[0043] Next, the unnecessary photoresist film 26 and the unnecessary seed layer (not shown) are removed. Fig.5I ).

[0044] Next, the first insulating layer 1 is formed so as to cover the metal core layer 10 and the interlayer connection portion 27 and fill the through hole 10a. Figure 5J ) The first insulating layer 1 can be formed by, for example, laminating a B-class insulating resin film and forming an insulating layer by heat pressing.

[0045] Next, an opening 1a is formed in the first insulating layer 1 so that the interlayer connection portion 27 is exposed. Figure 5K ) The opening 1a can be formed by, for example, laser irradiation or the like.

[0046] Next, use and use Figure 3A to Figure 3I Explanation Figure 2 The conductor layer 2, the terminal portion 51a, the second terminal portion 51b and the second insulating layer 3 are formed in the same manner as the method for manufacturing the wired circuit board shown in FIG. Figure 4 The wiring circuit substrate shown.

[0047] Figure 6 This is a schematic diagram of another embodiment of a wired circuit board. Figure 6 The wiring circuit substrate shown in the figure has a portion of the conductor layer 2 extending convexly in the through hole of the metal core layer 10 instead of Figure 4 The interlayer connection portion 27 of the through hole arranged in the metal core layer 10 in the wiring circuit substrate shown in the figure is responsible for the interlayer connection between the conductor layer 2 and the second conductor layer 22, and the opening portion of the third insulating layer 21 is not filled in the second conductor layer 22 ( Figure 4 In terms of the opening 21a in Figure 4 The wiring circuit board shown is different, but otherwise the same Figure 4 The wiring circuit substrates shown are the same.

[0048] use Figure 7A to Figure 7H right Figure 6 Here, a method for manufacturing the region indicated by the dotted line X in FIG. 7 will be mainly described.

[0049] First, a third insulating layer 21 ( Fig. 7A The third insulating layer 21 can be formed by, for example, laminating a B-class insulating resin film and forming an insulating layer by heat pressing.

[0050] Next, a patterned second conductor layer 22 ( Figure 7B ) The second conductor layer 22 can be formed, for example, as follows. Formation of a seed layer (not shown) on the third insulating layer 21 Formation of a photoresist film (not shown) on the seed layer · Formation of a resist pattern by selective exposure and development of a photoresist film (partial exposure of the seed layer) Electrolytic plating of the exposed seed layer ·Removal of photoresist film and unnecessary seed layer The formed patterned electrolytic plating layer serves as the second conductor layer 22 .

[0051] Next, a fourth insulating layer 23 ( 23a ) having an opening 23a is formed so as to cover the second conductive layer 22 and expose a portion of the second conductive layer 22. Figure 7C The fourth insulating layer 23 can be formed by laminating a B-class insulating resin film and forming the insulating layer by heat pressing. The opening 23a can be formed by irradiating the formed insulating layer with laser light, for example.

[0052] Next, a patterned third conductor layer 24 ( Fig.7D) The third conductor layer 24 can be formed, for example, as follows. Formation of a seed layer (not shown) on the fourth insulating layer 23 Formation of a photoresist film (not shown) on the seed layer · Formation of a resist pattern by selective exposure and development of a photoresist film (partial exposure of the seed layer) Electrolytic plating of the exposed seed layer ·Removal of photoresist film and unnecessary seed layer The formed patterned electrolytic plating layer becomes the third conductor layer 24 . A part of the third conductor layer 24 fills the opening 23 a and is electrically connected to the second conductor layer 22 .

[0053] Next, a fifth insulating layer 25 ( 25 ) having an opening 25 a is formed so as to cover the third conductive layer 24 and expose a portion of the third conductive layer 24 . Fig. 7E The fifth insulating layer 25 can be formed by laminating a B-class insulating resin film and forming the insulating layer by heat pressing. The opening 25a can be formed by irradiating the formed insulating layer with laser light, for example.

[0054] Next, a through hole 10a is formed at a given position of the metal core layer 10 ( Figure 7F The through hole 10a can be formed, for example, as follows. The predetermined position refers to a position where a part of the second conductor layer 22 exists in the thickness direction. Formation of a photoresist film (not shown) on the metal core layer 10 · Formation of a resist pattern by selective exposure and development of the photoresist film (partial exposure of the metal core layer 10) Wet etching of the exposed metal core layer 10 (for example, wet etching using ferric chloride) Removal of photoresist film Through the above steps, the through hole 10 a is formed.

[0055] Next, a first insulating layer 1 is formed so as to cover the metal core layer 10 and fill the through hole 10a. Figure 7G The first insulating layer 1 can be formed by, for example, laminating a B-class insulating resin film and forming an insulating layer by heat pressing.

[0056] Next, an opening 1a is formed, which penetrates the first insulating layer 1 in which the through hole 10a is buried and penetrates the third insulating layer 21 ( Figure 7H The opening 1a can be formed by, for example, irradiating the insulating layer with laser light.

[0057] Next, use and use Figure 3A to Figure 3I Explanation Figure 2 The conductor layer 2, the terminal portion 51a, the second terminal portion 51b and the second insulating layer 3 are formed in the same manner as the method for manufacturing the wired circuit board shown in FIG. Figure 6 At this time, when forming the conductor layer 2 by electrolytic plating, it is preferable to use an electrolytic plating solution that can fill the deep hole of the opening 1a.

[0058] Figure 8 This is a schematic diagram of another embodiment of a wired circuit board. Figure 8 The wiring circuit board shown in the figure is different from the wiring circuit board in that the interlayer connection portion 27 of the through hole arranged in the metal core layer 10 fills the opening of the third insulating layer 21 and the second conductor layer 22 in contact with the interlayer connection portion 27 is not convex. Figure 4 The wiring circuit board shown is different, but otherwise the same Figure 4 The wiring circuit substrates shown are the same.

[0059] (Semiconductor Package) The semiconductor package of the present invention includes the wiring circuit substrate of the present invention. The semiconductor package includes, for example, a semiconductor chip connected to a wiring circuit board. The semiconductor package includes, for example, a sealing resin that seals a semiconductor chip. Examples of semiconductor packages include FC-CSP (Flip Chip-Chip Scale Package), MIS-BGA (Molded Interconnect Substrate-Ball Grid Array) packages, ETS-BGA (Embedded Trace Substrate-Ball Grid Array) packages, Fan-out WLP (Wafer Level Package), Fan-in WLP, Fan-out PLP (Panel Level Package), Fan-in PLP, FC-BGA (Flip Chip-Chip, -Ball Grid Array), high-end 2.5D and 3D packages, and the like.

[0060] (Electronic equipment) The electronic device of the present invention includes the semiconductor package of the present invention. There are no particular restrictions on electronic devices, and examples include ICT infrastructure equipment such as servers, routers, supercomputers, mainframes, and workstations; antennas such as GPS antennas, antennas for wireless base stations, millimeter wave antennas, and RFID antennas; communication equipment such as portable phones, smart phones, PHS, PDAs, and tablet terminals; digital devices such as personal computers, televisions, digital cameras, digital video cameras, POS terminals, wearable terminals, and digital media players; in-vehicle electronic equipment such as electronic control system devices, in-vehicle communication equipment, car navigation equipment, millimeter wave radars, and in-vehicle camera modules; semiconductor testing equipment, high-frequency measuring equipment, etc. Explanation of symbols

[0061] 1: First insulation layer 2: Conductor layer 2x: Connection layer 3: Second insulation layer 3a: Opening 4: Barrier layer 4x: Barrier layer precursor 5: External connection layer 10: Metal core layer 15: Resist pattern 16: Resist pattern 21: The third insulation layer 22: Second conductor layer 23: The fourth insulation layer 23a: Opening 24: The third conductor layer 25: Fifth insulation layer 25a: Opening 26: Photoresist film 51: Terminal 51a: Terminal part 51b: Second terminal portion.

Claims

1. A wiring circuit substrate comprising: a first insulating layer; a conductive layer disposed on the first insulating layer; and a second insulating layer disposed on the conductive layer and having an opening, The wiring circuit substrate has a terminal portion, the terminal portion is located between the first insulating layer and the second insulating layer and is exposed to the outside through the opening portion. The terminal portion includes a connection layer as a part of the conductor layer, a barrier layer arranged on the connection layer, and an external connection layer arranged on the barrier layer. The external connection layer includes copper.

2. The wiring circuit substrate according to claim 1, wherein The barrier layer includes at least any one of chromium, titanium, and tungsten.

3. The wired circuit substrate according to claim 1, wherein: The conductor layer is a wiring layer having wiring in a portion other than the connection layer.

4. The wired circuit substrate according to claim 1, wherein: The wired circuit board further includes a metal core layer on a surface of the first insulating layer opposite to the conductor layer side.

5. The wired circuit substrate according to claim 4, wherein: The wired circuit board further includes a third insulating layer on a surface of the metal core layer opposite to the first insulating layer side.

6. The wired circuit substrate according to claim 1, wherein: The thickness of the external connection layer is 10 μm or less.

7. The wired circuit substrate according to claim 1, wherein: The barrier layer has a thickness of 1 μm or less. 8 . A semiconductor package comprising the wiring circuit substrate according to claim 1 . 9 . An electronic device comprising the semiconductor package according to claim 8 .

10. A method for manufacturing a wiring circuit substrate, for manufacturing the wiring circuit substrate according to any one of claims 1 to 7, comprising: forming a barrier layer precursor on the conductor layer formed on the first insulating layer; The process of forming an external connection layer on a portion of the barrier layer precursor by electrolytic plating using the barrier layer precursor as a seed layer, the portion of the barrier layer precursor being located on the connection layer which is a portion of the conductor layer and corresponding to the barrier layer; as well as A step of removing the barrier layer precursor except for a portion to be the barrier layer. 11 . The method for manufacturing a wired circuit board according to claim 10 , further comprising the step of forming a third insulating layer having the opening so that the external connection layer is exposed from the opening.

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