Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The preparation method comprises the following steps: providing a substrate, forming a first dielectric layer in an array region, and forming a first conductive layer in a peripheral region; forming a plurality of contact holes in the array region, wherein the contact holes penetrate through the first dielectric layer and expose the corresponding active regions; filling a second conductive layer in the contact hole; a third conductive layer and a second dielectric layer are formed on the sides, away from the substrate, of the first dielectric layer, the first conductive layer and the second conductive layer in a stacked mode; the second dielectric layer, the third conductive layer, the first dielectric layer and the second conductive layer are patterned to form a plurality of bit line structures, the second dielectric layer, the third conductive layer, the first dielectric layer and the second conductive layer are respectively patterned according to a preset sequence, and the first dielectric layer and the second conductive layer are respectively patterned by adopting different etching gases. The parasitic capacitance of the bit line structure is reduced, so that the performance and the reliability of the memory are effectively improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory commonly used in electronic devices such as computers, which is composed of multiple storage units. Among them, the storage unit includes: a storage capacitor, and a transistor electrically connected to the storage capacitor. The transistor includes a gate, a source region, and a drain region. The gate of the transistor is used to electrically connect to the word line structure, the source region of the transistor is used to form a bit line contact region and is electrically connected to the bit line structure, and the drain region of the transistor is used to form a storage node contact region and is electrically connected to the storage capacitor.

[0003] At present, in the manufacturing process of matching memory cells, the transistor is buried in the substrate, and the bit line structure can be connected to the bit line contact area through the contact hole and extend in a preset direction above the substrate. However, due to the footing effect in the dry etching process, the bottom of the extension part of the bit line structure located above the substrate is likely to have a size significantly larger than the middle and upper part of the extension part, which easily leads to a small distance between the bottom of the extension part and the adjacent bit line structure, resulting in a large parasitic capacitance of the bit line structure, which is easy to affect the performance and reliability of the memory. Summary of the invention

[0004] Based on this, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are beneficial to reducing the parasitic capacitance of the bit line structure, so as to effectively improve the performance and reliability of the memory.

[0005] On the one hand, an embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising the following steps.

[0006] A substrate is provided; the substrate has an array region and a peripheral region, and also includes: a plurality of active regions located in the array region.

[0007] A first dielectric layer is formed in the array region, and a first conductive layer is formed in the peripheral region. The first conductive layer is patterned to form a gate.

[0008] A plurality of contact holes are formed in the array region; the contact holes penetrate the first dielectric layer and expose the corresponding active regions.

[0009] The contact hole is filled with a second conductive layer.

[0010] A third conductive layer and a second dielectric layer are stacked on the side of the first dielectric layer, the first conductive layer and the second conductive layer facing away from the substrate.

[0011] The second dielectric layer, the third conductive layer, the first dielectric layer and the second conductive layer are patterned to form a plurality of bit line structures; wherein the second dielectric layer, the third conductive layer, the first dielectric layer and the second conductive layer are patterned in a preset order, and the first dielectric layer and the second conductive layer are patterned using different etching gases.

[0012] In some embodiments of the present disclosure, a top surface of the first dielectric layer facing away from the substrate is substantially flush with a top surface of the second conductive layer facing away from the substrate.

[0013] In some embodiments of the present disclosure, the forming of the first dielectric layer in the array region and the forming of the first conductive layer in the peripheral region include the following steps.

[0014] A first mask layer is formed, wherein the first mask layer covers the substrate in the array region and exposes the substrate in the peripheral region.

[0015] A first conductive layer is formed on the substrate in the peripheral region.

[0016] A first protection layer is formed on the first conductive layer.

[0017] The first mask layer is removed.

[0018] A first dielectric layer is formed on the substrate in the array region.

[0019] In some embodiments of the present disclosure, the first dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer. The step of forming the first dielectric layer on the substrate in the array region also includes the following steps.

[0020] A first sub-dielectric layer is formed on the substrate in the array region.

[0021] The first protective layer is removed.

[0022] A second mask layer is formed, wherein the second mask layer covers the first conductive layer and exposes the first sub-dielectric layer.

[0023] A second sub-dielectric layer is formed on the first sub-dielectric layer.

[0024] A second protection layer is formed on the second sub-dielectric layer.

[0025] removing the second mask layer;

[0026] Remove the second protective layer.

[0027] In some embodiments of the present disclosure, the first sub-dielectric layer and the second sub-dielectric layer are made of the same material.

[0028] In some other embodiments of the present disclosure, the forming of the first dielectric layer in the array region and the forming of the first conductive layer in the peripheral region include the following steps.

[0029] A first conductive material layer is formed on the substrate.

[0030] A third protection layer is formed on the first conductive material layer in the peripheral region.

[0031] The first conductive material layer in the array area is removed so that the first conductive material layer in the peripheral area constitutes a first conductive layer.

[0032] A third mask layer is formed, wherein the third mask layer covers the first conductive layer and exposes the substrate in the array region.

[0033] A first dielectric layer is formed on the substrate in the array region.

[0034] A fourth protection layer is formed on the first dielectric layer.

[0035] The third mask layer is removed.

[0036] The fourth protective layer is removed.

[0037] In some embodiments of the present disclosure, the etching gas for the first dielectric layer and the second dielectric layer includes: fluorine-containing gas or nitrogen. The etching gas for the second conductive layer includes: one or more of chlorine, hydrogen chloride or hydrogen bromide.

[0038] On the other hand, the embodiments of the present disclosure further provide a semiconductor structure, which can be prepared by using the semiconductor structure preparation methods in some of the above embodiments.

[0039] The semiconductor structure includes a substrate, a first conductive layer and a plurality of bit line structures. The substrate has an array region and a peripheral region, and the substrate includes: a plurality of active regions and a plurality of contact holes located in the array region; the contact holes expose the corresponding active regions. The first conductive layer is located in the peripheral region. The plurality of bit line structures are arranged on the substrate in parallel and spaced apart.

[0040] The bit line structure includes: a first part and a second part. The first part is located in the contact hole and is electrically connected to the active area. The first part includes: a second conductive layer, a third conductive layer, and a second dielectric layer stacked in sequence in a direction away from the active area. The second part is located on the substrate and is electrically connected to the first part. The second part includes: a first dielectric layer, a third conductive layer, and a second dielectric layer stacked in sequence in a direction away from the substrate, wherein the side wall of the first dielectric layer is flush with the side wall of the third conductive layer, and the side wall of the first dielectric layer is substantially perpendicular to the substrate.

[0041] In some embodiments of the present disclosure, a top surface of the first dielectric layer facing away from the substrate is substantially flush with a top surface of the second conductive layer facing away from the substrate.

[0042] In some embodiments of the present disclosure, the first dielectric layer includes: a first sub-dielectric layer and a second sub-dielectric layer stacked in a direction away from the substrate; the first sub-dielectric layer and the second sub-dielectric layer are made of the same material. The second dielectric layer includes: a third sub-dielectric layer and a fourth sub-dielectric layer stacked in a direction away from the substrate; the third sub-dielectric layer and the fourth sub-dielectric layer are made of the same material.

[0043] The embodiments of the present disclosure may or at least have the following advantages:

[0044] In the embodiment of the present disclosure, the first dielectric layer and the second conductive layer used to form the bit line structure are independently formed in a direction parallel to the substrate, and the second dielectric layer, the third conductive layer, the first dielectric layer and the second conductive layer used to form the bit line structure are patterned in a preset order, and the first dielectric layer and the second conductive layer are patterned using different etching gases. In this way, it is possible to ensure that the side wall of the first dielectric layer at the bottom of the bit line structure is kept as vertical as possible without damaging the isolation layer on the surface of the substrate, thereby effectively improving the problem of large parasitic capacitance between adjacent bit line structures caused by the large bottom size of the first dielectric layer due to the etching footing effect in the bit line structure. The embodiment of the present disclosure can reduce the parasitic capacitance of the bit line structure to effectively improve the performance and reliability of the memory.

[0045] The details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 A schematic flow chart of a method for preparing a semiconductor structure provided in some embodiments;

[0048] Figure 2 for Figure 1 A schematic flow chart of a step S200 in the method shown;

[0049] Figure 3 for Figure 2 A schematic flow chart of a step S250 in the method shown;

[0050] Figure 4 for Figure 1 A schematic flow chart of another step S200 in the method shown;

[0051] Figure 5 A structural comparison diagram of two semiconductor structures provided in some embodiments;

[0052] Figure 6 is a schematic top view of a semiconductor structure provided in some embodiments;

[0053] Figure 7 A schematic diagram of a structure obtained after forming a first sub-dielectric layer provided in some embodiments;

[0054] Figure 8 A schematic diagram of a structure obtained after forming a first photoresist pattern layer provided in some embodiments;

[0055] Fig. 9 A schematic diagram of a structure obtained after exposing a peripheral region substrate provided in some embodiments;

[0056] Fig.10 A schematic diagram of a structure obtained after forming a first conductive layer provided in some embodiments;

[0057] Fig.11 A schematic diagram of a structure obtained after forming a first protective layer and removing a first mask layer provided in some embodiments;

[0058] Fig.12 A schematic diagram of a structure obtained after removing the first protective layer provided in some embodiments;

[0059] Fig.13 A schematic diagram of a structure obtained after forming a second photoresist pattern layer provided in some embodiments;

[0060] Fig.14 is a schematic diagram of a structure obtained after the first sub-dielectric layer is exposed, provided in some embodiments;

[0061] Fig.15 A schematic diagram of a structure obtained after forming a second sub-dielectric layer and a second protective layer provided in some embodiments;

[0062] Fig.16 A schematic diagram of a structure obtained after removing the second mask layer in the peripheral area provided in some embodiments;

[0063] Fig.17 A schematic diagram of a structure obtained after forming a first dielectric layer in an array region and a first conductive layer in a peripheral region provided in some embodiments;

[0064] Fig.18 A schematic diagram of a structure obtained after forming a first conductive material layer provided in some embodiments;

[0065] Fig.19 A schematic diagram of a structure obtained after a third protective layer is formed in a peripheral region provided in some embodiments;

[0066] Fig. 20 A schematic diagram of a structure obtained after a first conductive layer is formed in a peripheral region provided in some embodiments;

[0067] Fig.21 A schematic diagram of a structure obtained after forming a third photoresist pattern layer provided in some embodiments;

[0068] Fig. 22 A schematic diagram of a structure obtained after exposing the first sub-dielectric layer in the array area provided in some embodiments;

[0069] Fig.23 A schematic diagram of a structure obtained after a second sub-dielectric layer is formed in an array region provided in some embodiments;

[0070] Fig.24 A schematic diagram of a structure obtained after a fourth protective layer is formed in an array region provided in some embodiments;

[0071] Fig.25 A schematic diagram of a structure obtained after exposing the first conductive layer in the peripheral area provided in some embodiments;

[0072] Fig.26 is a schematic diagram of a structure obtained after forming a fourth mask layer provided in some embodiments;

[0073] Fig. 27 A schematic diagram of a structure obtained after forming a contact hole in an array region provided in some embodiments;

[0074] Fig.28 A schematic diagram of a structure obtained after forming a second conductive material layer provided in some embodiments;

[0075] Fig.29 A schematic diagram of a structure obtained after forming a second conductive layer provided in some embodiments;

[0076] Fig.30 A schematic diagram of a structure obtained after forming a second dielectric layer and forming a gate structure in a peripheral region provided in some embodiments;

[0077] Fig.31 A schematic diagram of a structure obtained after forming a second interlayer dielectric layer provided in some embodiments;

[0078] Fig.32A schematic diagram of a structure obtained after forming a second anti-reflection layer provided in some embodiments;

[0079] Fig.33 A schematic diagram of a structure obtained after a hard mask layer is patterned provided in some embodiments;

[0080] Fig.34 A schematic diagram of a structure obtained after a bit line structure is formed in some embodiments;

[0081] Fig.35 It is a schematic diagram of the process of etching each thin film in a bit line structure provided in some embodiments.

[0082] Description of reference numerals:

[0083] 1-substrate, 01-bottom silicon nitride layer, 02-polysilicon layer, 03-titanium nitride layer, 04-tungsten metal layer, 05-top silicon nitride layer, 06-sidewall, 061-first silicon nitride layer, 062-silicon oxide layer, 063-second silicon nitride layer; AA-active area, BL-bit line structure, BLA-first part, BLB-second part, WL-word line structure, 11-isolation layer, 21-first dielectric layer, 211-first sub-dielectric layer, 212-second sub-dielectric layer, 22-second dielectric layer, 221-third sub-dielectric layer, 222-fourth sub-dielectric layer, 31-first conductive layer, 310-first conductive material layer, 32-second conductive layer, 33-third Conductive layer, 34-blocking layer, R1-array area, R2-peripheral area, H-contact hole, YM1-first mask layer, PR1-first photoresist pattern layer, YM2-second mask layer, PR2-second photoresist pattern layer, YM3-third mask layer, PR3-third photoresist pattern layer, 41-first protective layer, 42-second protective layer, 43-third protective layer, 44-fourth protective layer, YM4-fourth mask layer, SOH-spin coating mask layer, 51-pattern transfer layer, 61-gate dielectric layer, 62-side wall, 63-first interlayer dielectric layer, 64-second interlayer dielectric layer, 71-hard mask layer, 72-first anti-reflective layer, 73-second anti-reflective layer. DETAILED DESCRIPTION

[0084] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0085] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0086] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "electrically connected to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be an intervening element or layer. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0087] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0088] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present disclosure.

[0089] At present, in the manufacturing process of matching memory cells, the transistor is buried in the substrate, and the bit line structure can be connected to the bit line contact area through the contact hole and extend in a preset direction above the substrate. However, due to the footing effect in the dry etching process, the bottom of the extension part of the bit line structure located above the substrate is likely to have a size significantly larger than the middle and upper part of the extension part, which easily leads to a small distance between the bottom of the extension part and the adjacent bit line structure, resulting in a large parasitic capacitance of the bit line structure, which is easy to affect the performance and reliability of the memory.

[0090] Based on this, the embodiments of the present disclosure provide a method for preparing a semiconductor structure and a semiconductor structure, which are beneficial to reducing the parasitic capacitance of the bit line structure, so as to effectively improve the performance and reliability of the memory.

[0091] See also Figure 1 , an embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising the following steps.

[0092] S100, providing a substrate; the substrate has an array region and a peripheral region, and also includes: a plurality of active regions located in the array region.

[0093] S200, forming a first dielectric layer in the array region, forming a first conductive layer in the peripheral region, and patterning the first conductive layer to form a gate.

[0094] S300, forming a plurality of contact holes in the array region; the contact holes penetrate the first dielectric layer and expose the corresponding active regions.

[0095] S400, filling the contact hole with a second conductive layer.

[0096] S500 , stacking a third conductive layer and a second dielectric layer on a side of the first dielectric layer, the first conductive layer, and the second conductive layer facing away from the substrate.

[0097] S600, patterning the second dielectric layer, the third conductive layer, the first dielectric layer and the second conductive layer to form a plurality of bit line structures; wherein the second dielectric layer, the third conductive layer, the first dielectric layer and the second conductive layer are patterned in a preset order, and the first dielectric layer and the second conductive layer are patterned using different etching gases, respectively.

[0098] In the embodiment of the present disclosure, the first dielectric layer and the second conductive layer used to form the bit line structure are independently formed in a direction parallel to the substrate, and the second dielectric layer, the third conductive layer, the first dielectric layer and the second conductive layer used to form the bit line structure are patterned in a preset order, and the first dielectric layer and the second conductive layer are patterned using different etching gases. In this way, it is possible to ensure that the side wall of the first dielectric layer at the bottom of the bit line structure is kept as vertical as possible without damaging the isolation layer on the surface of the substrate, thereby effectively improving the problem of large parasitic capacitance between adjacent bit line structures caused by the large bottom size of the first dielectric layer due to the etching footing effect in the bit line structure. The embodiment of the present disclosure can reduce the parasitic capacitance of the bit line structure to effectively improve the performance and reliability of the memory.

[0099] In some embodiments of the present disclosure, a top surface of the first dielectric layer facing away from the substrate is substantially flush with a top surface of the second conductive layer facing away from the substrate.

[0100] In some embodiments of the present disclosure, please refer to Figure 2 In step S200, a first dielectric layer is formed in the array region, and a first conductive layer is formed in the peripheral region, including the following steps S210 to S250.

[0101] S210 , forming a first mask layer, wherein the first mask layer covers the substrate in the array area and exposes the substrate in the peripheral area.

[0102] S220, forming a first conductive layer on the substrate in the peripheral region.

[0103] S230, forming a first protective layer on the first conductive layer.

[0104] S240, removing the first mask layer.

[0105] S250, forming a first dielectric layer on the substrate in the array region.

[0106] In some embodiments of the present disclosure, the first dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer. Figure 3 In step S250, a first dielectric layer is formed on the substrate in the array area, and the following steps S251 to S257 are also included.

[0107] S251, forming a first sub-dielectric layer on the substrate in the array area.

[0108] S252, removing the first protective layer.

[0109] S253, forming a second mask layer, wherein the second mask layer covers the first conductive layer and exposes the first sub-dielectric layer.

[0110] S254, forming a second sub-dielectric layer on the first sub-dielectric layer.

[0111] S255, forming a second protection layer on the second sub-dielectric layer.

[0112] S256, removing the second mask layer;

[0113] S257, removing the second protective layer.

[0114] In some embodiments of the present disclosure, the first sub-dielectric layer and the second sub-dielectric layer are made of the same material.

[0115] In some other embodiments of the present disclosure, please refer to Figure 4 In step S200, a first dielectric layer is formed in the array region, and a first conductive layer is formed in the peripheral region, including the following steps S210' to S280'.

[0116] S210 ′, forming a first conductive material layer on the substrate.

[0117] S220 ′, forming a third protection layer on the first conductive material layer in the peripheral region.

[0118] S230 ′, removing the first conductive material layer in the array area, so that the first conductive material layer in the peripheral area constitutes a first conductive layer.

[0119] S240 ′, forming a third mask layer, wherein the third mask layer covers the first conductive layer and exposes the substrate in the array region.

[0120] S250 ′, forming a first dielectric layer on the substrate in the array region.

[0121] S260 ′, forming a fourth protection layer on the first dielectric layer.

[0122] S270 ′, removing the third mask layer.

[0123] S280', removing the fourth protective layer.

[0124] In some embodiments of the present disclosure, the etching gas for the first dielectric layer and the second dielectric layer includes: fluorine-containing gas or nitrogen. The etching gas for the second conductive layer includes: one or more of chlorine, hydrogen chloride or hydrogen bromide.

[0125] It can be understood that in some of the above embodiments, although Figure 1 to Figure 4 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 to Figure 4At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0126] In order to more clearly illustrate the method for preparing the semiconductor structure provided by the embodiment of the present disclosure, Figure 5 to Figure 35 Some possible implementation methods of the method for preparing the semiconductor structure are described in detail. In addition, before describing in detail the method for preparing the semiconductor structure provided by the embodiment of the present disclosure, for ease of understanding, a brief introduction is first given to the semiconductor structure provided by the embodiment of the present disclosure, and a structural comparison is made between the bit line structure in the related art and the present application. Figure 5 Figure (a) is a schematic diagram of a semiconductor structure in the related art. Figure 5 Figure (b) is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure.

[0127] See also Figure 5 In the semiconductor structure provided by the related art, the extension portion of the bit line structure BL located above the substrate 1 may include, for example, a bottom silicon nitride layer 01 and a polysilicon layer 02, a titanium nitride layer 03, a tungsten metal layer 04 and a top silicon nitride layer 05 stacked on the bottom silicon nitride layer 01. Since the polysilicon layer 02 will serve as a hard mask for patterning the bottom silicon nitride layer 01 when etching the bottom silicon nitride layer 01, the bottom silicon nitride layer 01 after patterning is likely to have a footing, resulting in a relatively small distance dimension D2 between the bottom silicon nitride layer 01 and the adjacent bit line structure BL, for example Figure 5 As shown in the middle (a), the distance dimension D2 is smaller than the distance dimension D1 between the tops of adjacent bit line structures BL. Accordingly, after the subsequent formation of the sidewall spacer 06 of the bit line structure BL (e.g., the NON sidewall spacer composed of the first silicon nitride layer 061, the silicon oxide layer 062, and the second silicon nitride layer 063), the sidewall spacer 06 will conformally cover the bottom silicon nitride layer 01, resulting in a large parasitic capacitance between adjacent bit line structures BL.

[0128] See also Figure 5 In (b) of FIG. 1 , the embodiment of the present disclosure changes the type of thin film to be deposited during the preparation of the extension portion of the bit line structure BL located above the substrate 1, and adjusts the etching sequence and process of each thin film accordingly (see the preparation method provided below for details), so that the extension portion includes a first dielectric layer 21, a third conductive layer 33, and a second dielectric layer 22 stacked in sequence in a direction away from the substrate 1, and ensures that the side wall of the first dielectric layer 21 is flush with the side wall of the third conductive layer 33, and the side wall of the first dielectric layer 21 is substantially perpendicular to the substrate 1. In this way, for example Figure 5 As shown in FIG. (b), the distance D3 between the bottom of the first dielectric layer 21 and the adjacent bit line structure BL can be consistent with the distance D1 between the tops of the adjacent bit line structures BL, that is, substantially equal. This can effectively reduce the parasitic capacitance of the bit line structure BL, thereby improving the performance and reliability of the semiconductor structure and memory.

[0129] Figure 6 A schematic top view of a semiconductor structure is shown. Figure 7 to Figure 34 In the aa views, bb views, cc views, dd views and ee views shown, the aa view corresponds to Figure 6 The cross-sectional view along the aa direction is shown in the figure, and the bb view corresponds to Figure 6 The cross-sectional view along the bb direction is shown in the figure, and the cc view corresponds to Figure 6 The cross-sectional view along the cc direction is shown in the figure, and the dd view corresponds to Figure 6 The cross-sectional view along the dd direction is shown in the figure, and the ee view corresponds to Figure 6 Schematic cross-sectional view along the ee direction.

[0130] In step S100, refer to Figure 6 and Figure 7 A substrate 1 is provided, wherein the substrate 1 has an array region R1 and a peripheral region R2. In addition, the substrate 1 further includes: a plurality of active regions AA located in the array region R1.

[0131] For example, the substrate 1 can be made of semiconductor material, insulating material, conductor material or any combination of their material types. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on insulator, etc.

[0132] For example, a shallow trench isolation structure STI is provided in the substrate 1. The shallow trench isolation structure STI can isolate a plurality of active areas AA arranged in an array in the array region R1 of the substrate 1.

[0133] In some examples, the shallow trench isolation (STI) structure includes but is not limited to silicon oxide (SiO 2 For example, the shallow trench isolation structure STI may also be formed by stacking multiple isolation layers.

[0134] It can be understood that the peripheral region R1 of the substrate 1 can also be isolated by the shallow trench isolation structure STI to form a plurality of active regions for accommodating the planar transistors required in the external circuit.

[0135] For example, see Figure 6 The array region R1 of the substrate 1 is usually also provided with a plurality of word line structures WL and a plurality of bit line structures BL which are arranged in parallel and spaced apart to match the distribution of the active region AA. The word line structure WL extends, for example, along the X direction, and the word line structure WL can be buried in the substrate 1, for example Figure 7 As shown in . The internal composition of the word line structure WL is not described in detail in the embodiment of the disclosure. The bit line structure BL, for example, extends along the Y direction. The preparation of the bit line structure BL can refer to the subsequent related steps in the embodiment of the disclosure. The aforementioned X direction and Y direction intersect, for example, are orthogonal.

[0136] Please continue reading Figure 7 After the word line structure WL is formed in the substrate 1, an isolation layer 11 may be formed on the surface of the substrate 1 in the array region R1 to cover the top surface of the word line structure WL and the surface of the substrate 1. The isolation layer 11 is, for example, a silicon oxide layer.

[0137] In some of the following embodiments, taking the first dielectric layer 21 including the first sub-dielectric layer 211 and the second sub-dielectric layer 212 as an example, two different implementation processes are respectively given for step S200.

[0138] In some embodiments, see Figure 7 to Figure 17 , step S200 may include the following steps S210 to S250, and step S250 may include the following steps S251 to S257.

[0139] In step S251, refer to Figure 7 , a first sub-dielectric layer 211 is formed on the substrate 1 in the array region R1 , for example, the first sub-dielectric layer 211 can be formed on the surface of the isolation layer 11 . In this way, the isolation layer 11 is advantageously etched and protected by the first sub-dielectric layer 211 .

[0140] In addition, it can be understood that the first sub-dielectric layer 211 can be adaptively formed in any step before the subsequent formation of the second sub-dielectric layer 212 , which is also allowed.

[0141] In step S210, refer to Figure 8 and Fig. 9 , a first mask layer YM1 is formed, and the first mask layer YM1 covers the substrate 1 of the array region R1 and exposes the substrate 1 of the peripheral region R2.

[0142] Illustratively, the first mask layer YM1 includes, but is not limited to, a spin coating mask layer.

[0143] For example, the first mask layer YM1 can be firstly entirely covered on the substrate 1, for example, covering the surface of the first sub-dielectric layer 211 of the array region R1 and the surface of the substrate 1 of the peripheral region R2 (for example, the surface of the shallow trench isolation structure STI); then, the first mask layer YM1 of the peripheral region R2 is etched away through the pattern in the first photoresist pattern layer PR1 formed on the first mask layer YM1 to expose the substrate 1 of the peripheral region R2.

[0144] In step S220, refer to Fig.10 , a first conductive layer 31 is formed on the substrate 1 in the peripheral region R2.

[0145] For example, Fig.10 and Fig.11 As shown in the figure, on the basis of retaining the first mask layer YM1 on the substrate 1 in the array area R1, the first conductive layer 31 can be first deposited as a whole layer on the substrate 1, for example, covering the surface of the first mask layer YM1 in the array area R1 and the surface of the substrate 1 in the peripheral area R2; then, the first conductive layer 31 located in the peripheral area R2 is obtained by removing the first mask layer YM1 and the first conductive layer 31 thereon.

[0146] For example, the first conductive layer 31 includes but is not limited to a polysilicon layer. After patterning, the first conductive layer 31 can form a gate of a planar transistor on the substrate 1 in the peripheral region R2.

[0147] In step S230, please continue to refer to Fig.10 , a first protection layer 41 is formed on the first conductive layer 31. The orthographic projection of the first protection layer 41 on the substrate 1 overlaps with the orthographic projection of the first conductive layer 31 on the substrate 1.

[0148] By way of example, the first protection layer 41 includes, but is not limited to, a photoresist material layer.

[0149] In step S240, refer to Fig.11 , remove the first mask layer YM1 to expose the first sub-dielectric layer 211 of the array region R1.

[0150] For example, the first mask layer YM1 may be removed by using a wet etching process.

[0151] In step S252, refer to Fig.12 , remove the first protection layer 41, so that the first conductive layer 31 of the peripheral region R2 is exposed.

[0152] In step S253, refer to Fig.13 and Fig.14 , a second mask layer YM2 is formed, the second mask layer YM2 covers the first conductive layer 31 and exposes the first sub-dielectric layer 211 .

[0153] Illustratively, the second mask layer YM2 includes, but is not limited to, a spin coating mask layer.

[0154] For example, the second mask layer YM1 can be first formed as a whole layer on the substrate 1, for example, covering the surface of the first sub-dielectric layer 211 in the array area R1 and the surface of the first conductive layer 31 in the peripheral area R2; then, the second mask layer YM2 in the array area R1 is etched and removed through the pattern in the second photoresist pattern layer PR2 formed on the second mask layer YM2, so that the second mask layer YM2 covers the first conductive layer 31 in the peripheral area R2 and exposes the first sub-dielectric layer 211 in the array area R1.

[0155] In step S254, refer to Fig.15 and Fig.16 , a second sub-dielectric layer 212 is formed on the first sub-dielectric layer 211 .

[0156] By way of example, the first sub-dielectric layer 211 and the second sub-dielectric layer 212 are made of the same material.

[0157] By way of example, the materials of the first sub-dielectric layer 211 and the second sub-dielectric layer 212 include, but are not limited to, silicon nitride.

[0158] For example, Fig.15 and Fig.16 As shown in the figure, on the basis of retaining the second mask layer YM2 on the substrate 1 in the peripheral region R2, the second sub-dielectric layer 212 can be first deposited as a whole layer on the substrate 1, for example, covering the surface of the first sub-dielectric layer 211 in the array region R1 and the surface of the second mask layer YM2 in the peripheral region R2; then, by removing the second mask layer YM2 and the second sub-dielectric layer 212 thereon, the second sub-dielectric layer 212 located in the array region R1 is obtained, and the second sub-dielectric layer 212 and the first sub-dielectric layer 211 together constitute the first dielectric layer 21.

[0159] In step S255, refer to Fig.16 , a second protective layer 42 is formed on the second sub-dielectric layer 212. The orthographic projection of the second protective layer 42 on the substrate 1 overlaps with the orthographic projection of the first dielectric layer 21 on the substrate 1.

[0160] By way of example, the second protection layer 42 includes, but is not limited to, a photoresist material layer.

[0161] In step S256, please continue to refer to Fig.16 , remove the second mask layer YM2 to expose the first conductive layer 31 in the peripheral region R2.

[0162] For example, the second mask layer YM2 may be removed by using a wet etching process or a dry etching process.

[0163] In step S257, refer to Fig.17 , the second protection layer 42 is removed, so that the first dielectric layer 21 (eg, the surface of the second sub-dielectric layer 212 facing away from the substrate 1 ) of the array region R1 is exposed.

[0164] In other embodiments, please combine Figure 7 , Figure 18 to Figure 25 as well as Fig.17 , step S200 may include the following steps S210' to S280'.

[0165] For example, before executing step S210', refer to Figure 7 Alternatively, the first sub-dielectric layer 211 may be formed on the substrate 1 in the array region R1 in advance. For example, the first sub-dielectric layer 211 may be formed on the surface of the isolation layer 11 .

[0166] On this basis, in step S210', refer to Fig.18 , a first conductive material layer 310 is formed on the substrate 1.

[0167] Here, the first conductive material layer 310 may be located on the entire substrate 1 , for example, covering the surface of the first sub-dielectric layer 211 in the array region R1 and the surface of the substrate 1 in the peripheral region R2 (for example, the surface of the shallow trench isolation structure STI).

[0168] By way of example, the first conductive material layer 310 includes, but is not limited to, a polysilicon layer.

[0169] In step S220', refer to Fig.19 , a third protection layer 43 is formed on the first conductive material layer 310 in the peripheral region R2.

[0170] By way of example, the third protection layer 43 includes, but is not limited to, a photoresist material layer.

[0171] In step S230', refer to Fig. 20 , the first conductive material layer 310 in the array region R1 is removed, so that the first conductive material layer 310 in the peripheral region R2 constitutes the first conductive layer 31 .

[0172] Here, it can be understood that the orthographic projection of the first conductive layer 31 on the substrate 1 overlaps with the orthographic projection of the third protective layer 43 on the substrate 1. The first conductive material layer 310 of the array region R1 can be removed by using the third protective layer 43 as a mask. Moreover, after removing the first conductive material layer 310 of the array region R1, the surface of the first sub-dielectric layer 211 in the array region R1 can also be exposed.

[0173] In step S240', refer to Fig.21 and Fig. 22, a third mask layer YM3 is formed, the third mask layer YM3 covers the first conductive layer 31 and exposes the substrate 1 of the array region R1.

[0174] Illustratively, the third mask layer YM3 includes, but is not limited to, a spin coating mask layer.

[0175] For example, Fig.21 and Fig. 22 As shown in the figure, the third mask layer YM3 can be first formed as a whole layer on the substrate 1, for example, covering the surface of the first sub-dielectric layer 211 in the array area R1 and the surface of the first conductive layer 31 in the peripheral area R2; then, the third mask layer YM3 of the array area R1 is etched and removed through the pattern in the third photoresist pattern layer PR3 formed on the third mask layer YM3, so that the third mask layer YM3 covers the first conductive layer 31 in the peripheral area R2 and exposes the first sub-dielectric layer 211 in the array area R1.

[0176] In step S250', please combine Figure 23 to Figure 25 It is understood that the first dielectric layer 21 is formed on the substrate 1 of the array region R1. Based on the first sub-dielectric layer 211 formed above, the second sub-dielectric layer 212 is formed on the surface of the first sub-dielectric layer 211 in step S250', so that the first dielectric layer 21 composed of the first sub-dielectric layer 211 and the second sub-dielectric layer 212 can be obtained.

[0177] Here, it can be understood that, in order to match different structures of the first dielectric layer 21 , the first dielectric layer 21 may be formed in other embodiments, which are also permitted.

[0178] For example, see Fig.23 On the basis of retaining the third mask layer YM3 on the substrate 1 in the peripheral region R2, the second sub-dielectric layer 212 can be firstly deposited on the substrate 1 in its entirety, for example, covering the surface of the first sub-dielectric layer 211 in the array region R1 and the surface of the second mask layer YM2 in the peripheral region R2; then, as Fig.24 and Fig.25 As shown in , after executing step S260' and step S270', the third mask layer YM3 and the second sub-dielectric layer 212 thereon can be removed synchronously, thereby obtaining the second sub-dielectric layer 212 located in the array region R1, and making the second sub-dielectric layer 212 and the first sub-dielectric layer 211 together constitute the first dielectric layer 21.

[0179] In step S260', refer to Fig.24 , a fourth protection layer 44 is formed on the first dielectric layer 21 .

[0180] By way of example, the fourth protection layer 44 includes, but is not limited to, a photoresist material layer.

[0181] In step S270', refer to Fig.25 , remove the third mask layer YM3 to expose the first conductive layer 31 in the peripheral region R2.

[0182] For example, the second sub-dielectric layer 212 on the third mask layer YM3 may be removed simultaneously in step S270 ′.

[0183] In step S280', refer to Fig.17 After the fourth protection layer 44 is removed, the first dielectric layer 21 (eg, the surface of the second sub-dielectric layer 212 facing away from the substrate 1 ) of the array region R1 can be exposed.

[0184] As described above, after executing step S200, the embodiment of the present disclosure can obtain a structure in which the first dielectric layer 21 is exposed in the array region R1 and the first conductive layer 31 is exposed in the peripheral region R2. Fig.17 as shown in .

[0185] In the above description of this specification, the terms “removing” and “etching” and the like can be implemented by using at least one etching process of wet etching and / or dry etching as required.

[0186] On this basis, see Fig.26 and Fig. 27 In step S300 , a plurality of contact holes H are formed in the array region R1 ; the contact holes H penetrate the first dielectric layer 21 and expose the corresponding active areas AA.

[0187] For example, see Fig.26 , a fourth mask layer YM4 is formed on the structure obtained after forming the first dielectric layer 21 and the first conductive layer 31. The fourth mask layer YM4, for example, includes a pattern transfer layer 51 and a spin-coating mask layer SOH stacked in sequence in a direction away from the substrate 1, and a mask pattern for defining a formation position of the contact hole H is formed in the pattern transfer layer 51 and the spin-coating mask layer SOH. Fig. 27 Based on the mask pattern in the fourth mask layer YM4 , the first dielectric layer 21 may be patterned and a contact hole H capable of exposing the corresponding active area AA may be formed in the first dielectric layer 21 .

[0188] In step S400, refer to Fig.28 and Fig.29 , the contact hole H is filled with a second conductive layer 32 .

[0189] For example, see Fig.28 , depositing a second conductive material layer 320 on the surface of each contact hole H and the pattern transfer layer 51. Fig.29 , the pattern transfer layer 51 and the second conductive material layer 320 on the surface of the first dielectric layer 21 are removed, so that the second conductive material layer 320 remaining in the contact hole H forms the second conductive layer 32 .

[0190] For example, the pattern transfer layer 51 and the second conductive material layer 320 on the surface of the first dielectric layer 21 may be removed by a grinding process.

[0191] By way of example, the second conductive material layer 320 includes, but is not limited to, a polysilicon material layer.

[0192] It is understood that in some embodiments, the surface of the first dielectric layer 21 is substantially flush with the surface of the first conductive layer 31. Accordingly, after removing the pattern transfer layer 51 and the second conductive material layer 320 above the surface of the first dielectric layer 21, the surface of the first conductive layer 31 in the peripheral region R2 is exposed.

[0193] In step S500, refer to Figure 30 to Figure 32 , a third conductive layer 33 and a second dielectric layer 22 are stacked on the side of the first dielectric layer 21 , the first conductive layer 31 and the second conductive layer 32 facing away from the substrate 1 .

[0194] By way of example, the third conductive layer 33 includes a metal material layer, such as a tungsten metal layer.

[0195] For example, before forming the third conductive layer 33, a barrier layer 34 may be formed on the side of the first dielectric layer 21, the first conductive layer 31 and the second conductive layer 32 facing away from the substrate 1. Accordingly, the third conductive layer 33 is formed on the surface of the barrier layer 34 facing away from the substrate 1.

[0196] For example, the barrier layer 34 includes at least one of a titanium layer or a titanium nitride layer. In this way, the barrier layer 34 can not only electrically connect the second conductive layer 32 and the third conductive layer 33, but also prevent the problem of ion diffusion between the third conductive layer 33 and the second conductive layer 32, for example, it can effectively prevent tungsten metal from diffusing into the polysilicon material, thereby avoiding affecting the electrical properties of the second conductive layer 32.

[0197] For example, the second dielectric layer 22 includes: a third dielectric layer 221 and a fourth dielectric layer 222 stacked in a direction away from the substrate 1; the third dielectric layer 221 and the fourth dielectric layer 222 are made of the same material, for example, silicon nitride. Moreover, the third dielectric layer 221 and the fourth dielectric layer 222 can be formed in different steps, for example, the third dielectric layer 221 can be formed first, and then the third dielectric layer 221 and the fourth dielectric layer 222 can be formed in different steps. Fig.30 and Fig.31 As shown in FIG. 1 , a fourth sub-dielectric layer 222 is formed after forming a gate structure in the peripheral region R2 , for example Fig.32 as shown in .

[0198] For some examples, see Fig.30After forming the barrier layer 34, the third conductive layer 33 and the third sub-dielectric layer 221 in sequence on the side of the first dielectric layer 21, the first conductive layer 31 and the second conductive layer 32 facing away from the substrate 1, the third sub-dielectric layer 221, the third conductive layer 33, the barrier layer 34, the first conductive layer 31 and the shallow trench isolation structure STI in the peripheral region R2 can be patterned first to form a gate structure in the peripheral region R2 and expose the active regions on both sides of the gate structure; wherein the portion of the shallow trench isolation structure STI retained at the bottom of the gate structure will constitute a gate dielectric layer 61 between the gate structure and the corresponding active region; the third sub-dielectric layer 221 in the peripheral region R2 can be used as a hard mask layer when patterning the gate structure.

[0199] See also Fig.31 , forming a sidewall 62 on the sidewall of the gate structure in the peripheral region R2. The sidewall 62 may be a single insulating layer or a stacked structure of multiple insulating layers, for example, the sidewall 62 includes a silicon nitride layer, a silicon oxide layer, and a silicon nitride layer stacked in sequence in a direction away from the sidewall of the gate structure.

[0200] Please continue reading Fig.31 , forming an interlayer dielectric layer covering the gate structure and the sidewall 62. The interlayer dielectric layer can be a single insulating layer or a stacked structure of multiple insulating layers. For example, the interlayer dielectric layer includes a first interlayer dielectric layer 63 and a second interlayer dielectric layer 64, wherein the first interlayer dielectric layer 63 includes but is not limited to a silicon nitride layer, and the second interlayer dielectric layer 64 includes but is not limited to a silicon oxide layer.

[0201] See also Fig.32 After forming the aforementioned interlayer dielectric layer, a fourth sub-dielectric layer 222 may be formed on the surface of the interlayer dielectric layer and the third sub-dielectric layer 221, and a mask structure for patterned etching of the second dielectric layer 22, the third conductive layer, the first dielectric layer 21 and the second conductive layer 32 may be formed on the surface of the fourth sub-dielectric layer 222, such as a stacked hard mask layer 71, a first anti-reflection layer 72, a spin-on mask layer SOH and a second anti-reflection layer 73.

[0202] By way of example, the hard mask layer 71 includes but is not limited to an amorphous carbon layer (ACL).

[0203] In step S600, refer to Fig.33 and Fig.34 , patterning the second dielectric layer 22, the third conductive layer 33, the first dielectric layer 21 and the second conductive layer 32 to form a plurality of bit line structures BL; wherein the second dielectric layer 22, the third conductive layer 33, the first dielectric layer 21 and the second conductive layer 32 are patterned respectively in a preset order, and the first dielectric layer 21 and the second conductive layer 32 are patterned respectively using different etching gases.

[0204] For example, see Fig.33 After forming a mask pattern in the hard mask layer 71, the fourth sub-dielectric layer 222, the third sub-dielectric layer 221, the third conductive layer 33, the barrier layer 34 and the second conductive layer 32 may be sequentially etched in the contact hole H in a preset order to form a first portion BLA of the bit line structure BL; the fourth sub-dielectric layer 222, the third sub-dielectric layer 221, the third conductive layer 33, the barrier layer 34 and the first dielectric layer 21 may be sequentially etched outside the contact hole H to form a second portion BLB of the bit line structure BL, for example Fig.34 as shown in .

[0205] For example, see Fig.35 In the process of forming the bit line structure BL, the first dielectric layer 21 and the second conductive layer 32 are patterned using different etching gases respectively; that is, the first dielectric layer 21 and the second conductive layer 32 are etched independently respectively.

[0206] For example, Fig.35 The order of (a) to (d) in the figure can be based on the mask pattern in the aforementioned hard mask layer 71, first patterning the second dielectric layer 22, then patterning the third conductive layer 33 and the barrier layer 34, then patterning the first dielectric layer 21, and finally patterning the second conductive layer 32, thereby obtaining the bit line structure BL.

[0207] By way of example, the etching gas for the first dielectric layer 21 and the second dielectric layer 22 includes, but is not limited to, fluorine-containing gas or nitrogen gas.

[0208] For example, the etching gas for the second conductive layer 32 includes, but is not limited to, one or more of chlorine, hydrogen chloride or hydrogen bromide.

[0209] The present disclosure also provides a semiconductor structure, which can be prepared by using the semiconductor structure preparation method in some of the above embodiments. The semiconductor structure also has the technical advantages of the above preparation method.

[0210] See also Figure 5 , Figure 6 and Fig.34 The semiconductor structure includes a substrate 1, a first conductive layer 31 and a plurality of bit line structures BL. The substrate 1 has an array region R1 and a peripheral region R2. The substrate 1 includes: a plurality of active regions AA and a plurality of contact holes located in the array region R1; the contact holes expose the corresponding active regions AA. The first conductive layer 31 is located in the peripheral region R2. A plurality of bit line structures BL are arranged on the substrate 1 in parallel and spaced apart.

[0211] The bit line structure BL includes: a first part BLA (for example, a connecting part connected to the active area AA) and a second part BLB (for example, an extension part located above the substrate 1). The first part BLA is located in the contact hole and is electrically connected to the active area AA. The first part BLA includes: a second conductive layer 32, a third conductive layer 33, and a second dielectric layer 22 stacked in sequence in a direction away from the active area AA. The second part BLB is located on the substrate 1 and is electrically connected to the first part BLA. The second part BLB includes: a first dielectric layer 21, a third conductive layer 33, and a second dielectric layer 22 stacked in sequence in a direction away from the substrate 1, wherein the sidewall of the first dielectric layer 21 is flush with the sidewall of the third conductive layer 33, and the sidewall of the first dielectric layer 21 is substantially perpendicular to the substrate 1.

[0212] In some embodiments, the first conductive layer 31 and the second conductive layer 32 include, but are not limited to, a polysilicon layer.

[0213] For example, the first conductive layer 31 is used to form a gate structure in the peripheral region R2 after patterning. However, it is understood that the gate structure in the peripheral region R2 may include the first conductive layer 31 and more film layers, such as the related records in some of the aforementioned embodiments, which will not be described in detail here.

[0214] In some embodiments, the third conductive layer 33 includes a metal material layer, such as a tungsten metal layer. The bit line structure BL also includes a barrier layer 34 located on a surface of the third conductive layer 33 close to the substrate 1; that is, a barrier layer 34 is further provided between the third conductive layer 33 and the second conductive layer 32 of the first part BLA, and a barrier layer 34 is further provided between the third conductive layer 33 and the first dielectric layer 21 of the second part BLB.

[0215] Illustratively, the barrier layer 34 includes, but is not limited to, at least one of a titanium layer or a titanium nitride layer.

[0216] In some embodiments, the top surface of the first dielectric layer 21 facing away from the substrate 1 is substantially flush with the top surface of the second conductive layer 32 facing away from the substrate 1 .

[0217] In some embodiments, the first dielectric layer 21 includes: a first sub-dielectric layer 211 and a second sub-dielectric layer 212 stacked in a direction away from the substrate 1. The first sub-dielectric layer 211 and the second sub-dielectric layer 212 are made of the same material, for example including but not limited to silicon nitride.

[0218] In some embodiments, the second dielectric layer 22 includes: a third sub-dielectric layer 221 and a fourth sub-dielectric layer 222 stacked in a direction away from the substrate 1. The third sub-dielectric layer 221 and the fourth sub-dielectric layer 222 are made of the same material, for example including but not limited to silicon nitride.

[0219] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0220] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0221] The above-mentioned embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, It is characterized in that include: providing a substrate; The substrate has an array region and a peripheral region, and further comprises: a plurality of active regions located in the array region; forming a first dielectric layer in the array region and forming a first conductive layer in the peripheral region; and forming a gate after patterning the first conductive layer; forming a plurality of contact holes in the array region; the contact holes penetrate the first dielectric layer and expose the corresponding active regions; Filling the contact hole with a second conductive layer; Forming a third conductive layer and a second dielectric layer by stacking on the side of the first dielectric layer, the first conductive layer and the second conductive layer away from the substrate; patterning the second dielectric layer, the third conductive layer, the first dielectric layer and the second conductive layer to form a plurality of bit line structures; The second dielectric layer, the third conductive layer, the first dielectric layer and the second conductive layer are patterned respectively according to a preset sequence, and the first dielectric layer and the second conductive layer are patterned respectively using different etching gases.

2. The method for preparing a semiconductor structure according to claim 1, It is characterized in that A top surface of the first dielectric layer facing away from the substrate is substantially flush with a top surface of the second conductive layer facing away from the substrate.

3. The method for preparing a semiconductor structure according to claim 1 or 2, It is characterized in that The forming of the first dielectric layer in the array region and the forming of the first conductive layer in the peripheral region comprises: forming a first mask layer, wherein the first mask layer covers the substrate in the array area and exposes the substrate in the peripheral area; forming the first conductive layer on the substrate in the peripheral region; forming a first protective layer on the first conductive layer; removing the first mask layer; The first dielectric layer is formed on the substrate in the array region.

4. The method for preparing a semiconductor structure according to claim 3, It is characterized in that The forming of the first dielectric layer on the substrate in the array region further comprises: forming a first sub-dielectric layer on the substrate in the array region; removing the first protective layer; forming a second mask layer, wherein the second mask layer covers the first conductive layer and exposes the first sub-dielectric layer; forming a second sub-dielectric layer on the first sub-dielectric layer; forming a second protective layer on the second sub-dielectric layer; removing the second mask layer; removing the second protective layer; The first dielectric layer includes the first sub-dielectric layer and the second sub-dielectric layer.

5. The method for preparing a semiconductor structure according to claim 4, It is characterized in that The first sub-dielectric layer and the second sub-dielectric layer are made of the same material.

6. The method for preparing a semiconductor structure according to claim 1 or 2, It is characterized in that The forming of the first dielectric layer in the array region and the forming of the first conductive layer in the peripheral region comprises: forming a first conductive material layer on the substrate; forming a third protective layer on the first conductive material layer in the peripheral area; removing the first conductive material layer in the array area so that the first conductive material layer in the peripheral area constitutes the first conductive layer; forming a third mask layer, wherein the third mask layer covers the first conductive layer and exposes the substrate in the array area; forming the first dielectric layer on the substrate in the array region; forming a fourth protective layer on the first dielectric layer; removing the third mask layer; The fourth protective layer is removed.

7. The method for preparing a semiconductor structure according to claim 1, It is characterized in that The etching gas for the first dielectric layer and the second dielectric layer includes: fluorine-containing gas or nitrogen; The etching gas for the second conductive layer includes one or more of chlorine, hydrogen chloride or hydrogen bromide.

8. A semiconductor structure, It is characterized in that include: A substrate having an array region and a peripheral region; The substrate comprises: a plurality of active regions and a plurality of contact holes located in the array region; the contact holes expose the corresponding active regions; A first conductive layer, located in the peripheral area; A plurality of bit line structures are arranged in parallel and spaced apart on the substrate; Wherein, the bit line structure comprises: A first portion is located in the contact hole and electrically connected to the active area; the first portion comprises: a second conductive layer, a third conductive layer, and a second dielectric layer stacked in sequence in a direction away from the active area; The second part is located on the substrate and electrically connected to the first part; the second part includes: a first dielectric layer, a third conductive layer and a second dielectric layer stacked in sequence in a direction away from the substrate; the side wall of the first dielectric layer is flush with the side wall of the third conductive layer, and the side wall of the first dielectric layer is approximately perpendicular to the substrate.

9. The semiconductor structure according to claim 8, It is characterized in that A top surface of the first dielectric layer facing away from the substrate is substantially flush with a top surface of the second conductive layer facing away from the substrate.

10. The semiconductor structure according to claim 8 or 9, It is characterized in that The first dielectric layer comprises: a first sub-dielectric layer and a second sub-dielectric layer stacked in a direction away from the substrate; the first sub-dielectric layer and the second sub-dielectric layer are made of the same material; The second dielectric layer includes: a third sub-dielectric layer and a fourth sub-dielectric layer stacked in a direction away from the substrate; the third sub-dielectric layer and the fourth sub-dielectric layer are made of the same material.

Images