Method of manufacturing semiconductor device

Abstract

The invention relates to a method of manufacturing a semiconductor device. An amorphous silicon film is formed on the semiconductor substrate in the first to fourth regions. The silicon film in the first region and the fourth region is removed such that the silicon film in the second region and the third region is left. The polycrystalline silicon film is formed by crystallizing the silicon film by heat treatment.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-206254 filed on December 6, 2023, including specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a method of manufacturing a semiconductor device, and in particular to a method of manufacturing a semiconductor device including a ferroelectric memory cell Background Art

[0004] In recent years, a ferroelectric memory cell using a ferroelectric film has been developed as a semiconductor memory element operating at a low voltage. The ferroelectric memory cell is a nonvolatile memory cell capable of changing a write state and an erase state by controlling the polarization direction of a ferroelectric.

[0005] The disclosed techniques are listed below.

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2018-96243

[0007] Patent Document 1 discloses a semiconductor device in which a ferroelectric memory cell and a MISFET (Metal Insulator Field Effect Transistor) constituting a logic circuit are mounted together.

[0008] In the manufacturing method disclosed in Patent Document 1, first, a gate insulating film is formed on a semiconductor substrate in each of a memory cell region and a peripheral region located at the periphery of the memory cell region. Then, a ferroelectric film is formed on each of the gate insulating films. Next, a titanium nitride film is formed on the ferroelectric film. Next, the titanium nitride film and the ferroelectric film located in the peripheral region are selectively removed. Next, a polysilicon film is formed on the titanium nitride film in the memory cell region, and a polysilicon film is formed on the gate insulating film in the peripheral region. These polysilicon films are formed to serve as gate electrodes of ferroelectric memory cells and MISFETs. Summary of the invention

[0009] In the case of forming a silicon film on a titanium nitride film in a ferroelectric memory cell, conventionally, a polycrystalline silicon film is formed at a film formation temperature of about 600 degrees Celsius by a film formation process using a CVD (chemical vapor deposition) method. However, the inventors of the present application have shown that in this case, abnormal growth of a polycrystalline silicon film is likely to occur on the titanium nitride film. Therefore, the inventors of the present application considered forming an amorphous silicon film at a temperature lower than the film formation temperature of the polycrystalline silicon film, rather than the polycrystalline silicon film.

[0010] At the same time, in the peripheral area, a resistor element and the like are also formed as a semiconductor element different from the MISFET. The silicon film constituting the resistor element is formed by the same manufacturing steps as the silicon film of the ferroelectric memory cell and the silicon film of the MISFET. Here, it has been found that if the resistor element is formed by an amorphous silicon film in consideration of the abnormal growth of the polysilicon film, the characteristics of the resistor element will fluctuate. Specifically, it has been found that the sheet resistance of the resistor element becomes lower than the sheet resistance in the case where the resistor element is previously formed by the polysilicon film. Therefore, there is a need for a technology that can improve the reliability of a semiconductor device by suppressing the fluctuation of the characteristics of the resistor element and suppressing the abnormal growth in the ferroelectric memory cell.

[0011] For example, it is conceivable to form an amorphous silicon film in the memory cell region and the peripheral region, and adjust the sheet resistance by selectively implanting ions. Specifically, by performing a first ion implantation on the silicon film located in the memory cell region, and performing a second ion implantation on the silicon film located in the peripheral region at a dose lower than the first ion implantation, the reduction of the sheet resistance of the resistor element can be suppressed.

[0012] However, the number of manufacturing steps and masks required to perform ion implantation increases, resulting in an increase in manufacturing cost. In addition, when two types of resistance elements (p-type and n-type) are to be formed, the number of manufacturing steps and masks further increases.

[0013] If selective ion implantation is not performed, it is also conceivable to form an amorphous silicon film for a ferroelectric memory cell and a polysilicon film for a resistor element separately. In this case, it is necessary to selectively leave an amorphous silicon film only in the memory cell region and selectively leave a polysilicon film only in the peripheral region. Therefore, due to repeated formation and patterning of the silicon film, the number of manufacturing steps and masks increases, resulting in an increase in manufacturing cost.

[0014] Therefore, a technology capable of improving the reliability of semiconductor devices while suppressing an increase in manufacturing costs is needed. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0015] An overview of typical embodiments disclosed in this application will be briefly described below.

[0016] According to one embodiment, a method for manufacturing a semiconductor device includes the steps of forming an amorphous first silicon film on a semiconductor substrate located in a first region and a second region, removing the first silicon film located in the first region, forming a first polycrystalline silicon film by crystallizing the first silicon film by a first heat treatment, forming a ferroelectric film on the semiconductor substrate located in the first region and the first polycrystalline silicon film located in the second region, forming a metal film on the ferroelectric film, removing the metal film and the ferroelectric film located in the second region, and forming a second silicon film on the metal film located in the first region and the first polycrystalline silicon film located in the second region.

[0017] According to one embodiment, the reliability of a semiconductor device can be improved while suppressing an increase in manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment.

[0019] Figure 2 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment.

[0020] Figure 3 It's a picture. Figure 1 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0021] Figure 4 It's a picture. Figure 2 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0022] Figure 5 It's a picture. Figure 3 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0023] Figure 6 It's a picture. Figure 4 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0024] Figure 7 It's a picture. Figure 5 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0025] Figure 8 It's a picture. Figure 6 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0026] Fig. 9 It's a picture. Figure 7 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0027] Fig.10 It's a picture. Figure 8A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0028] Fig.11 It's a picture. Fig. 9 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0029] Fig.12 It's a picture. Fig.10 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0030] Fig.13 It's a picture. Fig.11 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0031] Fig.14 It's a picture. Fig.12 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0032] Fig.15 It's a picture. Fig.13 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0033] Fig.16 It's a picture. Fig.14 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0034] Fig.17 It's a picture. Fig.15 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0035] Fig.18 It's a picture. Fig.16 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0036] Fig.19 It's a picture. Fig.17 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0037] Fig. 20 It's a picture. Fig.18 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0038] Fig.21 It's a picture. Fig.19 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0039] Fig. 22 It's a picture. Fig. 20 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0040] Fig.23 It's a picture. Fig.21 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0041] Fig.24 It's a picture. Fig. 22 A cross-sectional view of a subsequent manufacturing process of a semiconductor device.

[0042] Fig.25 The graphs show data obtained from experiments by the inventors of the present application. DETAILED DESCRIPTION

[0043] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. In all the drawings used to describe the embodiments, components having the same function are represented by the same reference numerals, and their repeated descriptions are omitted. Moreover, in the following embodiments, the description of the same or similar parts is not repeated in principle unless particularly required.

[0044] (First embodiment)

[0045] <Method of Manufacturing Semiconductor Device>

[0046] The semiconductor device includes a region 1A and regions 2A, 3A, and 4A located at the periphery of the region 1A. Fig.23 and Fig.24 The semiconductor elements formed in each region are described.

[0047] like Fig.23 As shown, a ferroelectric memory cell MC as a semiconductor element is formed in region 1A. The ferroelectric memory cell MC is an electrically rewritable nonvolatile memory cell and includes a memory transistor MQ and a selection transistor 1Q. The memory transistor MQ has a ferroelectric film FE, and the write state and the erase state can be changed by controlling the polarization direction of the ferroelectric film FE. During selection and non-selection of the ferroelectric memory cell MC, the selection transistor 1Q controls the supply of a write voltage, an erase voltage, and a read voltage to the drain region of the memory transistor MQ.

[0048] In region 2A, a plurality of MISFETs are formed as semiconductor elements. The plurality of MISFETs include a plurality of n-type and p-type high withstand voltage MISFETs and a plurality of n-type and p-type low withstand voltage MISFETs. The plurality of high withstand voltage MISFETs constitute, for example, a part of an I / O circuit. The low withstand voltage MISFET is driven at a voltage lower than that of the high withstand voltage MISFET and includes a gate insulating film thinner than that of the high withstand voltage MISFET. The plurality of low withstand voltage MISFETs constitute a logic circuit including, for example, a CPU and an SRAM. Fig.23 , an n-type high withstand voltage MISFET is illustrated as an example of the MISFET formed in the region 2A.

[0049] like Fig.24As shown, a plurality of resistance elements RS1 as semiconductor elements are formed in the region 3A. The polysilicon film PL1 and the polysilicon film PL2 formed in the region 3A serve as the resistance elements RS1, and n-type or p-type impurities are introduced into the polysilicon film PL1 and the polysilicon film PL2. Fig.24 , the resistance element RS1 including the n type polysilicon film PL1 and the n type polysilicon film PL2 is illustrated as an example of the resistance element formed in the region 3A.

[0050] In the region 4A, a plurality of resistance elements RS2 as semiconductor elements are formed. The polysilicon film PL3 formed in the region 4A serves as the resistance element RS2, and n-type or p-type impurities are introduced into the polysilicon film PL3. Fig.24 , the resistance element RS2 including the n-type polysilicon film PL3 is illustrated as an example of the resistance element formed in the region 4A.

[0051] The following will refer to Figures 1 to 24 Each manufacturing step included in the manufacturing method of the semiconductor device according to the first embodiment is described.

[0052] like Figure 1 and Figure 2 As shown, first, a semiconductor substrate SUB made of single crystal silicon into which, for example, p-type impurities are introduced is prepared. Next, an n-type well region DNW is formed in the semiconductor substrate SUB located in the regions 1A to 4A by photolithography and ion implantation.

[0053] Next, a plurality of grooves are formed in the semiconductor substrate SUB located in the regions 1A to 4A by photolithography and anisotropic etching. Next, an insulating film IF1 is formed by a film forming process using, for example, a CVD method to fill the inside of the plurality of grooves. Next, the insulating film IF1 located outside the plurality of grooves is removed by a polishing process using a CMP (chemical mechanical polishing) method. The insulating film IF1 is used as an element isolation portion for isolating the semiconductor elements formed in each region. The depth of the groove is, for example, 300nm or more and 400nm or less.

[0054] Next, by photolithography and ion implantation, a p-type well region PW1 is formed in the semiconductor substrate SUB located in region 1A, a p-type well region PW2 is formed in the semiconductor substrate SUB located in region 2A, and a p-type well region PW3 is formed in the semiconductor substrate SUB located in regions 3A and 4A.

[0055] Furthermore, although not shown, n-type impurities such as arsenic or phosphorus are introduced into the semiconductor substrate SUB in the region 2A where the p-type MISFET is formed by photolithography and ion implantation, thereby forming an n-type well region.

[0056] like Figure 3 and Figure 4 As illustrated, a gate insulating film GI3 is formed on the semiconductor substrate SUB located in the regions 1A to 4A by, for example, thermal oxidation. The gate insulating film GI3 is, for example, a silicon oxide film, and has a thickness of, for example, 8 nm or more and 10 nm or less.

[0057] Next, a silicon film in an amorphous state AM1 is formed on the semiconductor substrate SUB located in the regions 1A to 4A via the gate insulating film GI3 or the insulating film IF1. The silicon film AM1 is formed by a film forming process using, for example, a CVD method, and is formed within a temperature range of 400 degrees Celsius or higher and 550 degrees Celsius or lower. The thickness of the silicon film AM1 is, for example, 15 nm or more and 30 nm or less.

[0058] Note that when the thickness of the silicon film AM1 is relatively small (such as 30 nm or less), the silicon film AM1 is formed in an amorphous state without crystallizing even if the temperature of the film formation process is, for example, 600 degrees Celsius or higher.

[0059] like Figure 5 and Figure 6 As illustrated, the silicon film AM1 located in the region 1A and the region 4A is removed, so that the silicon film AM1 located in the region 2A and the region 3A remains.

[0060] First, a resist pattern RP1 is formed on the silicon film AM1. The resist pattern RP1 has a pattern that selectively covers the silicon film AM1 located in the region 2A and the region 3A. Next, anisotropic etching is performed using the resist pattern RP1 as a mask to remove the silicon film AM1 exposed from the resist pattern RP1. Next, isotropic etching is performed using the resist pattern RP1 as a mask to remove the gate insulating film GI3 exposed from the resist pattern RP1. Thereafter, the resist pattern RP1 is removed by an ashing process.

[0061] like Figure 7 and Figure 8 As shown, first, a gate insulating film GI2 is formed on the semiconductor substrate SUB located in the region 1A, on the silicon film AM1 located in the region 2A, and on the silicon film AM1 located in the region 3A by, for example, thermal oxidation. The gate insulating film GI2 is, for example, a silicon oxide film, and has a thickness of, for example, 5 nm or more and 7 nm or less. Next, a resist pattern RP2 is formed on a portion of the gate insulating film GI2 located in the region 1A. Next, isotropic etching is performed using the resist pattern RP2 as a mask to remove the gate insulating film GI2 exposed from the resist pattern RP2. Thereafter, the resist pattern RP2 is removed by an ashing process.

[0062] The portion of the region 1A where the gate insulating film GI2 is left is used for the selection transistor 1Q. The portion of the region 1A where the gate insulating film GI2 is removed and the semiconductor substrate SUB is exposed is used for the memory transistor MQ. In the region 2A and the region 3A, the silicon film AM1 is exposed, but the thickness of the silicon film AM1 is reduced due to the presence of the gate insulating film GI2.

[0063] like Fig. 9 and Fig.10 As shown, the silicon film AM1 is crystallized by heat treatment to form a polysilicon film PL1. The heat treatment is performed in a nitrogen atmosphere at a temperature range of 800 degrees Celsius or higher and 1000 degrees Celsius or lower and for a time range of 10 seconds or longer and 100 seconds or shorter. In this state, the thickness of the polysilicon film PL1 is preferably 20 nm or less.

[0064] like Fig.11 and Fig.12 As shown, first, by thermal oxidation using an ISSG (In Situ Steam Generation) oxidation method, a gate insulating film GI1 is formed on the semiconductor substrate SUB located in the region 1A, on the polysilicon film PL1 located in the region 2A, and on the polysilicon film PL1 located in the region 3A. The gate insulating film GI1 is, for example, a silicon oxide film, and has a thickness of, for example, 1 nm or more and 5 nm or less.

[0065] Next, by using a film forming process such as an ALD (atomic layer deposition) method, a ferroelectric film FE is formed on the semiconductor substrate SUB located in the region 1A via the gate insulating film GI1 or the gate insulating film GI2, the ferroelectric film FE is formed on the polysilicon film PL1 located in the regions 2A and 3A via the gate insulating film GI1, and the ferroelectric film FE is formed on the semiconductor substrate SUB located in the region 4A via the insulating film IF1. In this state, the ferroelectric layer FE is in an amorphous state.

[0066] The ferroelectric film FE is HfO 2 film or HfO to which at least one of zirconium (Zr), silicon (Si), nitrogen (N), carbon (C) and aluminum (Al) is added 2 The thickness of the ferroelectric film FE is, for example, 4 nm or more and 20 nm or less.

[0067] Next, a metal film MF is formed on the ferroelectric film FE located in the regions 1A to 4A by using a film forming process such as a CVD method or a sputtering method. The metal film MF is, for example, a titanium nitride film. The thickness of the ferroelectric film FE is, for example, 10 nm or more and 20 nm or less.

[0068] Next, the ferroelectric film FE is crystallized by heat treatment to form an orthogonal ferroelectric film FE. The heat treatment is performed in a temperature range of 400 degrees Celsius or higher and 600 degrees Celsius or lower. Here, the metal film MF applies stress to the ferroelectric film FE during the heat treatment and controls the crystal orientation of the ferroelectric film FE. In other words, the metal film MF has a function of orienting the crystal phase of the ferroelectric film FE into an orthogonal crystal.

[0069] like Fig.13 and Fig.14 As illustrated, the metal film MF and the ferroelectric film FE located in the regions 2A to 4A are removed so that the metal film MF and the ferroelectric film FE located in the region 1A remain.

[0070] First, a resist pattern RP3 is formed on the metal film MF. The resist pattern RP3 has a pattern that selectively covers the metal film MF located in the region 1A. Next, anisotropic etching is performed using the resist pattern RP3 as a mask to remove the metal film MF and the ferroelectric film FE exposed from the resist pattern RP3. Thereafter, the resist pattern RP3 is removed by an ashing process.

[0071] In the above anisotropic etching, over-etching is performed so that the metal film MF and the ferroelectric film FE located in the regions 2A to 4A are surely removed. This over-etching also removes the gate insulating film GI1 formed on the polysilicon film PL1 in the regions 2A and 3A. In addition, due to the presence of the gate insulating film GI1, the thickness of the polysilicon film PL1 is reduced.

[0072] The polysilicon film PL1 functions as a protective film for protecting the gate insulating film GI2 located in the region 2A from the above-mentioned over-etching.

[0073] Here, we will describe Fig. 9 and Fig.10 The reason why the thickness of the polysilicon film PL1 is preferably 20 nm or less in the state of. The metal film MF and the ferroelectric film FE are formed not only on the upper surface of the polysilicon film PL1 but also on the side surface of the polysilicon film PL1. Therefore, as the thickness of the polysilicon film PL1 increases, the step difference also increases, and the height of the metal film MF and the ferroelectric film FE formed on the side surface of the polysilicon film PL1 also increases.

[0074] Therefore, even after removing the metal film MF and the ferroelectric film FE formed on the upper surface of the polysilicon film PL1, it is difficult to completely remove the metal film MF and the ferroelectric film FE formed on the side surface of the polysilicon film PL1. Therefore, in order to reduce such step difference and make it easier to completely remove the metal film MF and the ferroelectric film FE, the thickness of the polysilicon film PL1 is preferably as small as possible, and is preferably 20 nm or less.

[0075] In addition, considering the purpose of making the polysilicon film PL1 serve as a protective film for the gate insulating film GI2, it is not always necessary to form the polysilicon film PL1 in the region 3A. In addition, after removing the metal film MF and the ferroelectric film FE, the polysilicon film PL1 located in the region 2A and the region 3A may be removed.

[0076] In the first embodiment, the polysilicon film PL1 is intentionally formed in the region 3A, and the polysilicon film PL1 is left in the region 2A and the region 3 A. The reason for this will be described in detail later.

[0077] like Fig.15 and Fig.16 As shown in the figure, first, a silicon film is formed on the metal film MF located in the region 1A, a silicon film is formed on the polysilicon film PL1 located in the region 2A, a silicon film is formed on the polysilicon film PL1 located in the region 3A, and a silicon film is formed on the semiconductor substrate SUB located in the region 4A via the insulating film IF1.

[0078] The silicon film is formed by a film forming process using, for example, a CVD method, and is formed at a temperature range of 400 degrees Celsius or more and 550 degrees Celsius or less. The thickness of the silicon film is greater than that of the polysilicon film PL1, for example, 40 nm or more and 100 nm or less.

[0079] In the film formation process, an amorphous silicon film is usually formed. Therefore, in the region 1A and the region 4A, the silicon film is formed as a silicon film of an amorphous state AM2. On the other hand, in the region 2A and the region 3A, since the polycrystalline silicon film PL1 is used as a seed film, the silicon film is formed as a polycrystalline silicon film PL2.

[0080] If the thickness of the polysilicon film PL1 is too small, the polysilicon film PL1 may not be used as a seed film. In order to make the polysilicon film PL1 used as a seed film, it is preferred that the thickness of the polysilicon film PL1 is 5 nm or more. Moreover, considering the purpose of more easily completely removing the metal film MF and the ferroelectric film FE formed on the side surface of the polysilicon film PL1 as described above, it is preferred that the thickness of the polysilicon film PL1 is 5 nm or more and 20 nm or less.

[0081] Next, through photolithography and ion implantation, n-type impurities such as arsenic or phosphorus are introduced into the silicon film AM2 located in region 1A, the polycrystalline silicon film PL2 and the polycrystalline silicon film PL1 located in region 2A, the polycrystalline silicon film PL2 and the polycrystalline silicon film PL1 located in region 3A, and the silicon film AM2 located in region 4A.

[0082] In addition, although not shown in the figure, p-type impurities such as boron or boron difluoride are introduced into the polycrystalline silicon film serving as the gate electrode of the p-type MISFET in region 2A, the polycrystalline silicon film serving as the p-type resistance element in region 3A, and the amorphous silicon film serving as the p-type resistance element in region 4A through photolithography and ion implantation.

[0083] Thereafter, an insulating film IF2 is formed on the silicon film AM2 and the polysilicon film PL2 by a film forming process using, for example, a CVD method. The insulating film IF2 is, for example, a silicon nitride film and has a thickness of, for example, 20 nm or more and 40 nm or less.

[0084] exist Figures 17 to 20 In the illustrated manufacturing process, the silicon film AM2, the metal film MF and the ferroelectric film FE located in the region 1A are patterned, the polysilicon film PL2 and the polysilicon film PL1 located in the region 2A are patterned, the polysilicon film PL2 and the polysilicon film PL1 located in the region 3A are patterned, and the silicon film AM2 located in the region 4A is patterned.

[0085] like Fig.17 and Fig.18 As shown, first, a resist pattern RP4 is formed on the insulating film IF2. The resist pattern RP4 has a pattern that selectively covers a portion of the insulating film IF2 located in the regions 1A to 4A. Next, anisotropic etching is performed using the resist pattern RP4 as a mask to remove the insulating film IF2, the silicon film AM2, the polysilicon film PL2, and the polysilicon film PL1 exposed from the resist pattern RP4. Thereafter, the resist pattern RP4 is removed by an ashing process.

[0086] like Fig.19 and Fig. 20 As illustrated, first, anisotropic etching is performed using the insulating film IF2 as a mask to remove the metal film MF and the ferroelectric film FE exposed from the insulating film IF2 in the region 1A.

[0087] Next, n-type impurities such as arsenic or phosphorus are introduced into the semiconductor substrate SUB located in the regions 1A to 4A by photolithography and ion implantation, thereby forming n-type extension regions (impurity regions) EX.

[0088] Furthermore, although not shown, p-type impurities such as boron or boron difluoride are introduced into the semiconductor substrate SUB located in the region 2A by photolithography and ion implantation, thereby forming a p-type extension region as a source region or a drain region of the p-type MISFET.

[0089] like Fig.21 and Fig. 22As shown, first, in the regions 1A to 4A, a silicon oxide film and a silicon nitride film are sequentially formed on the semiconductor substrate SUB to cover the insulating film IF2 by using a film forming process such as a CVD method. Next, the silicon oxide film and the silicon nitride film are processed by anisotropic etching to form sidewall spacers SW. Note that the insulating film IF2 is removed by this anisotropic etching.

[0090] In region 1A, sidewall spacers SW are formed on each of the side surfaces of the ferroelectric film FE, the metal film MF, and the silicon film AM2. In regions 2A and 3A, sidewall spacers SW are formed on each of the side surfaces of the polysilicon film PL2 and the polysilicon film PL1. In region 4A, sidewall spacers SW are formed on the side surface of the silicon film AM2.

[0091] Next, by photolithography and ion implantation, n-type impurities such as arsenic or phosphorus are introduced into the semiconductor substrate SUB located in the regions 1A to 4A, thereby forming an n-type diffusion region (impurity region) ND. The diffusion region ND and the extension region EX form a part of the source region or a part of the drain region of the memory transistor MQ and the selection transistor 1Q in the region 1A, and form a part of the source region or a part of the drain region of the MISFET 2Q in the region 2A.

[0092] When the diffusion region ND is formed, n-type impurities are also introduced into the silicon film AM2 located in the region 1A, the polycrystalline silicon film PL2 and the polycrystalline silicon film PL1 located in the region 2A, the polycrystalline silicon film PL2 and the polycrystalline silicon film PL1 located in the region 3A, and the silicon film AM2 located in the region 4A.

[0093] Furthermore, although not shown, p-type impurities such as boron or boron difluoride are introduced into the semiconductor substrate SUB located in the region 2A by photolithography and ion implantation, thereby forming a p-type diffusion region as a source region or a drain region of the p-type MISFET.

[0094] When forming the p-type diffusion region, p-type impurities are also introduced into the polycrystalline silicon film serving as the gate electrode of the p-type MISFET in region 2A, the polycrystalline silicon film serving as the p-type resistance element in region 3A, and the amorphous silicon film serving as the p-type resistance element in region 4A.

[0095] like Fig.23 and Fig.24As shown, by heat treatment, the diffusion region ND and the extension region EX are activated, and the silicon film AM2 located in the region 1A and the region 4A is crystallized, thereby forming a polysilicon film PL3. The heat treatment is performed by an RTA (rapid thermal annealing) method in a nitrogen atmosphere at a temperature range of 1000 degrees Celsius or more and 1100 degrees Celsius or less and at a time range of 0.1 seconds or more and 1.0 seconds or less.

[0096] The polysilicon film PL3 and the metal film MF located in the region 1A are used as the gate electrode GE1 of the memory transistor MQ and the gate electrode GE2 of the selection transistor 1Q. The polysilicon film PL2 and the polysilicon film PL1 located in the region 2A are used as the gate electrode GE3 of the MISFET 2Q. The polysilicon film PL2 and the polysilicon film PL1 located in the region 3A are used as the resistance element RS1. The polysilicon film PL3 located in the region 4A is used as the resistance element RS2.

[0097] As described above, the ferroelectric memory cell MC including the memory transistor MQ and the selection transistor 1Q is formed in the region 1A, the MISFET 2Q is formed in the region 2A, the resistance element RS1 is formed in the region 3A, and the resistance element RS2 is formed in the region 4A.

[0098] <Main Features of First Embodiment>

[0099] like Fig.15 and Fig.16 As shown, when the silicon film for the gate electrode of the ferroelectric memory cell MC is formed on the metal film MF in the region 1A, the temperature of the film formation process is set to 400 degrees Celsius or higher and 550 degrees Celsius or lower. Therefore, a silicon film of an amorphous state AM2 is formed on the metal film MF. Therefore, the problem of abnormal growth of the polycrystalline silicon film that may occur when the polycrystalline silicon film is formed on the metal film MF can be solved.

[0100] On the other hand, in the region 3A, the silicon film formed by the same manufacturing step as the silicon film of the ferroelectric memory cell MC is applied to the resistance element RS1. Therefore, since it is not necessary to separately form a silicon film for the resistance element RS1, the manufacturing process can be simplified and an increase in manufacturing cost can be suppressed. When the amorphous silicon film AM2 is applied to the resistance element RS1, Fig.23 and Fig.24 The heat treatment shown in the figure crystallizes the silicon film AM2. However, in this case, it has been found that the sheet resistance of the resistance element RS1 becomes lower than the sheet resistance in the case where the resistance element is formed in advance from a polysilicon film.

[0101] Therefore, in the first embodiment, as shown in FIG. Fig. 9 and Fig.10As described, the polysilicon film PL1 is formed by crystallizing the silicon film AM1 formed in the region 2A and the region 3A. Further, the polysilicon film PL1 remains in the region 2A and the region 3A without being removed. Since the polysilicon film PL1 is used as a seed film in the region 2A and the region 3A when the silicon film of the amorphous state AM2 is formed, the silicon film in the region 2A and the region 3A is formed into the polysilicon film PL2.

[0102] Fig.25 A comparison between the resistance element RS1 (polysilicon film PL1 / polysilicon film PL2 ) of the first embodiment and a resistance element of a comparative example is illustrated. The resistance element of the comparative example is made of a polysilicon film obtained by crystallizing a silicon film in an amorphous state.

[0103] In the case of the resistor element of the comparative example, Fig.15 and Fig.16 The manufacturing steps shown and Fig.21 and Fig. 22 In the illustrated manufacturing steps, ions are implanted into the silicon film when the silicon film is in an amorphous state. One possible reason for the low sheet resistance is that the ion implantation into the amorphous silicon film increases the solid solubility. Moreover, the thickness of the amorphous silicon film is, for example, 40 nm or more and 100 nm or less. Another possible reason for the low sheet resistance is that the grain size in the polycrystalline silicon film crystallized from the amorphous state becomes larger.

[0104] In the first embodiment, since the polysilicon film PL1 is used as a seed film, when a silicon film is formed on the seed film, a large number of crystal nuclei exist in the silicon film. Therefore, it is assumed that the grain size in the polysilicon film PL3 of the first embodiment is smaller than that in the polysilicon film of the comparative example.

[0105] Note that, conventionally, a polysilicon film formed at a film formation temperature of about 600 degrees Celsius is used as a resistance element, but the sheet resistance of the resistance element RS1 of the first embodiment is almost the same as that of the conventional resistance element. In this way, in the first embodiment, the reduction in the sheet resistance of the resistance element RS1 can be suppressed, and the fluctuation of the characteristics of the resistance element RS1 can be suppressed, so that the reliability of the semiconductor device can be improved.

[0106] In addition, in the first embodiment, the resistance element RS2 is formed in the region 4A. Since the polysilicon film PL1 is removed in the region 4A, the resistance element RS2 is made of the polysilicon film PL3 obtained by crystallizing the silicon film in the amorphous state AM2. In other words, the resistance element RS2 corresponds to the resistance element of the comparative example and has a lower sheet resistance than the resistance element RS1.

[0107] Depending on the product specification, a plurality of resistor elements having different sheet resistances may be required. As described in the first embodiment, by simply leaving the polysilicon film PL1 in the region 3A and removing the polysilicon film PL1 in the region 4A, the resistor element RS1 and the resistor element RS2 having different sheet resistances can be obtained without adding any manufacturing steps. In the case of the first embodiment, an n-type resistor element RS1, a p-type resistor element RS1, an n-type resistor element RS2, and a p-type resistor element RS2 having different sheet resistances can be obtained.

[0108] Although the present disclosure made by the inventors of the present application has been specifically described above based on the embodiments, the present disclosure is not limited to the above embodiments and may be modified in various ways within the scope not departing from the gist of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, the semiconductor device comprising a first region in which a ferroelectric memory cell is formed and a second region located at a periphery of the first region, the method comprising: (a) preparing a semiconductor substrate; (b) forming a first silicon film in an amorphous state on the semiconductor substrate located in the first region and the second region; (c) after (b), removing the first silicon film located in the first region so that the first silicon film located in the second region remains; (d) after the step (c), forming a first polysilicon film by crystallizing the first silicon film through a first heat treatment; (e) after (d), forming a ferroelectric film on the semiconductor substrate located in the first region and on the first polysilicon film located in the second region; (f) after step (e), forming a metal film on the ferroelectric film located in the first region and the second region; (g) after step (f), removing the metal film and the ferroelectric film located in the second region so that the metal film and the ferroelectric film located in the first region remain; as well as (h) After (g), a second silicon film is formed on the metal film in the first region and on the first polysilicon film in the second region.

2. The method for manufacturing the semiconductor device according to claim 1, In (h), the second silicon film formed on the metal film is formed in an amorphous state, and the second silicon film formed on the first polysilicon film is formed as a second polysilicon film because the first polysilicon film serves as a seed film.

3. The method for manufacturing the semiconductor device according to claim 2, further comprising: (i) after step (h), patterning the second silicon film, the metal film, and the ferroelectric film in the first region, and patterning the first polysilicon film and the second polysilicon film in the second region; (j) after step (i), forming an impurity region in the semiconductor substrate located in the first region; as well as (k) After (j), the impurity region is activated and a third polysilicon film is formed by crystallizing the second silicon film located in the first region by a second heat treatment.

4. The method for manufacturing the semiconductor device according to claim 3, Wherein, after (k), the third polysilicon film and the metal film located in the first region are used as gate electrodes of the transistor included in the ferroelectric memory cell, and the first polysilicon film and the second polysilicon film located in the second region are used as gate electrodes of a resistance element or a MISFET.

5. The method for manufacturing the semiconductor device according to claim 4, wherein the semiconductor device further includes a third region located at the periphery of the first region and different from the second region, wherein in (b), the first silicon film is also formed in the third region, wherein in (c), the first silicon film located in the first region and the third region is removed so that the first silicon film located in the second region remains, wherein in said (e), said ferroelectric film is also formed in said third region, wherein in said (f), said metal film is also formed on said ferroelectric film located in said third region, wherein in (g), the metal film and the ferroelectric film located in the second region and the third region are removed so that the metal film and the ferroelectric film located in the first region remain, wherein in said (h), the second silicon film in an amorphous state is also formed on the semiconductor substrate located in the third region, wherein in said (i), said second silicon film located in said third region is also patterned, wherein in said (k), the fourth polysilicon film is formed by crystallizing the second silicon film located in the third region by the second heat treatment, and After (k), the first polysilicon film and the second polysilicon film located in the second region function as a first resistance element, and the fourth polysilicon film located in the third region functions as a second resistance element.

6. The method for manufacturing the semiconductor device according to claim 5, The sheet resistance of the second resistance element is lower than the sheet resistance of the first resistance element.

7. The method for manufacturing the semiconductor device according to claim 2, In the (h), the thickness of the first polysilicon film is 5 nm or greater.

8. The method for manufacturing the semiconductor device according to claim 7, In the (e), the thickness of the first polysilicon film is 20 nm or less.

9. The method for manufacturing the semiconductor device according to claim 1, The thickness of the second silicon film is greater than the thickness of the first polysilicon film.

10. The method for manufacturing the semiconductor device according to claim 9, wherein the thickness of the first polysilicon film is 5 nm or more and 20 nm or less, and wherein the thickness of the second silicon film is 40 nm or more and 100 nm or less.

11. The method for manufacturing the semiconductor device according to claim 1, Wherein in the (d), the first heat treatment is performed in a nitrogen atmosphere at a temperature range of 800 degrees Celsius or higher and 1000 degrees Celsius or lower and for a time range of 10 seconds or longer and 100 seconds or shorter.

12. The method for manufacturing the semiconductor device according to claim 1, In the (h), the second silicon film is formed at a temperature within a range of 400 degrees Celsius or higher and 550 degrees Celsius or lower.

13. The method for manufacturing the semiconductor device according to claim 1, The metal film is a titanium nitride film.

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