SiC UMOSFET super-junction four-terminal device resistant to single-particle irradiation effect and preparation method of SiC UMOSFET super-junction four-terminal device

Abstract

The invention provides a SiC UMOSFET super-junction four-terminal device capable of resisting a single-particle irradiation effect and a preparation method, and can be applied to the technical field of semiconductor devices. The device comprises a substrate; the drain electrode is arranged on the lower surface of the substrate; the N-type epitaxial layer is arranged on the upper surface of the substrate; the P column is arranged in the N-type epitaxial layer, and the thickness of the P column in the vertical direction does not exceed the thickness of the N-type epitaxial layer in the vertical direction; the P base region is close to one side of the upper surface of the N-type epitaxial layer and the upper surface of the P column; the source region is close to one side of the upper surface of the P base region; the gate trench is arranged on one side close to the upper surface of the N-type epitaxial layer; the P + injection region is arranged below the bottom of the gate trench; the N + injection region is arranged in the P + injection region; the control electrode is a control electrode groove formed in the N + injection region; the gate dielectric layer is arranged on the side wall of the gate groove; the gate is arranged on the upper surface of the gate dielectric layer; the interlayer dielectric is arranged on the upper surface of the grid electrode; and the source electrode is arranged on the upper surfaces of the interlayer dielectric and part of the source region.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and more specifically, to a SiCUMOSFET super junction four-terminal device resistant to single particle irradiation effects and a preparation method thereof. Background Art

[0002] With the increasing demand for applications, the electrical performance of traditional Si-based power devices has approached its physical performance limit, restricting the application and development of power semiconductor devices. Silicon carbide (SiC), especially SiC metal-oxide-semiconductor field-effect transistor (MOSFET), as a third-generation semiconductor material, has the advantages of wide bandgap, high breakdown field strength and high thermal conductivity, and has broad application prospects in the fields of high frequency, high voltage and high power.

[0003] However, with the development of SiC MOSFET, the relationship between on-resistance and breakdown voltage has limited its application in high-voltage fields, so exploring ways to break this limit will help further improve the performance of SiC MOSFET. In addition, SiC materials are susceptible to the radiation environment in space, and high-energy ion bombardment of SiC MOSFET can cause radiation damage, such as single event burnout (SEB) and single event gate rupture (SEGR). Summary of the invention

[0004] In view of this, the present disclosure provides a SiC UMOSFET super junction four-terminal device resistant to single particle irradiation effects and a preparation method thereof.

[0005] One aspect of the present disclosure provides a SiC UMOSFET super junction four-terminal device resistant to single particle irradiation effects, comprising:

[0006] substrate;

[0007] A drain electrode is arranged on the lower surface of the substrate;

[0008] An N-type epitaxial layer is disposed on the upper surface of the substrate;

[0009] A P column is disposed inside the N-type epitaxial layer, wherein the thickness of the P column along the vertical direction does not exceed the thickness of the N-type epitaxial layer along the vertical direction;

[0010] A P base region is arranged on a side close to the upper surface of the N-type epitaxial layer and the upper surface of the P column;

[0011] A source region, arranged on a side close to the upper surface of the P base region;

[0012] A gate trench is arranged on a side close to the upper surface of the N-type epitaxial layer;

[0013] A P+ implantation region is provided below the bottom of the gate trench;

[0014] An N+ injection region is arranged inside the P+ injection region;

[0015] A control electrode, arranged in a control electrode trench formed inside the N+ implantation region;

[0016] A gate dielectric layer, disposed on the sidewall of the gate trench;

[0017] A gate, disposed on the upper surface of the gate dielectric layer;

[0018] An interlayer dielectric is disposed on the upper surface of the gate;

[0019] The source electrode is arranged on the upper surface of the interlayer dielectric and part of the source region.

[0020] According to an embodiment of the present disclosure, the implantation depth of the N+ implantation region is 0.2-1.0 μm less than that of the P+ implantation region, and the width of the N+ implantation region is 0.1-1.0 μm less than that of the P+ implantation region.

[0021] According to an embodiment of the present disclosure, the width of the control electrode trench is 0.1-1.0 μm smaller than the width of the N+ implantation region, and the depth of the control electrode trench is 0.02-0.72 μm.

[0022] According to an embodiment of the present disclosure, the thickness of the N-type epitaxial layer in the vertical direction is 10-20 μm, and the doping concentration of the N-type epitaxial layer is 5e14-5e16 cm -3 .

[0023] According to an embodiment of the present disclosure, the thickness of the gate trench along the vertical direction is 0.5-1.5 μm, and the width of the gate trench along the horizontal direction is 0.3-2.0 μm.

[0024] According to an embodiment of the present disclosure, the thickness of the P+ injection region in the vertical direction is 0.3-1.0 μm, and the peak doping concentration of the P+ injection region is 1e16-5e19 cm -3 The upper surface of the P+ implantation region is arranged above the bottom of the gate trench.

[0025] According to the embodiment of the present disclosure, the peak doping concentration of the N+ implantation region is 1e17~5e21 cm -3 .

[0026] According to an embodiment of the present disclosure, the thickness of the P column in the vertical direction is 5.2-15.2 μm, the width of the P column in the horizontal direction is 1.5-5 μm, and the ion implantation concentration of the P column is 5e14-5e16 cm -3 .

[0027] Another aspect of the present disclosure provides a method for preparing a SiC UMOSFET super junction four-terminal device resistant to single particle irradiation effects, comprising:

[0028] forming an N-type epitaxial layer on a substrate;

[0029] forming a P column inside the N-type epitaxial layer;

[0030] forming a P base region on one side close to the upper surface of the N-type epitaxial layer and the upper surface of the P column;

[0031] forming a source region on one side close to the upper surface of the P base region;

[0032] forming a gate trench on one side close to the upper surface of the N-type epitaxial layer;

[0033] forming a P+ implantation region below the bottom of the gate trench;

[0034] forming an N+ implantation region inside the P+ implantation region;

[0035] forming a control electrode inside the N+ implantation region;

[0036] Depositing a gate dielectric layer and filling the gate trench with polysilicon to form a gate;

[0037] forming an interlayer dielectric on the upper surface of the gate;

[0038] A source electrode is formed on the upper surface of the interlayer dielectric and part of the source region.

[0039] A drain electrode is formed on the lower surface of the substrate.

[0040] According to an embodiment of the present disclosure, the step of forming a control electrode inside the N+ implantation region includes:

[0041] Forming a control electrode trench inside the N+ implantation region by etching;

[0042] Filling polysilicon inside the control electrode trench;

[0043] The redundant polysilicon is removed by photolithography and etching to form the control electrode.

[0044] According to the embodiments of the present disclosure, the SiC UMOSFET super junction four-terminal device 200 resistant to single particle radiation effect provided by the present disclosure replaces the conventional gate structure with a trench gate structure, which can significantly reduce the device size, reduce the on-resistance, and increase the current density; at the same time, the gate-drain capacitance of the trench gate structure is smaller, which can reduce the Miller effect of the device caused by the drain capacitance and enhance the dynamic characteristics of the device. In addition, a P-column super junction structure is formed in the drift region, which can not only improve the voltage resistance of the device, but also further reduce the on-resistance, thereby improving the compromise relationship between the breakdown voltage and the on-resistance. The SiC UMOSFET superjunction four-terminal device 200 that is resistant to single-particle irradiation effects adds a fourth control electrode below the gate trench, which can not only provide a steady supply of electrons to the N+ injection region to neutralize a large number of holes generated by single-particle incidence and avoid breakdown of the transient electric field concentration at the bottom of the gate dielectric layer, but also modulate the potential at the bottom of the trench gate to reduce the electric field of the gate dielectric layer, thereby further protecting the gate dielectric layer. In addition, the added control electrode can also adjust the control electrode potential to make the device work in different states, making it flexibly applicable to various scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0046] Figure 1 The cross-sectional structure diagram of a MOSFET device in the related art is schematically shown;

[0047] Figure 2 The cross-sectional structure diagram of a SiC UMOSFET super junction four-terminal device resistant to single particle irradiation effect according to an embodiment of the present disclosure is schematically shown;

[0048] Figure 3 A flow chart schematically shows a method for preparing a SiC UMOSFET super junction four-terminal device resistant to single particle irradiation effects according to an embodiment of the present disclosure;

[0049] Figure 4 The cross-sectional structure diagram of the device after forming an N-type epitaxial layer on a substrate according to an embodiment of the present disclosure is schematically shown;

[0050] Figure 5 A schematic diagram of the cross-sectional structure of a device according to an embodiment of the present disclosure after a P-column deep trench is formed inside an N-type epitaxial layer;

[0051] Figure 6 The cross-sectional structure diagram of the device after forming a P column inside the N-type epitaxial layer according to the embodiment of the present disclosure is schematically shown;

[0052] Figure 7The cross-sectional structure diagram of the device according to the embodiment of the present disclosure after a P base region is formed on one side of the upper surface of the N-type epitaxial layer is schematically shown;

[0053] Figure 8 The schematic diagram of the cross-sectional structure of the device according to the embodiment of the present disclosure after the source region is formed on the side close to the upper surface of the P base region;

[0054] Fig. 9 A schematic diagram of the cross-sectional structure of a device after an oxide layer is formed in the source region according to an embodiment of the present disclosure is shown;

[0055] Fig.10 A schematic diagram of the cross-sectional structure of a device according to an embodiment of the present disclosure after a gate trench is formed on one side close to the upper surface of an N-type epitaxial layer;

[0056] Fig.11 The schematic diagram shows the cross-sectional structure of the device according to the embodiment of the present disclosure after a P+ implantation region is formed below the bottom of the gate trench;

[0057] Fig.12 A schematic diagram of the cross-sectional structure of a device according to an embodiment of the present disclosure after an N+ implantation region is formed inside a P+ implantation region;

[0058] Fig.13 The cross-sectional structure diagram of the device after forming the control electrode trench according to the embodiment of the present disclosure is schematically shown;

[0059] Fig.14 A schematic diagram of the cross-sectional structure of the device according to an embodiment of the present disclosure after a control electrode is formed inside the N+ implantation region;

[0060] Fig.15 A schematic diagram of the cross-sectional structure of a device according to an embodiment of the present disclosure after a gate dielectric layer is deposited inside a gate trench;

[0061] Fig.16 A schematic diagram of the cross-sectional structure of a device according to an embodiment of the present disclosure after polysilicon is filled inside a gate trench to form a gate;

[0062] Fig.17 A schematic diagram of the cross-sectional structure of a device according to an embodiment of the present disclosure after an interlayer dielectric is formed on the upper surface of the gate;

[0063] Fig.18 The cross-sectional structure diagram of the device according to the embodiment of the present disclosure after the source electrode is formed on the upper surface of the interlayer dielectric and part of the source region is schematically shown. DETAILED DESCRIPTION

[0064] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0065] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0066] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0067] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0068] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0069] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element or an intervening layer / element may exist therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, the layer / element may be "below" the other layer / element when the orientation is reversed.

[0070] In the related art, a lot of research has been done on the performance improvement of SiC MOSFET. For example, a 4H-SiC asymmetric trench MOSFET proposed in the related art effectively utilizes <1120> The characteristics of high channel mobility are used to reduce channel resistance; for example, related technologies also propose to add a buffer layer to the SiC VDMOSFET substrate to improve its SEB resistance. In addition, there are technologies such as increasing the thickness of the gate oxide layer or increasing the intrinsic breakdown of the gate dielectric to improve the SEGR resistance of SiCMOSFET devices, and adding a floating junction in the drift region to reduce the device's specific on-resistance.

[0071] Figure 1 The cross-sectional structure diagram of a MOSFET device in the related art is schematically shown.

[0072] like Figure 1 As shown, the SiC MOSFET device in the related art includes a source 101, a gate insulating dielectric 102, an interlayer dielectric 103, a gate 104, a P+ source region 105, an N+ source region 106, a P base region 107, an epitaxial layer 108, a SiC substrate 109 and a drain 110. On-resistance R on and breakdown voltage V B The limiting relation is R on ∝1. 32×10 －11 V B 2. 43 In order to obtain a higher breakdown voltage, the drift layer needs to be thicker and have a lower concentration, which increases the on-resistance. In addition, due to the inherent gate oxide dielectric and parasitic triode structure, under single-particle irradiation, the gate oxide layer of the conventional SiC MOSFET will be damaged at a lower drain bias, resulting in an increase in gate leakage current and a decrease in the long-term reliability of the device. At a higher drain bias, the device will directly burn out and fail. In order to ensure the long-term stable operation of the device in space, the single-particle resistance of the SiC MOSFET needs to be reinforced.

[0073] In view of this, the present disclosure proposes a SiC UMOSFET super junction four-terminal device resistant to single particle irradiation effects, such as Figure 2 shown.

[0074] Figure 2 The cross-sectional structure diagram of a SiC UMOSFET super junction four-terminal device resistant to single particle irradiation effect according to an embodiment of the present disclosure is schematically shown.

[0075] like Figure 2As shown, the SiC UMOSFET super junction four-terminal device 200 resistant to single particle irradiation effect includes: a substrate 201; a drain 202, arranged on the lower surface of the substrate 201; an N-type epitaxial layer 203, arranged on the upper surface of the substrate 201; a P column 204, arranged inside the N-type epitaxial layer 203, wherein the thickness of the P column 204 along the vertical direction does not exceed the thickness of the N-type epitaxial layer 203 along the vertical direction; a P base region 205, arranged on a side close to the upper surface of the N-type epitaxial layer 203 and the upper surface of the P column; a source region 206, arranged on a side close to the upper surface of the P base region 205; a gate groove The groove is arranged on one side close to the upper surface of the N-type epitaxial layer 203; the P+ injection region 207 is arranged below the bottom of the gate groove; the N+ injection region 208 is arranged inside the P+ injection region 207; the control electrode 209 is arranged in the control electrode groove formed inside the N+ injection region; the gate dielectric layer 210 is arranged on the side wall of the gate groove; the gate 211 is arranged on the upper surface of the gate dielectric layer 212; the interlayer dielectric 212 is arranged on the upper surface of the gate 211; the source 213 is arranged on the upper surface of the interlayer dielectric 212 and part of the source region 206.

[0076] According to the embodiments of the present disclosure, Figure 2 As shown in FIG. 2 , an oxide layer 214 is further disposed between the source electrode 213 and the gate electrode 211 to prevent the source electrode 213 and the gate electrode 211 from contacting each other.

[0077] According to the embodiments of the present disclosure, the SiC UMOSFET super junction four-terminal device 200 resistant to single particle radiation effect provided by the present disclosure replaces the conventional gate structure with a trench gate structure, which can significantly reduce the device size, reduce the on-resistance, and increase the current density; at the same time, the gate-drain capacitance of the trench gate structure is smaller, which can reduce the Miller effect of the device caused by the drain capacitance and enhance the dynamic characteristics of the device. In addition, a P-column super junction structure is formed in the drift region, which can not only improve the voltage resistance of the device, but also further reduce the on-resistance, thereby improving the compromise relationship between the breakdown voltage and the on-resistance. The SiC UMOSFET superjunction four-terminal device 200 that is resistant to single-particle irradiation effects adds a fourth control electrode below the gate trench, which can not only provide a steady supply of electrons to the N+ injection region to neutralize a large number of holes generated by single-particle incidence and avoid breakdown of the transient electric field concentration at the bottom of the gate dielectric layer, but also modulate the potential at the bottom of the trench gate to reduce the electric field of the gate dielectric layer, thereby further protecting the gate dielectric layer. In addition, the added control electrode can also adjust the control electrode potential to make the device work in different states, making it flexibly applicable to various scenarios.

[0078] The following describes the relationship between the various layer structures in the SiC UMOSFET superjunction four-terminal device resistant to single particle irradiation effect in combination with the preparation method of the SiC UMOSFET superjunction four-terminal device resistant to single particle irradiation effect.

[0079] Figure 3 The flowchart of the method for preparing a SiC UMOSFET super junction four-terminal device resistant to single particle irradiation effect according to an embodiment of the present disclosure is schematically shown.

[0080] like Figure 3 As shown, the method includes operations S301 to S312.

[0081] In operation S301 , an N-type epitaxial layer is formed on a substrate.

[0082] In operation S302 , a P column is formed inside the N-type epitaxial layer.

[0083] In operation S303 , a P base region is formed on a side close to an upper surface of the N-type epitaxial layer and an upper surface of the P column.

[0084] In operation S304 , a source region is formed at a side close to an upper surface of the P base region.

[0085] In operation S305 , a gate trench is formed at a side close to an upper surface of the N-type epitaxial layer.

[0086] In operation S306 , a P+ implantation region is formed below the bottom of the gate trench.

[0087] In operation S307 , an N+ implantation region is formed inside the P+ implantation region.

[0088] In operation S308 , a control electrode is formed inside the N+ implantation region.

[0089] In operation S309 , a gate dielectric layer is deposited and polysilicon is filled inside the gate trench to form a gate.

[0090] In operation S310 , an interlayer dielectric is formed on an upper surface of a gate.

[0091] In operation S311, a source electrode is formed on an upper surface of the interlayer dielectric and a portion of the source region.

[0092] In operation S312 , a drain is formed on a lower surface of the substrate.

[0093] Combine the following Figure 4 to Figure 18 Describe operations S301 to S312.

[0094] Figure 4 The cross-sectional structure diagram of the device after forming an N-type epitaxial layer on a substrate according to an embodiment of the present disclosure is schematically shown.

[0095] like Figure 4As shown, an epitaxial process can be used to form an N-type epitaxial layer 203 on a substrate 201. The substrate 201 can be an N-type SiC substrate, or Si, GaN, etc., and there is no limitation to this. The resistivity of the N-type SiC substrate 201 can be 0.01-0.03 The thickness along the vertical direction can be 100-500 μm, and the doping concentration of the N-type epitaxial layer 203 can be 5e14-5e16 cm -3 , the thickness along the vertical direction can be 10~20μm.

[0096] Figure 5 The cross-sectional structure diagram of the device according to the embodiment of the present disclosure after a P-column deep trench is formed inside the N-type epitaxial layer is schematically shown.

[0097] Figure 6 The cross-sectional structure diagram of the device according to the embodiment of the present disclosure after a P column is formed inside the N-type epitaxial layer is schematically shown.

[0098] like Figure 5 and Figure 6 As shown, a photolithography and etching process can be used to form a deep trench A1 on the N-type epitaxial layer 203. The thickness of the deep trench A1 along the vertical direction can be 5.2-15.2μm. The depth of the deep trench A1 needs to ensure that the thickness of the P column 204 along the vertical direction does not exceed the N-type epitaxial layer 203. The width of the deep trench along the horizontal direction is 1.5-5μm. An epitaxial backfill process can be used to form a P column 204 in the area of ​​the deep trench A1. The concentration of the P column 204 can be 5e14~5e16cm -3 . It should be noted that the schematic diagram in the embodiment of the present disclosure only illustrates the cross-section of a single cell of the device. The two sides of the P column in the horizontal direction can also be N-type epitaxial layers. Therefore, the P column 204 and the N-type epitaxial layer 203 form a super junction structure in which the P column and the N column are arranged alternately. The present disclosure forms a P column super junction structure in the drift region (i.e., the N-type epitaxial layer 203) by trench etching-epitaxial backfilling. When withstand voltage, the P region and the N region are mutually depleted to withstand high voltage, thereby improving the withstand voltage. At the same time, increasing the doping concentration of the N column can reduce the on-resistance.

[0099] Figure 7 The cross-sectional structure diagram of the device according to the embodiment of the present disclosure after a P base region is formed on one side of the upper surface of the N-type epitaxial layer is schematically shown.

[0100] like Figure 7 As shown, an epitaxial process can be used to form a P base region 205 on the upper surface of the N-type epitaxial layer 203 and one side of the upper surface of the P column. The thickness of the P base region 204 in the vertical direction can be 0.5-1.0 μm, and the peak injection concentration of the P base region 205 can be 1e16-3e17 cm -3 .

[0101] Figure 8 The cross-sectional structure diagram of the device according to the embodiment of the present disclosure after the source region is formed on the side close to the upper surface of the P base region is schematically shown.

[0102] like Figure 8 As shown, the source region 206 may include an N+ source region 2061 and a P+ source region 2062. The N+ source region 2061 may be formed on a side of the P base region 205 close to the upper surface by using photolithography and ion implantation processes. The thickness of the N+ source region 2061 in the vertical direction may be 0.1-0.5 μm, and the thickness of the N+ source region 2061 in the vertical direction is less than the thickness of the P base region 205 in the vertical direction by 0.1-1.5 μm. The peak doping concentration of the N+ source region 2061 is 5e18-5e20 cm -3 .

[0103] The formation of the P+ source region 2062 is similar to that of the N+ source region 2061. The photolithography and ion implantation processes can also be used to form the P+ source region 2062 next to the P base region 205 and the N+ source region 2061. The thickness of the P+ source region 2062 in the vertical direction can be 0.2~3.0μm, and the peak implantation concentration of the P+ source region 2062 can be 5e18~5e21cm -3 .

[0104] Fig. 9 The cross-sectional structure diagram of the device after an oxide layer is formed in the source region according to an embodiment of the present disclosure is schematically shown.

[0105] like Fig. 9 As shown, a thermal oxidation or deposition process may be used to generate an oxide layer 214 on the surface of the N+ source region 2061 and the P+ source region 2062 . The thickness of the oxide layer 214 along the vertical direction may be 10-200 nm.

[0106] Fig.10 The cross-sectional structure diagram of the device according to the embodiment of the present disclosure after a gate trench is formed on one side close to the upper surface of the N-type epitaxial layer is schematically shown.

[0107] like Fig.10 As shown, a photolithography and etching process can be used to form a gate trench A2 in the middle of the N+ source region 2061, the thickness of the gate trench A2 along the vertical direction is 0.5-1.5 μm, and the width of the gate trench A2 along the horizontal direction can be 0.3-2.0 μm.

[0108] Fig.11 The cross-sectional structure diagram of the device according to the embodiment of the present disclosure after a P+ implantation region is formed below the bottom of the gate trench is schematically shown.

[0109] like Fig.11As shown, a P+ implantation region 207 can be formed at the bottom of the gate trench A2 by using photolithography and ion implantation processes. The thickness of the P+ implantation region 207 along the vertical direction is 0.3-1.0 μm, and the peak doping concentration of the P+ implantation region 207 is 1e16-5e19 cm -3 , the upper surface of the P+ injection region 207 is arranged above the bottom of the gate trench A2, in order to form a depletion region between the P+ injection region 207 and the N-type epitaxial layer 203 to protect the corner position of the gate trench A2. After the P+ is injected into the gate trench, the formed P+ region can not only alleviate the high electric field at the corner of the gate trench, protect the gate oxide layer from premature breakdown, but also provide a discharge path for a large number of holes generated by single particle impact, thereby suppressing the accumulation of holes under the gate oxide, relieving the electric field in the gate dielectric, and avoiding premature damage to the gate dielectric. After the N+ is injected under the gate, the formed N+ region can provide a large number of electrons to recombine with the holes in the P+.

[0110] Fig.12 The cross-sectional structure diagram of the device according to the embodiment of the present disclosure after an N+ implantation region is formed inside a P+ implantation region is schematically shown.

[0111] like Fig.12 As shown, a photolithography and ion implantation process can be used to form an N+ implantation region 208 above the P+ implantation region 207. The thickness of the N+ implantation region 208 along the vertical direction is 0.10-0.8 μm. At the same time, the implantation depth of the N+ implantation region 208 is 0.2-1.0 μm less than the implantation depth of the P+ implantation region 207. The width of the N+ implantation region 208 is 0.1-1.0 μm less than the width of the P+ implantation region 207. The peak doping concentration of the N+ implantation region 208 is 1e17-5e21 cm -3 By adjusting the implantation depth, implantation width and implantation concentration of the N+ implantation region 208 and the P+ implantation region 207, a low-resistance current path can be formed in the N+ implantation region 208 for current to pass through when the device is turned on. The impurities in the P+ implantation region 207 and the N+ implantation region 208 can be activated by high-temperature annealing.

[0112] Fig.13 The cross-sectional structure diagram of the device after forming the control electrode trench according to the embodiment of the present disclosure is schematically shown.

[0113] Fig.14 The cross-sectional structure diagram of the device according to the embodiment of the present disclosure after a control electrode is formed inside the N+ implantation region is schematically shown.

[0114] like Fig.13 and 14As shown, photolithography and etching processes can be used to form a control electrode trench A3 inside the N+ implantation region 208. The thickness of the control electrode trench along the vertical direction can be 0.02-0.72 μm, and the width of the control electrode trench A3 along the horizontal direction needs to be less than the width of the N+ implantation region 208 by 0.1-1.0 μm. Deposition, photolithography and etching processes can be used to fill polysilicon inside the control electrode trench A3, and excess polysilicon is removed by photolithography and etching to form a control electrode 209.

[0115] According to an embodiment of the present disclosure, the layout of the P base region, N+ source region, P+ short circuit region, N+ injection region, and P+ injection region can be square, hexagonal, lattice array, etc.

[0116] Fig.15 The cross-sectional structure diagram of the device according to the embodiment of the present disclosure after the gate dielectric layer is deposited inside the gate trench is schematically shown.

[0117] like Fig.15 As shown, a gate dielectric layer 210 may be formed on the inner sidewall of the gate trench A3 by using a thermal oxidation or deposition process. The thickness of the gate dielectric layer 210 may be 10-100 nm.

[0118] Fig.16 The cross-sectional structure diagram of the device according to the embodiment of the present disclosure after polysilicon is filled inside the gate trench to form a gate is schematically shown.

[0119] like Fig.16 As shown, a layer of polysilicon may be filled inside the gate trench A3 and above the gate dielectric layer 210 by using deposition, photolithography and etching processes, and excess polysilicon may be removed by photolithography and etching to form a gate 211 .

[0120] Fig.17 The cross-sectional structure diagram of the device according to the embodiment of the present disclosure after an interlayer dielectric is formed on the upper surface of the gate is schematically shown.

[0121] like Fig.17 As shown, deposition, photolithography and etching processes can be used to deposit interlayer dielectric 212 above gate 211 and oxide layer 214, and excess interlayer dielectric and oxide layer can be removed by photolithography and etching to drain the source region.

[0122] Fig.18 The cross-sectional structure diagram of the device according to the embodiment of the present disclosure after the source electrode is formed on the upper surface of the interlayer dielectric and part of the source region is schematically shown.

[0123] like Fig.18 As shown, deposition, photolithography and etching processes can be used to form the source 213 on the front side of the device.

[0124] Laser annealing, metal thickening and deposition processes can be used to form the drain electrode 202 on the back of the device and the protective glue on the front, so that the device can be obtained as shown in FIG. Figure 2 The SiC UMOSFET superjunction four-terminal device resistant to single-event irradiation effects shown in the figure.

[0125] The preparation method provided by the present disclosure is highly compatible with the conventional SiC MOSFET device preparation process, and mass production can be achieved without special adjustment of the SiC process.

[0126] The device provided by the present disclosure alleviates the trade-off relationship between the specific on-resistance and breakdown voltage of the existing SiC MOSFET device, and solves the problem of single particle burnout and single particle gate penetration when it is irradiated by particles, resulting in reduced device reliability and failure. The device provided by the present disclosure can effectively reduce its specific on-resistance while maintaining the device's voltage resistance, and at the same time greatly improves the long-term reliability of SiC MOSFET devices in harsh space environments.

[0127] The SiC UMOSFET super junction four-terminal device and preparation method provided in the embodiments of the present disclosure are not only applicable to SiC materials, but also to Si-based, C-based, GaN-based, Ga 2 O 3 Power MOSFET devices and circuits of separate material systems such as base, and power MOSFET devices and circuits of heterogeneous fusion systems.

[0128] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram may represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box may also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions. It can be understood by those skilled in the art that the features recorded in the various embodiments of the present disclosure can be combined and / or combined in a variety of ways, even if such a combination or combination is not explicitly recorded in the present disclosure. In particular, without departing from the spirit and teaching of the present disclosure, the features described in the various embodiments of the present disclosure may be combined and / or combined in a variety of ways. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0129] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A SiC UMOSFET superjunction four-terminal device resistant to single-particle irradiation effects, characterized in that: include: substrate; A drain electrode is arranged on the lower surface of the substrate; An N-type epitaxial layer is disposed on the upper surface of the substrate; A P column is disposed inside the N-type epitaxial layer, wherein the thickness of the P column along the vertical direction does not exceed the thickness of the N-type epitaxial layer along the vertical direction; A P base region is arranged on a side close to the upper surface of the N-type epitaxial layer and the upper surface of the P column; A source region, arranged on a side close to the upper surface of the P base region; A gate trench is arranged on a side close to the upper surface of the N-type epitaxial layer; A P+ implantation region, disposed below the bottom of the gate trench; An N+ injection region, arranged inside the P+ injection region; A control electrode, arranged in a control electrode trench formed inside the N+ implantation region; A gate dielectric layer, disposed on the sidewall of the gate trench; A gate, disposed on the upper surface of the gate dielectric layer; An interlayer dielectric, disposed on the upper surface of the gate; The source electrode is arranged on the upper surface of the interlayer dielectric and a part of the source region.

2. The device according to claim 1, characterized in that The injection depth of the N+ injection region is 0.2-1.0 μm less than the injection depth of the P+ injection region, and the width of the N+ injection region is 0.1-1.0 μm less than the width of the P+ injection region.

3. The device according to claim 2, characterized in that The width of the control electrode trench is 0.1-1.0 μm smaller than the width of the N+ implantation region, and the depth of the control electrode trench is 0.02-0.72 μm.

4. The device according to claim 2, characterized in that The thickness of the N-type epitaxial layer in the vertical direction is 10-20 μm, and the doping concentration of the N-type epitaxial layer is 5e14-5e16 cm -3 .

5. The device according to claim 2, characterized in that The thickness of the gate trench along the vertical direction is 0.5-1.5 μm, and the width of the gate trench along the horizontal direction is 0.3-2.0 μm.

6. The device according to any one of claims 1 to 5, characterized in that: The thickness of the P+ injection region in the vertical direction is 0.3-1.0 μm, and the peak doping concentration of the P+ injection region is 1e16-5e19 cm -3 , the upper surface of the P+ implantation region is arranged above the bottom of the gate trench.

7. The device according to any one of claims 1 to 5, characterized in that The peak doping concentration of the N+ implantation region is 1e17~5e21 cm -3 .

8. The device according to claim 1, characterized in that The thickness of the P column along the vertical direction is 5.2-15.2 μm, the width of the P column along the horizontal direction is 1.5-5 μm, and the ion implantation concentration of the P column is 5e14-5e16 cm -3 .

9. A method for preparing a SiC UMOSFET superjunction four-terminal device resistant to single particle irradiation effects, characterized in that: include: forming an N-type epitaxial layer on a substrate; forming a P column inside the N-type epitaxial layer; forming a P base region on a side close to the upper surface of the N-type epitaxial layer and the upper surface of the P column; forming a source region on one side close to the upper surface of the P base region; forming a gate trench on one side close to the upper surface of the N-type epitaxial layer; forming a P+ implantation region below the bottom of the gate trench; forming an N+ implantation region inside the P+ implantation region; forming a control electrode inside the N+ implantation region; Depositing a gate dielectric layer and filling the gate trench with polysilicon to form a gate; forming an interlayer dielectric on the upper surface of the gate; forming a source electrode on the upper surface of the interlayer dielectric and a portion of the source region, A drain is formed on the lower surface of the substrate.

10. The manufacturing method according to claim 9, characterized in that: The forming of a control electrode inside the N+ implantation region comprises: Forming a control electrode trench inside the N+ implantation region by etching; Filling polysilicon inside the control electrode trench; The redundant polysilicon is removed by photolithography and etching to form the control electrode.

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