Semiconductor device and preparation method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, and relates to the technical field of semiconductors, a semiconductor body comprises a first surface and a second surface which are oppositely arranged, the first surface is provided with a gate trench, and the gate trench extends into the semiconductor body from the first surface. The gate structure is located in the gate trench. The first barrier layer is located between the gate structure and the inner wall of the gate trench, and the second barrier layer at least covers a third surface of the gate structure away from one side of the second surface. In the process of forming the second barrier layer, the sharp corner of the gate structure is oxidized and flattened, and the joint of the side surface of the gate structure and the third surface is relatively smooth in the related technology, so that charge concentration can be avoided, the risk of gate-source electric leakage is greatly reduced, the reliability of the device is improved, the source-drain on-resistance of the device is reduced, and the performance of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] In a silicon carbide double trench device, the gate structure is usually formed by depositing polysilicon in the gate trench and etching the polysilicon. Affected by the polysilicon etching process, some sharp corners will be formed on the surface of the gate structure in the gate trench after etching. In semiconductor devices, the sharp corners of the gate structure will lead to electric field concentration, which is easy to cause gate-source leakage and affect device reliability. Summary of the invention

[0003] Embodiments of the present application provide a semiconductor device and a preparation method, a power module, a power conversion circuit and a vehicle, aiming to improve device reliability.

[0004] In a first aspect, the present application provides a semiconductor device, including a semiconductor body, a gate structure, a source, a drain, a first barrier layer, and a second barrier layer. The semiconductor body is set to a first conductivity type, including a first surface and a second surface arranged opposite to each other, the first surface is provided with a gate trench, the gate trench extends from the first surface to the semiconductor body, and the gate structure is located in the gate trench. The first barrier layer is located between the gate structure and the inner wall of the gate trench, and the second barrier layer at least covers a third surface of the gate structure away from the second surface. The source is located on the first surface, and the drain is located on the second surface.

[0005] In some embodiments, the gate structure further includes a side surface close to the inner wall of the gate trench, the third surface is connected to the side surface, and the minimum angle between the third surface and the side surface is in the range of 80° to 100°.

[0006] In some embodiments, in a direction in which the second surface points to the first surface, a projection of the first barrier layer on the first surface falls within a projection of the second barrier layer on the first surface.

[0007] In some embodiments, the first surface is further provided with a source trench, the source trench extending from the first surface into the semiconductor body. The semiconductor device further includes a source trench structure, the source trench structure being located in the source trench. The first barrier layer is also located between the source trench structure and the inner wall of the source trench, and the second barrier layer also covers a side of the first barrier layer away from the second surface.

[0008] In some embodiments, the first barrier layer and the second barrier layer are made of the same material, both comprising silicon oxide.

[0009] In a second aspect, the present application further provides a method for preparing a semiconductor device, comprising the following steps S01 to S04: Step S01: forming a gate trench on a semiconductor body, wherein the semiconductor body is set to a first conductivity type, the semiconductor body includes a first surface and a second surface arranged opposite to each other, and the gate trench extends from the first surface into the semiconductor body.

[0010] Step S02: forming a gate structure in the gate trench, and forming a first barrier layer and a second barrier layer, wherein the first barrier layer is located between the gate structure and the inner wall of the gate trench, and the second barrier layer at least covers a third surface of the gate structure away from the second surface.

[0011] Step S03: forming a source electrode on the first surface.

[0012] Step S04: forming a drain on the second surface.

[0013] In some embodiments, forming the second barrier layer includes: performing a thermal oxidation process on the third surface of the gate structure to form the second barrier layer.

[0014] On the other hand, an embodiment of the present application further provides a power module, which includes a substrate and a semiconductor device as described in any of the above embodiments, wherein the substrate is used to carry the semiconductor device.

[0015] In another aspect, an embodiment of the present application further provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and a semiconductor device as in any of the above embodiments, and the semiconductor device is electrically connected to the circuit board.

[0016] On the other hand, an embodiment of the present application also provides a vehicle, which includes a load and a power conversion circuit as described in the above embodiment, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0017] In the embodiment provided in the present application, the semiconductor body includes a first surface and a second surface arranged opposite to each other, the first surface is provided with a gate groove, the gate groove extends from the first surface into the semiconductor body, and the semiconductor body also includes a first barrier layer and a second barrier layer located in the gate groove. The gate structure is located in the gate groove, the first barrier layer is located between the gate structure and the inner wall of the gate groove, and the second barrier layer at least covers a third surface of the gate structure away from the second surface. In the related art, in order to form a patterned gate structure and a source trench structure, the deposited polysilicon material needs to be etched. Affected by the device structure, after the etching is completed, there will be sharp corners on the surface edge of the gate structure. In the semiconductor device, these sharp corners will cause electric field concentration and gate-source leakage, affecting the reliability of the device, and also causing the gate insulation layer of the semiconductor device to need a wider size to protect the gate structure, which is not conducive to the size reduction of the semiconductor device. In the present application, the third surface of the gate structure can be modified during the process of thermal oxidation to form the second barrier layer. The sharp corners in the related art are oxidized and smoothed, and the connection between the side of the gate structure and the third surface is relatively smooth, which can avoid charge concentration, greatly reduce the risk of gate-source leakage, improve device reliability, and help reduce the source-drain on-resistance of the device and improve device performance. It is beneficial to reduce the width of the gate insulation layer, to expand the relevant dimensions and overlay accuracy in the subsequent connection hole etching process, to reduce the difficulty of subsequent processes, and to achieve the miniaturization of semiconductor devices.

[0018] The above-mentioned power module, power conversion circuit and vehicle have the same structure and beneficial technical effects as the semiconductor devices provided in some of the above-mentioned embodiments, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 A schematic diagram of a sharp corner of a gate structure in the related art; Figure 2 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application; Figure 3 A flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application; Figure 4 to Figure 12 A diagram of each step of preparing a semiconductor device provided in an embodiment of the present application; Fig.13 A structural diagram of a power module provided in an embodiment of the present application; Fig.14 A structural diagram of a power conversion circuit provided in an embodiment of the present application; Fig.15A structural diagram of a vehicle provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0021] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0022] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0023] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0024] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0025] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0026] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0027] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0028] As mentioned in the background art, in the silicon carbide double trench device, affected by the polysilicon etching process, the surface of the gate structure 12' in the gate trench will form some sharp corners, such as Figure 1 As shown in the dashed box, Figure 1 Schematic diagram of the sharp corners of the gate structure in the related art. In semiconductor devices, the sharp corners of the gate structure will lead to electric field concentration, which is easy to cause gate-source leakage and affect device reliability.

[0029] Based on this, the present application provides a semiconductor device, such as Figure 2 As shown, Figure 2 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application.

[0030] The semiconductor device 10 includes a semiconductor body 11, a gate structure 12, a source 14, a drain 15, a first barrier layer 16, and a second barrier layer 17. The semiconductor body 11 is set to a first conductivity type, including a first surface P1 and a second surface P2 arranged opposite to each other, and the first surface P1 is provided with a gate trench T1, and the gate trench T1 extends from the first surface P1 to the semiconductor body 11. The gate structure 12 is located in the gate trench T1. The first barrier layer 16 is located between the gate structure 12 and the inner wall of the gate trench T1, and the second barrier layer 17 at least covers the third surface P3 of the gate structure 12 away from the second surface P2. The source 14 is located on the first surface P1, and the drain 15 is located on the second surface P2.

[0031] In some embodiments, both the first barrier layer 16 and the second barrier layer 17 are at least partially located in the gate trench T1 .

[0032] For example, Figure 2 As shown, in some embodiments, the semiconductor body 11 further includes a well region 101 set to the second conductivity type, a first region 102 set to the first conductivity type, and a second region 103 set to the second conductivity type. The first conductivity type may be N-type, and correspondingly, the second conductivity type is P-type, that is, the semiconductor device is an N-type semiconductor device, and accordingly, the well region 101 may also be referred to as a "P-type well region (P-well)", and the first region 102 may also be referred to as an "N + The second region 103 may also be referred to as “P +The semiconductor device 10 further includes an ohmic contact layer 18, which is located between the first surface P1 and the source 14 to form a good electrical contact. The ohmic contact metal of the ohmic contact layer 18 may include at least one of nickel (Ni) or titanium (Ti) or a nickel-titanium alloy (NiTi alloy metal). Alternatively, in other embodiments, the first conductivity type may be a P-type, and the second conductivity type may be an N-type, and accordingly, the semiconductor device is a P-type semiconductor device.

[0033] Taking an N-type semiconductor device as an example, by transmitting a turn-on voltage to the gate structure 12, when the semiconductor device 10 is forward-conducting and the operating current is small, the operating current flows from the drain 15 through the semiconductor body 11, the well region 101, the first region 102, and the ohmic contact layer 18 to finally reach the source 14. Since the P-type ion concentration in the second region 103 is higher than that in the well region 101, the second region 103 can form more PN junctions with the semiconductor body 11. When the operating current is large, the operating current flows from the drain 15 through the semiconductor body 11 and the ohmic contact layer 18 of the second region 103 to finally reach the source 14, thereby preventing a large operating current from flowing through the well region 101, thereby protecting the channel in the well region 101.

[0034] In an embodiment of the present application, the first barrier layer 16 and the second barrier layer 17 are located in the gate trench T1, and the first barrier layer 16 is located between the gate structure 12 and the inner wall of the gate trench T1. The first barrier layer 16 here is an insulating dielectric layer, which can be used to provide good electrical insulation performance, prevent current leakage, and protect the gate structure 12.

[0035] The third surface P3 of the gate structure 12 is covered by the second barrier layer 17, and the second barrier layer 17 can be used to modify the gate structure 12. Exemplarily, the second barrier layer 17 is formed by performing a thermal oxidation process on the third surface P3 of the gate structure 12.

[0036] The material of the gate structure 12 includes polysilicon, Figure 1 It can be understood from the preparation step diagrams in the following text that in the related art, in order to form a patterned gate structure, the deposited polysilicon material needs to be etched. Affected by the device structure, after the etching is completed, there will be sharp corners on the surface edge of the gate structure. In semiconductor devices, these sharp corners will cause electric field concentration and gate-source leakage, affecting device reliability, and also causing the gate insulation layer of the semiconductor device to require a wider size to protect the gate structure, which is not conducive to the size reduction of the semiconductor device.

[0037] In the embodiment of the present application, the third surface P3 of the gate structure 12 is thermally oxidized to form a second barrier layer 17, so that the third surface P3 of the gate structure 12 can be modified. The second barrier layer 17 is used to form a relatively flat surface. The sharp corners in the related technology are oxidized and smoothed. The connection between the side surface of the gate structure 12 and the third surface P3 is relatively smooth, which can avoid charge concentration, greatly reduce the risk of gate-source leakage, improve device reliability, and help reduce the source-drain on-resistance of the device and improve device performance.

[0038] Furthermore, since the sharp corners are oxidized and smoothed, the risk of gate-source leakage is reduced, which is beneficial for reducing the width of the gate insulation layer 104, and is beneficial for expanding the relevant dimensions and overlay accuracy in the subsequent connection hole etching process, reducing the difficulty of subsequent processes, and facilitating the miniaturization of semiconductor devices.

[0039] In some embodiments, Figure 2 As shown, the gate structure 12 further includes a side surface close to the inner wall of the gate trench T1, and the third surface P3 is connected to the side surface. The minimum angle between the third surface P3 and the side surface is in the range of 80° to 100°.

[0040] Combination Figure 1 ,like Figure 1 As shown in the dashed box, in the related art, the gate structure has a sharp angle a (ie, the minimum angle between the third surface and the side surface). In some embodiments, the angle range of the sharp angle a is 30° to 45°.

[0041] In this embodiment, the third surface P3 of the gate structure 12 is thermally oxidized to form the second barrier layer 17, and the sharp corners are oxidized and smoothed. Figure 2 As shown in the dotted box, after processing, the minimum angle b between the third surface P3 and the side is in the range of 80°~100°, for example, 80°, 85°, 90° or 100°. The angles between the cut surfaces at different positions on the third surface P3 and the inner wall side of the gate groove may be different. When the angle is the minimum angle b, it indicates that the connection between this place and the side is the sharpest. In the embodiment of the present application, the minimum angle b is in the range of 80°~100°, which indicates that the connection between the third surface P3 and the side is relatively smooth, which can avoid charge concentration, greatly reduce the risk of gate-source leakage, improve device reliability, and help reduce the source-drain on-resistance of the device and improve device performance.

[0042] In some embodiments, in a direction from the second surface P2 to the first surface P1 , a projection of the first barrier layer 16 on the first surface P1 falls within a projection of the second barrier layer 17 on the first surface P1 .

[0043] In this embodiment, the first barrier layer 16 is located between the gate structure 12 and the inner wall of the gate trench T1, the second barrier layer 17 at least covers the third surface P3 of the gate structure 12 away from the second surface P2, the second barrier layer 17 is also located on the side of the first barrier layer 16 away from the second surface P2, and the projection of the first barrier layer 16 on the first surface P1 falls into the projection of the second barrier layer 17 on the first surface P1, which is equivalent to the positive projection of the second barrier layer 17 on the second surface P2, covering the positive projection of the first barrier layer 16 on the second surface P2. The first barrier layer 16 and the second barrier layer 17 work together to completely wrap the gate structure 12 in the gate trench T1, thereby enhancing the protection of the gate structure 12, helping to reduce the risk of gate-source leakage, helping to reduce the source-drain on-resistance of the device, and improving the device performance.

[0044] In some embodiments, Figure 2 As shown, the first surface P1 is further provided with a source trench T2, the source trench T2 extends from the first surface P1 into the semiconductor body 11, and the semiconductor device further includes a source trench structure 13, the source trench structure 13 is located in the source trench T2. The first barrier layer 16 is also located between the source trench structure 13 and the inner wall of the source trench T2, and the second barrier layer 17 also covers the side of the first barrier layer 16 away from the second surface P2.

[0045] In some embodiments, both the first barrier layer 16 and the second barrier layer 17 are at least partially located in the source trench T2 .

[0046] It is understandable that in other embodiments, the semiconductor device may not be provided with the source trench T2 and the source trench structure 13. For example, during the preparation process, the source trench T2 is no longer formed synchronously during the formation of the gate trench T1, and only the second region 103 is formed at the corresponding position, which will not be repeated here.

[0047] Alternatively, in other embodiments, the first surface P1 is provided with a source trench T2, but the source trench structure 13 is not provided in the source trench T2. For example, in the preparation process, after the gate trench T1 and the gate structure 12 are formed, the source trench T2 is formed, and then the second region 103 is formed at the corresponding position. The source trench T2 is no longer filled with polysilicon, but the subsequent process is directly carried out. At this time, in the semiconductor device finally formed, the source trench T2 may include the material of the source 14, or also include a cavity. It will not be repeated here.

[0048] like Figure 2As shown, taking the case where the materials of the gate structure 12 and the source trench structure 13 both include polysilicon, generally, the source trench T2 and the gate trench T1 are prepared and formed in the same process, the gate structure 12 and the source trench structure 13 are prepared and formed in the same process, the first barrier layer 16 in the source trench T2 and the first barrier layer 16 in the gate trench T1, and the second barrier layer 17 in the source trench T2 and the second barrier layer 17 in the gate trench T1 are also prepared and formed in the same process. Based on this, the morphology and relative position relationship of the gate structure 12, the first barrier layer 16 and the second barrier layer 17 in the source trench T2 are similar to the morphology and relative position relationship of the source trench structure 13, the first barrier layer 16 and the second barrier layer 17 in the gate trench T1.

[0049] Furthermore, the material of the semiconductor body 11 includes silicon carbide, the first region 102 is formed by ion doping of the silicon carbide material, and the material of the source trench structure 13 includes polycrystalline silicon. The process required to form metal silicide on the surface of silicon carbide is significantly different from the process required to form metal silicide on the surface of polycrystalline silicon. Exposing a portion of the source trench structure 13 on the first surface of the semiconductor body 11 will increase the difficulty of forming an ohmic contact.

[0050] For example, in the related art, after the ohmic contact layer 18 is formed on the first surface P1 of the semiconductor body 11, a high-temperature annealing process is required to allow the ohmic contact layer 18 to form an ohmic contact with the first region 102. Since the temperature required to form metal silicide on the silicon carbide surface is relatively high, at this temperature, the polysilicon of the source trench structure 13 reacts too violently with the ohmic contact metal, easily forming corrosion defects, which in turn affects the stability of the device.

[0051] Based on this, in the embodiment of the present application, in the process of thermally oxidizing the third surface P3 of the gate structure 12 to form the second barrier layer 17, the second barrier layer 17 is simultaneously formed on the side of the source trench structure 13 away from the second surface P2. The second barrier layer 17 and the first barrier layer 16 work together to wrap the source trench structure 13, which can not only modify the surface of the source trench structure 13 and make it flat to facilitate the subsequent formation of the ohmic contact layer 18, but also prevent the polysilicon material of the source trench structure 13 from directly contacting the subsequently formed ohmic contact layer 18, thereby avoiding the ohmic contact metal and polysilicon from reacting to form corrosion defects in the subsequent process of forming the ohmic contact. That is, the second barrier layer 17 covers the side of the source trench structure 13 away from the second surface P2, which is beneficial to improving the reliability of the device.

[0052] In some embodiments, the first barrier layer 16 and the second barrier layer 17 are made of the same material, both comprising silicon oxide.

[0053] Based on the silicon carbide material of the semiconductor body 11, the polysilicon material of the source trench structure 13 and the gate structure 12, the first barrier layer 16 and the second barrier layer 17 can be formed by an oxidation process. Silicon oxide has a high stability of insulation properties and can be used to reduce leakage current, which is beneficial to reducing the risk of gate-source leakage and improving the stability of semiconductor devices.

[0054] In a second aspect, the present application also provides a method for preparing a semiconductor device, such as Figure 3 As shown, Figure 3 A flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application, Figure 4 to Figure 12 A diagram of the various steps of preparing a semiconductor device provided in an embodiment of the present application.

[0055] like Figure 3 As shown, the preparation method includes the following steps S01 to S04: Step S01: Figure 4~Figure 5 As shown, a gate trench T1 is formed on a semiconductor body 11 , wherein the semiconductor body 11 is set to a first conductivity type, the semiconductor body 11 includes a first surface P1 and a second surface P2 oppositely arranged, and the gate trench T1 extends from the first surface P1 into the semiconductor body 11 .

[0056] The first conductivity type may be N-type, for example, Figure 4 As shown, the conductivity type of the semiconductor body 11 is N type. On the first surface P1 of the semiconductor body 11, a mask is formed by a photolithography process to define an ion implantation area and perform P + Ion implantation is performed to form a well region 101. After the mask is removed, a mask is formed again through a photolithography process to define the ion implantation area and perform N + Ion implantation is performed to form the first region 102. The implantation energy is controlled to control the ion implantation depth, so that the first region 102 is located on the first surface P1, and the well region 101 is located on a side of the first region 102 away from the first surface P1.

[0057] Afterwards, if Figure 5 As shown, a gate trench T1 is formed by an etching process.

[0058] In some embodiments, the first surface P1 is further provided with a source trench T2, and the source trench T2 extends from the first surface P1 to the semiconductor body 11. During the process of forming the gate trench T1, the source trench T2 is also formed simultaneously. After forming the gate trench T1 and the gate structure 12, a second region 103 is formed on the surface of the source trench T2. The second region 103 may also be referred to as “P +After that, a carbon film is deposited on the surface of the device and activated by high-temperature annealing, and the carbon film is removed after the annealing activation is completed. This process helps to activate the doped ions and repair the lattice defects caused by processes such as ion implantation, which is beneficial to improve the yield and reliability of the device.

[0059] Step S02: Figure 6~Figure 11 As shown, a gate structure 12 is formed in the gate trench T1, and a first barrier layer 16 and a second barrier layer 17 are formed. The first barrier layer 16 is located between the gate structure 12 and the inner wall of the gate trench T1, and the second barrier layer 17 at least covers the third surface P3 of the gate structure 12 away from the second surface P2.

[0060] In some embodiments, the semiconductor device further includes a source trench structure 13, and the source trench structure 13 is located in the source trench T2. During the process of forming the gate structure 12, the source trench structure 13 is also formed simultaneously.

[0061] like Figure 6 As shown, the insulating dielectric layer on the sidewall and the bottom is grown by thermal oxidation in the trench through a high temperature gate oxide process, that is, the first barrier layer 16 is formed on the inner wall of the gate trench T1, and the first barrier layer 16 is formed on the inner wall of the source trench T2. The first barrier layer 16 can be used to provide good electrical insulation performance to prevent current leakage, and the first barrier layer 16 formed on the inner wall of the gate trench T1 can also protect the gate structure 12.

[0062] Then, if Figure 7~Figure 8 As shown, polysilicon is deposited and etched, and finally, a gate structure 12 is formed in the gate trench T1 , and a source trench structure 13 is formed in the source trench T2 .

[0063] like Figure 8 As shown in the dotted box, due to the influence of the device structure, after etching is completed, the surface edge of the gate structure 12 will have sharp corners.

[0064] To avoid gate-source leakage caused by this sharp corner, Fig. 9 As shown, the second barrier layer 17 may be formed first.

[0065] In some embodiments, forming the second barrier layer 17 includes: performing a thermal oxidation process on the third surface P3 of the gate structure 12 to form the second barrier layer 17. In some embodiments, the portion of the source trench structure 13 away from the second surface P2 and the exposed portion of the first surface P1 of the semiconductor body 11 are both thermally oxidized simultaneously, that is, the formed second barrier layer 17 also covers the portion of the source trench structure 13 away from the second surface P2 and the first surface P1 of the semiconductor body 11.

[0066] The thermal oxidation treatment can modify the polysilicon surface to make the third surface P3 of the gate structure 12 more flat. Figure 8 Similarly, the surface of the source trench structure 13 away from the second surface P2 can be made flatter.

[0067] Thermal oxidation treatment includes but is not limited to high temperature dry oxygen oxidation, high temperature wet oxygen oxidation, and rapid thermal oxidation. For example, oxygen, hydrogen chloride, nitrogen and other gases may be introduced to perform thermal oxidation at a temperature of 800° C. to 1200° C. to form a second barrier layer 17 with a thickness ranging from 100 angstroms to 1000 angstroms.

[0068] Afterwards, if Fig.10 As shown, a gate insulating layer 104 is formed, and the gate insulating layer 104 covers the gate structure 12 to isolate and protect the gate structure 12. In some embodiments, the gate insulating layer 104 and the first barrier layer 16 and the second barrier layer 17 are made of the same material, both of which include silicon oxide. Fig.10 As shown, during the process of patterning the gate insulating layer 104 , the second barrier layer 17 can be patterned simultaneously to remove unnecessary portions of the second barrier layer 17 without adding an additional etching process.

[0069] Then, if Fig.11 As shown, an ohmic contact layer 18 is formed on the first surface P1. Due to the existence of the second barrier layer 17, during the process of forming the ohmic contact, the source trench structure 13 will not form corrosion defects due to the reaction with the ohmic contact metal.

[0070] Step S03: Fig.12 As shown, a source electrode 14 is formed on the first surface P1. For example, aluminum is deposited to form a thick metal by sputtering or evaporation to form the source electrode 14.

[0071] Step S04: Fig.12 As shown, a drain 15 is formed on the second surface P2.

[0072] At this point, the semiconductor device 10 is completed.

[0073] In the above preparation method, after forming the patterned gate structure 12 and the source trench structure 13 and before forming the ohmic contact layer 18, a thermal oxidation process is added to perform thermal oxidation on the third surface P3 of the gate structure 12 to form a second barrier layer 17, so that the third surface P3 of the gate structure 12 can be modified, the sharp corners caused by polysilicon etching can be removed, and charge concentration can be avoided, which greatly reduces the risk of gate-source leakage, improves device reliability, and is conducive to reducing the source-drain on-resistance of the device and improving device performance. In addition, for the source trench structure 13, by adding a thermal oxidation process, a second barrier layer 17 can be formed to protect and cover the source trench structure 13, so as to avoid the polysilicon of the source trench structure 13 and the ohmic contact metal from reacting violently in the subsequent ohmic contact process to form corrosion defects.

[0074] The added thermal oxidation process is mature, simple and easy to operate, and does not require an additional etching process. The patterning of the second barrier layer 17 can be performed simultaneously during the subsequent patterning of the gate insulating layer 104. Based on this, the device reliability can be greatly improved at a lower cost by adding a process.

[0075] On the other hand, an embodiment of the present application further provides a power module, Fig.13 A structural diagram of a power module provided in an embodiment of the present application.

[0076] like Fig.13 As shown, the power module 200 includes a substrate 201 and the semiconductor device 10 in any of the above embodiments, and the substrate 201 is used to carry the semiconductor device 10 .

[0077] Exemplarily, the power module 200 can be used as one of a power amplifier, a power converter, a power controller, a power management module, or a power regulator. The power amplifier is used to amplify the power of an electrical signal. The power converter is used to convert electrical energy from one form to another form. For example, the power converter can be an AC / DC converter or a DC / DC converter. The power controller is used to control the device of power flow. The power management module is used to manage the power supply to ensure that the power is stably and efficiently distributed to different parts of the electronic device. The power regulator is used to adjust the power output to meet the needs of a specific application.

[0078] On the other hand, an embodiment of the present application further provides a power conversion circuit, Fig.14 A structural diagram of a power conversion circuit provided in an embodiment of the present application.

[0079] like Fig.14As shown, the power conversion circuit 300 includes a circuit board 301 and a semiconductor device 10 in any of the above embodiments. The semiconductor device 10 is electrically connected to the circuit board 301. The power conversion circuit 300 can be used for current conversion, voltage conversion or power factor correction.

[0080] Exemplarily, the power conversion circuit 300 can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter or a power factor correction (PFC) circuit, wherein the AC / DC converter is used to convert alternating current into direct current, the AC / AC converter is used to convert alternating current into alternating current, the DC / DC converter is used to convert direct current into direct current, the DC / AC inverter is used to convert direct current into alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce the harmonic pollution of the power grid.

[0081] On the other hand, an embodiment of the present application further provides a vehicle, Fig.15 A structural diagram of a vehicle provided in an embodiment of the present application.

[0082] like Fig.15 As shown, the vehicle 400 includes a load 401 and the power conversion circuit 300 in the above embodiment, and the power conversion circuit 300 is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load 401 to power the load 401.

[0083] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, the semiconductor body is set to a first conductivity type, including a first surface and a second surface arranged opposite to each other, the first surface is provided with a gate trench, and the gate trench extends from the first surface into the semiconductor body; A gate structure, located in the gate trench; a first barrier layer and a second barrier layer, wherein the first barrier layer is located between the gate structure and the inner wall of the gate trench, and the second barrier layer at least covers a third surface of the gate structure away from the second surface; A source electrode, located on the first surface; The drain is located on the second surface.

2. The semiconductor device according to claim 1, wherein: The gate structure further includes a side surface close to an inner wall of the gate trench, and the third surface is connected to the side surface; The minimum angle between the third surface and the side surface is in the range of 80° to 100°.

3. The semiconductor device according to claim 1, wherein: In a direction from the second surface to the first surface, a projection of the first barrier layer on the first surface falls within a projection of the second barrier layer on the first surface.

4. The semiconductor device according to claim 1, wherein: The first surface is also provided with a source trench, and the source trench extends from the first surface into the semiconductor body; The semiconductor device further comprises a source trench structure, wherein the source trench structure is located in the source trench; The first barrier layer is also located between the source trench structure and the inner wall of the source trench, and the second barrier layer also covers a side of the first barrier layer away from the second surface.

5. The semiconductor device according to claim 1, wherein: The first barrier layer and the second barrier layer are made of the same material, both comprising silicon oxide.

6. A method for preparing a semiconductor device, characterized in that: include: Forming a gate trench on a semiconductor body, wherein the semiconductor body is set to a first conductivity type, the semiconductor body includes a first surface and a second surface arranged opposite to each other, and the gate trench extends from the first surface into the semiconductor body; forming a gate structure in the gate trench, and forming a first barrier layer and a second barrier layer, wherein the first barrier layer is located between the gate structure and the inner wall of the gate trench, and the second barrier layer at least covers a third surface of the gate structure away from the second surface; forming a source electrode on the first surface; A drain electrode is formed on the second surface.

7. The preparation method according to claim 6, characterized in that: Forming the second barrier layer comprises: The third surface of the gate structure is thermally oxidized to form the second barrier layer.

8. A power module, characterized in that: include: At least one semiconductor device according to any one of claims 1 to 5; A substrate is used to carry the semiconductor device.

9. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 5, wherein the semiconductor device is electrically connected to the circuit board.

10. A vehicle, characterized in that: include: A load and a power conversion circuit as claimed in claim 9, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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