Semiconductor device and forming method thereof

Abstract

The method includes forming a complementary field effect transistor including a lower transistor and an upper transistor, the lower transistor including a lower source / drain region, and the upper transistor including an upper source / drain region. The upper dielectric layer over the upper source / drain region and the lower dielectric layer under the upper source / drain region are etched to form an opening. A sidewall of the upper source / drain region and a top surface of the lower source / drain region are exposed to the opening. An epitaxial process is performed to form a first semiconductor layer on sidewalls of the upper source / drain region and a second semiconductor layer on a top surface of the lower source / drain region. The first semiconductor layer is then removed. A contact plug is formed in the opening to electrically connect the upper source / drain region to the second semiconductor layer and the lower source / drain region. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] Complementary field effect transistors (CFETs) are being developed recently to meet the increasingly demanding requirements of increasing transistor density in integrated circuits. In a CFET circuit, an upper transistor is formed that overlaps a lower transistor. In order to electrically connect to the lower transistor, a contact plug is formed. Contact plugs have a high aspect ratio, and therefore their formation presents challenges. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a complementary field effect transistor, comprising: a lower transistor, comprising a lower source / drain region; and an upper transistor, comprising an upper source / drain region; etching an upper dielectric layer above the upper source / drain region and a lower dielectric layer between the upper source / drain region and the lower source / drain region to form an opening, wherein the sidewalls of the upper source / drain region and the top surface of the lower source / drain region are exposed to the opening; performing an epitaxial process to form: a first semiconductor layer, located on the sidewalls of the upper source / drain region; and a second semiconductor layer, located on the top surface of the lower source / drain region; removing the first semiconductor layer, wherein the second semiconductor layer is retained, wherein the second semiconductor layer and the lower source / drain region together form a combined source / drain region; and forming a contact plug in the opening, wherein the contact plug electrically connects the upper source / drain region to the combined source / drain region.

[0004] Some other embodiments of the present application provide a semiconductor device, comprising: a lower transistor, comprising a lower source / drain region, wherein the lower source / drain region comprises: a lower portion; and an upper portion, located above the upper portion and connected to the upper portion; a lower contact etch stop layer, located on the lower portion of the lower source / drain region, wherein a first top surface of the upper portion of the lower source / drain region is higher than a second top surface of the lower contact etch stop layer; a lower interlayer dielectric, located above the lower contact etch stop layer; a lower silicide layer located on the first top surface of the upper portion of the lower source / drain region; an upper source / drain region overlapping the lower source / drain region; an upper silicide layer located on the upper source / drain region; an upper contact etch stop layer located on the upper source / drain region; an upper interlayer dielectric located above the upper contact etch stop layer; and a contact plug contacting both the upper silicide layer and the lower silicide layer.

[0005] Still other embodiments of the present application provide a semiconductor device, comprising: a complementary field effect transistor, comprising: a lower transistor, comprising a lower source / drain region, and the lower source / drain region comprises a lower portion and an upper portion located above the lower portion; and an upper transistor, comprising an upper source / drain region; a lower contact etch stop layer, located on the lower portion of the lower source / drain region, wherein the upper portion of the lower source / drain region penetrates the lower contact etch stop layer; a lower silicide layer, located on the top surface of the upper portion of the lower source / drain region; an upper silicide layer, located on the sidewalls of the upper source / drain region; and a contact plug, contacting the upper silicide layer and the lower silicide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figures 1 to 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A and Fig.18B A view showing an intermediate stage in the formation of a complementary field effect transistor (CFET) and a contact plug according to some embodiments of the present disclosure.

[0008] Fig.19 A process flow for forming a CFET according to some embodiments is shown. DETAILED DESCRIPTION

[0009] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0010] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0011] A local interconnect for electrically connecting the source / drain regions of an upper transistor and a lower transistor in a complementary field effect transistor (CFET) is provided, comprising a contact plug. A formation process is also provided. According to some embodiments of the present disclosure, a contact opening is formed to extend to a lower source / drain region of a lower transistor in the CFET. An epitaxial layer is selectively formed on the lower source / drain region. The formation of the epitaxial layer causes a favorable reduction in the aspect ratio of the opening, wherein the contact plug is formed to electrically interconnect the lower source / drain region with the upper source / drain region.

[0012] It should be understood that although a full-all-around gate (GAA) transistor is used as an example to explain the concepts of the embodiments, the embodiments of the present disclosure may also be applicable to CFETs formed by other transistors including but not limited to FinFETs, planar transistors, etc. The embodiments discussed herein are intended to provide examples of the subject matter of the embodiments of the present disclosure that can be manufactured or used, and those of ordinary skill in the art will readily understand the modifications that can be made while remaining within the scope of consideration of the different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although method embodiments may be discussed as being implemented in a particular order, other method embodiments may be implemented in any logical order.

[0013] Figures 1 to 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A and Fig.18B 1 shows a view of an intermediate stage in the formation of a complementary field effect transistor (CFET) according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in Fig.19 In the process flow shown in .

[0014] refer to Figure 1 , a wafer 2 is provided, the wafer 2 comprising a substrate 20. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (eg, with a p-type or n-type dopant) or undoped.

[0015] A multilayer stack 22 is formed over the substrate 20. The corresponding process is shown as follows Fig.19 202 in the process flow 200 shown in FIG. The multilayer stack 22 includes alternating dummy semiconductor layers 24 and semiconductor layers 26. The dummy semiconductor layers 24 include dummy semiconductor layers 24A and dummy semiconductor layers 24B. The semiconductor layers 26 include lower semiconductor nanostructures 26L and upper semiconductor nanostructures 26U. The lower semiconductor nanostructures 26L and the upper semiconductor nanostructures 26U are used to form lower FETs and upper FETs, respectively.

[0016] The dummy semiconductor layer 24A is formed of a first semiconductor material, and the dummy semiconductor layer 24B is formed of a second semiconductor material different from the first semiconductor material. The first semiconductor material and the second semiconductor material can be selected from the same candidate semiconductor material group of the substrate 20. The first semiconductor material and the second semiconductor material have high etching selectivity to each other. Therefore, in the subsequent process, the dummy semiconductor layer 24B can be removed at a faster rate than the dummy semiconductor layer 24A.

[0017] The semiconductor layer 26 (including the lower semiconductor nanostructure 26L and the upper semiconductor nanostructure 26U) is formed of one or more semiconductor materials. The semiconductor material may also be selected from the same candidate semiconductor material group of the substrate 20. The lower semiconductor nanostructure 26L and the upper semiconductor nanostructure 26U may be formed of the same semiconductor material, or may be formed of different semiconductor materials.

[0018] According to some embodiments, dummy semiconductor layer 24A is formed of or includes silicon germanium, semiconductor layer 26 is formed of silicon, and dummy semiconductor layer 24B may be formed of germanium or silicon germanium having a higher atomic percentage of germanium than dummy semiconductor layer 24A.

[0019] refer to Figure 2 , patterning the multilayer stack 22 and the substrate 20 to form semiconductor strips 28. The corresponding process is shown as Fig.19 The process 204 in the process flow 200 shown in FIG. Each of the semiconductor strips 28 includes a semiconductor strip 20 ′ ( Figure 2 , part of the original substrate 20) and a multilayer stack 22', which is the remaining portion of the multilayer stack 22. The layers in the remaining portion 22' may be referred to as nanostructures hereinafter. Etching may be implemented by any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. Etching may be anisotropic. The pseudo semiconductor layer 24A and the pseudo nanostructure 24B may be further collectively referred to as pseudo nanostructure 24.

[0020] The lower semiconductor nanostructure 26L will be used as the channel region of the lower nanostructure-FET for the CFET. The upper semiconductor nanostructure 26U will be used as the channel region of the upper nanostructure-FET for the CFET. The intermediate semiconductor nanostructure 26M is a semiconductor nanostructure directly located above / below (e.g., in contact with) the pseudo nanostructure 24B. The intermediate semiconductor nanostructure 26M can be used for isolation and may or may not be used as a channel region for the CFET. Subsequently, the pseudo nanostructure 24B will be replaced with a dielectric isolation structure. The dielectric isolation structure and the intermediate semiconductor nanostructure 26M can define the boundaries of the lower nanostructure-FET and the upper nanostructure-FET.

[0021] Isolation regions 32 are formed above substrate 20 and between adjacent semiconductor strips 28. The corresponding process is shown as follows. Fig.19. The isolation region 32 may include a dielectric liner and a dielectric material over the dielectric liner. Each of the dielectric liner and the dielectric material may include an oxide such as silicon oxide, a nitride such as silicon nitride, or the like, or a combination thereof. The formation of the isolation region 32 may include: depositing a dielectric layer; and performing a planarization process such as a chemical mechanical polishing (CMP) process, a mechanical polishing process, or the like, to remove excess portions of the dielectric material. The deposition process may include chemical vapor deposition (CVD), atomic layer deposition (ALD), HDP-CVD, flowable chemical vapor deposition (FCVD), or the like, or a combination thereof. According to some embodiments, the isolation region 32 includes silicon oxide formed by an FCVD process and a subsequent annealing process.

[0022] After the planarization process, the isolation regions 32 are recessed. Some upper portions of the semiconductor strips 28 (including the multilayer stack 22') protrude above the remaining isolation regions 32 to form protruding fins 34. The corresponding process is also shown as Fig.19 Process 206 in process flow 200 is shown in FIG.

[0023] A dummy gate dielectric 36 is then formed on the protruding fin 34. The dummy gate dielectric 36 may be formed of or include, for example, silicon oxide, silicon nitride, combinations thereof, etc., and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 38 is formed over the dummy gate dielectric 36. The dummy gate layer 38 may be deposited, for example, by physical vapor deposition (PVD), CVD, or other techniques, and then planarized, such as by a CMP process. The material of the dummy gate layer 38 may be conductive or non-conductive, and may be selected from a group including amorphous silicon, polycrystalline silicon (poly silicon), polycrystalline silicon germanium (poly-SiGe), etc. One or more mask layers 40, which may include, for example, silicon nitride, silicon oxynitride, etc., are formed over the planarized dummy gate layer 38.

[0024] Next, mask layer 40 may be patterned by photolithography and etching processes to form a mask, which is then used to etch and pattern dummy gate layer 38 , and possibly dummy gate dielectric 36 . Figure 3 The resulting structure is shown in Figure 3 Shows Figure 2 The vertical cross section 3-3 in FIG. 3 is along the longitudinal direction of the semiconductor strip 28. The remaining portion of the mask layer 40, the dummy gate layer 38 and the dummy gate dielectric 36 form a dummy gate stack 42, as shown in FIG. Figure 3 The corresponding process is shown as Fig.19 Process 208 in process flow 200 is shown in FIG.

[0025] Then, gate spacers 44 are formed over the multilayer stack 22' and on the exposed sidewalls of the dummy gate stack 42. The corresponding process is shown as follows: Fig.19 The process 210 in the process flow 200 shown in FIG. The gate spacer 44 may be formed by conformal deposition of one or more dielectric layers and subsequent anisotropic etching of the dielectric layers. Applicable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride oxide, etc., which may be formed by deposition processes such as CVD, ALD, etc.

[0026] refer to Figure 4 , a source / drain recess 46 is formed in the semiconductor strip 28. The corresponding process is also shown as Fig.19 The process 210 in the process flow 200 shown in FIG. The source / drain recess 46 is formed by etching and can extend through the multilayer stack 22' and into the semiconductor strip 20'. The bottom surface of the source / drain recess 46 can be located at a level above, below, or flush with the top surface of the isolation region 32 ( Figure 4 4. In the etching process, the gate spacers 44 and the dummy gate stack 42 mask some portions of the semiconductor strips 28. The etching may include a single etching process or multiple etching processes. When the source / drain recesses 46 reach a desired depth, a timed etching process may be used to stop the etching of the source / drain recesses 46.

[0027] exist Figure 5 In the embodiment, an internal spacer 54 and a dielectric isolation layer 56 are formed. The corresponding process is shown as follows. Fig.19 The process 212 in the process flow 200 shown in FIG. The formation of the inner spacer 54 and the dielectric isolation layer 56 may include an etching process ( Figure 6 ).

[0028] The etching process may be isotropic and may be selective to the material of dummy semiconductor layer 24A, thereby laterally etching dummy semiconductor layer 24A at a faster rate than semiconductor nanostructures 26U and 26L. The etching process may also be selective to the material of dummy nanostructure 24B ( Figure 4 ), thereby etching the pseudo nanostructure 24B at a faster rate than the pseudo semiconductor layer 24A. In this way, the pseudo nanostructure 24B can be completely removed, while the pseudo semiconductor layer 24A is laterally recessed.

[0029] According to some embodiments, the dummy nanostructure 24B is formed of germanium or silicon germanium with a high germanium atomic percentage, the dummy semiconductor layer 24A is formed of silicon germanium with a low germanium atomic percentage, and the semiconductor nanostructure 26 (including 26M) Figure 4), 26U and 26L) are formed of silicon without germanium, and the etching process may include a dry etching process using chlorine gas, with or without plasma.

[0030] Since the dummy gate stack 42 is in contact with the sidewalls of the semiconductor nanostructure 26 (see Figure 2 ), so the dummy gate stack 42 can support the upper semiconductor nanostructure 26U so that the upper semiconductor nanostructure 26U does not collapse when the dummy nanostructure 24B is removed. In addition, although the sidewalls of the dummy semiconductor layer 24A are shown to be straight after etching, the sidewalls may be concave or convex.

[0031] An internal spacer 54 is formed on the sidewall of the laterally recessed dummy semiconductor layer 24A, and a dielectric isolation layer 56 is formed between the upper semiconductor nanostructure 26U (collectively) and the lower semiconductor nanostructure 26L (collectively). In the subsequent formation of the source / drain region, the internal spacer 54 can be used as an isolation component between the subsequently formed source / drain region and the subsequently formed gate structure. In addition, the internal spacer 54 can be used to prevent damage to the subsequently formed source / drain region by a subsequent etching process (such as an etching process for forming a gate structure). On the other hand, the dielectric isolation layer 56 is used to isolate the upper semiconductor nanostructure 26U (collectively) from the lower semiconductor nanostructure 26L (collectively). In addition, the intermediate semiconductor nanostructure 26M and the dielectric isolation layer 56 can define the boundary of the lower transistor (nanostructure-FET) and the upper transistor.

[0032] The internal spacer 54 and the dielectric isolation layer 56 can be formed by conformally depositing a dielectric insulating material in the source / drain recess 46 and between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L and then etching the insulating material. The insulating material can be a non-low-k dielectric material, which can be a carbon-containing dielectric material, such as silicon oxynitride, silicon oxycarbon, silicon oxynitride, etc. The insulating material can be formed by a deposition process, such as ALD, CVD, etc. The etching of the insulating material can be anisotropic or isotropic. The insulating material (after etching) has a portion remaining on the sidewall of the dummy semiconductor layer 24A (thus forming the internal spacer 54), and has a portion remaining between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L (thus forming the dielectric isolation layer 56).

[0033] Further references Figure 5 , forming a lower epitaxial source / drain region 62L. The lower epitaxial source / drain region 62L is formed in the lower portion of the source / drain recess 46. The corresponding process is shown as follows Fig.19214 in the process flow 200 shown in FIG. The lower epitaxial source / drain region 62L contacts the lower semiconductor nanostructure 26L and does not contact the upper semiconductor nanostructure 26U. The inner spacer 54 electrically insulates the lower epitaxial source / drain region 62L from the dummy semiconductor layer 24A, which will be replaced with a replacement gate in a subsequent process.

[0034] The lower epitaxial source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure-FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the corresponding material may include silicon or carbon-doped silicon, which is doped with n-type dopants such as phosphorus, arsenic, etc. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the corresponding material may include silicon or silicon germanium, which is doped with p-type dopants such as boron, indium, etc.

[0035] The lower epitaxial source / drain region 62L may be in-situ doped and may or may not be implanted with corresponding p-type or n-type dopants. During epitaxy of the lower epitaxial source / drain region 62L, the upper semiconductor nanostructure 26U may be masked to prevent undesired epitaxial growth on the upper semiconductor nanostructure 26U. After growing the lower epitaxial source / drain region 62L, the mask on the upper semiconductor nanostructure 26U is removed.

[0036] A first contact etch stop layer (CESL) 66 and a first interlayer dielectric (ILD) 68 are formed over the lower epitaxial source / drain regions 62L. The first CESL 66 may be formed of a dielectric material having a high etch selectivity relative to the etching of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which may be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 68 may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 68 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

[0037] The formation process may include: depositing a conformal CESL layer; depositing a material for the first ILD 68; and a subsequent planarization process and then an etch-back process. According to some embodiments, the first ILD 68 is first etched, leaving the first CESL 66 unetched. An anisotropic etching process is then performed to remove the portion of the first CESL 66 that is above the recessed first ILD 68. After the recessing, the sidewalls of the upper semiconductor nanostructure 26U are exposed.

[0038] An upper epitaxial source / drain region 62U is then formed in the upper portion of the source / drain recess 46. The corresponding process is also shown as Fig.19 214 in the process flow 200 shown in FIG. The upper epitaxial source / drain region 62U may be epitaxially grown from the exposed surface of the upper semiconductor nanostructure 26U. The epitaxy of the lower source / drain region 62L and the upper source / drain region 62U may be performed at a wafer temperature in the range of about 450° C. to about 600° C. In addition, an etching gas such as hydrogen fluoride (HF) may be used to achieve selective growth from the nanostructure 26 rather than from the dielectric material.

[0039] The material of the upper epitaxial source / drain region 62U may be selected from the same set of candidate materials used to form the lower source / drain region 62L, depending on the desired conductivity type of the upper epitaxial source / drain region 62U.

[0040] The conductivity type of the upper epitaxial source / drain region 62U can be opposite to the conductivity type of the lower epitaxial source / drain region 62L. For example, the upper epitaxial source / drain region 62U can be oppositely doped relative to the lower epitaxial source / drain region 62L. The upper epitaxial source / drain region 62U can be in-situ doped and / or can be implanted with n-type or p-type dopants. Adjacent upper source / drain regions 62U can remain separated after the epitaxial process, or can be merged.

[0041] After forming the epitaxial source / drain regions 62U, the second CESL 70 and the second ILD 72 are formed. The materials and formation methods may be similar to those of the first CESL 66 and the first ILD 68, respectively, and are not discussed in detail herein. The formation process may include: depositing layers for the CESL 70 and the ILD 72; and performing a planarization process to remove excess portions of the corresponding layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacers 44, and the dummy gate stack 42 are coplanar (within process variations). The planarization process may remove the mask 40, or leave the hard mask 40 unremoved.

[0042] Then, in one or more etching steps, the Figure 5 , thereby forming a groove extending to a level lower than the multilayer stack 22' between the gate spacers 44. Therefore, the sidewalls of the multilayer stack 22' are exposed, and the sidewalls of the nanostructures 26U and 26L and the dummy semiconductor layer 24A are exposed.

[0043] The dummy semiconductor layer 24A is then removed such that the recess extends laterally between the semiconductor nanostructures 26U and 26L. According to some embodiments, the dummy gate stack 42 and the dummy dielectric 36 are removed by an isotropic etching process. The dummy semiconductor layer 24A may be removed by any acceptable etching process that selectively etches the material of the dummy semiconductor layer 24A at a faster rate than the material of the semiconductor nanostructures 26, the internal spacers 54, and the isolation structures 56. The etching may be isotropic.

[0044] exist Figure 6 In the embodiment, a replacement gate stack 82 (including gate stacks 82U and 82L) is formed, which includes a gate dielectric 78 and a gate electrode 80 (also including gate electrodes 80U and 80L). The corresponding process is shown as follows Fig.19 215 in the process flow 200 shown in . The gate dielectric 78 may be conformally formed on the channel region of the semiconductor nanostructure 26. Each of the gate dielectrics 78 may include an interfacial layer (IL) that may be formed of or include an oxide such as silicon oxide or a metal oxide, a silicate such as a metal silicate, a combination thereof, a multilayer thereof, etc. Each of the gate dielectrics 78 may also include a high dielectric constant (high-k) dielectric layer formed of a high-k dielectric material having a k value greater than 3.9. The high-k dielectric material may include a metal oxide or a metal nitride of a metal such as hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, and lead. The formation method of the gate dielectric 78 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0045] Further references Figure 6 , the lower gate electrode 80L is formed on the gate dielectric 78. The lower gate electrode 80L is disposed between the lower semiconductor nanostructures 26L. Therefore, the lower gate electrode 80L also wraps the lower semiconductor nanostructure 26L. The upper gate electrode 80U is formed on the gate dielectric 78. The upper gate electrode 80U is disposed between the upper semiconductor nanostructures 26U. Therefore, the upper gate electrode 80U also wraps the upper semiconductor nanostructure 26U.

[0046] The lower gate electrode 80L and the upper gate electrode 80U may include an adhesion layer, a work function layer, a fill metal, etc. The material of the work function layer is selected based on the conductivity type of the corresponding FET. For example, for an n-type FET, an n-type work function material such as TiAl, TiAlN, etc. can be used to form the work function layer. For a p-type FET, a p-type work function material such as TiN can be used to form the work function layer. According to some embodiments, the upper gate electrode 80U can be recessed to form a groove between the opposing gate spacers 44, and then a dielectric material is filled into the groove to form a gate hard mask (not shown). Figure 6 The structure shown in FIG. 1 includes a lower transistor 10L and an upper transistor 10U, which together form a CFET 10.

[0047] Fig. 7A and FIG. 7B to FIG. 18A and Fig.18B The formation of a local interconnect for electrically connecting the lower source / drain region 62L to the upper source / drain region 62U is shown in accordance with some embodiments. Fig. 7A and Figure 7B , forming CESL 84 , ILD 86 and hard mask 88 . Figure 7B Shows Fig. 7A Vertical section BB in.

[0048] According to some embodiments, CESL 84 and ILD 86 are formed using materials similar to or the same as those of CESL 70 and ILD 72, respectively. The corresponding processes are also shown as follows. Fig.19 216 in the process flow 200 shown in FIG. The hard mask 88 may be formed of amorphous silicon (α-Si), tungsten-doped carbide (WDC), SiN, TiN, BN, etc., or multiple layers thereof. According to an embodiment, a top layer of the hard mask 88 includes α-Si, and a bottom layer of the hard mask 88 includes WDC.

[0049] Fig. 8A and Figure 8B The formation and patterning of an etch mask 90 (which may include a photoresist and may or may not include a bottom anti-reflective coating (BARC)) according to some embodiments is shown. According to some embodiments, an opening 92 is formed in the etch mask 90. ​​Then, the top layer of the hard mask 88 is etched using the etch mask 90 to define a pattern, and then the remaining etch mask 90 is removed. After etching, the layers of the hard mask 88, for example, the top layer formed of amorphous silicon, are removed. The resulting structure is Fig.9A and Fig. 9B Shown in.

[0050] refer to Fig. 10A and Fig. 10B , ILD 86, CESL 84, ILD 72 and CESL 70 are etched to form opening 94, exposing the upper source / drain region 62U below. Hard mask 88 is used as an etch mask. The corresponding process is also shown as Fig.19 The process 218 in the process flow 200 shown in FIG. The opening 94 includes an opening 94A, which is used to form a contact plug to connect to the upper source / drain region 62U. The opening 94 also includes an opening 94B, which is used to form a contact plug (also called a local interconnect) that electrically interconnects the lower source / drain region 62L and the upper source / drain region 62U.

[0051] Fig.11A and Fig. 11B The formation of a contact spacer 101 (liner) according to some embodiments is shown. The contact spacer 101 can be formed by depositing a conformal dielectric layer using a conformal deposition process (such as ALD, CVD, etc.) and performing an anisotropic etching process to remove horizontal portions of the dielectric liner. The contact spacer 101 can be formed of or include silicon nitride (SiN), however other dielectric materials such as SiC, SiON, SiCN, etc. can also be used.

[0052] Fig.11A and Fig. 11B Also shown is the etching process for extending the opening 94B downward to the lower source / drain region 62L. The corresponding process is also shown as Fig.19 200 in the process flow 200 shown in FIG. According to some embodiments, a BARC 96 is formed to fill the opening 94. According to some embodiments, the BARC 96 may be a polymer and may be a cross-linked photoresist. According to some embodiments, the BARC 96 is etched using another etch mask (not shown), which may be a patterned photoresist.

[0053] Next, etching is performed through the upper source / drain region 62U, followed by etching of the ILD 68 and CESL 66, so that the opening 94 extends to the lower source / drain region 62L. During the etching process, the remaining hard mask 88 can be used to stop the etching and define some sidewalls of the opening 94B ( Fig. 11B , the rightmost wall of BARC 96). The lower source / drain region 62L is exposed.

[0054] Subsequently, the BARC 96 is removed, and then a sacrificial layer 102 is formed, as shown in FIG. Fig. 12A and Fig. 12B . According to some embodiments, sacrificial layer 102 is formed of another BARC material such as a cross-linked photoresist, however other materials having sufficient etch selectivity relative to ILD 86, CESL 84, upper source / drain region 62U, and lower source / drain region 62L may be used. Sacrificial layer 102 is formed to have a flat top surface and then etched back so that its top surface is lower than the top surface of ILD 86. The remaining hard mask 88 ( Fig.11A and Fig. 11B ), the remaining hard mask 88 may include a WDC layer, wherein a sacrificial layer 102 is used to protect the exposed upper source / drain region 62U and the lower source / drain region 62L.

[0055] According to some embodiments, the top corners of the contact spacers 101 and the ILD 86 are rounded by, for example, an isotropic etching process. The corresponding process is also referred to as top corner rounding (TCR). As a result, the top portion of the opening 94 is enlarged and rounded, so that subsequent processes can be performed with less difficulty. Then, the sacrificial layer 102 is removed, for example, by an etching process.

[0056] Fig.13A and Fig. 13B 1 shows a deposition process for selectively depositing semiconductor layers 104U and 104L (collectively referred to as semiconductor layer 104) on the exposed surfaces of the upper source / drain region 62U and the lower source / drain region 62L, respectively. The corresponding process is also shown as Fig.19 222 in the process flow 200 shown in . According to some embodiments, the deposition process is an epitaxial process. The formation of the semiconductor layers 104U and 104L can be implemented at a temperature lower than the wafer temperature range for the epitaxy of the lower source / drain region 62L and the upper source / drain region 62U. This can advantageously reduce the thermal budget because high temperature growth at this stage may cause damage. For example, low temperature epitaxy of the semiconductor layers 104U and 104L can be implemented at a temperature in a range between about 200°C and about 400°C, which is lower than the temperature range in the epitaxy of the lower source / drain region 62L and the upper source / drain region 62U (e.g., between about 450°C and about 600°C).

[0057] With low temperature growth, selectivity (which is the ratio of the semiconductor growth rate on the semiconductor region to the growth rate on the dielectric material) is unfavorably reduced. To solve this problem, the flow rate of the etching gas (which is used to remove the semiconductor layer 104 grown on the dielectric) is increased, and can be increased to twice, three times, five times or more times the flow rate of the etching gas used in the epitaxy of the lower source / drain region 62L and the upper source / drain region 62U. Increasing the flow rate of the etching gas can also make the vertical growth rate higher than the horizontal growth rate, and make the growth of the semiconductor layer 104 more bottom-up. This is advantageous. For example, the thickness T1 and T3 of the vertical growth portion are greater than the thickness T2 of the sidewall portion, wherein T1 / T2 (and T3 / T2) is greater than about 1.5, greater than about 2, greater than about 5 or even greater.

[0058] In addition, because low temperatures are used and growth selectivity decreases, chlorine-containing precursors (which provide silicon) are used to increase growth selectivity. For example, trichlorosilane (SiH 3 Cl, TCS), dichlorosilane (SiH 2 Cl 2 , DCS) and / or SiH 3 Cl can be used as a silicon precursor. These precursors have higher 4) high activation energy Ea, and for Si, it is more difficult to have nucleation on the surface of the dielectric material. This combined with a higher flow rate of the etching gas can improve the selectivity of the growth.

[0059] According to some embodiments, the semiconductor layer 104 has a crystalline structure. Alternatively, due to a low growth temperature, the semiconductor layer 104 may have a polysilicon structure.

[0060] According to some embodiments, semiconductor layer 104 is formed of similar materials and may have the same dopant type as the dopant type of lower source / drain region 62L. For example, when lower source / drain region 62L is a p-type region including SiGeB, semiconductor layer 104 may also be in-situ doped with boron and may be formed of SiGeB. In an exemplary embodiment, the atomic percentage of germanium in semiconductor layer 104 may be in a range between about 20% and about 60%. According to some embodiments, the boron concentration may be about 1E20 / cm 3 and about 9E20 / cm 3 Alternatively, if the lower source / drain region 62L is an n-type region including SiP, the semiconductor layer 104 may also be formed of SiP.

[0061] Fig.14A and Fig. 14B The protective liner 108 is shown formed by a conformal deposition process (eg, ALD or CVD). The corresponding process is also shown as Fig.19 The process 224 in the process flow 200 shown in FIG. The protective liner 108 may be formed of or include a material having a high etch selectivity to the material in contact with it. For example, the protective liner 108 may be formed of or include an oxide, such as silicon oxide, AlN, AlO, TiN, SiC, etc.

[0062] Fig.15A and Fig. 15B The formation of the sacrificial layer 110 according to some embodiments is shown. The corresponding process is also shown as follows Fig.19 226 in the process flow 200 shown in FIG. According to some embodiments, the sacrificial layer 110 is formed of or includes a polymer, which may also be a photoresist according to some embodiments. According to some embodiments, the formation process includes spin coating and curing the sacrificial layer 110. The sacrificial layer 110 (which includes the photoresist) may also be cross-linked by performing an exposure process. The sacrificial layer 110 is then etched back so that its top surface is lower than the bottom end of the semiconductor layer 104U. The semiconductor layer 104L is covered by the sacrificial layer 110. The etch back process may use, for example, H 2 、N 2 etc. or a combination thereof is used as the etching gas.

[0063] refer to Fig.16A and Fig. 16B , for example, etching the exposed portion of the protective liner 108 in an isotropic etching process, which can be a wet etching process or a dry etching process. The corresponding process is also shown as Fig.19 The process 228 in the process flow 200 is shown in FIG. Thus, the semiconductor layer 104U is exposed.

[0064] The exposed semiconductor layer 104U is then etched. The corresponding process is also shown as Fig.19 The process 230 in the process flow 200 shown in FIG. 1 can be used to remove the protective liner 108 and the semiconductor layer 104U using HCl or a catalyst including NH 4 OH, H 2 O 2 and H 2 O (sometimes referred to as Standard Clean 1 (SC1) solution) or a chemical solution including HCl, H 2 O 2 and H 2 O chemical solution (sometimes called Standard Clean 2 (SC2) solution).

[0065] After the etching process, the remaining sacrificial layer 110 and the protective liner 108 are removed, for example in an isotropic etching process. The corresponding process is also shown as Fig.19 The process 232 in the process flow 200 shown in FIG. The resulting structure is Fig.17A and Fig. 17B As shown in Fig.11A and FIG. 11B to FIG. 17A and Fig. 17B The process shown in has the net effect of selectively forming the semiconductor layer 104L on the lower source / drain region 62U, and the semiconductor layer 104L becomes an extension of the lower source / drain region 62L. Throughout the description, the lower source / drain region 62L and the semiconductor layer 104L are collectively referred to as the lower source / drain region 62L'. As the lower semiconductor layer 104L is formed, the aspect ratio of the opening 94B is reduced.

[0066] Fig.18A and Fig.18B The formation of the silicide layers 112L and 112U and the formation of the contact plugs 118 and 120 are shown. The corresponding processes are also shown as follows. Fig.19 The formation of the silicide layers 112L and 112U may include: depositing a metal layer (such as a titanium layer or a cobalt layer) extending into the opening 94; performing an annealing process to form the silicide layers 112L and 112U; and removing the remaining metal layer (if any).

[0067] Contact plugs 118 and 120 are then formed which may include a barrier / adhesion layer 114 and a metal region 116 on the adhesion layer 114. The corresponding process is also shown as Fig.19 The process 236 in the process flow 200 shown in FIG. The barrier / adhesion layer 114 may include Ti, TiN, Ta, TaN, etc. The metal region 116 may include tungsten, cobalt, etc. The contact plugs 118 and 120 may also be barrier-free, where there is no barrier / adhesion layer.

[0068] The contact plug 120 is electrically connected to the upper source / drain region 62U. The contact plug 118 serves as a local interconnection that electrically interconnects the lower source / drain region 62' and the upper source / drain region 62U.

[0069] Embodiments of the present disclosure have some advantageous features. By forming a semiconductor layer over the lower source / drain region, the aspect ratio of the opening for forming the local interconnect is reduced. Because the opening has a high aspect ratio, and also because the upper silicide layer occupies the already narrow opening, it is difficult to form deep local interconnects. In embodiments of the present disclosure, as the aspect ratio decreases, the difficulty of forming the local interconnect is reduced, and it is less likely to have voids in the local interconnect.

[0070] According to some embodiments of the present disclosure, the method includes: forming a complementary field effect transistor, including: a lower transistor, including a lower source / drain region; and an upper transistor, including an upper source / drain region; etching an upper dielectric layer above the upper source / drain region and a lower dielectric layer between the upper source / drain region and the lower source / drain region to form an opening, wherein the sidewalls of the upper source / drain region and the top surface of the lower source / drain region are exposed to the opening; performing an epitaxial process to form: a first semiconductor layer, located on the sidewalls of the upper source / drain region; and a second semiconductor layer, located on the top surface of the lower source / drain region; removing the first semiconductor layer, wherein the second semiconductor layer remains, wherein the second semiconductor layer and the lower source / drain region together form a combined source / drain region; and forming a contact plug in the opening, wherein the contact plug electrically connects the upper source / drain region to the combined source / drain region.

[0071] In an embodiment, the upper source / drain region has a first conductivity type, the lower source / drain region has a second conductivity type opposite to the first conductivity type, and wherein, in an epitaxial process, the first semiconductor layer and the second semiconductor layer are in-situ doped with a dopant of the second conductivity type. In an embodiment, the first semiconductor layer is removed by a process comprising: forming a sacrificial layer to fill the opening; recessing the sacrificial layer so that the first semiconductor layer is exposed and the second semiconductor layer is covered by the sacrificial layer; etching the first semiconductor layer; and removing the sacrificial layer.

[0072] In an embodiment, the method further comprises: depositing a protective liner extending into the opening, wherein a sacrificial layer is formed on the protective liner, and the method further comprises: after recessing the sacrificial layer, etching a portion of the protective liner above the sacrificial layer, wherein the protective liner is also removed after removing the first semiconductor layer. In an embodiment, the method further comprises: epitaxially growing the lower source / drain region and the upper source / drain region at a first wafer temperature, wherein the epitaxial process is performed at a second wafer temperature lower than the first wafer temperature. In an embodiment, the epitaxial process is performed at a wafer temperature in a range between about 200°C and about 400°C.

[0073] In an embodiment, the epitaxial process is implemented using a chlorine-containing silicon precursor. In an embodiment, the epitaxial process is implemented with a vertical growth rate greater than a horizontal growth rate. In an embodiment, the epitaxial process is implemented using an etching gas having a first flow rate, and one of the lower source / drain region and the upper source / drain region is epitaxially grown using an etching gas having a second flow rate, and the first flow rate is greater than the second flow rate. In an embodiment, the etching gas includes hydrogen fluoride (HF), and the ratio of the first flow rate to the second flow rate is greater than about 2. In an embodiment, the method further includes, before forming the contact plug: forming a lower silicide layer on the second semiconductor layer; and forming an upper silicide layer on the sidewalls of the upper source / drain region.

[0074] According to some embodiments of the present disclosure, a device includes: a lower transistor including a lower source / drain region, and the lower source / drain region includes: a lower portion; and an upper portion located above the upper portion and connected to the upper portion; a lower CESL located on the lower portion of the lower source / drain region, wherein a first top surface of the upper portion of the lower source / drain region is higher than a second top surface of the lower CESL; a lower ILD located above the lower CESL; a lower silicide layer located on the first top surface of the upper portion of the lower source / drain region; an upper source / drain region overlapping the lower source / drain region; an upper silicide layer located on the upper source / drain region; an upper CESL located on the upper source / drain region; an upper ILD located above the upper CESL; and a contact plug contacting both the upper silicide layer and the lower silicide layer.

[0075] In an embodiment, the lower portion and the upper portion of the lower source / drain region have the same conductivity type. In an embodiment, the upper portion of the lower source / drain region is lower than the top surface of the lower ILD. In an embodiment, the first sidewall of the upper portion of the lower source / drain region is substantially vertical and substantially straight. In an embodiment, the portion of the contact plug located in the lower ILD includes a second sidewall vertically aligned with the first sidewall.

[0076] According to some embodiments of the present disclosure, a device includes: a complementary field effect transistor, including: a lower transistor, including a lower source / drain region, and the lower source / drain region includes a lower portion and an upper portion above the lower portion; and an upper transistor, including an upper source / drain region; a lower contact etch stop layer, located on the lower portion of the lower source / drain region, wherein the upper portion of the lower source / drain region penetrates the lower contact etch stop layer; a lower silicide layer, located on the top surface of the upper portion of the lower source / drain region; an upper silicide layer, located on the sidewall of the upper source / drain region; and a contact plug, contacting the upper silicide layer and the lower silicide layer.

[0077] In an embodiment, a first edge of an upper portion of the lower source / drain region is vertically aligned with a corresponding second edge of a lower portion of the contact plug. In an embodiment, an upper portion of the lower source / drain region has the same top-view shape as a lower portion of the contact plug. In an embodiment, the device further comprises a lower interlayer dielectric located on the lower contact etch stop layer, wherein a top surface of the upper portion of the lower source / drain region is located at an intermediate level between an additional top surface and a bottom surface of the lower interlayer dielectric.

[0078] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a complementary field effect transistor, comprising: a lower transistor, comprising a lower source / drain region; and an upper transistor, comprising an upper source / drain region; etching an upper dielectric layer above the upper source / drain region and a lower dielectric layer between the upper source / drain region and the lower source / drain region to form an opening, wherein the sidewalls of the upper source / drain region and the top surface of the lower source / drain region are exposed to the opening; performing an epitaxial process to form: a first semiconductor layer, located on the sidewalls of the upper source / drain region; and a second semiconductor layer, located on the top surface of the lower source / drain region; removing the first semiconductor layer, wherein the second semiconductor layer is retained, wherein the second semiconductor layer and the lower source / drain region together form a combined source / drain region; and forming a contact plug in the opening, wherein the contact plug electrically connects the upper source / drain region to the combined source / drain region.

[0079] In some embodiments, the upper source / drain region has a first conductivity type, the lower source / drain region has a second conductivity type opposite to the first conductivity type, and wherein, in the epitaxial process, the first semiconductor layer and the second semiconductor layer are in-situ doped with dopants of the second conductivity type.

[0080] In some embodiments, the first semiconductor layer is removed by a process including: forming a sacrificial layer to fill the opening; recessing the sacrificial layer so that the first semiconductor layer is exposed and the second semiconductor layer is covered by the sacrificial layer; etching the first semiconductor layer; and removing the sacrificial layer.

[0081] In some embodiments, the method also includes: depositing a protective liner extending into the opening, wherein the sacrificial layer is formed on the protective liner, and the method also includes: after recessing the sacrificial layer, etching a portion of the protective liner that is higher than the sacrificial layer, wherein the protective liner is also removed after removing the first semiconductor layer.

[0082] In some embodiments, the method further comprises:

[0083] The lower source / drain region and the upper source / drain region are epitaxially grown at a first wafer temperature, wherein the epitaxial growth process is performed at a second wafer temperature lower than the first wafer temperature.

[0084] In some embodiments, the epitaxial process is performed at a wafer temperature in a range between 200°C and 400°C.

[0085] In some embodiments, the epitaxial process is performed using a chlorine-containing silicon precursor.

[0086] In some embodiments, the epitaxial process is performed with a vertical growth rate greater than a horizontal growth rate.

[0087] In some embodiments, the epitaxial process is performed using an etching gas having a first flow rate, and one of the lower source / drain region and the upper source / drain region is epitaxially grown using the etching gas having a second flow rate, and the first flow rate is greater than the second flow rate.

[0088] In some embodiments, the etching gas includes hydrogen fluoride (HF), and a ratio of the first flow rate to the second flow rate is greater than 2.

[0089] In some embodiments, the method further includes, before forming the contact plug: forming a lower silicide layer on the second semiconductor layer; and forming an upper silicide layer on the sidewalls of the upper source / drain region.

[0090] Some other embodiments of the present application provide a semiconductor device, comprising: a lower transistor, comprising a lower source / drain region, wherein the lower source / drain region comprises: a lower portion; and an upper portion, located above the upper portion and connected to the upper portion; a lower contact etch stop layer, located on the lower portion of the lower source / drain region, wherein a first top surface of the upper portion of the lower source / drain region is higher than a second top surface of the lower contact etch stop layer; a lower interlayer dielectric, located above the lower contact etch stop layer; a lower silicide layer located on the first top surface of the upper portion of the lower source / drain region; an upper source / drain region overlapping the lower source / drain region; an upper silicide layer located on the upper source / drain region; an upper contact etch stop layer located on the upper source / drain region; an upper interlayer dielectric located above the upper contact etch stop layer; and a contact plug contacting both the upper silicide layer and the lower silicide layer.

[0091] In some embodiments, the lower portion and the upper portion of the lower source / drain region have the same conductivity type.

[0092] In some embodiments, the upper portion of the lower source / drain region is below a top surface of the lower interlayer dielectric.

[0093] In some embodiments, the first sidewall of the upper portion of the lower source / drain region is substantially vertical and substantially straight.

[0094] In some embodiments, a portion of the contact plug located in the lower interlayer dielectric includes a second sidewall vertically aligned with the first sidewall.

[0095] Still other embodiments of the present application provide a semiconductor device, comprising: a complementary field effect transistor, comprising: a lower transistor, comprising a lower source / drain region, and the lower source / drain region comprises a lower portion and an upper portion located above the lower portion; and an upper transistor, comprising an upper source / drain region; a lower contact etch stop layer, located on the lower portion of the lower source / drain region, wherein the upper portion of the lower source / drain region penetrates the lower contact etch stop layer; a lower silicide layer, located on the top surface of the upper portion of the lower source / drain region; an upper silicide layer, located on the sidewalls of the upper source / drain region; and a contact plug, contacting the upper silicide layer and the lower silicide layer.

[0096] In some embodiments, a first edge of the upper portion of the lower source / drain region is vertically aligned with a corresponding second edge of a lower portion of the contact plug.

[0097] In some embodiments, the upper portion of the lower source / drain region has the same top-view shape as the lower portion of the contact plug.

[0098] In some embodiments, the semiconductor device further includes a lower interlayer dielectric on the lower contact etch stop layer, wherein the top surface of the upper portion of the lower source / drain region is at an intermediate level between an additional top surface and a bottom surface of the lower interlayer dielectric.

[0099] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: A complementary field effect transistor is formed, comprising: a lower transistor including a lower source / drain region; and an upper transistor including an upper source / drain region; Etching an upper dielectric layer above the upper source / drain region and a lower dielectric layer between the upper source / drain region and the lower source / drain region to form an opening, wherein a sidewall of the upper source / drain region and a top surface of the lower source / drain region are exposed to the opening; An epitaxial process is performed to form: A first semiconductor layer located on the sidewalls of the upper source / drain region; and a second semiconductor layer located on the top surface of the lower source / drain region; removing the first semiconductor layer, wherein the second semiconductor layer remains, wherein the second semiconductor layer and the lower source / drain region together form a combined source / drain region; and A contact plug is formed in the opening, wherein the contact plug electrically connects the upper source / drain region to the combined source / drain region.

2. The method according to claim 1, wherein: The upper source / drain region has a first conductivity type, the lower source / drain region has a second conductivity type opposite to the first conductivity type, and wherein, in the epitaxial process, the first semiconductor layer and the second semiconductor layer are in-situ doped with dopants of the second conductivity type.

3. The method according to claim 1, wherein: The first semiconductor layer is removed by a process comprising: forming a sacrificial layer to fill the opening; recessing the sacrificial layer so that the first semiconductor layer is exposed and the second semiconductor layer is covered by the sacrificial layer; etching the first semiconductor layer; as well as The sacrificial layer is removed.

4. The method according to claim 3, further comprising: A protective liner is deposited extending into the opening, wherein the sacrificial layer is formed on the protective liner, and the method further comprises: after recessing the sacrificial layer, etching a portion of the protective liner above the sacrificial layer, wherein the protective liner is removed after removing the first semiconductor layer.

5. The method according to claim 1, further comprising: The lower source / drain region and the upper source / drain region are epitaxially grown at a first wafer temperature, wherein the epitaxial growth process is performed at a second wafer temperature lower than the first wafer temperature.

6. The method according to claim 1, wherein: The epitaxial process is performed at a wafer temperature ranging between 200°C and 400°C.

7. The method according to claim 1, wherein: The epitaxial process is performed using a chlorine-containing silicon precursor.

8. The method according to claim 1, wherein: The epitaxial process is performed with a vertical growth rate greater than a horizontal growth rate.

9. A semiconductor device comprising: A lower transistor including a lower source / drain region, and the lower source / drain region includes: a lower portion; and an upper portion located above and connected to the upper portion; a lower contact etch stop layer located on the lower portion of the lower source / drain region, wherein a first top surface of the upper portion of the lower source / drain region is higher than a second top surface of the lower contact etch stop layer; a lower interlayer dielectric disposed above the lower contact etch stop layer; a lower silicide layer disposed on the first top surface of the upper portion of the lower source / drain region; an upper source / drain region overlapping the lower source / drain region; an upper silicide layer located on the upper source / drain region; an upper contact etch stop layer located on the upper source / drain region; an upper interlayer dielectric located above the upper contact etch stop layer; and A contact plug contacts both the upper silicide layer and the lower silicide layer.

10. A semiconductor device comprising: Complementary field effect transistors, including: a lower transistor including a lower source / drain region, wherein the lower source / drain region includes a lower portion and an upper portion located above the lower portion; and an upper transistor including an upper source / drain region; a lower contact etch stop layer on the lower portion of the lower source / drain region, wherein the upper portion of the lower source / drain region penetrates the lower contact etch stop layer; a lower silicide layer disposed on a top surface of the upper portion of the lower source / drain region; an upper silicide layer located on the sidewalls of the upper source / drain region; and A contact plug contacts the upper silicide layer and the lower silicide layer.

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