Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes: a back surface wiring line; a first fin pattern on the back surface wiring line; a second fin-shaped pattern spaced apart from the first fin-shaped pattern; a field insulating film on the first surface of the back wiring line, covering sidewalls of the first fin pattern and sidewalls of the second fin pattern, and including an upper surface and a bottom surface; a back contact guide pattern on the first surface of the back wiring line between the first fin pattern and the second fin pattern, and including an upper surface and a bottom surface, the bottom surface of the back contact guide pattern facing the first surface of the back wiring line; a first source / drain pattern on the first fin pattern; and a backside source / drain contact connecting the first source / drain pattern to the backside wiring line, in which at least a portion of the backside source / drain contact is disposed in the first fin pattern.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0174024 filed in the Korean Intellectual Property Office on December 5, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a semiconductor device. Background Art

[0003] As one of scaling technologies for increasing the density of semiconductor devices, a multi-gate transistor having a fin-shaped or nanowire-shaped multi-channel active pattern (or silicon body) formed on a substrate and a gate formed on a surface of the multi-channel active pattern has been proposed.

[0004] Since such a multi-gate transistor utilizes a three-dimensional channel, it is easy to scale. In addition, the current control capability can be improved even without increasing the gate length of the multi-gate transistor. In addition, the SCE (short channel effect) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed.

[0005] On the other hand, as the pitch size of semiconductor devices decreases, it becomes important to reduce capacitance between contacts in the semiconductor devices and to ensure electrical stability. Summary of the invention

[0006] Aspects of the present disclosure provide a semiconductor device that can improve element performance and reliability.

[0007] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] According to one aspect of the present disclosure, a semiconductor device is provided, which includes: a back wiring line, including a first surface and a second surface opposite to each other in a first direction; a first fin pattern, on the first surface of the back wiring line and extending in the second direction; a second fin pattern, spaced apart from the first fin pattern in a third direction, the second fin pattern extending in the second direction; a field insulating film, on the first surface of the back wiring line, the field insulating film covers the sidewalls of the first fin pattern and the sidewalls of the second fin pattern, and includes an upper surface and a bottom surface opposite to each other in the first direction, the bottom surface of the field insulating film faces the first surface of the back wiring line; a back contact guide pattern, located on the first surface of the back wiring line between the first fin pattern and the second fin pattern, the back contact guide pattern including an upper surface and a bottom surface opposite to each other in the first direction, the bottom surface of the back contact guide pattern faces the first surface of the back wiring line; a first source / drain pattern, on the first fin pattern; and a back source / drain contact, connecting the first source / drain pattern to the back wiring line, wherein at least a portion of the back source / drain contact is disposed in the first fin pattern.

[0009] According to another aspect of the present disclosure, a semiconductor device is provided, which includes: a back wiring line, including a first surface and a second surface opposite to each other in a first direction; a first fin pattern, on the first surface of the back wiring line and extending in the second direction; a field insulating film, on the first surface of the back wiring line, the field insulating film covers the sidewalls of the first fin pattern and includes an upper surface and a bottom surface opposite to each other in the first direction, the bottom surface of the field insulating film faces the first surface of the back wiring line; a source / drain pattern, on the first fin pattern; a back source / drain contact, connecting the source / drain pattern to the back wiring line; and a back contact guide pattern, on both sides of the back source / drain contact and in contact with the back source / drain contact, wherein the back contact guide pattern includes an upper surface and a bottom surface opposite to each other in the first direction, the bottom surface of the back contact guide pattern faces the first surface of the back wiring line, and the height from the second surface of the back wiring line to the bottom surface of the field insulating film is less than the height from the second surface of the back wiring line to the upper surface of the back contact guide pattern.

[0010] According to another aspect of the present disclosure, a semiconductor device is provided, the semiconductor device comprising: a substrate, comprising an upper surface and a bottom surface opposite to each other in a first direction; a first fin pattern, protruding from the upper surface of the substrate in the first direction and extending in a second direction; a second fin pattern, protruding from the upper surface of the substrate in the first direction, spaced apart from the first fin pattern in a third direction, and extending in the second direction; a field insulating film, on the substrate, the field insulating film covering sidewalls of the first fin pattern and sidewalls of the second fin pattern; a back contact guide pattern, between the first fin pattern and the second fin pattern, the back contact guide pattern being disposed in the field insulating film and the substrate; A source / drain pattern on the first fin pattern; a back wiring line on the bottom surface of the substrate; and a back source / drain contact connecting the source / drain pattern to the back wiring line and contacting a back contact guide pattern, wherein the back contact guide pattern includes a first portion arranged in the substrate and a second portion arranged in the field insulating film, the back contact guide pattern includes a first side wall and a second side wall opposite to each other in a third direction, the first side wall of the back contact guide pattern contacts the back source / drain contact, and in the first portion of the back contact guide pattern, the second side wall of the back contact guide pattern forms an acute angle with the bottom surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the attached drawings.

[0012] Figure 1 is a layout diagram for explaining a semiconductor device according to some embodiments.

[0013] Figures 2 to 7 Along the Figure 1 Cross-sectional views taken along lines AA, BB, CC, DD, EE, and FF.

[0014] Figures 8 to 10 They are shown respectively Figure 5 An enlarged view of part P.

[0015] Fig.11 and Fig.12 is a diagram for explaining a semiconductor device according to some embodiments.

[0016] Fig.13 and Fig.14 is a diagram for explaining a semiconductor device according to some embodiments.

[0017] Figures 15 to 17 is a diagram for explaining a semiconductor device according to some embodiments.

[0018] Fig.18 and Fig.19 is a diagram for explaining a semiconductor device according to some embodiments.

[0019] Figure 20 to Figure 23 is a diagram for explaining a semiconductor device according to some embodiments.

[0020] Fig.24 and Fig.25 is a diagram for explaining a semiconductor device according to some embodiments.

[0021] Figure 26 to Figure 28 is a diagram for explaining a semiconductor device according to some embodiments.

[0022] Figure 29 to Figure 44 is a diagram of an intermediate stage for explaining a method for manufacturing a semiconductor device according to some embodiments.

[0023] Figures 45 to 49 is a diagram of an intermediate stage for explaining a method for manufacturing a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0024] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the "first" element discussed below may also be referred to as the "second" element.

[0025] Although the drawings of the semiconductor device according to some embodiments show a fin transistor (FinFET) including a channel region having a fin pattern shape, a transistor including a nanowire or a nanosheet, and an MBCFET TM (Multi-bridge channel field effect transistor) is taken as an example, but the embodiment is not limited thereto.

[0026] Of course, the semiconductor device according to some embodiments may include a tunneling transistor (tunneling FET), a three-dimensional (3D) transistor, or a vertical transistor (vertical FET). Of course, the semiconductor device according to some embodiments may include a planar transistor. In addition, the technical concept of the present disclosure may be applied to transistors based on two-dimensional materials (FETs based on 2D materials) and their heterostructures. In addition, the semiconductor device according to some embodiments may also include a bipolar junction transistor, a lateral diffused metal oxide semiconductor (LDMOS), etc.

[0027] Will refer to Figures 1 to 10 A semiconductor device according to some embodiments is described.

[0028] Figure 1 is a layout diagram for explaining a semiconductor device according to some embodiments. Figures 2 to 7 Along the Figure 1 Cross-sectional views taken along lines AA, BB, CC, DD, EE and FF. Figures 8 to 10 They are shown respectively Figure 5 An enlarged view of part P.

[0029] For ease of explanation, Figure 1 The front wiring line 197 and the front wiring via 196 are not shown. Although not shown, a cross-sectional view taken along the third active pattern AP3 in the first direction X may be similar to Figure 3 sectional view of .

[0030] Reference Figures 1 to 10 According to some embodiments, the semiconductor device may include a substrate 100, a field insulating film 105, a first active pattern AP1, a second active pattern AP2, a third active pattern AP3, a back wiring line 50, a back source / drain contact 70, a back contact guide pattern 80, a plurality of gate electrodes 120, a first source / drain pattern 150, a second source / drain pattern 250, a third source / drain pattern 350, a first front source / drain contact 170, a second front source / drain contact 270, a third front source / drain contact 370, and a source / drain etch stop film 185.

[0031] The substrate 100 may include a first surface 100US and a second surface 100BS opposite to each other in the third direction Z. Since the gate electrode 120 and the source / drain patterns 150, 250, and 350 may be disposed on the first surface 100US of the substrate, the first surface 100US of the substrate may be an upper surface (e.g., a top surface) of the substrate 100. The second surface 100BS of the substrate opposite to the first surface 100US of the substrate may be a lower surface (e.g., a bottom surface) of the substrate 100.

[0032] As used herein, a first element described as being “on” or “disposed on” a second element may be directly on and in contact with the second element, or one or more other elements disposed between the first and second elements may be present.

[0033] For ease of description, spatially relative terms such as "under," "below," "below," "above," "up," "top," "bottom," and the like may be used herein to describe the relationship of one element or feature to another element or features as shown in the figures. It will be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figure is turned over, an element described as "below" or "beneath" other elements or features will then be oriented as "above" the other elements or features. Thus, the term "below" may cover both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0034] The substrate 100 may be made of or include a semiconductor material. The substrate 100 may be a silicon substrate or a silicon-on-insulator (SOI) substrate. Conversely, the substrate 100 may include, for example but not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0035] Each of the active patterns AP1, AP2, and AP3 may be disposed on the substrate 100. For example, each of the active patterns AP1, AP2, and AP3 may be disposed on the first surface 100US of the substrate. Each of the active patterns AP1, AP2, and AP3 may extend longitudinally in the first direction X, respectively.

[0036] As used herein, an object, layer, or portion of an object or layer described as "extending" or "longitudinally extending" in a particular direction has a length in the particular direction and a width perpendicular to the direction, wherein the length is greater than the width.

[0037] The first active pattern AP1 may be spaced apart from the second active pattern AP2 and the third active pattern AP3 in the second direction Y. The first active pattern AP1 may be disposed between the second active pattern AP2 and the third active pattern AP3. The second active pattern AP2 and the third active pattern AP3 may be adjacent to the first active pattern AP1 in the second direction Y, respectively.

[0038] As an example, the first active pattern AP1 and the second active pattern AP2 may be regions where transistors of the same conductivity type are formed. The third active pattern AP3 may be a region where transistors of a conductivity type different from that of the first active pattern AP1 are formed. For example, if the first active pattern AP1 is a region where a p-type transistor is formed, the second active pattern AP2 is a region where a p-type transistor is formed, and the third active pattern AP3 may be a region where an n-type transistor is formed.

[0039] As another example, the first active pattern AP1 and the third active pattern AP3 may be regions where transistors of the same conductivity type are formed. The second active pattern AP2 may be a region where transistors of a conductivity type different from that of the first active pattern AP1 are formed. For example, if the first active pattern AP1 is a region where a p-type transistor is formed, the second active pattern AP2 may be a region where an n-type transistor is formed, and the third active pattern AP3 may be a region where a p-type transistor is formed.

[0040] Each of the active patterns AP1, AP2, and AP3 may be a multi-channel active pattern. For example, the first active pattern AP1 may include a first lower pattern BP1 and a plurality of first sheet patterns NS1. The second active pattern AP2 may include a second lower pattern BP2 and a plurality of second sheet patterns NS2. The third active pattern AP3 may include a third lower pattern BP3 and a plurality of third sheet patterns NS3. In the semiconductor device according to some embodiments, each of the active patterns AP1, AP2, and AP3 may be an active pattern including nanosheets or nanowires.

[0041] Each of the lower patterns BP1, BP2, and BP3 may protrude from the substrate 100. For example, each of the lower patterns BP1, BP2, and BP3 may protrude from the first surface 100US of the substrate in the third direction Z. Each of the lower patterns BP1, BP2, and BP3 may be a fin pattern.

[0042] Each of the lower patterns BP1, BP2, and BP3 may extend longitudinally in the first direction X. The first lower pattern BP1 may be spaced apart from the second and third lower patterns BP2 and BP3 in the second direction Y. The first lower pattern BP1 may be disposed between the second and third lower patterns BP2 and BP3.

[0043] Each of the lower patterns BP1 , BP2 , and BP3 may be separated by a fin trench FT extending in the first direction X. For example, the first surface 100US of the substrate may be a bottom surface of the fin trench FT.

[0044] Reference Figure 7 , for example, the first lower pattern BP1 may include a sidewall BP1_SW extending in the first direction X. The second lower pattern BP2 may include a sidewall BP2_SW extending in the first direction X. The third lower pattern BP3 may include a sidewall BP3_SW extending in the first direction X. The sidewall BP1_SW of the first lower pattern, the sidewall BP2_SW of the second lower pattern, and the sidewall BP3_SW of the third lower pattern may each be defined by the fin trench FT.

[0045] The plurality of first sheet patterns NS1 may be disposed on the first lower pattern BP1. The plurality of first sheet patterns NS1 may be spaced apart from the upper surface BP1_US of the first lower pattern in the third direction Z.

[0046] The plurality of second sheet patterns NS2 may be disposed on the second lower pattern BP2. The plurality of second sheet patterns NS2 may be spaced apart from the upper surface BP2_US of the second lower pattern in the third direction Z.

[0047] A plurality of third sheet patterns NS3 may be disposed on the third lower pattern BP3. The plurality of third sheet patterns NS3 may be spaced apart from the upper surface BP3_US of the third lower pattern in the third direction Z. The first sheet pattern NS1, the second sheet pattern NS2, and the third sheet pattern NS3 may be disposed on the first surface 100US of the substrate.

[0048] Here, the first direction X may intersect the second direction Y and the third direction Z. In addition, the second direction Y may intersect the third direction Z. The third direction Z may be a thickness direction of the substrate 100 .

[0049] The sheet patterns NS1, NS2, and NS3 may each include an upper surface (e.g., top surface) and a bottom surface (e.g., lower surface) opposite to each other in the third direction Z. The bottom surfaces of the sheet patterns NS1, NS2, and NS3 may respectively face the substrate 100. Although it is shown that three sheet patterns NS1, NS2, and NS3 are provided in the third direction Z, this is only for convenience of explanation, and the embodiment is not limited thereto.

[0050] The upper surface AP1_US of the first active pattern may be an upper surface of a first sheet pattern NS1 disposed at the uppermost portion among the plurality of first sheet patterns NS1. The upper surface AP2_US of the second active pattern may be an upper surface of a second sheet pattern NS2 disposed at the uppermost portion among the plurality of second sheet patterns NS2. Although not shown, the upper surface of the third active pattern AP3 may be an upper surface of a third sheet pattern NS3 disposed at the uppermost portion among the plurality of third sheet patterns NS3.

[0051] Each of the lower patterns BP1, BP2, and BP3 may be formed by etching a portion of the substrate 100, or may include an epitaxial layer grown from the substrate 100. Each of the lower patterns BP1, BP2, and BP3 may be formed of, or include, silicon or germanium as an elemental semiconductor material. In addition, each of the lower patterns BP1, BP2, and BP3 may include a compound semiconductor, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0052] The Group IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping these elements with a Group IV element.

[0053] The III-V compound semiconductor may be one of a binary compound, a ternary compound, and a quaternary compound formed, for example, by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as Group III elements with one of phosphorus (P), arsenic (As), and antimony (Sb) as Group V elements.

[0054] Each of the sheet patterns NS1, NS2, and NS3 may be formed of or include one of silicon and germanium, group IV-IV compound semiconductors, and group III-V compound semiconductors as elemental semiconductor materials. Taking the first sheet pattern NS1 as an example, the width of the first sheet pattern NS1 in the second direction Y may be increased or decreased in proportion to the width of the first lower pattern BP1 in the second direction Y. Although the width of each first sheet pattern NS1 disposed on the first lower pattern BP1 in the second direction Y is shown to be the same, the embodiment is not limited thereto.

[0055] The field insulating film 105 is disposed on the substrate 100. For example, the field insulating film 105 may be disposed on the first surface 100US of the substrate. The field insulating film 105 may fill at least a portion of the fin trench FT separating the lower patterns BP1, BP2, and BP3.

[0056] Field insulating film 105 (see, for example, Figures 4 to 7 ) may be disposed between the lower patterns BP1, BP2, and BP3 on the substrate 100. The field insulating film 105 may cover the sidewall BP1_SW of the first lower pattern, the sidewall BP2_SW of the second lower pattern, and the sidewall BP3_SW of the third lower pattern.

[0057] As an example, the field insulating film 105 may cover the entire side wall BP1_SW of the first lower pattern, the entire side wall BP2_SW of the second lower pattern, and the entire side wall BP3_SW of the third lower pattern. Different from the illustrated example, as another example, the field insulating film 105 may cover a portion of the side walls of the lower patterns BP1, BP2, and BP3. In this case, a portion of the lower patterns BP1, BP2, and BP3 may protrude beyond the upper surface of the field insulating film 105 in the third direction Z.

[0058] The field insulating film 105 does not cover the upper surface BP1_US of the first lower pattern. The field insulating film 105 does not cover the upper surface BP2_US of the second lower pattern. The field insulating film 105 does not cover the upper surface BP3_US of the third lower pattern.

[0059] The field insulating film 105 may include an upper surface (e.g., top surface) 105US and a lower surface (e.g., bottom surface) 105BS opposite to each other in the third direction Z. The bottom surface 105BS of the field insulating film may face the substrate 100. The upper surface 105US of the field insulating film may face the gate electrode 120. Each of the sheet patterns NS1, NS2, and NS3 is disposed higher than the upper surface 105US of the field insulating film 105.

[0060] The field insulating film 105 may be formed of, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof, or include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof. Although the field insulating film 105 is shown as a single film, this is for ease of explanation, and the embodiment is not limited thereto.

[0061] exist Figures 5 to 7 Although an upper surface 105US of the field insulating film between the first and second lower patterns BP1 and BP2 and an upper surface 105US of the field insulating film between the first and third lower patterns BP1 and BP3 are illustrated as being coplanar, embodiments are not limited thereto.

[0062] The first lower pattern BP1 will be explained as an example. The first lower pattern BP1 includes a first region overlapping the first sheet pattern NS1 in the third direction Z, and a second region overlapping the first source / drain pattern 150 in the third direction Z. An upper surface BP1_US in the first region of the first lower pattern BP1 may be higher than an upper surface BP1_US in the second region of the first lower pattern BP1. While forming the first source / drain pattern 150, a portion of the first lower pattern BP1 may be etched to lower the upper surface BP1_US of the first lower pattern.

[0063] The field insulating film 105 may include a first region overlapping the gate electrode 120 in the third direction Z, and a second region disposed between the gate electrodes 120. An upper surface 105US in the first region of the field insulating film 105 may be higher than an upper surface 105US in the second region of the field insulating film 105. While forming the first source / drain pattern 150, a portion of the field insulating film 105 disposed between the gate electrodes 120 may be etched to lower the upper surface 105US of the field insulating film 105.

[0064] A plurality of gate structures GS may be disposed on the first surface 100US of the substrate. Each gate structure GS may extend in the second direction Y. The gate structures GS may be spaced apart in the first direction X. The gate structures GS may be adjacent to each other in the first direction X.

[0065] The gate structure GS may be disposed on each of the active patterns AP1 , AP2 , and AP3 . For example, the gate structure GS may cross the first active pattern AP1 , the second active pattern AP2 , and the third active pattern AP3 . The gate structure GS may be disposed on the upper surface 105US of the field insulating film 105 .

[0066] The gate structure GS may be disposed on the first lower pattern BP1, the second lower pattern BP2, and the third lower pattern BP3. The gate structure GS may intersect the first lower pattern BP1, the second lower pattern BP2, and the third lower pattern BP3. The gate structure GS may surround each first sheet pattern NS1 (see, for example, Figure 7 ). The gate structure GS may surround each second sheet pattern NS2. The gate structure GS may surround each third sheet pattern NS3.

[0067] Although the gate structure GS is shown as being disposed over the first to third active patterns AP1 , AP2 , and AP3 , the embodiment is not limited thereto. Unlike the illustrated example, at least one of the gate structures GS may be separated into two or more parts.

[0068] The gate structure GS may include, for example, a gate electrode 120 and a gate insulating film 130 .

[0069] The gate structure GS may include a plurality of inner gate structures I_GS disposed between first sheet patterns NS1 adjacent to each other in the third direction Z and between the first lower pattern BP1 and the first sheet pattern NS1. The plurality of inner gate structures I_GS may be disposed between second sheet patterns NS2 adjacent to each other in the third direction Z and between the second lower pattern BP2 and the second sheet pattern NS2. Although not shown, the plurality of inner gate structures I_GS may be disposed between third sheet patterns NS3 adjacent to each other in the third direction Z and between the third lower pattern BP3 and the third sheet pattern NS3.

[0070] The first active pattern AP1 and the inner gate structure I_GS will be explained as an example. The inner gate structure I_GS may be disposed between the upper surface BP1_US of the first lower pattern and the lower surface of the lowermost first sheet pattern NS1 and between the upper surface of the first sheet pattern NS1 and the bottom surface of the adjacent first sheet pattern NS1 facing each other in the third direction Z.

[0071] The number of the inner gate structures I_GS may be the same as the number of the first sheet patterns NS1. The inner gate structure I_GS contacts the upper surface BP1_US of the first lower pattern, the upper surface of the first sheet pattern NS1, and the bottom surface of the first sheet pattern NS1. The inner gate structure I_GS includes a gate electrode 120 and a gate insulating film 130 disposed between adjacent first sheet patterns NS1 and between the first lower pattern BP1 and the first sheet pattern NS1.

[0072] As an example, the inner gate structure I_GS may contact the first source / drain pattern 150 and the second source / drain pattern 250 to be described at the lower surface. Although not shown, the inner gate structure I_GS may contact the third source / drain pattern 350. As another example, since the inner spacer is disposed between the inner gate structure I_GS and the third source / drain pattern 350, the inner gate structure I_GS may not contact the third source / drain pattern 350.

[0073] Unlike the illustrated example, as an example, the inner gate structure I_GS may not contact the first source / drain pattern 150 and the second source / drain pattern 250. The inner gate structure I_GS may contact the third source / drain pattern 350. As another example, the inner gate structure I_GS may not contact the first source / drain pattern 150 and the third source / drain pattern 350. The inner gate structure I_GS may contact the second source / drain pattern 250.

[0074] The gate electrode 120 may be disposed on the first, second, and third lower patterns BP1, BP2, and BP3. The gate electrode 120 may cross the first, second, and third lower patterns BP1, BP2, and BP3. The gate electrode 120 may surround the first, second, and third sheet patterns NS1, NS2, and NS3.

[0075] Although the upper surface of the gate electrode 120 is Figure 2 and Figure 3 The cross-sectional view shown in FIG. 1 is shown as a concave curved surface, but the embodiment is not limited thereto. The upper surface of the gate electrode 120 may be a flat surface.

[0076] The gate electrode 120 may be formed of at least one of a metal, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride, or may include at least one of a metal, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The gate electrode 120 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN) , tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (NiPt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V) and combinations thereof. Conductive metal oxides and conductive metal oxynitrides may include, but are not limited to, oxidized forms of the foregoing materials.

[0077] The gate insulating film 130 may extend along the upper surface 105US of the field insulating film, the upper surface BP1_US of the first lower pattern, the upper surface BP2_US of the second lower pattern, and the upper surface BP3_US of the third lower pattern. The gate insulating film 130 may surround a plurality of first patterns NS1. The gate insulating film 130 may surround a plurality of second patterns NS2. The gate insulating film 130 may surround a plurality of third patterns NS3. The gate insulating film 130 may be disposed along the periphery of the first pattern NS1, the periphery of the second pattern NS2, and the periphery of the third pattern NS3. The gate electrode 120 is disposed on the gate insulating film 130.

[0078] The gate insulating film 130 is disposed between the gate electrode 120 and the first sheet pattern NS1, between the gate electrode 120 and the second sheet pattern NS2, and between the gate electrode 120 and the third sheet pattern NS3. When the inner gate structure I_GS and the first source / drain pattern 150 contact each other, the gate insulating film 130 included in the inner gate structure I_GS may contact the first source / drain pattern 150.

[0079] The gate insulating film 130 may be formed of silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a higher dielectric constant than silicon oxide, or include silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a higher dielectric constant than silicon oxide. The high dielectric constant material may include, for example, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0080] Although the gate insulating film 130 is shown as a single film, this example is only for convenience of explanation and is not limited thereto. The gate insulating film 130 may include a plurality of films. The first active pattern AP1 will be explained as an example. The gate insulating film 130 may include an interface layer and a high dielectric constant insulating film, the interface layer being disposed between the first active pattern AP1 and the gate electrode 120. For example, the interface layer may not be formed along the contour of the upper surface 105US of the field insulating film.

[0081] The semiconductor device according to some embodiments may include an NC (Negative Capacitance) FET using a negative capacitor. For example, the gate insulating film 130 may include a ferroelectric material film having a ferroelectric property and a paraelectric material film having a paraelectric property.

[0082] The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, when two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance is reduced from the capacitance of each of the individual capacitors. On the other hand, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance may be greater than the absolute value of each of the individual capacitors while having a positive value.

[0083] When a ferroelectric material film having negative capacitance is connected in series with a paraelectric material film having positive capacitance, the total capacitance value of the ferroelectric material film and the paraelectric material film connected in series can be increased. By using the increased total capacitance value, a transistor including the ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0084] The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may be formed of, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide, or may include at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0085] The ferroelectric material film may further include a dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on which type of ferroelectric material is included in the ferroelectric material film, the type of dopant included in the ferroelectric material film may vary.

[0086] When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0087] When the dopant is aluminum (Al), the ferroelectric material film may include 3 at % (atomic %) to 8 at % of aluminum. Here, the ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum.

[0088] When the dopant is silicon (Si), the ferroelectric material film may include 2at% to 10at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may include 2at% to 10at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may include 1at% to 7at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may include 50at% to 80at% zirconium.

[0089] The paraelectric material film may have paraelectric properties. The paraelectric material film may be formed of, for example, at least one of silicon oxide and a metal oxide with a high dielectric constant, or may include, for example, at least one of silicon oxide and a metal oxide with a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, but not limited to, at least one of hafnium oxide, zirconium oxide, and aluminum oxide.

[0090] The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film has ferroelectric properties, but the paraelectric material film may not have ferroelectric properties. For example, when the ferroelectric material film and the paraelectric material film include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film is different from the crystal structure of the hafnium oxide included in the paraelectric material film.

[0091] The ferroelectric material film may have a thickness that provides ferroelectric properties. The thickness of the ferroelectric material film may be, for example, but not limited to, 0.5 nm to 10 nm. Since the critical thickness that exhibits ferroelectric properties may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0092] As an example, the gate insulating film 130 may include a single ferroelectric material film. As another example, the gate insulating film 130 may include a plurality of ferroelectric material films spaced apart from each other. The gate insulating film 130 may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0093] The gate spacer 140 may be disposed on the sidewall of the gate electrode 120. For example, the gate spacer 140 may be disposed on the long sidewall of the gate structure GS. The long sidewall of the gate structure GS may extend in the second direction Y. The gate spacer 140 may not be disposed between the first lower pattern BP1 and the first sheet pattern NS1, and between the first sheet patterns NS1 adjacent in the third direction Z. The gate spacer 140 may not be disposed between the second lower pattern BP2 and the second sheet pattern NS2, and between the second sheet patterns NS2 adjacent in the third direction Z.

[0094] The gate spacer 140 may be made of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof, or may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. Although the gate spacer 140 is shown as a single film, this example is only for ease of explanation, and embodiments are not limited thereto.

[0095] The gate capping pattern 145 may be disposed on the gate electrode 120. The gate capping pattern 145 may be disposed on an upper surface of the gate spacer 140. Unlike the illustrated example, the gate capping pattern 145 may be disposed between the gate spacers 140.

[0096] The gate cap pattern 145 may be formed of, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and combinations thereof, or may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and combinations thereof.

[0097] Unlike the illustrated example, the gate capping pattern 145 may not be disposed on the gate electrode 120. In this case, the gate electrode 120 may be in contact with the first etch stopper film 193.

[0098] The first source / drain pattern 150 may be disposed on the first active pattern AP1. The first source / drain pattern 150 may be disposed on the first lower pattern BP1. The first source / drain pattern 150 may be disposed between the gate electrodes 120 adjacent in the first direction X. The first source / drain pattern 150 may contact the first active pattern AP1. The first source / drain pattern 150 may contact the first sheet pattern NS1. The first source / drain pattern 150 is connected to the first sheet pattern NS1 on the first surface 100US of the substrate.

[0099] The second source / drain pattern 250 may be disposed on the second active pattern AP2. The second source / drain pattern 250 may be disposed on the second lower pattern BP2. The second source / drain pattern 250 may be disposed between the gate electrodes 120 adjacent in the first direction X. The second source / drain pattern 250 may contact the second active pattern AP2. The second source / drain pattern 250 may contact the second sheet pattern NS2. The second source / drain pattern 250 is connected to the second sheet pattern NS2 on the first surface 100US of the substrate.

[0100] The third source / drain pattern 350 may be disposed on the third active pattern AP3. The third source / drain pattern 350 may be disposed on the third lower pattern BP3. Although not shown, the third source / drain pattern 350 may contact the third sheet pattern NS3.

[0101] The source / drain patterns 150, 250, and 350 may include a bottom surface (e.g., a lower surface) facing the lower patterns BP1, BP2, and BP3, and a sidewall extending from the bottom surface of the source / drain patterns 150, 250, and 350 in the third direction Z. The sidewalls of the source / drain patterns 150, 250, and 350 may include, but are not limited to, facet intersections at which chamfers join.

[0102] For example, the source / drain patterns 150, 250, and 350 may include upper surfaces (eg, top surfaces) connected to sidewalls of the source / drain patterns 150, 250, and 350. The upper surface 150US of the first source / drain pattern 150 that is not connected to the first front source / drain contact 170 may be a plane in a cross-sectional view (see, e.g., FIG. 1 ). Figure 5 ).

[0103] Unlike the illustrated example, the source / drain patterns 150, 250, and 350 may not include an upper surface. That is, two sidewalls extending from bottom surfaces of the source / drain patterns 150, 250, and 350 in the third direction Z may be directly joined.

[0104] although Figure 5 and Figure 6The outer shape of the source / drain patterns 150, 250, and 350 is shown to be similar to a hexagon, but the shape is not limited thereto. Unlike the illustrated example, the outer shape of the source / drain patterns 150, 250, and 350 may be similar to a pentagon or a square.

[0105] The first source / drain pattern 150 may be included in the source / drain of a transistor using the first sheet pattern NS1 as a channel region. The second source / drain pattern 250 may be included in the source / drain of a transistor using the second sheet pattern NS2 as a channel region. The third source / drain pattern 350 may be included in the source / drain of a transistor using the third sheet pattern NS3 as a channel region.

[0106] Taking the first source / drain pattern 150 as an example, the first source / drain pattern 150 may include a first upper connection source / drain pattern 150_1 (i.e., a first front connection source / drain pattern) and a first lower connection source / drain pattern 150_2 (i.e., a first back connection source / drain pattern). The first upper connection source / drain pattern 150_1 may be connected to the first front source / drain contact 170. The first lower connection source / drain pattern 150_2 may be connected to the back source / drain contact 70. Although not shown, each of the second source / drain pattern 250 and the third source / drain pattern 350 may include a front connection source / drain pattern and a back connection source / drain pattern.

[0107] Each of the source / drain patterns 150, 250, and 350 may include an epitaxial pattern. Each of the source / drain patterns 150, 250, and 350 may be formed of a semiconductor material, or may include a semiconductor material.

[0108] Some of the source / drain patterns 150, 250, and 350 may include a p-type dopant. The p-type dopant may include, but is not limited to, at least one of boron (B) and gallium (Ga). The remaining source / drain patterns 150, 250, and 350 may include an n-type dopant. The n-type dopant may include, but is not limited to, at least one of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

[0109] The source / drain etch stop film 185 may extend along the sidewalls of the gate spacer 140 and the sidewalls of the source / drain patterns 150, 250, and 350. The source / drain etch stop film 185 may extend along the upper surface 105US of the field insulating film. The source / drain etch stop film 185 may extend along the upper surfaces of the source / drain patterns 150, 250, and 350. For example, the source / drain etch stop film 185 may extend along the upper surface 150US of the first source / drain pattern 150.

[0110] The source / drain etch stop film 185 may not extend along the sidewalls of the gate capping pattern 145. Unlike the illustrated example, the source / drain etch stop film 185 may extend along the sidewalls of the gate capping pattern 145.

[0111] The source / drain etch stop film 185 may be formed of, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof, or may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

[0112] The first front interlayer insulating film 190 is disposed on the first surface 100US of the substrate. The first front interlayer insulating film 190 is disposed on the upper surface 105US of the field insulating film. The first front interlayer insulating film 190 may be disposed on the source / drain patterns 150 , 250 , and 350 .

[0113] The first front-side interlayer insulating film 190 may not cover the upper surface 145US of the gate capping pattern. For example, the upper surface of the first front-side interlayer insulating film 190 may be disposed on, but not limited to, the same plane as the upper surface 145US of the gate capping pattern.

[0114] The first front interlayer insulating film 190 may be formed of, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material, or may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. The dielectric constant of the low dielectric constant material may have a value smaller than 3.9, which is the dielectric constant of silicon oxide.

[0115] The first front source / drain contact 170 may be disposed on the first surface 100US of the substrate. The first front source / drain contact 170 may be disposed on the first source / drain pattern 150. For example, the first front source / drain contact 170 may be disposed on the first upper connection source / drain pattern 150_1. The first front source / drain contact 170 is electrically connected to the first source / drain pattern 150. The first source / drain pattern 150 is disposed between the first front source / drain contact 170 and the first lower pattern BP1.

[0116] The second front source / drain contact 270 may be disposed on the first surface 100US of the substrate. The second front source / drain contact 270 may be disposed on the second source / drain pattern 250. The second front source / drain contact 270 is electrically connected to the second source / drain pattern 250. The second source / drain pattern 250 is disposed between the second front source / drain contact 270 and the second lower pattern BP2.

[0117] The third front source / drain contact 370 may be disposed on the first surface 100US of the substrate. The third front source / drain contact 370 may be disposed on the third source / drain pattern 350. The third front source / drain contact 370 is electrically connected to the third source / drain pattern 350. The third source / drain pattern 350 is disposed between the third front source / drain contact 370 and the third lower pattern BP3.

[0118] The height from the upper surface AP1_US of the first active pattern to the upper surface 170US of the first front source / drain contact may be the same as the height from the upper surface AP1_US of the first active pattern to the upper surface 145US of the gate cap pattern. The height from the upper surface AP2_US of the second active pattern to the upper surface 270US of the second front source / drain contact may be the same as the height from the upper surface AP2_US of the second active pattern to the upper surface 145US of the gate cap pattern. For example, the upper surface of the third front source / drain contact 370 may be arranged in the same plane as the upper surface 170US of the first front source / drain contact and the upper surface 270US of the second front source / drain contact.

[0119] Although the front source / drain contacts 170, 270, and 370 are shown as having a single conductive film structure, the embodiment is not limited thereto. The front source / drain contacts 170, 270, and 370 may have a plurality of conductive film structures including a front contact barrier film and a front contact plug. The front source / drain contacts 170, 270, and 370 may be formed of, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material, or may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material.

[0120] The 2D material may include a 2D allotrope or a 2D compound, and may include, for example, but not limited to, at least one of graphene, boron nitride (BN), molybdenum sulfide, molybdenum selenide, tungsten sulfide, tungsten selenide, and tantalum sulfide. That is, since the above 2D materials are listed only by way of example, the 2D materials that may be included in the semiconductor device of the present disclosure are not limited to the above materials.

[0121] The first front contact silicide film 155 may be disposed between the first source / drain pattern 150 and the first front source / drain contact 170. The second front contact silicide film 255 may be disposed between the second source / drain pattern 250 and the second front source / drain contact 270. The third front contact silicide film 355 may be disposed between the third source / drain pattern 350 and the third front source / drain contact 370. Each of the front contact silicide films 155, 255, and 355 may be formed of, or include, a metal silicide material.

[0122] The back interlayer insulating film 290 may be disposed on the second surface 100BS of the substrate. The back interlayer insulating film 290 may be formed of, for example, at least one of silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and a low dielectric constant material, or may include, for example, at least one of silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, and a low dielectric constant material. The dielectric constant of the low dielectric constant material may have a value smaller than 3.9, which is the dielectric constant of silicon oxide.

[0123] The back wiring line 50 may be disposed in the back interlayer insulating film 290. The back wiring line 50 may be disposed on the second surface 100BS of the substrate. In the semiconductor device according to some embodiments, the substrate 100 may be disposed between the back wiring line 50 and the first lower pattern BP1. The substrate 100 may be disposed between the back wiring line 50 and the second lower pattern BP2 and between the back wiring line 50 and the third lower pattern BP3.

[0124] The backside wiring line 50 may extend in the first direction X, but the embodiment is not limited thereto. Unlike the example shown, the backside wiring line 50 may extend in the second direction Y. In this case, along Figure 1 The shapes of the cross-sectional views taken along lines AA, BB, CC, DD, EE, and FF may vary.

[0125] As an example, the backside wiring 50 may be a power supply line that supplies power to the semiconductor device. As another example, the backside wiring line 50 may be a signal line that supplies an operation signal of the semiconductor device.

[0126] The backside wiring line 50 may include a first surface 50_S1 and a second surface 50_S2 opposite to each other in the third direction Z. The first surface 50_S1 of the backside wiring line may face the substrate 100. The substrate 100 may be disposed on the first surface 50_S1 of the backside wiring line.

[0127] The first to third lower patterns BP1, BP2, and BP3 may be disposed on the first surface 50_S1 of the backside wiring line. The field insulating film 105 may be disposed on the first surface 50_S1 of the backside wiring line. The bottom surface 105BS of the field insulating film may face the first surface 50_S1 of the backside wiring line.

[0128] Although the backside wiring line 50 is shown as having a trapezoidal cross section (see e.g. Figure 6 and Figure 7 ), but the embodiment is not limited thereto. For example, the width of the first surface 50_S1 of the back wiring line in the second direction Y may be smaller than the width of the second surface 50_S2 of the back wiring line in the second direction Y. Unlike the example shown, the back wiring line 50 may have a rectangular cross-section.

[0129] The back side wiring via 55 may be provided in the back side interlayer insulating film 290. The back side wiring via 55 may protrude in the third direction Z from the first surface 50_S1 of the back side wiring line.

[0130] The backside wiring vias 55 may connect the backside source / drain contacts 70 to the backside wiring lines 50. Unlike the illustrated example, the backside wiring lines 50 may be connected to the backside source / drain contacts 70 without the backside wiring vias 55.

[0131] The backside wiring line 50 and the backside wiring via 55 may have, but are not limited to, an integrated structure not divided by an interface. Unlike the illustrated example, the backside wiring line 50 and the backside wiring via 55 may be divided by an interface.

[0132] Although the backside wiring line 50 and the backside wiring via 55 are shown as having a single conductive film structure, the embodiment is not limited thereto. Unlike the illustrated example, the backside wiring line 50 and the backside wiring via 55 may have a plurality of conductive film structures.

[0133] The back wiring line 50 and the back wiring via 55 may be formed of, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material, or may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material.

[0134] The back contact guide pattern 80 may be disposed on the first surface 50_S1 of the back wiring line. The back contact guide pattern 80 may be disposed between the first active pattern AP1 and the second active pattern AP2 and between the first active pattern AP1 and the third active pattern AP3.

[0135] A pair of back contact guide patterns 80 may be disposed on both sides of the first active pattern AP1. For example, one of the back contact guide patterns 80 may be disposed on one side of the first active pattern AP1, and the other of the back contact guide patterns 80 may be disposed on the other side of the first active pattern AP1. The back contact guide patterns 80 may include a first back contact guide pattern 80_1 and a second back contact guide pattern 80_2.

[0136] The first back contact guide pattern 80_1 may be disposed between the first and second lower patterns BP1 and BP2. The second back contact guide pattern 80_2 may be disposed between the first and third lower patterns BP1 and BP3. The first lower pattern BP1 may be disposed between the first and second back contact guide patterns 80_1 and 80_2.

[0137] The back contact guide pattern 80 may include an upper surface (eg, top surface) 80US and a bottom surface (eg, lower surface) 80BS opposite to each other in the third direction Z. The bottom surface 80BS of the back contact guide pattern may face the first surface 50_S1 of the back wiring line.

[0138] The back interlayer insulating film 290 may be disposed on the bottom surface 80BS of the back contact guide pattern. For example, the bottom surface 80BS of the back contact guide pattern may contact the back interlayer insulating film 290. The substrate 100 may not be disposed between the back contact guide pattern 80 and the back interlayer insulating film 290. The substrate 100 may not cover the bottom surface 80BS of the back contact guide pattern.

[0139] The back contact guide pattern 80 may be disposed in the substrate 100 and the field insulating film 105. A portion of the back contact guide pattern 80 protrudes beyond the first surface 100US of the substrate in the third direction Z. A height H2 from the second surface 50_S2 of the back wiring line to the bottom surface 105BS of the field insulating film may be smaller than a height H1 from the second surface 50_S2 of the back wiring line to the upper surface 80US of the back contact guide pattern.

[0140] For example, a portion of the back contact guide pattern 80 may be disposed in the field insulating film 105. The remaining portion of the back contact guide pattern 80 may be disposed in the substrate 100.

[0141] The back contact guide pattern 80 may include a first sidewall 80_SW1 and a second sidewall 80_SW2 connecting an upper surface 80US and a bottom surface 80BS of the back contact guide pattern.

[0142] The first sidewall 80_SW1 of the back contact guide pattern may contact the back source / drain contact 70 . The second sidewall 80_SW2 of the back contact guide pattern may not contact the back source / drain contact 70 .

[0143] The back contact guide pattern 80 may include a first portion 80_P1 disposed in the substrate 100 and a second portion 80_P2 disposed in the field insulating film 105. An interface between the first portion 80_P1 and the second portion 80_P2 of the back contact guide pattern may be the first surface 100US of the substrate.

[0144] The second sidewall 80_SW2 of the back contact guide pattern may include a first portion 80_SW21 in contact with the substrate 100 and a second portion 80_SW22 in contact with the field insulating film 105. The first portion 80_SW21 of the second sidewall of the back contact guide pattern may be the second sidewall of the back contact guide pattern in the first portion 80_P1 of the back contact guide pattern. The second portion 80_SW22 of the second sidewall of the back contact guide pattern may be the second sidewall of the back contact guide pattern in the second portion 80_P2 of the back contact guide pattern.

[0145] exist Figure 8 and Fig. 9 In the first portion 80_P1 of the back contact guide pattern, the first portion 80_SW21 of the second side wall of the back contact guide pattern may form an acute angle with the second surface 100BS of the substrate. For example, a horizontal distance from the central vertical axis of the back contact guide pattern 80 to the upper edge of the first portion 80_SW21 of the second side wall of the back contact guide pattern may be greater than a horizontal distance from the central vertical axis of the back contact guide pattern 80 to the lower edge of the first portion 80_SW21 of the second side wall of the back contact guide pattern. For example, a width of the bottom surface 80BS of the back contact guide pattern in the second direction Y may be less than a width of the back contact guide pattern at a middle portion in the Z direction (see, for example, FIG. 1 ). Figure 5 , Figure 8 and Fig. 9 ).

[0146] exist Fig.10 In the first portion 80_P1 of the back contact guide pattern, the first portion 80_SW21 of the second sidewall of the back contact guide pattern may be perpendicular to the second surface 100BS of the substrate.

[0147] exist Figure 8In the second portion 80_P2 of the back contact guide pattern, the second portion 80_SW22 of the second side wall of the back contact guide pattern may form an acute angle with the second surface 100BS of the substrate. For example, a horizontal distance from a central vertical axis of the back contact guide pattern 80 to an upper edge of the second portion 80_SW22 of the second side wall of the back contact guide pattern may be greater than a horizontal distance from a central vertical axis of the back contact guide pattern 80 to a lower edge of the second portion 80_SW22 of the second side wall of the back contact guide pattern. For example, a width of the back contact guide pattern 80 may increase from a bottom surface 80BS of the back contact guide pattern to an upper surface 80US of the back contact guide pattern.

[0148] exist Fig. 9 and Fig.10 In the second portion 80_P2 of the back contact guide pattern, the second portion 80_SW22 of the second sidewall of the back contact guide pattern may form an obtuse angle with the second surface 100BS of the substrate. For example, a horizontal distance from a central vertical axis of the back contact guide pattern 80 to an upper edge of the second portion 80_SW22 of the second sidewall of the back contact guide pattern may be smaller than a horizontal distance from a central vertical axis of the back contact guide pattern 80 to a lower edge of the second portion 80_SW22 of the second sidewall of the back contact guide pattern.

[0149] In the semiconductor device according to some embodiments, the field insulating film 105 may cover the upper surface 80US of the back contact guide pattern. The height H3 from the second surface 50_S2 of the back wiring line to the upper surface 105US of the field insulating film may be greater than the height H1 from the second surface 50_S2 of the back wiring line to the upper surface 80US of the back contact guide pattern. The upper surface 80US of the back contact guide pattern may not contact the source / drain etch stop film 185.

[0150] The back contact guide pattern 80 may be spaced apart from the first lower pattern BP1 and the second lower pattern BP2 in the second direction Y. The back contact guide pattern 80 may be spaced apart from the third lower pattern BP3 in the second direction Y. The back contact guide pattern 80 is spaced apart from the lower patterns BP1, BP2, BP3 in the second direction Y, and the back contact guide pattern 80 does not overlap with the upper surface BP1_US of the first lower pattern, the upper surface BP2_US of the second lower pattern, and the upper surface BP3_US of the third lower pattern in the third direction Z.

[0151] Since the back contact guide pattern 80 does not overlap the upper surface BP1_US of the first lower pattern in the third direction Z, the first sheet pattern NS1 does not overlap the back contact guide pattern 80 in the third direction Z.

[0152] exist Figure 4 In the embodiment, the back contact guide pattern 80 may be disposed between the gate structures GS adjacent to each other in the first direction X. The back contact guide pattern 80 may not overlap the gate structure GS in the third direction Z.

[0153] The back contact guide pattern 80 may be formed of an insulating material or include an insulating material. The back contact guide pattern 80 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), and combinations thereof. Although the back contact guide pattern 80 is shown as a single film, embodiments are not limited thereto.

[0154] The back source / drain contact 70 may be disposed between the back wiring line 50 and the first source / drain pattern 150. The back source / drain contact 70 may connect the first lower connection source / drain pattern 150_2 to the back wiring line 50. The back source / drain contact 70 may be disposed on the first surface 50_S1 of the back wiring line.

[0155] The back source / drain contacts 70 may be disposed between the back contact guide patterns 80 adjacent to each other in the second direction Y. The back source / drain contacts 70 may be disposed between the first back contact guide pattern 80_1 and the second back contact guide pattern 80_2.

[0156] The back contact guide patterns 80 may be disposed at both sides of the back source / drain contacts 70. The back source / drain contacts 70 may be in contact with the back contact guide patterns 80.

[0157] At least a portion of the back source / drain contact 70 may be disposed in the first lower pattern BP1. In a semiconductor device according to some embodiments, a portion of the back source / drain contact 70 may be disposed in the first lower pattern BP1, and the remaining portion of the back source / drain contact 70 may be disposed in the substrate 100 (see, e.g., Figure 5 ).

[0158] Although the back source / drain contact 70 is shown as having a single conductive film structure, the embodiment is not limited thereto. The back source / drain contact 70 may have a plurality of conductive film structures including a back contact barrier film and a back contact plug. The back source / drain contact 70 may be formed of, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material, or may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material.

[0159] The back side contact guide pattern 80 may be used as a mask for forming the back side source / drain contacts 70. That is, by using the back side contact guide pattern 80, the back side source / drain contacts 70 may be formed in the form of a self-aligned contact (SAC). Since the back side contact guide pattern 80 defines the area where the back side source / drain contacts 70 are formed, it is possible to prevent the back side source / drain contacts 70 from being misaligned.

[0160] In addition, since the back contact guide pattern 80 is disposed between the lower patterns adjacent to each other in the first direction X, the back contact guide pattern 80 can prevent the source / drain patterns 250 and 350 that are not connected to the back source / drain contacts 70 from being connected to the back source / drain contacts 70. Therefore, the performance and reliability of the semiconductor device can be improved.

[0161] The second front-side interlayer insulating film 191 may be disposed on the first front-side interlayer insulating film 190. The first etch stopper film 193 is disposed between the first front-side interlayer insulating film 190 and the second front-side interlayer insulating film 191.

[0162] A back contact silicide film 75 may be disposed between the first source / drain pattern 150 and the back source / drain contact 70. The back contact silicide film 75 may be formed of a metal silicide material, or may include a metal silicide material.

[0163] The second etch stopper film 194 and the third front-side interlayer insulating film 192 may be sequentially disposed on the second front-side interlayer insulating film 191. The second etch stopper film 194 may be disposed between the second front-side interlayer insulating film 191 and the third front-side interlayer insulating film 192.

[0164] The first etch stop film 193 and the second etch stop film 194 may be formed of, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxycarbide (AlOC), and combinations thereof, or may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxycarbide (AlOC), and combinations thereof. The second front interlayer insulating film 191 and the third front interlayer insulating film 192 may each be formed of at least one of, for example, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride and a low dielectric constant material, or may each include, for example, at least one of, for example, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride and a low dielectric constant material.

[0165] The front wiring structure 195 is disposed on the first surface 100US of the substrate and may be connected to the first, second, and third front source / drain contacts 170 , 270 , and 370 .

[0166] The front wiring structure 195 may include a front wiring via 196 and a front wiring line 197. The front wiring via 196 may be provided in the second front interlayer insulating film 191. The front wiring via 196 may pass through the first etch stop film 193 and may be connected to the first front source / drain contact 170, the second front source / drain contact 270, and the third front source / drain contact 370.

[0167] The front wiring line 197 may be disposed in the third front interlayer insulating film 192. The front wiring line 197 may be connected to the front source / drain contacts 170, 270, and 370 through the front wiring via 196. The front wiring line 197 penetrates the second etching stopper film 194 and may be connected to the front wiring via 196.

[0168] Unlike the illustrated example, the front side wiring lines 197 may be connected to the front side source / drain contacts 170 , 270 , and 370 without the front side wiring vias 196 .

[0169] Each of the front wiring vias 196 and the front wiring lines 197 may be formed of, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material, or may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material.

[0170] Although the front wiring via 196 and the front wiring line 197 are each shown as having a single conductive film structure, this is only for convenience of explanation, and the embodiment is not limited thereto. Different from the example shown, as an example, at least one of the front wiring via 196 and the front wiring line 197 may have a plurality of conductive film structures. As another example, the front wiring structure 195 may have an integrated structure without an interface division between the front wiring via 196 and the front wiring line 197.

[0171] Unlike the illustrated example, at least one of the first etch stopper film 193 and the second etch stopper film 194 may be omitted.

[0172] Fig.11 and Fig.12 is a diagram for explaining a semiconductor device according to some embodiments. Fig.13 and Fig.14 is a diagram for explaining a semiconductor device according to some embodiments. Figures 1 to 10 The different points described are explained.

[0173] Reference Figures 11 to 14 In the semiconductor device according to some embodiments, the field insulating film 105 does not cover the upper surface 80US of the back contact guide pattern.

[0174] The source / drain etch stop film 185 may be in contact with the upper surface 80US of the back contact guide pattern. The source / drain etch stop film 185 may extend along the upper surface 80US of the back contact guide pattern.

[0175] exist Fig.11 and Fig.12 In the embodiment, the back contact guide pattern 80 may not include a portion protruding beyond the upper surface 105US of the field insulating film.

[0176] On the contrary, Fig.13 and Fig.14 As shown in FIG. 1 , a portion of the back contact guide pattern 80 may protrude beyond the upper surface 105US of the field insulating film. A portion of the sidewalls 80_SW1 and 80_SW2 of the back contact guide pattern 80 may contact the source / drain etch stop film 185 .

[0177] Figures 15 to 17 is a diagram for explaining a semiconductor device according to some embodiments. Figures 1 to 10 The different points described are explained.

[0178] Reference Figures 15 to 17 , in the semiconductor device according to some embodiments, when viewed in the third direction Z, a portion of the upper surface 80US of the back side contact guide pattern may overlap the gate structure GS.

[0179] When viewed in the third direction Z, at least a portion of the plurality of gate structures GS may overlap the back contact guide pattern 80. When viewed in the third direction Z, the plurality of gate structures GS may include a first sub-gate structure GS and a second sub-gate structure GS overlapping the back contact guide pattern 80. The first sub-gate structure GS and the second sub-gate structure GS may be directly adjacent to each other in the first direction X.

[0180] From Fig.15 From the perspective of the cross-sectional view in , when viewed in the third direction Z, a portion of the first sub-gate structure GS and the second sub-gate structure GS overlap with the upper surface 80US of the back contact guide pattern, and when viewed in the third direction Z, the remaining portions of the first sub-gate structure GS and the second sub-gate structure GS may not overlap with the upper surface 80US of the back contact guide pattern.

[0181] From Fig.16 From the perspective of the cross-sectional view in FIG. 1 , when viewed in the third direction Z, the first sub-gate structure GS and the second sub-gate structure GS may completely overlap the upper surface 80US of the back contact guide pattern. Fig.16 Unlike that shown in FIG. 8 , the back contact guide pattern 80 may have a line shape longitudinally extending along the first lower pattern BP1 in the first direction X. When viewed in the third direction Z, the back contact guide pattern 80 may overlap three or more gate structures GS.

[0182] From Fig.17 From the perspective of the cross-sectional view in FIG. 8 , the gate structure GS may be disposed on the back contact guide pattern 80 .

[0183] When the back contact guide pattern 80 is as Fig.15 When set as in Figure 1 The cross section taken along line FF can be compared with Figure 7 That is, in a portion where the gate structure GS and the field insulating film 105 overlap in the third direction Z, the back contact guide pattern 80 may not be visible.

[0184] Fig.18 and Fig.19is a diagram for explaining a semiconductor device according to some embodiments. Figure 20 to Figure 23 is a diagram for explaining a semiconductor device according to some embodiments. Fig.24 and Fig.25 is a diagram for explaining a semiconductor device according to some embodiments. Figures 1 to 10 The different points described are explained.

[0185] Reference Fig.18 and Fig.19 In the semiconductor device according to some embodiments, a portion of the substrate 100 may be disposed between the back contact guide pattern 80 and the back interlayer insulating film 290 .

[0186] The substrate 100 may cover the bottom surface 80BS of the back contact guide pattern. The bottom surface 80BS of the back contact guide pattern may not be in contact with the back interlayer insulating film 290.

[0187] A height H4 from the second surface 50_S2 of the backside wiring line to the second surface 100BS of the substrate (see, for example Fig.19 ) may be smaller than a height H5 from the second surface 50_S2 of the back-side wiring line to the bottom surface 80BS of the back-side contact guide pattern.

[0188] Reference Figure 20 to Figure 23 In the semiconductor device according to some embodiments, the substrate ( Figures 2 to 7 100 ) may not be disposed between the lower patterns BP1 , BP2 , and BP3 and the back-side interlayer insulating film 290 .

[0189] The back interlayer insulating film 290 may contact the first to third lower patterns BP1 , BP2 , and BP3 . The back interlayer insulating film 290 may contact the field insulating film 105 .

[0190] Reference Fig.24 and Fig.25 , in the semiconductor device according to some embodiments, each of the first active pattern AP1 , the second active pattern AP2 , and the third active pattern AP3 does not include a sheet pattern.

[0191] The first active pattern AP1, the second active pattern AP2, and the third active pattern AP3 may be fin-shaped patterns protruding above the upper surface 105US of the field insulating film. Fig.25 In the embodiment, the field insulating film 105 may cover a portion of the sidewalls of the active patterns AP1, AP2, and AP3.

[0192] The gate structure GS does not include the inner gate structure I_GS.

[0193] Figure 26 to Figure 28is a diagram for explaining a semiconductor device according to some embodiments. Figures 1 to 10 and Figures 15 to 17 The different points described are explained.

[0194] As a reference, Fig.26 is a layout diagram for explaining a semiconductor device according to some embodiments. Fig. 27 and Fig.28 Along the Fig.26 A cross-sectional view taken along line FF.

[0195] Reference Figure 26 to Figure 28 The semiconductor device according to some embodiments may further include a gate isolation structure GCS disposed on the back contact guide pattern 80 .

[0196] The gate isolation structure GCS may be disposed on the upper surface 80US of the back contact guide pattern 80. The gate isolation structure GCS may be in contact with the back contact guide pattern 80.

[0197] The gate isolation structure GCS may be made of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), and combinations thereof, or may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), and combinations thereof. Although the gate isolation structure GCS is illustrated as a single film, embodiments are not limited thereto.

[0198] The gate isolation structure GCS may separate at least one gate structure GS into two parts. The gate isolation structure GCS may separate the gate structure GS into a first part and a second part.

[0199] The gate isolation structure GCS can separate one gate electrode 120 into a first gate electrode portion 120_1 and a second gate electrode portion 120_2. The gate isolation structure GCS can separate one gate insulating film 130 into a first gate insulating film portion 130_1 and a second gate insulating film portion 130_2.

[0200] The gate isolation structure GCS may separate the gate capping pattern 145 into two parts. An upper surface GCS_US of the gate isolation structure may be disposed in the same plane as an upper surface 145US of the gate capping pattern.

[0201] The first portion of the gate structure GS may include a first portion 120_1 of a gate electrode and a first portion 130_1 of a gate insulating film. The second portion of the gate structure GS may include a second portion 120_2 of a gate electrode and a second portion 130_2 of a gate insulating film.

[0202] The first portion of the gate structure GS and the second portion of the gate structure GS may each include a sidewall GS_SW facing the gate isolation structure GCS. The sidewall GS_SW of the first portion of the gate structure GS and the sidewall GS_SW of the second portion of the gate structure GS may contact the gate isolation structure GCS.

[0203] exist Fig. 27 In the embodiment, the first portion 120_1 of the gate electrode and the second portion 120_2 of the gate electrode may contact the gate isolation structure GCS. The first portion 130_1 of the gate insulating film and the second portion 130_2 of the gate insulating film do not extend in the third direction Z along the sidewall of the gate isolation structure GCS.

[0204] exist Fig.28 In the embodiment, the first portion 130_1 of the gate insulating film and the second portion 130_2 of the gate insulating film may extend along the sidewall of the gate isolation structure GCS in the third direction Z. The first portion 120_1 of the gate electrode and the second portion 120_2 of the gate electrode may not contact the gate isolation structure GCS.

[0205] Figure 29 to Figure 44 is a diagram of an intermediate stage for explaining a method for manufacturing a semiconductor device according to some embodiments.

[0206] Reference Fig.29 and Fig.30 , a first lower pattern BP1 , a second lower pattern BP2 , and a third lower pattern BP3 may be formed on the substrate 100 .

[0207] The first lower pattern BP1, the second lower pattern BP2, and the third lower pattern BP3 may be separated by the fin trench FT. When forming the lower patterns BP1, BP2, and BP3, an upper pattern structure UAP may be formed on each of the first lower pattern BP1, the second lower pattern BP2, and the third lower pattern BP3. The upper pattern structure UAP may extend in the first direction X.

[0208] The upper pattern structure UAP may include a plurality of sacrificial patterns SCL and a plurality of active patterns ACTL alternately stacked on the lower patterns BP1, BP2, and BP3. For example, the sacrificial patterns SCL may be formed of a silicon germanium film or may include a silicon germanium film. The active patterns ACTL may be formed of a silicon film or may include a silicon film.

[0209] A fin hard mask F_HM may be formed on each upper pattern structure UAP. The upper pattern structure UAP and the lower patterns BP1, BP2, and BP3 may be formed by using the fin hard mask F_HM as an etching mask. The fin hard mask F_HM may be formed of, or may include, but is not limited to, silicon nitride.

[0210] Subsequently, a preliminary field insulating film 105P1 may be formed on the substrate 100. The preliminary field insulating film 105P1 may fill the fin trench FT. The preliminary field insulating film 105P1 may cover the sidewalls of the lower patterns BP1, BP2, and BP3 and the sidewalls of the upper pattern structure UAP. The preliminary field insulating film 105P1 may not cover the upper surface of the fin hard mask F_HM.

[0211] Reference Fig.31 and Fig.32 , a back contact guide hole 80H may be formed in the preliminary field insulating film 105P1 and the substrate 100 .

[0212] The back contact guide hole 80H may be formed between the upper pattern structures UAP adjacent to each other in the second direction Y. The back contact guide hole 80H is formed between the first and second lower patterns BP1 and BP2 and between the first and third lower patterns BP1 and BP3.

[0213] Reference Fig.33 and Fig.34 , a back contact guide pattern 80 may be formed in the back contact guide hole 80H.

[0214] The back contact guide pattern 80 may fill a portion of the back contact guide hole 80H. The fin hard mask F_HM may be removed while the back contact guide pattern 80 is formed, but the embodiment is not limited thereto.

[0215] More specifically, a pre-contact guide film may be formed in the back contact guide hole 80H. The pre-contact guide film may fill the back contact guide hole 80H. The pre-contact guide film may also be formed on the fin hard mask F_HM. A back contact guide pattern 80 may be formed in the back contact guide hole 80H by etching a portion of the pre-contact guide film. The fin hard mask F_HM may be removed while removing a portion of the pre-contact guide film.

[0216] Different from the example shown, it is possible to Fig.35 and Fig.36 The fin hard mask F_HM is removed while the field insulating film 105 is formed.

[0217] Reference Figure 35 to Figure 36 A preliminary field insulating film ( Fig.30105P1).

[0218] Subsequently, the field insulating film 105 may be formed on the substrate 100 by removing a portion of the preliminary field insulating film 105P1. The upper pattern structure UAP may protrude above the field insulating film 105.

[0219] Although the field insulating film 105 is illustrated as covering the back contact guide pattern 80 , embodiments are not limited thereto. The field insulating film 105 may not cover the upper surface of the back contact guide pattern 80 .

[0220] Reference Figure 37 to Figure 39 , a dummy gate electrode 120P, a dummy gate insulating film 130P, and a dummy gate capping film 120HM extending in the second direction Y may be formed on the field insulating film 105 and the upper pattern structure UAP.

[0221] The dummy gate electrode 120P may cross the upper pattern structure UAP.

[0222] The dummy gate insulating film 130P may be formed of, for example, but not limited to, silicon oxide, or may include, for example, but not limited to, silicon oxide. The dummy gate electrode 120P may be formed of, for example, but not limited to, polysilicon, or may include, for example, but not limited to, polysilicon. The dummy gate cap film 120HM may be formed of, for example, but not limited to, silicon nitride, or may include, for example, but not limited to, silicon nitride.

[0223] Although not shown, a gate spacer ( Figure 2 of 140).

[0224] Next, first to third source / drain recesses may be formed between the dummy gate electrodes 120P by removing the upper pattern structure UAP between the dummy gate electrodes 120P adjacent to each other in the first direction X. While the first to third source / drain recesses are formed, a portion of the field insulating film 105 between the dummy gate electrodes 120P adjacent to each other in the first direction X may be etched.

[0225] A first source / drain pattern 150 may be formed in the first source / drain recess. The first source / drain pattern 150 may be formed on the first lower pattern BP1. A second source / drain pattern 250 may be formed in the second source / drain recess. The second source / drain pattern 250 may be formed on the second lower pattern BP2. A third source / drain pattern 350 may be formed in the third source / drain recess. The third source / drain pattern 350 may be formed on the third lower pattern BP3.

[0226] Reference Figure 40 to Figure 41 , a source / drain etch stop film 185 may be formed on the source / drain patterns 150 , 250 , and 350 and the field insulating film 105 .

[0227] The source / drain etch stop film 185 may extend along outlines of the first source / drain pattern 150 , the second source / drain pattern 250 , and the third source / drain pattern 350 .

[0228] A first front-side interlayer insulating film 190 may be formed on the source / drain etch stop film 185 .

[0229] Subsequently, the dummy gate capping film 120HM is removed to expose the upper surface of the dummy gate electrode 120P. The dummy gate insulating film 130P and the dummy gate electrode 120P may be removed to expose the upper pattern structure UAP.

[0230] Next, the first, second, and third sheet patterns NS1, NS2, and NS3 may be formed by removing the sacrificial pattern SCL. The active pattern ACTL of the upper pattern structure UAP may be the first, second, and third sheet patterns NS1, NS2, and NS3.

[0231] Subsequently, a gate insulating film 130 and a gate electrode 120 may be sequentially formed. A gate capping pattern 145 may be formed on the gate electrode 120.

[0232] Reference Fig.40 and Fig.42 , second and third front source / drain contacts 270 and 370 may be formed on the second and third source / drain patterns 250 and 350 .

[0233] Although not shown, a first front source / drain contact ( Figure 6 of 170).

[0234] Before forming the second and third front source / drain contacts 270 and 370 , the second and third front contact silicide films 255 and 355 may be formed.

[0235] Subsequently, a front-side wiring structure 195 may be formed on the first front-side interlayer insulating film 190 .

[0236] Thereafter, a portion of the substrate 100 may be removed to reduce the thickness of the substrate 100. Thus, the second surface 100BS of the substrate 100 may be formed. The back contact guide pattern 80 may be exposed while removing a portion of the substrate 100.

[0237] Unlike the illustrated example, as an example, the substrate 100 may remain on the bottom surface 80BS of the back contact guide pattern. As another example, the entire substrate 100 may be removed. In this case, the field insulating film 105 and the lower patterns BP1, BP2, and BP3 may be exposed.

[0238] Reference Fig.43 , a back contact hole 70H may be formed in the substrate 100 and the first lower pattern BP1 by using the back contact guide pattern 80 as a mask.

[0239] The back contact hole 70H may expose the first source / drain pattern 150. The back contact hole 70H may be formed by removing a portion of the back contact guide pattern 80, but the embodiment is not limited thereto.

[0240] Reference Fig.43 and Fig.44 , back source / drain contacts 70 may be formed in the back contact holes 70H.

[0241] Before forming the back source / drain contacts 70 , a back contact silicide film 75 may be formed.

[0242] Next, refer to Figure 5 , a backside wiring line 50 can be formed.

[0243] Figures 45 to 49 is an intermediate stage diagram for explaining a method for manufacturing a semiconductor device according to some embodiments. For ease of explanation, the explanation will focus on the use of Figure 29 to Figure 44 Different points of explanation.

[0244] Reference Fig.45 and Fig.46 , the dummy lower pattern D_BP may be formed between the first and second lower patterns BP1 and BP2 adjacent to each other in the second direction Y. The dummy lower pattern D_BP may be formed between the first and third lower patterns BP1 and BP3 adjacent to each other in the second direction Y.

[0245] The dummy lower pattern D_BP may be formed on the substrate 100. The dummy lower pattern D_BP is formed while the lower patterns BP1, BP2, BP3 are formed. The dummy lower pattern D_BP, the first lower pattern BP1, the second lower pattern BP2, and the third lower pattern BP3 may be separated by the fin trench FT.

[0246] The length of the dummy lower pattern D_BP in the first direction X may be smaller than the length of the lower patterns BP1 , BP2 , and BP3 in the first direction X.

[0247] While forming the dummy lower pattern D_BP, a dummy upper pattern structure D_UAP may be formed on the dummy lower pattern D_BP. The upper pattern structure UAP may be formed simultaneously with the dummy upper pattern structure D_UAP.

[0248] The dummy upper pattern structure D_UAP may include a plurality of dummy sacrificial patterns D_SCL and a plurality of dummy active patterns D_ACTL alternately stacked on the dummy lower pattern D_BP. The dummy sacrificial patterns D_SCL may be formed of, or may include, a silicon germanium film. The dummy active patterns D_ACTL may be formed of, or may include, a silicon film.

[0249] Subsequently, a preliminary field insulating film 105P1 may be formed on the substrate 100. The preliminary field insulating film 105P1 may not cover the upper pattern structure UAP and the dummy upper pattern structure D_UAP. The upper pattern structure UAP and the dummy upper pattern structure D_UAP may be exposed.

[0250] Unlike the example shown, a fin hard mask ( Fig.29 and Fig.30 In addition, a fin hard mask F_HM may be formed on the dummy upper pattern structure D_UAP.

[0251] Reference Figure 47 to Figure 48 , the dummy upper pattern structure D_UAP and the dummy lower pattern D_BP may be removed to form a back contact guide hole 80H.

[0252] The back contact guide hole 80H may be formed at a position corresponding to the dummy lower pattern D_BP. As an example, the back contact guide hole 80H may be formed by removing a portion of the substrate 100, the dummy upper pattern structure D_UAP, and the dummy lower pattern D_BP. As another example, the back contact guide hole 80H may be formed by removing a portion of the substrate 100, a portion of the preparatory field insulating film 105P1, the dummy upper pattern structure D_UAP, and the dummy lower pattern D_BP. The profile of the sidewall of the back contact guide hole 80H may change depending on which film is removed to form the back contact guide hole 80H.

[0253] Reference Fig.49 , a back contact guide pattern 80 may be formed in the back contact guide hole 80H.

[0254] The back contact guide pattern 80 may be formed at a position corresponding to the dummy lower pattern D_BP.

[0255] After that, you can use Figures 35 to 44 Describe the manufacturing process.

[0256] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the preferred embodiments without departing substantially from the principles of the present invention. Therefore, the disclosed preferred embodiments disclosed are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A semiconductor device comprising: a backside wiring circuit including a first surface and a second surface opposite to each other in a first direction; a first fin pattern on the first surface of the backside wiring line and extending in the second direction; a second fin pattern, spaced apart from the first fin pattern in the third direction, the second fin pattern extending in the second direction; a field insulating film on the first surface of the back wiring line, the field insulating film covering the sidewalls of the first fin pattern and the sidewalls of the second fin pattern and including an upper surface and a bottom surface opposite to each other in a first direction, the bottom surface of the field insulating film facing the first surface of the back wiring line; a back contact guide pattern located on the first surface of the back wiring line between the first fin pattern and the second fin pattern, the back contact guide pattern comprising an upper surface and a bottom surface opposite to each other in a first direction, the bottom surface of the back contact guide pattern facing the first surface of the back wiring line; a first source / drain pattern on the first fin pattern; as well as a back source / drain contact, connecting the first source / drain pattern to the back wiring line, Wherein, at least a portion of the back source / drain contact is disposed in the first fin pattern.

2. The semiconductor device according to claim 1, wherein The back contact guide pattern does not overlap an upper surface of the second fin pattern in the first direction.

3. The semiconductor device according to claim 1, wherein A portion of the back contact guide pattern is disposed in the field insulating film, and The field insulating film covers an upper surface of the back contact guide pattern.

4. The semiconductor device according to claim 1, further comprising: a source / drain etch stop film extending along the sidewalls of the first source / drain pattern and the upper surface of the field insulating film, The source / drain etch stop film contacts an upper surface of the back contact guide pattern.

5. The semiconductor device according to claim 1, further comprising: a plurality of sheet patterns on the first fin pattern and connected to the first source / drain pattern; as well as A gate structure, on the first fin pattern, the gate structure includes a gate insulating film and a gate electrode, the gate insulating film surrounds the sheet pattern, Wherein, the sheet pattern does not overlap with the back contact guide pattern in the first direction.

6. The semiconductor device according to claim 5, in, The back contact guiding pattern does not overlap the gate structure in the first direction.

7. The semiconductor device according to claim 5, wherein: A portion of an upper surface of the back contact guide pattern overlaps the gate structure in the first direction.

8. The semiconductor device according to claim 1, further comprising: The gate isolation structure is on the back contact guide pattern and contacts the sidewall of the gate structure.

9. The semiconductor device according to claim 1, further comprising: a substrate, between the backside wiring line and the second fin pattern, wherein the second fin pattern protrudes from the substrate in a first direction, and A portion of the back contact guide pattern is disposed in the substrate.

10. The semiconductor device according to claim 9, wherein The substrate includes a bottom surface facing the back wiring line and an upper surface opposite to the bottom surface of the substrate in a first direction, The second fin pattern protrudes from the upper surface of the substrate, and A height from the second surface of the back wiring line to the bottom surface of the substrate is smaller than a height from the second surface of the back wiring line to the bottom surface of the back contact guide pattern.

11. The semiconductor device according to claim 1, further comprising: a back-side interlayer insulating film on a bottom surface of the back-side contact guide pattern and in contact with the back-side contact guide pattern, Among them, the back wiring line is arranged in the back interlayer insulating film.

12. The semiconductor device according to claim 1, further comprising: a second source / drain pattern on the second fin pattern; as well as A front source / drain contact connected to the second source / drain pattern, The second source / drain pattern is between the second fin pattern and the front source / drain contact.

13. A semiconductor device comprising: a backside wiring circuit including a first surface and a second surface opposite to each other in a first direction; a first fin pattern on the first surface of the backside wiring line and extending in the second direction; a field insulating film on the first surface of the backside wiring line, the field insulating film covering the sidewalls of the first fin pattern and including an upper surface and a bottom surface opposite to each other in a first direction, the bottom surface of the field insulating film facing the first surface of the backside wiring line; a source / drain pattern on the first fin pattern; Backside source / drain contacts, connecting the source / drain pattern to the backside wiring lines; as well as a back contact guide pattern on both sides of the back source / drain contacts and in contact with the back source / drain contacts, wherein the back contact guide pattern includes an upper surface and a bottom surface opposite to each other in a first direction, A bottom surface of the back contact guide pattern faces the first surface of the back wiring line, and A height from the second surface of the back-side wiring line to the bottom surface of the field insulating film is smaller than a height from the second surface of the back-side wiring line to the upper surface of the back-side contact guide pattern.

14. The semiconductor device according to claim 13, wherein: A height from the second surface of the back-side wiring line to the upper surface of the field insulating film is greater than a height from the second surface of the back-side wiring line to the upper surface of the back-side contact guide pattern.

15. The semiconductor device according to claim 13, further comprising: a source / drain etch stop film extending along the sidewalls of the source / drain pattern and the upper surface of the field insulating film, The source / drain etch stop film contacts an upper surface of the back contact guide pattern.

16. The semiconductor device according to claim 13, further comprising: a second fin pattern, spaced apart from the first fin pattern in the third direction, the second fin pattern extending in the second direction, The back contact guide pattern is spaced apart from the second fin pattern in the third direction.

17. The semiconductor device according to claim 13, further comprising: a substrate, between the backside wiring line and the first fin pattern, wherein the first fin pattern protrudes from the substrate in a first direction, and A portion of the back contact guide pattern is disposed in the substrate.

18. The semiconductor device according to claim 13, further comprising: a back-side interlayer insulating film on a bottom surface of the back-side contact guide pattern and in contact with the back-side contact guide pattern, Among them, the back wiring line is arranged in the back interlayer insulating film.

19. A semiconductor device comprising: a substrate including an upper surface and a bottom surface opposite to each other in a first direction; a first fin pattern protruding from the upper surface of the substrate in a first direction and extending in a second direction; a second fin-shaped pattern protruding from the upper surface of the substrate in the first direction, spaced apart from the first fin-shaped pattern in the third direction, and extending in the second direction; A field insulating film, on the substrate, the field insulating film covers the sidewalls of the first fin-shaped pattern and the sidewalls of the second fin-shaped pattern; a back contact guide pattern between the first fin pattern and the second fin pattern, the back contact guide pattern being disposed in the field insulating film and the substrate; a source / drain pattern on the first fin pattern; a backside wiring circuit on a bottom surface of the substrate; as well as a back source / drain contact, connecting the source / drain pattern to the back wiring line and contacting the back contact guide pattern, wherein the back contact guide pattern includes a first portion disposed in the substrate and a second portion disposed in the field insulating film, The back contact guide pattern includes a first sidewall and a second sidewall opposite to each other in a third direction, A first sidewall of the back contact guide pattern contacts the back source / drain contact, and In the first portion of the back contact guide pattern, a second sidewall of the back contact guide pattern forms an acute angle with the bottom surface of the substrate.

20. The semiconductor device according to claim 19, wherein In the second portion of the back contact guide pattern, a second sidewall of the back contact guide pattern forms an acute angle with the bottom surface of the substrate.

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