Pixel structure and display panel

Abstract

The application discloses a pixel structure and a display panel, and relates to the technical field of display. The pixel structure comprises a first pixel unit, a second pixel unit and a third pixel unit, the first pixel unit, the second pixel unit and the third pixel unit are arranged in a diamond shape, and the working voltage of the first pixel unit is higher than the working voltage of the second pixel unit and the third pixel unit. The first metal isolation layer is arranged around the first pixel unit, and the second metal isolation layer is arranged around the second pixel unit and the third pixel unit. The first insulating layer is arranged between the first metal isolation layer and the second metal isolation layer, the cathode of the first pixel unit is connected to the first metal isolation layer, and the cathode of the second pixel unit and the cathode of the third pixel unit are connected to the second metal isolation layer. The first metal isolation layer is connected to the first pin on the power management chip through the first wire, and the second metal isolation layer is connected to the second pin on the power management chip through the second wire.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, and in particular, to a pixel structure and a display panel. BACKGROUND

[0002] With the development of display technology, the organic light emitting diode (OLED) display panel has been more and more widely used due to its advantages of thinness, flexibility, high contrast, wide color gamut, etc. The display panel includes red, green and blue pixel units. The working voltages of the red, green and blue pixel units are not the same, and the cathodes of the red, green and blue pixel units are connected to the same circuit common ground voltage (VSS). This results in the need to provide a uniform working voltage for the red, green and blue pixel units, which causes power consumption waste. In addition, since the red and green pixel units belong to low cross-voltage pixel units, the uniform working voltage causes the thin film transistor (TFT) of the red and green pixel units to work in the deep saturation region, which brings about display abnormalities and other problems. SUMMARY

[0003] Embodiments of the present application provide a pixel structure and a display panel, which are used to solve the problems of power consumption waste in the existing display panel and display abnormalities of some pixel units in the display panel.

[0004] To achieve the above-mentioned purpose, embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, a pixel structure is provided, which includes a first pixel unit, a second pixel unit, a third pixel unit, a first metal isolation layer and a second metal isolation layer. The first pixel unit, the second pixel unit and the third pixel unit can adopt a diamond arrangement or an RGB arrangement, and the specific arrangement manner is not limited. The working voltage of the first pixel unit is higher than that of the second pixel unit and the third pixel unit. That is, in the display panel, the working voltages of pixel units of various colors are not the same, and there are pixel units with higher working voltage and pixel units with lower working voltage.

[0006] The first metal isolation layer is arranged around the first pixel unit, and the first pixel unit is located in the first metal isolation layer. The second metal isolation layer is arranged around the second pixel unit and the third pixel unit, and the second pixel unit and the third pixel unit are located in the second metal isolation layer. Since the working voltage of the first pixel unit is relatively high, the first metal isolation layer and the second metal isolation layer are arranged to isolate the first pixel unit from other pixel units with lower working voltages. The first insulating layer is arranged between the first metal isolation layer and the second metal isolation layer, so as to avoid electrical connection between the first metal isolation layer and the second metal isolation layer.

[0007] The cathode of the first pixel unit is connected to the first metal isolation layer, and the cathodes of the second pixel unit and the third pixel unit are connected to the second metal isolation layer. The first metal isolation layer is connected to the first pin on the power management chip through the first trace, and the second metal isolation layer is connected to the second pin on the power management chip through the second trace. By using different traces to transmit electrical signals to pixel units with different working voltages, appropriate voltages can be provided according to the different working voltages, avoiding the waste of power consumption caused by providing a high working voltage to the pixel unit with the first working voltage. At the same time, various pixel units can work in an appropriate voltage range, avoiding the problem of working in a deep saturation region caused by an unsuitable working voltage of the low-cross-pixel unit, avoiding the display abnormality problem caused by an unsuitable working voltage of the low-cross-pixel unit (such as the second pixel unit and the third pixel unit), and improving the display stability of the display panel with the pixel structure.

[0008] In a possible implementation manner of the first aspect, the first insulating layer includes a first part and a second part, and the second part is connected to the middle part of the first part, so that the first insulating layer is in a T shape. The first part is in contact with the top of the first metal isolation layer and the second metal isolation layer, respectively, and the second part is located between the first metal isolation layer and the second metal isolation layer to insulate the first metal isolation layer and the second metal isolation layer.

[0009] On this basis, the example shows a specific structure of the first insulating layer. By arranging the first insulating layer in a T shape, the first metal isolation layer and the second metal isolation layer can be effectively isolated.

[0010] In a possible implementation of the first aspect, the first pixel unit comprises a first anode, a first pixel definition layer, a first organic layer and a first cathode. The first pixel definition layer is arranged on the first anode, and the first cathode is connected to the first pixel definition layer through the first organic layer. The second pixel unit comprises a second anode, a second pixel definition layer, a second organic layer and a second cathode. The second pixel definition layer is arranged on the second anode, and the second cathode is connected to the second pixel definition layer through the second organic layer. The first cathode is connected to the first metal isolation layer, and the second cathode is connected to the second metal isolation layer.

[0011] On this basis, the specific structure of the first pixel unit and the second pixel unit is shown in this design. By arranging the first metal isolation layer and the second metal isolation layer between the pixel definition layers of the two pixels, the structure between the pixels can be fully utilized. By connecting the first cathode to the first metal isolation layer, a plurality of first metal isolation layers can be connected in series to provide a unified electrical signal, thereby realizing the individual control of the first pixel unit. Similarly, by connecting the second cathode to the second metal isolation layer, a plurality of second metal isolation layers can be connected in series to provide a unified electrical signal, thereby realizing the individual control of the second pixel unit.

[0012] In a possible implementation of the first aspect, the thickness of the first metal isolation layer is 600-1200 nm, and the width of the first metal isolation layer is 3-4 um. The thickness of the second metal isolation layer is 600-1200 nm, and the width of the second metal isolation layer is 3-4 um.

[0013] On this basis, some specific dimensions of the first metal isolation layer and the second metal isolation layer are given. For example, the thickness of the first metal layer / second metal layer can be 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1100 nm, 1200 nm, etc. The width of the first metal layer / second metal layer can be 3 um, 3.5 um, 4 um, etc. It should be noted that the thickness and width of the first metal layer / second metal layer can be a fixed value or a range, for example, the cross section of the first metal layer / second metal layer in the thickness and width directions is trapezoidal, wherein the width gradually changes, the minimum width is 3 um, and the maximum width is 4 um.

[0014] In a possible implementation of the first aspect, the thickness of the first insulating layer is 300-600 nm.

[0015] On this basis, this implementation gives the thickness range of the first insulating layer, wherein the thickness of the first insulating layer can be 300 nm, 400 nm, 500 nm, 600 nm, etc.

[0016] In a possible implementation manner of the first aspect, the second metal isolation layer includes a third metal isolation layer and a fourth metal isolation layer. The third metal isolation layer is arranged around the second pixel unit, and the second pixel unit is located in the third metal isolation layer. The fourth metal isolation layer is arranged around the third pixel unit, and the third pixel unit is located in the fourth metal isolation layer. That is, in this scheme, three isolation layers are arranged in total, and the three isolation layers correspond to the first pixel unit, the second pixel unit and the third pixel unit respectively, so that each pixel unit can be isolated from other pixel units.

[0017] The cathode of the second pixel unit is connected to the third metal isolation layer, and the cathode of the third pixel unit is connected to the fourth metal isolation layer. The second insulation layer is arranged between the first metal isolation layer and the third metal isolation layer, the third insulation layer is arranged between the third metal isolation layer and the fourth metal isolation layer, and the fourth insulation layer is arranged between the first metal isolation layer and the fourth metal isolation layer. The third metal isolation layer is connected to the third pin on the power management chip through the third trace, and the fourth metal isolation layer is connected to the fourth pin on the power management chip through the fourth trace. By connecting each pixel unit to the corresponding metal isolation layer and connecting the metal isolation layers of the same kind in series to the different pins on the power management chip through the traces, the power management chip can output corresponding electrical signals to different pixel units, avoid power waste caused by outputting the same signal, and can control the working voltage of each pixel unit individually, so that each pixel unit can work in a suitable voltage range and avoid abnormal pixel unit light emission.

[0018] In a possible implementation manner of the first aspect, the first pixel unit includes a first anode, a first pixel definition layer, a first organic layer and a first cathode, the first pixel definition layer is arranged on the first anode, and the first cathode is connected to the first pixel definition layer through the first organic layer. The third pixel unit includes a third anode, a third pixel definition layer, a third organic layer and a third cathode, the third pixel definition layer is arranged on the third anode, and the third cathode is connected to the third pixel definition layer through the third organic layer. The fourth pixel unit includes a fourth anode, a fourth pixel definition layer, a fourth organic layer and a fourth cathode, the fourth pixel definition layer is arranged on the fourth anode, and the fourth cathode is connected to the fourth pixel definition layer through the fourth organic layer. The first cathode is connected to the first metal isolation layer, the third cathode is connected to the third metal isolation layer, and the fourth cathode is connected to the fourth metal isolation layer.

[0019] On this basis, the specific structure of the first pixel unit, the third pixel unit and the fourth pixel unit is shown in the design mode. The first cathode is connected to the first metal isolation layer, a plurality of first metal isolation layers can be connected in series to provide a unified electrical signal, and the first pixel unit is controlled individually. Similarly, the third cathode is connected to the third metal isolation layer, a plurality of third metal isolation layers can be connected in series to provide a unified electrical signal, and the third pixel unit is controlled individually. The fourth cathode is connected to the fourth metal isolation layer, a plurality of fourth metal isolation layers can be connected in series to provide a unified electrical signal, and the fourth pixel unit is controlled individually.

[0020] In a possible implementation of the first aspect, the second insulating layer is the first insulating layer, and the second insulating layer, the third insulating layer and the fourth insulating layer are T-shaped.

[0021] In a possible implementation of the first aspect, the thickness of the first metal isolation layer is 600-1200 nm, and the width of the first metal isolation layer is 3-4 um; the thickness of the third metal isolation layer is 600-1200 nm, and the width of the third metal isolation layer is 3-4 um; and the thickness of the fourth metal isolation layer is 600-1200 nm, and the width of the fourth metal isolation layer is 3-4 um.

[0022] On this basis, some specific dimensions of the first metal isolation layer, the third metal isolation layer and the fourth metal isolation layer are given. For example, the thickness of the first metal layer / third metal layer / fourth metal isolation layer can be 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, 1100 nm, 1200 nm, etc. The width of the first metal layer / third metal layer / fourth metal isolation layer can be 3 um, 3.5 um, 4 um, etc. It should be noted that the thickness and width of the first metal layer / third metal layer / fourth metal isolation layer can be a fixed value or a range, for example, the cross section of the first metal layer / third metal layer / fourth metal isolation layer in the thickness and width directions is trapezoidal, and the width gradually changes, the minimum width is 3 um, and the maximum width is 4 um.

[0023] In a possible implementation of the first aspect, the thickness of the second insulating layer is 300-600 nm, the thickness of the third insulating layer is 300-600 nm, and the thickness of the fourth insulating layer is 300-600 nm.

[0024] On this basis, the implementation gives the thickness range of the second insulating layer, the third insulating layer and the fourth insulating layer, wherein the thickness of the second insulating layer / third insulating layer / fourth insulating layer can be 300 nm, 400 nm, 500 nm, 600 nm, etc.

[0025] In a second aspect, the present application provides a display panel, comprising a substrate and the pixel structure in the first aspect and any possible implementation manner thereof, wherein the pixel structure is arranged on the substrate.

[0026] It can be understood that the display panel provided in the second aspect has the beneficial effects as described in the first aspect and any possible implementation manner thereof, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 A connection diagram between each pixel unit and a power management chip in a display panel provided in the prior art;

[0028] Figure 2 A structure diagram of a pixel structure provided in an embodiment of the present application;

[0029] Figure 3 An internal structure diagram of a pixel structure provided in an embodiment of the present application;

[0030] Figure 4 A structure diagram of another pixel structure provided in an embodiment of the present application;

[0031] Figure 5 A structure diagram of still another pixel structure provided in an embodiment of the present application;

[0032] Figure 6 An internal structure diagram of still another pixel structure provided in an embodiment of the present application;

[0033] Figure 7 A structure diagram of yet another pixel structure provided in an embodiment of the present application.

[0034] In the figure: 101-pixel unit area; 102-connection trace; 103-PAD area; 104-circuit board; 105-power management chip; 106-high signal area; 107-low signal area;

[0035] 110-blue pixel unit; 120-green pixel unit; 130-red pixel unit; 140-first metal isolation layer; 150-second metal isolation layer; 160-third metal isolation layer; 170-fourth metal isolation layer;

[0036] 111-first anode; 112-first pixel definition layer; 113-first organic layer; 114-first cathode;

[0037] 121-second anode; 122-second pixel definition layer; 123-second organic layer; 124-second cathode;

[0038] 131 - third anode; 132 - third pixel defining layer; 133 - third organic layer; 134 - third cathode;

[0039] 141 - fourth anode; 142 - fourth pixel defining layer; 143 - fourth organic layer; 144 - fourth cathode;

[0040] 210 - first insulating layer; 220 - second insulating layer; 230 - third insulating layer; 240 - fourth insulating layer;

[0041] 211 - first part; 212 - second part;

[0042] 310 - first trace; 320 - second trace; 330 - third trace; 340 - fourth trace;

[0043] 410 - first pin; 420 - second pin; 430 - third pin; 440 - fourth pin. DETAILED DESCRIPTION

[0044] The technical solutions in the present application will be described below with reference to the drawings.

[0045] In the present application, the word "exemplary" or "for example" is used to mean serving as an example, instance, or illustration. Any implementation described herein as "exemplary" or "for example" is not necessarily to be construed as preferred or advantageous over other implementations. The

[0046] In the embodiments of the present application, the terms "first", "second", etc. are used only for the purpose of description, and should not be understood as indicating or implying relative importance or implying the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features.

[0047] It should be understood that the terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used in the description of the various embodiments, the singular forms "a", "an" and "the" are intended to include plural forms as well, unless the context clearly indicates otherwise.

[0048] In this application, "at least one", "one or more", and "multiple" mean one, two, or more. "At least one of the following (one or more)" or similar expressions means any combination of these items, including any combination of single item (one) or multiple items. For example, at least one of a, b, or c can mean a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.

[0049] It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The term "and / or", is a description of the associated relationship between the associated objects, which means that there can be three relationships, for example, A and / or B, which can mean that A exists alone, A and B exist together, and B exists alone. In addition, the character " / " in this application generally means that the associated objects are in an "or" relationship.

[0050] It should also be understood that in this application, unless otherwise explicitly specified and limited, the term "connection" should be understood broadly, for example, "connection" can mean that two elements are directly connected, or that two elements are indirectly connected through other elements, fixed connection, or sliding connection, or detachable connection, or one-piece, etc.

[0051] It should also be understood that the term "includes" (also referred to as "includes", "including", "comprises" and / or "comprising") when used in this specification specifies the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0052] It should be understood that the "one embodiment", "another embodiment", "a possible design" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment or implementation are included in at least one embodiment of the application. Therefore, "in one embodiment of the present application" or "in another embodiment of the present application", "a possible design" appearing throughout the specification does not necessarily mean the same embodiment. In addition, these specific features, structures or characteristics can be combined in any suitable manner in one or more embodiments.

[0053] It should also be understood that the specific numerical values mentioned in the embodiments of the present application are not limited to the specific dimensions of the specific features, and the related values may be for the convenience of understanding or may be the best theoretical value of a certain feature. In practice, the related dimensions can be a range around the value, for example, the range can be ±10% of the best theoretical value, or ±20% of the best theoretical value, and in practice, the corresponding technical effect can be achieved.

[0054] With the development of display technology, organic light emitting diode (OLED) display panels have been more and more widely used due to their advantages such as thinness, lightness, wide viewing angle, active light-emitting, continuous adjustable light-emitting color, low cost, fast response speed, low energy consumption, low driving voltage, wide working temperature range, simple production process, high light-emitting efficiency, and flexible display.

[0055] The display panel includes red, green, and blue pixel units, wherein each pixel unit includes a thin film transistor (TFT), and the working voltage of the TFT in pixel units of different colors is different. In the existing technical solution, the cathodes of the TFTs in pixel units of each color are connected to a circuit common ground voltage (VSS), and the power management chip 105 (PMIC) provides the same voltage for pixel units of different colors. In the prior art, the connection relationship between each pixel unit and the power management chip 105 can be referred to as Figure 1 , Figure 1 is a connection diagram between each pixel unit and the power management chip 105 in a display panel provided by the prior art. As shown in Figure 1 , the diagram includes a pixel unit area 101, a connection trace 102, a PAD area 103, a circuit board 104, and a power management chip 105. The power management chip 105 is connected to the circuit board 104, the PAD area 103 is in contact with one side of the pixel unit area 101, the cathodes of each pixel unit in the pixel unit area 101 are connected to the connection trace 102 through anode metal, the connection trace 102 is routed along the frame of the pixel unit area 101, and passes through the PAD area 103 to be connected to the power management chip 105 on the circuit board 104. As shown in Figure 1 , the pixel unit area 101 and the RE are mainly connected at the upper side, the left side, and the right side of the frame area. Due to the existence of the cathode resistance, the cathode resistance will cause different VSS write values at different positions, forming a VSS high signal area 106 and a VSS low signal area 107 as shown in Figure 1 . On a 7.92-in screen, if the cathode resistance is 7-9 Ω / m2 Therefore, the voltage difference between the VSS high signal area 106 and the VSS low signal area 107 caused by the cathode side resistance is 0.4-0.6V.

[0056] In addition, in the prior technical solution, the pixel units of different colors in the pixel unit area 101 receive the same VSS signal, and the low-cross voltage pixel units such as green pixel units and red pixel units are included in the pixel units of different colors. There is a large voltage difference between the VSS signal received by the low-cross voltage pixel unit and the VSS signal that just meets the working requirement of the low-cross voltage pixel unit, which causes the TFT of the low-cross voltage pixel unit to work in the deep saturation area, not only causing the waste of power consumption, but also causing the problem of reliability color shift.

[0057] To solve the above problems, the display panel provided by the embodiment of the present application can reduce the overall power consumption of the pixel unit when working in the display panel, and at the same time, avoid the low-cross voltage pixel unit working in the deep saturation area, avoid the TFT aging caused by the electric stress, and improve the problem of reliability color shift (for example, the display picture turns green at low gray scale), and improve the low gray scale picture quality effect.

[0058] In the embodiment of the present application, the display panel includes a substrate and a pixel structure, and the pixel structure is arranged on the substrate. The pixel structure includes a plurality of pixel units, which can include pixel units of multiple colors, for example, can include red pixel units 130, green pixel units 120, blue pixel units 110 and white pixel units, etc., wherein each color of pixel unit is provided with a plurality of pixel units, and pixel units of different colors constitute a display unit. For example, the red pixel units 130, the green pixel units 120 and the blue pixel units 110 can constitute a display unit. In the embodiment of the present application, the structure and circuit connection between the pixel units of different colors in the display panel are mainly introduced by taking the red pixel units 130, the green pixel units 120 and the blue pixel units 110 as examples. The arrangement mode between the red pixel units 130, the green pixel units 120 and the blue pixel units 110 can adopt diamond arrangement. Diamond arrangement refers to the diamond arrangement of four sub-pixels, also known as diamond-like arrangement. For diamond arrangement, please refer to the prior art.

[0059] Reference Figure 2 , Figure 2 A structure schematic diagram of a pixel structure provided by the embodiment of the present application is shown in FIG. 1. As shown in FIG. 1, the pixel structure includes a red pixel unit 130, a green pixel unit 120 and a blue pixel unit 110. Figure 2As shown, the pixel structure includes a first pixel unit, a second pixel unit and a third pixel unit, wherein the first pixel unit, the second pixel unit and the third pixel unit are arranged in a diamond arrangement. The working voltage of the first pixel unit, the working voltage of the second pixel unit and the working voltage of the third pixel unit are different, and the working voltage of the first pixel unit is higher than the working voltage of the second pixel unit and the working voltage of the third pixel unit. The working voltage of the second pixel unit can be similar to the working voltage of the third pixel unit. The first pixel unit can be one of the red pixel unit 130, the green pixel unit 120 and the blue pixel unit 110, the second pixel unit can be another of the red pixel unit 130, the green pixel unit 120 and the blue pixel unit 110, and the third pixel unit can be another of the red pixel unit 130, the green pixel unit 120 and the blue pixel unit 110. In the embodiment of the present application, the first pixel unit is taken as the blue pixel unit 110, the second pixel unit is taken as the green pixel unit 120, and the third pixel unit is taken as the red pixel unit 130 as an example for description.

[0060] As shown in Figure 2 The outer side of the blue pixel unit 110 is provided with a first metal isolation layer 140, the first metal isolation layer 140 is annular, and the blue pixel unit 110 is arranged around the first metal isolation layer 140, so that the blue pixel unit 110 is located in the first metal isolation layer 140. The outer side of the red pixel unit 130 and the green pixel unit 120 is provided with a second metal isolation layer 150, the second metal isolation layer 150 is annular, and the red pixel unit 130 and the green pixel unit 120 are arranged around the second metal isolation layer 150, so that the red pixel unit 130 and the green pixel unit 120 are located in the second metal isolation layer 150. The cathode of the blue pixel unit 110 is connected to the first metal isolation layer 140, and the cathode of the red pixel unit 130 and the cathode of the green pixel unit 120 are both connected to the second metal isolation layer 150. The first metal isolation layer 140 and the second metal isolation layer 150 are provided with a first insulating layer 210. The first insulating layer 210 prevents electrical connection between the first metal isolation layer 140 and the second metal isolation layer 150. The first metal isolation layer 140 is connected to the first wire 310, and the second metal isolation layer 150 is connected to the second wire 320. The first wire 310 is connected to the first pin 410 of the power management chip, and the second wire 320 is connected to the second pin 420 of the power management chip.

[0061] It should be noted that the display panel includes a plurality of pixel units, specifically including a plurality of blue pixel units 110, a plurality of red pixel units 130 and a plurality of green pixel units 120, wherein the outer side of each blue pixel unit 110 is provided with a first metal isolation layer 140, that is, a plurality of first metal isolation layers 140 are provided in the display panel, and the number of first metal isolation layers 140 can be equal to the number of blue pixel units 110. The cathode of each blue pixel unit 110 is connected to the corresponding first metal isolation layer 140, and then all the first metal isolation layers 140 are connected to the first wire 310, and the first wire 310 is connected to the first pin 410 of the power management chip. Through the signal output by the first pin 410 of the power management chip, the working voltage of all blue pixel units 110 can be controlled individually.

[0062] Correspondingly, the display panel includes a plurality of red pixel units 130 and green pixel units 120, wherein the number of red pixel units 130 can be equal to the number of green pixel units 120. A plurality of second metal isolation layers 150 are provided in the display panel, each second metal isolation layer 150 surrounds one red pixel unit 130 and one green pixel unit 120. The number of second metal isolation layers 150 is the same as the number of red pixel units 130 (or green pixel units 120), wherein the cathodes of the red pixel units 130 and the green pixel units 120 are connected to the corresponding second metal isolation layer 150, that is, the cathode of one red pixel unit 130 and the cathode of one green pixel unit 120 are connected to each second metal isolation layer 150. All second metal isolation layers 150 are connected to the second wire 320, and the second wire 320 is connected to the second pin 420 of the power management chip. Through the power management chip, the working voltage of all red pixel units 130 and green pixel units 120 can be controlled.

[0063] Since the cathodes of the red pixel units 130 and the green pixel units 120 are connected to the second wire 320, the working voltage of the red pixel units 130 and the green pixel units 120 can be the same in this embodiment. Since the blue pixel units 110 are connected to the first wire 310, the power management chip can control the working voltage output by the first wire 310 and the second wire 320, so that the working voltage of the blue pixel units 110 is different from the working voltage of the red pixel units 130 and the green pixel units 120, and each pixel unit works within its rated working voltage range. For example, the working voltage of the blue pixel units 110 can be controlled to be -4v, and the working voltage of the red pixel units 130 and the green pixel units 120 can be controlled to be -2.5v.

[0064] In the prior art, all pixel units are connected to the same VSS, and pixel units of various colors receive the same electrical signal. In order to ensure that all pixel units can work normally, a higher voltage needs to be output, so that the pixel units with a higher working voltage can work normally. For low-cross-pixel units (green pixel unit 120 and red pixel unit 130), receiving a higher working voltage will make the low-cross-pixel units work in a deep saturation region, which affects the display effect of the display panel and causes power waste.

[0065] Compared with the prior art, the pixel units with different working voltages are connected to the power management chip through different traces in the present application. The working voltages of the pixel units with different working voltages are controlled separately, so that the pixel units of various colors can work near the rated voltage, avoiding power waste and reducing the overall power consumption of the display panel. Taking the working voltage of the blue pixel unit 110 as -4v and the working voltage of the red pixel unit 130 and the green pixel unit 120 as -2.5v as an example, compared with the working voltage of all pixel units being -4v, the overall power consumption of the display panel can be reduced by 5%-7%. In addition, by controlling the working voltages of pixel units of different colors, the low-cross-pixel units (green pixel unit 120 and red pixel unit 130) can work in a near saturation region, which can improve the display effect of the display panel. For example, it can improve the display quality at low gray levels and improve the problem of green after RA.

[0066] Reference Figure 3 , Figure 3 An internal structure schematic diagram of a pixel structure provided by an embodiment of the present application. Since in the embodiment of the present application, the red pixel unit 130 and the green pixel unit 120 are both arranged in the second metal isolation layer 150, in the Figure 3 , the relationship between the first metal isolation layer 140 and the second metal isolation layer 150 is shown from the perspective of the blue pixel unit 110 and the green pixel unit 120, and the red pixel unit 130 is not shown.

[0067] As Figure 3As shown, the pixel structure includes a first pixel unit (blue pixel unit 110) and a second pixel unit (green pixel unit 120), wherein the blue pixel unit 110 includes a first anode 111, a first pixel definition layer 112 (PDL), a first organic layer 113, and a first cathode 114, the first pixel definition layer 112 is arranged on the first anode 111, and the first cathode 114 is connected with the first pixel definition layer 112 through the first organic layer 113. The green pixel unit 120 includes a second anode 121, a second pixel definition layer 122 (PDL), a second organic layer 123, and a second cathode 124, the second pixel definition layer 122 is arranged on the second anode 121, and the second cathode 124 is connected with the second pixel definition layer 122 through the second organic layer 123. The first metal isolation layer 140 and the second metal isolation layer 150 are arranged between the blue pixel unit 110 and the green pixel unit 120, the first cathode 114 is overlapped on the first metal isolation layer 140, and the second cathode 124 is overlapped on the second metal isolation layer 150. The first metal isolation layer 140 is connected with the first pin 410 of the power management chip, and the second metal isolation layer 150 is connected with the second pin 420 of the power management chip. The first insulating layer 210 is further arranged between the first metal isolation layer 140 and the second metal isolation layer 150, and the first insulating layer 210 is used to insulate the first metal isolation layer 140 and the second metal isolation layer 150, so as to avoid the electrical connection between the first metal isolation layer 140 and the second metal isolation layer 150.

[0068] In an embodiment of the present application, the first insulating layer 210 includes a first part 211 and a second part 212, and the second part 212 is connected with the middle part of the first part 211, so that the first insulating layer 210 is in T shape. The first part 211 of the first insulating layer 210 is in contact with the top of the first metal isolation layer 140 and the second metal isolation layer 150 respectively, and the second part 212 of the first insulating layer 210 is located at the gap between the first metal isolation layer 140 and the second metal isolation layer 150, and insulates the first metal isolation layer 140 and the second metal isolation layer 150. The first insulating layer 210 can be an insulating layer made of organic material, or an insulating layer made of inorganic material. For example, the first insulating layer 210 can be an insulating layer made of photosensitive polyimide (PSPI), or an insulating layer made of silicon nitride (SiNx). SiNx is an amorphous material, and its properties depend on the ratio of nitrogen and silicon, i.e. the value of x. When the first insulating layer 210 is made, an exposure and development process can be used for making.

[0069] The thickness L1 of the first insulating layer 210 can be set to 600-1200 nm. The thickness of the first insulating layer 210 refers to the height of the entire T-shaped insulating layer, that is, the height of the first insulating layer 210 in the vertical direction. Figure 3 The height of the first insulating layer 210 in the vertical direction.

[0070] In an embodiment of the present application, the first metal isolation layer 140 and the second metal isolation layer 150 can be made of the same material or different materials, but are generally made of the same material. The first metal isolation layer 140 and the second metal isolation layer 150 can be made of molybdenum (Mo), aluminum (Al), titanium (Ti), etc. The thickness h1 of the first metal isolation layer 140 is 600-1200 nm, and the width w1 of the first metal isolation layer 140 is 3-4 um. The thickness h2 of the second metal isolation layer 150 is 600-1200 nm, and the width w2 of the second metal isolation layer 150 is 3-4 um. Generally, the thickness of the first metal isolation layer 140 is equal to the thickness of the second metal isolation layer 150, and the width of the first metal isolation layer 140 is equal to the width of the second metal isolation layer 150. Thus, the cross-sectional shape of the first metal isolation layer 140 (shown in Figure 2 ) is the same as the cross-sectional shape of the second metal isolation layer 150 (shown in Figure 2 ).

[0071] It should be noted that the width of the first metal isolation layer 140 refers to the width of the first metal isolation layer 140 in the horizontal direction, and the thickness of the first metal isolation layer 140 refers to the height of the first metal isolation layer 140 in the vertical direction. Figure 2 Figure 3 It should be noted that the width of the first metal isolation layer 140 refers to the width of the first metal isolation layer 140 in the horizontal direction, and the thickness of the first metal isolation layer 140 refers to the height of the first metal isolation layer 140 in the vertical direction. Figure 3 Figure 2 It should be noted that the width of the first metal isolation layer 140 refers to the width of the first metal isolation layer 140 in the horizontal direction, and the thickness of the first metal isolation layer 140 refers to the height of the first metal isolation layer 140 in the vertical direction.

[0072] In the pixel structure described above, the pixel units are arranged in a diamond arrangement. In addition, the pixel units in the pixel structure can also be arranged in other arrangements. For example, Figure 2 , Figure 4 , Figure 4 Another pixel structure provided by an embodiment of the present application is shown in the structure diagram. As shown in Figure 4 , the pixel units in the pixel structure can also be arranged in an RGB arrangement, Figure 4 , which is different from the arrangement of the pixel units in the technical solution shown in Figure 2 . The other settings can be referred to the technical solution shown in Figure 2 ​​The relevant descriptions in the corresponding embodiments will not be repeated here.

[0073] In one embodiment of this application, to further improve the technical problems described above, another pixel structure is also provided. In this pixel structure, the connection structure between pixel units can refer to... Figure 5 . Figure 5 This is a schematic diagram of another pixel structure provided in an embodiment of this application. For example... Figure 5 As shown, the pixel structure includes a first pixel unit, a second pixel unit, and a third pixel unit. The first pixel unit is a blue pixel unit 110, the second pixel unit is a green pixel unit 120, and the third pixel unit is a red pixel unit 130. The first, second, and third pixel units are arranged in a diamond pattern. A first metal isolation layer 140 is disposed around the blue pixel unit 110 in a ring shape, so that the blue pixel unit 110 is located within the first metal isolation layer 140. A third metal isolation layer 160 is disposed around the green pixel unit 120 in a ring shape, so that the green pixel unit 120 is located within the third metal isolation layer 160. A fourth metal isolation layer 170 is disposed around the red pixel unit 130 in a ring shape, so that the red pixel unit 130 is located within the fourth metal isolation layer 170.

[0074] The cathode of the blue pixel unit 110 is connected to the first metal isolation layer 140, the cathode of the green pixel unit 120 is connected to the third metal isolation layer 160, and the cathode of the red pixel unit 130 is connected to the fourth metal isolation layer 170. A second insulating layer 220 is disposed between the first metal isolation layer 140 and the third metal isolation layer 160 to prevent electrical connection between them. A third insulating layer 230 is disposed between the third metal isolation layer 160 and the fourth metal isolation layer 170 to prevent electrical connection between them. A fourth insulating layer 240 is disposed between the first metal isolation layer 140 and the fourth metal isolation layer 170 to prevent electrical connection between them.

[0075] The first metal isolation layer 140 corresponding to the blue pixel unit 110 is connected to the first wire 310, the third metal isolation layer 160 corresponding to the green pixel unit 120 is connected to the third wire 330, and the fourth metal isolation layer 170 corresponding to the red pixel unit 130 is connected to the fourth wire 340. The first wire 310 is connected to the first pin 410 of the power management chip, the third wire 330 is connected to the third pin 430 of the power management chip, and the fourth wire 340 is connected to the fourth pin 440 of the power management chip.

[0076] The difference between the embodiment and the embodiment shown in Figure 2 The difference between the embodiment and the embodiment shown in Figure 2 The difference between the embodiment and the embodiment shown in Figure 2 The difference between the embodiment and the embodiment shown in Figure 5 The difference between the embodiment and the embodiment shown in Figure 2 The difference between the embodiment and the embodiment shown in Figure 3 The difference between the embodiment and the embodiment shown in The difference between the embodiment and the embodiment shown in

[0077] The difference between the embodiment and the embodiment shown in Figure 5 The difference between the embodiment and the embodiment shown in Figure 6 The difference between the embodiment and the embodiment shown in Figure 5 The difference between the embodiment and the embodiment shown in Figure 6 The difference between the embodiment and the embodiment shown in Figure 2 The difference between the embodiment and the embodiment shown in Figure 3 The difference between the embodiment and the embodiment shown in Figure 5 The difference between the embodiment and the embodiment shown in Figure 6 The difference between the embodiment and the embodiment shown in Figure 2 The difference between the embodiment and the embodiment shown in Figure 3 The difference between the embodiment and the embodiment shown inFigure 5 and Figure 6 The first trace 310 in the structure shown in FIG. 13A can be Figure 2 and Figure 3 The first trace 310 in the structure shown in FIG. 13A, Figure 5 and Figure 6 The fourth trace 340 in the structure shown in FIG. 13D can be Figure 2 and Figure 3 The second trace 320 in the structure shown in FIG. 13B.

[0078] It should be noted that the pixel structure in the display panel includes a plurality of blue pixel units 110, a plurality of red pixel units 130 and a plurality of green pixel units 120, wherein the outer side of each blue pixel unit 110 is provided with a first metal isolation layer 140, that is, a plurality of first metal isolation layers 140 are provided in the display panel, and the number of first metal isolation layers 140 can be equal to the number of blue pixel units 110. The cathode of each blue pixel unit 110 is connected to the corresponding first metal isolation layer 140, and then all the first metal isolation layers 140 are connected to the first trace 310, and the first trace 310 is connected to the first pin 410 of the power management chip. Such a setting can separately control the working voltage of all blue pixel units 110 through the power management chip.

[0079] The outer side of each green pixel unit 120 is provided with a third metal isolation layer 160, that is, a plurality of third metal isolation layers 160 are provided in the display panel, and the number of third metal isolation layers 160 can be equal to the number of green pixel units 120. The cathode of each green pixel unit 120 is connected to the corresponding third metal isolation layer 160, and then all the third metal isolation layers 160 are connected to the third trace 330, and the third trace 330 is connected to the third pin 430 of the power management chip. Such a setting can separately control the working voltage of all green pixel units 120 through the power management chip.

[0080] The outer side of each red pixel unit 130 is provided with a fourth metal isolation layer 170, that is, a plurality of fourth metal isolation layers 170 are provided in the display panel, and the number of fourth metal isolation layers 170 can be equal to the number of red pixel units 130. The cathode of each red pixel unit 130 is connected to the corresponding fourth metal isolation layer 170, and then all the fourth metal isolation layers 170 are connected to the fourth trace 340, and the fourth trace 340 is connected to the fourth pin 440 of the power management chip. Such a setting can separately control the working voltage of all red pixel units 130 through the power management chip.

[0081] The structure design between pixel units of different colors and metal isolation layers can refer toFigure 5 and Figure 6 . Figure 6 This is a schematic diagram of the internal structure of another pixel structure provided in an embodiment of this application. Figure 6 Image (a) shows the connection structure between the blue pixel unit 110, the green pixel unit 120, the first metal isolation layer 140, and the third metal isolation layer 160. Figure 6 Figure (b) shows the connection structure between the green pixel unit 120, the red pixel unit 130, the third metal isolation layer 160, and the fourth metal isolation layer 170. Figure 6 (c) shows the connection structure between the blue pixel unit 110, the red pixel unit 130, the first metal isolation layer 140 and the fourth metal isolation layer 170.

[0082] like Figure 6 As shown in (a), the display panel includes a blue pixel unit 110 and a green pixel unit 120. The blue pixel unit 110 includes a first anode 111, a first pixel definition layer (PDL), a first organic layer 113, and a first cathode 114. The first pixel definition layer 112 is disposed on the first anode 111, and the first cathode 114 is connected to the first pixel definition layer 112 through the first organic layer 113. The green pixel unit 120 includes a third anode 131, a third pixel definition layer 132, a third organic layer 133, and a third cathode 134. The third pixel definition layer 132 is disposed on the third anode 131, and the third cathode 134 is connected to the third pixel definition layer 132 through the third organic layer 133. A first metal isolation layer 140 and a third metal isolation layer 160 are disposed between the blue pixel unit 110 and the green pixel unit 120. The first cathode 114 is attached to the first metal isolation layer 140, and the third cathode 134 is attached to the third metal isolation layer 160. The first metal isolation layer 140 is connected to the first pin 410 of the power management chip, and the third metal isolation layer 160 is connected to the third pin 430 of the power management chip. A second insulating layer 220 is also provided between the first metal isolation layer 140 and the third metal isolation layer 160. The second insulating layer 220 is used to isolate the first metal isolation layer 140 and the third metal isolation layer 160, and to prevent electrical connection between the first metal isolation layer 140 and the third metal isolation layer 160.

[0083] like Figure 6As shown in (b) of FIG. 12, the display panel includes a green pixel unit 120 and a red pixel unit 130. The green pixel unit 120 includes a third anode 131, a third pixel definition layer 132, a third organic layer 133, and a third cathode 134. The third pixel definition layer 132 is disposed on the third anode 131, and the third cathode 134 is connected to the third pixel definition layer 132 through the third organic layer 133. The red pixel unit 130 includes a fourth anode 141, a fourth pixel definition layer 142, a fourth organic layer 143, and a fourth cathode 144. The fourth pixel definition layer 142 is disposed on the fourth anode 141, and the fourth cathode 144 is connected to the fourth pixel definition layer 142 through the fourth organic layer 143. The third cathode 134 is overlapped on a third metal isolation layer 160, and the fourth cathode 144 is overlapped on a fourth metal isolation layer 170. The third metal isolation layer 160 is connected to a third pin 430 of the power management chip, and the fourth metal isolation layer 170 is connected to a fourth pin 440 of the power management chip. A third insulating layer 230 is further disposed between the third metal isolation layer 160 and the fourth metal isolation layer 170. The third insulating layer 230 is used to insulate the third metal isolation layer 160 and the fourth metal isolation layer 170, so as to avoid electrical connection between the third metal isolation layer 160 and the fourth metal isolation layer 170.

[0084] As Figure 6As shown in (c) of FIG. 1, the display panel includes a blue pixel unit 110 and a red pixel unit 130. The blue pixel unit 110 includes a first anode 111, a first pixel definition layer 112, a first organic layer 113, and a first cathode 114. The first pixel definition layer 112 is disposed on the first anode 111, and the first cathode 114 is connected to the first pixel definition layer 112 through the first organic layer 113. The red pixel unit 130 includes a fourth anode 141, a fourth pixel definition layer 142, a fourth organic layer 143, and a fourth cathode 144. The fourth pixel definition layer 142 is disposed on the fourth anode 141, and the fourth cathode 144 is connected to the fourth pixel definition layer 142 through the fourth organic layer 143. The first cathode 114 is overlapped on a first metal isolation layer 140, and the fourth cathode 144 is overlapped on a fourth metal isolation layer 170. The first metal isolation layer 140 is connected to a first pin 410 of the power management chip, and the fourth metal isolation layer 170 is connected to a fourth pin 440 of the power management chip. A fourth insulating layer 240 is further disposed between the first metal isolation layer 140 and the fourth metal isolation layer 170, and the fourth insulating layer 240 is used to insulate the first metal isolation layer 140 and the fourth metal isolation layer 170, so as to avoid the electrical connection between the first metal isolation layer 140 and the fourth metal isolation layer 170.

[0085] It should be noted that the second insulating layer 220, the third insulating layer 230, and the fourth insulating layer 240 have the same function as the first insulating layer 210. The material, shape, and manufacturing process of the second insulating layer 220, the third insulating layer 230, and the fourth insulating layer 240 can be referred to the first insulating layer 210 described in the foregoing embodiments, which will not be repeated here. The material, thickness, width, and cross-sectional shape of the third metal isolation layer 160 and the fourth metal isolation layer 170 can be set according to the foregoing embodiments of the first metal isolation layer 140 or the second metal isolation layer 150, which will not be repeated here.

[0086] For example, the first metal isolation layer 140, the third metal isolation layer 160, and the fourth metal isolation layer 170 can be made of molybdenum (Mo), aluminum (Al), titanium (Ti), or the like. The thickness of the first metal isolation layer 140h1, the third metal isolation layer 160h3, and the fourth metal isolation layer 170h4 is 600-1200 nm, and the width w4 of the first metal isolation layer 140w1, the third metal isolation layer 160w3, and the fourth metal isolation layer 170 is 3-4 um. The thickness L2 of the second insulating layer 220 is 300-600 nm, the thickness L3 of the third insulating layer 230 is 300-600 nm, and the thickness L4 of the fourth insulating layer 240 is 300-600 nm.

[0087] In the embodiment of the present application, the blue pixel unit 110, the green pixel unit 120 and the red pixel unit 130 are respectively connected to the power management chip through three independent wires, so as to independently control the working voltage of the pixel units of different colors, and the working voltage of the pixel units of each color is more accurately controlled. Each color of the pixel unit can work in its rated working voltage range, thereby avoiding the power waste caused by unified power supply. And it avoids the low-cross voltage pixel unit working in a higher working voltage range, avoids the low-cross voltage pixel unit working in a deep saturation region, and by making the low-cross voltage pixel unit work in the rated working voltage range, it works in the near saturation region, which is conducive to improving the display effect of the display panel.

[0088] In Figure 5 The pixel structure introduced in the embodiment of the present application is arranged in a diamond arrangement. In addition, the pixel units in the pixel structure can also be arranged in other arrangements. For Figure 7 , Figure 7 Another pixel structure provided in the embodiment of the present application is shown in the structure diagram. As Figure 7 indicated, the pixel units in the pixel structure can also be arranged in an RGB arrangement, Figure 7 and Figure 5 The difference between the technical solutions shown in the embodiment of the present application is only that the arrangement of the pixel units in the pixel structure is different, and other settings can refer to the related description in the embodiment corresponding to Figure 5 , which will not be repeated here.

[0089] In an embodiment of the present application, a display panel is also provided. The display panel comprises a substrate and a pixel structure, and the pixel structure is arranged on the substrate. The pixel structure can be any of the pixel structures introduced in the above embodiments.

[0090] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered within the protection scope of the present application.

[0091] Each embodiment in the present specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts between the embodiments can be referred to each other.

[0092] Although the preferred embodiments of the present application have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic creative concept. Therefore, the protection scope of the present application includes the preferred embodiments and all changes and modifications falling within the scope of the embodiments of the present application.

[0093] The pixel structure and the display panel provided by the present application are described in detail above, and the principles and implementation manners of the present application are described by using specific examples. The above description of the examples is only used to help understand the transmission circuit and the core idea thereof. Meanwhile, for those skilled in the art, the specific implementation manners and application ranges can be changed according to the idea of the present application. In summary, the content of the description should not be understood as a limitation of the present application.

[0094] The above is only a specific implementation manner of the present application, but the protection scope of the present application is not limited to this. Any change or replacement within the technical scope disclosed by the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A pixel structure, characterized by, The first pixel unit, the second pixel unit, the third pixel unit, the first metal isolation layer and the second metal isolation layer are included, and the working voltage of the first pixel unit is higher than the working voltage of the second pixel unit and the third pixel unit; The first metal isolation layer is arranged around the first pixel unit, and the first pixel unit is located in the first metal isolation layer; the second metal isolation layer is arranged around the second pixel unit and the third pixel unit, and the second pixel unit and the third pixel unit are located in the second metal isolation layer; The first insulating layer is arranged between the first metal isolation layer and the second metal isolation layer; The cathode of the first pixel unit is connected to the first metal isolation layer, and the cathodes of the second pixel unit and the third pixel unit are connected to the second metal isolation layer; The first metal isolation layer is connected to the first pin on the power management chip through the first wire, and the second metal isolation layer is connected to the second pin on the power management chip through the second wire.

2. The pixel structure of claim 1, wherein, The first insulating layer includes a first part and a second part, and the second part is connected to the middle part of the first part, so that the first insulating layer is T-shaped; The first part is in contact with the top of the first metal isolation layer and the second metal isolation layer respectively, and the second part is located between the first metal isolation layer and the second metal isolation layer to insulate the first metal isolation layer and the second metal isolation layer.

3. The pixel structure of claim 1, wherein, The first pixel unit includes a first anode, a first pixel definition layer, a first organic layer and a first cathode, the first pixel definition layer is arranged on the first anode, and the first cathode is connected to the first pixel definition layer through the first organic layer; The second pixel unit includes a second anode, a second pixel definition layer, a second organic layer and a second cathode, the second pixel definition layer is arranged on the second anode, and the second cathode is connected to the second pixel definition layer through the second organic layer; The first cathode is connected to the first metal isolation layer, and the second cathode is connected to the second metal isolation layer.

4. The pixel structure according to any one of claims 1 to 3, characterized in that, The thickness of the first metal isolation layer is 600-1200nm, and the width of the first metal isolation layer is 3-4um; the thickness of the second metal isolation layer is 600-1200nm, and the width of the second metal isolation layer is 3-4um.

5. The pixel structure of claim 4, wherein, The thickness of the first insulating layer is 300-600nm.

6. The pixel structure of claim 1, wherein, The second metal isolation layer includes a third metal isolation layer and a fourth metal isolation layer, the third metal isolation layer is arranged around the second pixel unit, and the second pixel unit is located in the third metal isolation layer; the fourth metal isolation layer is arranged around the third pixel unit, and the third pixel unit is located in the fourth metal isolation layer; The cathode of the second pixel unit is connected to the third metal isolation layer, and the cathode of the third pixel unit is connected to the fourth metal isolation layer; A second insulating layer is arranged between the first metal isolation layer and the third metal isolation layer, a third insulating layer is arranged between the third metal isolation layer and the fourth metal isolation layer, and a fourth insulating layer is arranged between the first metal isolation layer and the fourth metal isolation layer; The second trace includes a third trace and a fourth trace, the second pin includes a third pin and a fourth pin, the third metal isolation layer is connected to the third pin on the power management chip through the third trace, and the fourth metal isolation layer is connected to the fourth pin on the power management chip through the fourth trace.

7. The pixel structure of claim 6, wherein, The first pixel unit includes a first anode, a first pixel definition layer, a first organic layer, and a first cathode, the first pixel definition layer is arranged on the first anode, and the first cathode is connected to the first pixel definition layer through the first organic layer; The second pixel unit includes a third anode, a third pixel definition layer, a third organic layer, and a third cathode, the third pixel definition layer is arranged on the third anode, and the third cathode is connected to the third pixel definition layer through the third organic layer; The third pixel unit includes a fourth anode, a fourth pixel definition layer, a fourth organic layer, and a fourth cathode, the fourth pixel definition layer is arranged on the fourth anode, and the fourth cathode is connected to the fourth pixel definition layer through the fourth organic layer; The first cathode is connected to the first metal isolation layer, the third cathode is connected to the third metal isolation layer, and the fourth cathode is connected to the fourth metal isolation layer.

8. The pixel structure according to claim 6 or 7, characterized in that, The second insulating layer is the first insulating layer, and the second insulating layer, the third insulating layer, and the fourth insulating layer are all T-shaped.

9. The pixel structure of claim 8, wherein, The thickness of the first metal isolation layer is 600-1200 nm, and the width of the first metal isolation layer is 3-4 um; the thickness of the third metal isolation layer is 600-1200 nm, and the width of the third metal isolation layer is 3-4 um; and the thickness of the fourth metal isolation layer is 600-1200 nm, and the width of the fourth metal isolation layer is 3-4 um.

10. The pixel structure of claim 9, wherein, The thickness of the second insulating layer is 300-600 nm, the thickness of the third insulating layer is 300-600 nm, and the thickness of the fourth insulating layer is 300-600 nm.

11. A display panel, characterized by, The pixel structure includes a substrate and the pixel structure according to any one of claims 1-10, and the pixel structure is arranged on the substrate.

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