Data model adjustment method and device and model construction method and device

Abstract

The invention provides a graphic processing method and device and a computer readable storage medium. The method comprises: acquiring a to-be-processed graph, the to-be-processed graph comprising a plurality of sub-graphs (S101); performing graphics processing on the plurality of sub-graphics using a plurality of graphics processing modules (S102), each graphics processing module processing at most one sub-graphics within a processing cycle; obtaining a storage space size required by each graphics processing module for processing the sub-graphics (S103); and allocating a corresponding number of storage units to each graphics processing module according to the size of the storage space (S104). Compared with the prior art, the graphic processing method and device and the computer readable storage medium provided by the embodiment of the invention have the advantage that the overall requirement for the size of the storage space can be reduced.

Description

[Corrected 11.03.2024 according to Rule 91] Graphics processing method, device and computer-readable storage medium Technical Field

[0001] [Corrected 11.03.2024 according to Rule 91] The present application relates to the field of graphics processing, and in particular to a graphics processing method, apparatus and computer-readable storage medium. Background Art

[0002] With the continuous development of applications such as machine vision and the Internet of Things, graphics processor chips are increasingly demanding in terms of area and performance, placing significant pressure on both internal and external memory. Complex graphics processing often requires multiple graphics processing modules within a graphics processor, each of which processes different parts of the image simultaneously.

[0003] In different scenarios, each graphics processing module requires different amounts of storage space depending on the sub-graphics it processes. In the prior art, when allocating storage areas to each graphics processing module, to ensure normal operation of each graphics processing module, each area is allocated the maximum storage space required in different scenarios, placing a significant demand on the overall storage space.

[0004] Summary of the Invention

[0005] [Corrected 11.03.2024 according to Rule 91] The object of the present application is to provide a graphics processing method, apparatus and computer-readable storage medium capable of reducing the overall requirement for the size of storage space.

[0006] In a first aspect, the present application provides a graphics processing method, which is applied to a graphics processing apparatus, wherein the graphics processing apparatus includes a graphics processing device and a memory, the graphics processing device includes multiple graphics processing modules, and the memory includes multiple storage units. The graphics processing method includes: obtaining a graphic to be processed, wherein the graphic to be processed includes multiple sub-graphics; using the multiple graphics processing modules to perform graphics processing on the multiple sub-graphics, each of the graphics processing modules processing at most one sub-graphic within one processing cycle; obtaining the storage space size required for each of the graphics processing modules to process the sub-graphics; and allocating a corresponding number of the storage units to each of the graphics processing modules according to the storage space size.

[0007] Compared with the prior art, in the graphics processing method provided in the embodiment of the present application, the graphics processing device divides the graphics to be processed into multiple sub-graphics when processing each graphic to be processed. Each graphics processing module in the graphics processing device processes one sub-graphic correspondingly. In this process, a corresponding number of storage units are allocated to each graphics processing module according to the size of the storage space required for each graphics processing module to process the corresponding sub-graphic. The storage units in the memory can be flexibly allocated without affecting the processing of the corresponding sub-graphic by each graphics processing module, thereby reducing the overall demand for the size of the storage space of the graphics processing device.

[0008] In an optional embodiment, allocating a corresponding number of storage units to each graphics processing module based on the storage space size includes: allocating a corresponding cache address to each graphics processing module based on the number of storage units; establishing a correspondence between the cache address and the storage unit number and the address within the unit, wherein the address within the unit is the storage address within the storage unit. Cache addresses are allocated based on the storage space requirements of each graphics processing module, and then the allocated cache addresses are converted to the storage unit number and the address within the storage unit, so that the storage units allocated to each graphics processing module can be distributed anywhere in the memory, thereby better utilizing the storage space in the memory.

[0009] In an optional embodiment, performing graphics processing on the multiple sub-graphics using the multiple graphics processing modules includes: obtaining write information and a corresponding write cache address; obtaining a target number and an address within the target unit corresponding to the write cache address based on the corresponding relationship; and writing the write information to the storage location corresponding to the target number and the address within the target unit. When writing the write information to the memory, the write information is written to the storage location corresponding to the target number and the address within the target unit, thereby more accurately writing the write information to storage units distributed throughout the memory.

[0010] In an optional embodiment, performing graphics processing on the multiple sub-graphics using the multiple graphics processing modules includes: obtaining a read cache address; obtaining a target number and an address within the target unit of the storage unit corresponding to the read cache address based on the corresponding relationship; and reading back target information from the storage location corresponding to the target number and the address within the target unit. When reading target information from the memory, the target information is read back from the storage location corresponding to the target number and the address within the target unit, thereby more accurately reading back target information from storage units distributed throughout the memory.

[0011] In an optional embodiment, after reading back the target information from the storage location corresponding to the target number and the target unit address, the graphics processing method further includes releasing the cache address corresponding to the target number and the target unit address. Releasing the corresponding cache address after the read operation allows the cache address to be reused, thereby improving the utilization efficiency of storage space in the memory.

[0012] In an optional embodiment, performing graphics processing on the multiple sub-graphics using the multiple graphics processing modules includes: releasing all storage units allocated to each graphics processing module after each graphics processing module completes graphics processing on the sub-graphics. Releasing all storage units after each frame of graphics processing is completed allows the storage units to be allocated and utilized again in subsequent graphics processing processes, thereby improving the utilization efficiency of storage space in the memory.

[0013] In an optional embodiment, there are multiple graphics to be processed, and the graphics processing method includes:

[0014] The size of the storage unit is determined according to the graphic formats and resolutions of the plurality of graphics to be processed. The size of the storage unit is determined according to all the plurality of graphics to be processed, so that the storage space in the memory can be better divided and utilized according to actual needs.

[0015] In a second aspect, the present application provides a graphics processing apparatus, comprising: a graphics processing device and a memory, the memory comprising a plurality of storage units; the graphics processing device comprising a graphics acquisition device, a plurality of graphics processing modules, and a storage unit allocation device, the graphics acquisition device being used to acquire a graphic to be processed, the graphic to be processed comprising a plurality of sub-graphics, the plurality of graphics processing modules being used to perform graphics processing on the plurality of sub-graphics, each of the graphics processing modules processing at most one sub-graphic within one processing cycle, the storage unit allocation device being used to acquire the size of the storage space required for each of the graphics processing modules to process the sub-graphics, and to allocate a corresponding number of the storage units to each of the graphics processing modules according to the size of the storage space.

[0016] In an optional embodiment, the graphics processing module further includes: a cache address management sub-device; the storage unit allocation device is used to allocate corresponding cache addresses to each of the graphics processing modules according to the number of the storage units, and the cache address management sub-device is used to establish a correspondence between the cache address and the number of the storage unit and the address within the unit, and the address within the unit is the storage address within the storage unit.

[0017] In an optional embodiment, the graphics processing module also includes: a cache write sub-device; the cache write sub-device is used to obtain write information and a corresponding write cache address, obtain the target number and the address within the target unit of the storage unit corresponding to the write cache address according to the corresponding relationship, and write the write information into the storage location corresponding to the target number and the address within the target unit.

[0018] In an optional embodiment, the graphics processing module further includes: a cache reading sub-device; the cache reading sub-device is used to obtain a read cache address, obtain the target number and the target unit internal address of the storage unit corresponding to the read cache address according to the corresponding relationship, and read back the target information from the storage location corresponding to the target number and the target unit internal address.

[0019] In an optional embodiment, after the cache reading sub-device reads back the target information from the storage location corresponding to the target number and the address within the target unit, the cache address management sub-device is further used to: release the cache address corresponding to the target number and the address within the target unit.

[0020] In an optional implementation, after each of the graphics processing modules completes graphics processing on the sub-graphic, the storage unit allocation device is further configured to release all storage units allocated to the graphics processing module.

[0021] In an optional embodiment, there are multiple graphics to be processed, and the storage unit allocation device is further used to determine the size of the storage unit according to the graphic formats and resolutions of the multiple graphics to be processed.

[0022] In a third aspect, the present application provides a computer-readable storage medium storing a computer program, wherein the computer program is executed by a processor to implement the graphics processing method described in any one of the aforementioned embodiments.

[0023] [Corrected 11.03.2024 according to Rule 91] Compared with the prior art, in the graphics processing method, device, and computer-readable storage medium provided in the embodiments of the present application, a corresponding number of storage units are allocated to each graphics processing module according to the size of the storage space required for each graphics processing module to process the corresponding sub-graphic. The storage units in the memory can be flexibly allocated without affecting the processing of the corresponding sub-graphic by each graphics processing module, thereby reducing the overall demand for the size of the storage space of the graphics processing device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0025] FIG1 is a flow chart of a graphics processing method provided in Example 1 of the present application;

[0026] FIG2 is a schematic diagram illustrating the correspondence between cache addresses, storage unit numbers, and addresses within the units in the graphics processing method provided in the first embodiment of the present application;

[0027] FIG3 is a schematic diagram of the structure of a graphics processing device provided in Example 2 of the present application;

[0028] FIG4 is a schematic diagram of the structure of a graphics processing device provided by another embodiment of the present application;

[0029] FIG5 is a flow chart of a graphics processing method exemplified in this application. DETAILED DESCRIPTION

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0031] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0032] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0033] In the description of this application, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product of the application is usually placed when in use. It is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation on this application.

[0034] In addition, the terms "first", "second", etc., if used, are merely used to distinguish and describe, and should not be understood as indicating or implying relative importance.

[0035] It should be noted that, in the absence of conflict, the features in the embodiments of this application can be combined with each other.

[0036] A first embodiment of the present application provides a graphics processing method, which is applied to a graphics processing apparatus. The graphics processing apparatus includes a graphics processing device and a memory. The graphics processing device includes multiple graphics processing modules, and the memory includes multiple storage units. The graphics processing method is shown in FIG1 and includes:

[0037] Step S101: obtaining a graphic to be processed, where the graphic to be processed includes a plurality of sub-graphics.

[0038] In this step, the graphic to be processed is an image that needs to be processed by the graphics processing device, which can be different images in different embodiments. For example, in some embodiments of the present application, the graphic to be processed can be an image frame in a video, or in some other embodiments of the present application, the graphic to be processed can also be an image in an image set during the model training process, etc. Specifically, in different application scenarios, the graphic to be processed can be different images.

[0039] In this step, each sub-graph is a portion of the graph to be processed, that is, a graph to be processed can be divided into multiple sub-graphs. In different embodiments of the present application, the sub-graphs can be different portions of the graph to be processed. For example, in some embodiments of the present application, the graph to be processed can be divided into regions, and the portion of the graph to be processed in each region is a sub-graph. In some other embodiments of the present application, the graph to be processed can be divided into layers, and each layer of the graph to be processed forms a sub-graph, etc. Specifically, in different application scenarios, the sub-graphs can be different portions of the graph to be processed.

[0040] In addition, in some embodiments of the present application, the method of dividing each graphic to be processed into sub-graphics may also be different. For example, in the application scenario of video images, continuous frame images are used as graphics to be processed, and each frame image can be divided into sub-graphics in a different way, which can be used flexibly according to actual needs.

[0041] In addition, in different embodiments of the present application, dividing the graphics to be processed into multiple sub-graphics can be performed in the graphics processing device provided in the embodiment of the present application, or the division can be completed in other devices. The graphics processing device provided in the embodiment of the present application can directly obtain each sub-graphic when obtaining the graphics to be processed, and can be used flexibly according to actual needs.

[0042] Step S102: using multiple graphics processing modules to perform graphics processing on multiple sub-graphics.

[0043] In this step, each graphics processing module processes at most one sub-graphic within a processing cycle. During the graphics processing of a to-be-processed graphic, sub-graphics can be assigned to multiple graphics processing modules based on the number of sub-graphics that actually need to be processed. For example, when the number of sub-graphics is less than the number of graphics processing modules, one sub-graphic can be assigned to some graphics processing modules for graphics processing, while no sub-graphics are assigned to other graphics processing modules. When the number of sub-graphics equals the number of graphics processing modules, one sub-graphic can be assigned to each graphics processing module for graphics processing. When the number of sub-graphics exceeds the number of graphics processing modules, one or more sub-graphics can be assigned to each graphics processing module for graphics processing. Regardless of how many sub-graphics are assigned to each graphics processing module for graphics processing, each graphics processing module processes only one sub-graphic within a processing cycle (i.e., within a sub-module processing process). When a graphics processing module is assigned more than one sub-graphic for graphics processing, it processes only one sub-graphic at a time, and only processes the remaining sub-graphics after the sub-graphic is processed.

[0044] Step S103: obtaining the storage space required by each graphics processing module for processing the sub-graphics.

[0045] In various embodiments of the present application, the amount of storage space required by each graphics processing module to process a sub-graphic can be obtained within the graphics processing device provided in the embodiments of the present application, for example, based on graphics parameters such as the sub-graphic size, resolution, and format. Alternatively, the amount of storage space required can be determined in another device, and the graphics processing device provided in the embodiments of the present application can directly obtain the amount of storage space required to process each sub-graphic when acquiring the graphics to be processed. This can be flexibly used based on actual needs.

[0046] Step S104: allocating a corresponding number of storage units to each graphics processing module according to the size of the storage space.

[0047] In this step, a storage unit is the smallest storage unit in the memory used to allocate storage space. That is, when allocating storage space, it can be allocated according to an integer number of storage units. For example, an integer number of storage units, such as 2, 3, 4, 5, or 6, can be allocated to a graphics processing module. When the storage space required by a graphics processing module is a non-integer multiple of the storage space size of a storage unit, a further method can be used to allocate storage units. For example, if the storage space required by a graphics processing module is 1.5 times the storage space size of a storage unit, two storage units can be allocated to the graphics processing module.

[0048] [Corrected 11.03.2024 according to Rule 91] The size of the storage unit can be divided according to actual needs. When the graphics processing device processes multiple related graphics to be processed at a time, such as performing graphics processing on each frame image in a video image, the size of the storage unit can be determined based on the graphic format, resolution, size, and other graphic data of all the graphics to be processed. For example, the storage unit size can be determined based on the greatest common divisor of the storage space required for each graphic to be processed, or the storage space size of a certain fraction of the greatest common divisor can be used as the storage unit size. In addition, in some other embodiments of the present application, the size of the storage unit can also be determined based on the sub-graphics division method, which can be flexibly used according to actual needs.

[0049] Furthermore, in some embodiments of the present application, the process of allocating a corresponding number of storage units to each graphics processing module may include allocating corresponding cache addresses to each graphics processing module based on the number of storage units allocated to each graphics processing module. For example, in some embodiments of the present application, if three storage units are allocated to graphics processing module A1, cache addresses 0 to 3A-1 may be allocated to graphics processing module A1; if four storage units are allocated to graphics processing module A2, cache addresses 3A to 7A-1 may be allocated to graphics processing module A2, and so on.

[0050] As shown in Figure 2, after assigning cache addresses to each graphics processing module, a correspondence can be established between cache addresses 0 to nA-1, storage unit numbers 0 to n-1, and intra-unit addresses 0 to A-1. The intra-unit address is the storage address within the storage unit. The storage unit number identifies the storage unit to which the cache address corresponds. The intra-unit storage address can be the storage address within each storage unit. A storage unit can include intra-unit storage addresses 0 to A-1, and A is the storage space size of the storage unit. Each cache address corresponds to {storage unit number, storage address within the storage unit}. For example, for a cache address of 2A-15, the corresponding correspondence is {1, A-15}, where 1 is the storage unit number and A-15 is the storage location of cache address A-15 within storage unit number 1. A cache address is allocated based on the storage space requirements of each graphics processing module. The allocated cache address is then converted into a storage unit number and an address within the storage unit. When searching for each cache address, the corresponding storage unit is found based on the corresponding storage unit number, and then the corresponding storage address is found based on the address within the unit. This allows the storage unit allocated to each graphics processing module to be distributed anywhere in the memory, eliminating the need to allocate a continuous storage area to each graphics processing module, thereby better utilizing the storage space in the memory.

[0051] For example, the process of using multiple graphics processing modules to perform graphics processing on multiple sub-graphics may include a write operation, that is, writing write information to the memory. During the write operation, the write information and the corresponding write buffer address are first obtained. The write buffer address is the address of the storage area to which the write information is written. Then, based on the corresponding relationship, the target number and the address within the target unit corresponding to the write buffer address are obtained, and the write information is written to the storage location corresponding to the target number and the address within the target unit. When writing the write information to the memory, the write information is written to the storage location corresponding to the target number and the address within the target unit, which more accurately writes the write information to the storage units distributed throughout the memory.

[0052] In some embodiments of the present application, the write information may be, for example, pixel information of a graphic to be processed. After the pixel information is written into a storage unit in a memory, a correspondence between the pixel information and a write cache address may be established.

[0053] Furthermore, the process of using multiple graphics processing modules to perform graphics processing on multiple sub-graphics may also include a read operation, namely, reading back target information stored in the memory from the memory. During the read operation, the read operation address, namely, the address where the target information is stored, is first obtained. Then, based on the corresponding relationship, the target number and the target unit address of the storage unit corresponding to the read cache address are obtained; and the target information is read back from the storage location corresponding to the target number and the target unit address. When reading the target information from the memory, the target information is read back from the storage location corresponding to the target number and the target unit address, thereby more accurately reading back the target information from storage units distributed throughout the memory.

[0054] In some embodiments of the present application, the target information may also be, for example, pixel information of a to-be-processed graphic. The read operation address may be obtained, for example, based on a correspondence between pixel information and a write cache address, by obtaining a cache address corresponding to the pixel information in the target information as the read operation address.

[0055] In some embodiments of the present application, after reading back the target information from the storage location corresponding to the target number and the target unit address, the method may further include: releasing the cache address corresponding to the target number and the target unit address. After the cache address is released, the released cache address can be reused to write data to the corresponding cache location during a write operation, thereby allowing the cache address to be reused and improving the utilization efficiency of the storage space in the memory.

[0056] Furthermore, in some embodiments of the present application, after each graphics processing module completes graphics processing on a sub-graphic, it releases all storage units allocated to the graphics processing module. For example, while graphics processing module A1 is processing sub-graphic B1, three storage units numbered 0, 1, and 2 are allocated to graphics processing module A1. After graphics processing module A1 completes processing sub-graphic B1, the three storage units numbered 0, 1, and 2 are released. The three storage units numbered 0, 1, and 2 can then be reallocated to other graphics processing modules or reallocated to graphics processing module A1 to process other sub-graphics. All storage units are released after each frame of graphics processing is completed, allowing subsequent graphics processing processes to allocate and utilize the storage units again, thereby improving the efficiency of memory space utilization.

[0057] In addition, in some embodiments of the present application, before performing a read operation or a write operation, the read operation and the write operation may be arbitrated, and the read operation and the write operation may be performed only after the arbitration passes.

[0058] Compared with the prior art, in the graphics processing method provided in the first embodiment of the present application, the graphics processing device divides the graphics to be processed into multiple sub-graphics when processing each graphic to be processed. Each graphics processing module in the graphics processing device processes one sub-graphic correspondingly. In this process, a corresponding number of storage units are allocated to each graphics processing module according to the size of the storage space required for each graphics processing module to process the corresponding sub-graphic. This allows the storage units in the memory to be flexibly allocated without affecting the processing of the corresponding sub-graphic by each graphics processing module, thereby reducing the overall demand for the size of the storage space by the graphics processing device.

[0059] In a specific embodiment of the present application, the number of images to be processed is 3. For example, the storage unit can be set to a storage particle, and the size of a storage particle is 32KB (a total of 32 storage locations, each storage location is 1KB in size). In this case, the processing flow includes:

[0060] Scenario 1, processing image 1: sub-graph 0 requires 2 memory cells, sub-graph 1 requires 2 memory cells, sub-graph 2 requires 1 memory cell, and sub-graph 3 requires 2 memory cells;

[0061] Scenario 2, processing image 2: sub-graph 0 requires 4 memory cells, sub-graph 1 requires 1 memory cell, sub-graph 2 requires 2 memory cells, and sub-graph 3 does not require any memory cells;

[0062] Scene 3, processing image 3: sub-graphic 0 requires 3 storage units, sub-graphic 1 requires 3 storage units, sub-graphic 2 requires 1 storage unit, and sub-graphic 3 requires 1 storage unit.

[0063] A single sub-graphic requires a maximum of 4 storage units, and a total of 8 storage units are required when processing image 3. According to the graphics processing method provided in the embodiment of the present application, the overall storage space only requires 8 storage units, while according to the graphics processing method of the prior art, each sub-graphic needs to be allocated 4 storage units, for a total of 16 storage units.

[0064] There are a total of 8 storage units of 32KB in size, for example, 8 storage particles of 32KB in size, numbered grp0, grp1, grp2, ..., grp7; their corresponding cache address ranges are 0-31 {0, 0-31}, 32-63 {1, 0-31}, 64-95 {2, 0-31}, ..., 224-255 {7, 0-31}. In the graphics processing method provided in the embodiment of the present application, when processing each to-be-processed graphic, the number of storage particles required to be allocated to each sub-graphic is determined, and then the corresponding number is allocated to the corresponding sub-graphic storage particle by the storage unit allocation device. For example, when processing to-be-processed graphic 1, sub-graphic 0 uses grp2 and grp3 for a total of 64KB of storage space, and sub-graphic 1 uses grp7, grp0, and grp1 for a total of 96KB of storage space. Based on the amount of space required for the current sub-graphic, as informed by the software, the cache address management sub-device allocates the corresponding storage space address. For example, if sub-graphic 1 is allocated 96KB of storage space, the cache address management sub-device will allocate addresses 0 to 95 corresponding to sub-graphic 1. 0 to 31 correspond to grp7 storage granules, 32 to 63 correspond to grp0 storage granules, and 64 to 95 correspond to grp1 storage granules. When the cache address management sub-device and cache read sub-device use the read cache address to read pixels, they convert the corresponding address into a target number (grpN storage granule number, 0 to 31) and a target unit address, and send it to the memory access management device. After receiving the target number and target unit address, the memory access management device converts the grpN storage granule number in the high-order bit of the address into an access signal for the corresponding storage granule. This access signal is then used to complete the data reading.

[0065] Processing Graphic 1 corresponds to Scene 1, and processing Graphic 2 corresponds to Scene 2. When processing Graphic 1, the storage unit allocation device allocates grp0 and grp1 to sub-graphic 0, grp2 and grp3 to sub-graphic 1, grp4 to sub-graphic 2, and grp5 and grp6 to sub-graphic 3. When processing Graphic 2, the storage unit allocation device allocates grp7, grp0, grp1, and grp2 to sub-graphic 0, grp3 to sub-graphic 1, grp4 and grp5 to sub-graphic 2, and no allocation to sub-graphic 3.

[0066] When processing sub-graph 0 in graph 1, 64KB of storage space is allocated. The cache address management sub-device outputs addresses 0-63. The cache write sub-device matches addresses 0-63 based on grp0 and grp1, issues a write access {0 / 1, 0-31}, and writes the corresponding info information to the cache address management sub-device. This info information contains the correspondence between pixel information and write cache addresses. This info information allows the cache read sub-device to match the cache address corresponding to the requested pixel coordinates as the read cache address. After matching the address, the cache read sub-device also matches the cache address based on the granule number and issues a read access {0 / 1, 0-31}. After reading back the cached pixel, the address is released to the cache address management sub-device, which in turn outputs the address to the cache write sub-device. This cycle of recycling continues until the processing of a pending graph is completed. The cache read sub-device releases the storage granule to the storage unit allocation device, notifying it that the cache space is no longer needed and can be reclaimed for grp0 and grp1. The cache read sub-device then determines the local access to the storage granule based on the high-order bits of the read and write addresses and converts them into the corresponding access sequence.

[0067] Processing sub-graph 0 of graph 2 requires allocating 128KB of storage space. Processing graph 1 leaves grp7 with 32KB of cache space. After processing sub-graph 0 of graph 1, grp0 and grp1 are released. However, the remaining space must be released after processing other sub-graphs of graph 1 before allocating 128KB of storage space to sub-graph 0 of graph 2. After waiting for allocation, sub-graph 0 begins operation, corresponding to storage granules grp7, grp0, grp1, and grp2. The cache address management sub-device outputs addresses 0 to 127. The cache write sub-device matches addresses 0 to 127 based on grp7, grp0, grp1, and grp2, issues a write access {7 / 0 / 1 / 2, 0 to 31}, and writes the corresponding info information to the cache address management sub-device, allowing the cache read sub-device to match the requested pixel information to the corresponding read cache address. After matching the address, the cache read sub-device also matches the cache address according to the granule number and issues a read access {7 / 0 / 1 / 2, 0-31}. After reading back the cached pixel information, the address is released to the cache address management sub-device, which then returns the address to the cache write sub-device. This cycle is repeated until all pixels in Graphic 2 are read. The cache read sub-device then releases the granules to the storage unit allocation device, informing it that the cache space is no longer needed and can be reclaimed: grp7, grp0, grp1, and grp2.

[0068] A second embodiment of the present application provides a graphics processing apparatus, as shown in FIG3 , including: a graphics processing device 100 and a memory 200 , wherein the memory 200 includes a plurality of storage units 201 .

[0069] The graphics processing device 100 includes a graphics acquisition device 101, multiple graphics processing modules 102, and a storage unit allocation device 103. The graphics acquisition device 101 is used to acquire a graphics to be processed, which includes multiple sub-graphics. The multiple graphics processing modules 102 are used to perform graphics processing on the multiple sub-graphics, and each graphics processing module 102 processes at most one sub-graphic. The storage unit allocation device 103 is used to acquire the storage space required by each graphics processing module 102 when processing a sub-graphic, and allocate a corresponding number of storage units to each graphics processing module according to the storage space size.

[0070] In some embodiments of the present application, the graphics processing device 100 may be a graphics processor, and the memory 200 may be an external storage device connected to the graphics processor. In other embodiments of the present application, the graphics processing device 100 may be part of the graphics processor, and the memory 200 may also be part of the graphics processor, that is, the memory 200 may be an internal cache unit in the graphics processor.

[0071] Compared with the prior art, in the graphics processing apparatus provided in the second embodiment of the present application, when the graphics processing device 100 processes each graphic to be processed, the graphics acquisition device 100 divides the graphic to be processed into multiple sub-graphics, and each graphics processing module 102 processes one sub-graphic accordingly. In this process, a corresponding number of storage units 201 are allocated to each graphics processing module 102 according to the size of the storage space required for each graphics processing module 102 to process the corresponding sub-graphic. The storage units 201 in the memory 200 can be flexibly allocated without affecting the processing of the corresponding sub-graphic by each graphics processing module 102, thereby reducing the overall demand for the size of the storage space of the graphics processing device 100.

[0072] In some other embodiments of the present application, as shown in FIG. 4 , the graphics processing module 102 includes a cache writing sub-device 1021 , a cache reading sub-device 1022 , and a cache address management sub-device 1023 .

[0073] The storage unit allocation device 103 allocates cache units to each graphics processing module 102 and also allocates cache addresses to each graphics processing module 102. The cache address management sub-device 1023 is used to establish a correspondence between the cache address and the storage unit number and the address within the unit. The address within the unit is the storage address within the storage unit.

[0074] The cache write sub-device 1021 is used to obtain write information and the corresponding write cache address. Based on the correspondence established by the cache address management sub-device 1023, it obtains the target number and address within the target unit of the storage unit corresponding to the write cache address, and writes the write information to the storage location corresponding to the target number and address within the target unit. After the information is written, the cache address management sub-device 1023 may, for example, include a first portion 1024 that notifies the cache read sub-device 1022 of the written information number, the storage location corresponding to the address within the unit, and the corresponding write cache address. The cache read sub-device 1022 can then read the information from the storage location where the written information has been stored.

[0075] The cache read sub-device 1022 is configured to obtain a read cache address, obtain the target number and the target unit address of the storage unit corresponding to the read cache address based on the corresponding relationship, and read back the target information from the storage location corresponding to the target number and the target unit address. After the cache read sub-device 1022 reads back the target information from the storage location corresponding to the target number and the target unit address, the cache address management sub-device 1023 may, for example, include a second portion 1025 to release the cache address corresponding to the target number and the target unit address, allowing the cache write sub-device 1021 to write data to the released cache location again.

[0076] By setting the cache address management sub-device 1023 to convert the allocated cache address with the number of the storage unit and the address in the storage unit, the storage unit allocated to each graphics processing module can be distributed in different locations in the memory, thereby better utilizing the storage space in the memory.

[0077] In addition, in some embodiments of the present application, the storage unit allocation device 103 is further configured to release all storage units allocated to each graphics processing module 102 after the graphics processing module 102 completes graphics processing on the sub-graphic.

[0078] In some embodiments of the present application, there are multiple graphics to be processed, and the storage unit allocation device 103 is further configured to determine the size of the storage unit according to the graphic formats and resolutions of the multiple graphics to be processed.

[0079] The following examples illustrate the graphics processing device and graphics processing method provided in the embodiments of the present application. It should be understood that the following examples are merely examples of a specific embodiment of the present application and do not constitute a limitation. As shown in FIG5 , the following examples may specifically include:

[0080] Before processing the graphics to be processed, the storage unit allocation process may be completed in advance, including: S501: Determine the size of the storage unit. Specifically, the storage unit allocation device 103 may determine the size of the storage unit according to the graphics format and resolution of the graphics to be processed.

[0081] S502 : Allocating storage units. Specifically, the storage unit allocation device 103 may allocate storage units to the cache address management sub-device 1023 .

[0082] During the process of processing the graphics to be processed, it is also possible to determine in real time whether the graphics to be processed are processed completely, specifically including: S503: determining whether the graphics to be processed are processed completely, if so, executing S504, if not, executing S506 or S512.

[0083] S504: The cache reading sub-device releases all storage units to the storage unit allocation device. The graphics to be processed have been processed, and the cache reading sub-device no longer needs storage units. All storage units can be released to the storage unit allocation device 103 for reallocation.

[0084] S505: The storage unit allocation device releases all storage units. The storage unit allocation device 103 may release all storage units to facilitate subsequent use of the storage units by other devices.

[0085] Processing the graphics to be processed may include data writing operations and data reading operations. The data writing operation may specifically include: S506 : allocating a write cache address. Specifically, the storage unit allocation device 103 may allocate a write cache address to the cache writing sub-device 1021 .

[0086] S507: Determine the target number and the address within the target unit of the storage unit corresponding to the write cache address. Specifically, the target number and the address within the target unit of the storage unit corresponding to the write cache address may be obtained according to the corresponding relationship established by the cache address management sub-device.

[0087] S508: Acquire writing information. Specifically, the writing information may be pixel information corresponding to the graphics to be processed, such as coordinate information.

[0088] S509: Polling arbitration. Specifically, polling arbitration determines whether a corresponding read operation or write operation can be performed. If the arbitration result is that the corresponding read operation or write operation can be performed, the cache write sub-device 1021 performs the corresponding write operation or the cache read sub-device 1022 performs the corresponding read operation. Conversely, if the arbitration result is that the corresponding read operation or write operation cannot be performed, the cache write sub-device 1021 suspends the corresponding write operation or the cache read sub-device 1022 suspends the corresponding read operation.

[0089] S510: Write the write information into the storage unit. Specifically, the cache write sub-device 1021 may write the write information into the storage location of the target unit address in the storage unit 201 with the target number corresponding to the write cache address.

[0090] S511: Determine the correspondence between the write cache address and the write information. Specifically, the write information may be, for example, pixel information of the image to be processed. After the pixel information is written into the storage unit 201 in the memory, a correspondence between the pixel information and the write cache address may be established. This correspondence between the pixel information and the write cache address may then be sent to the cache address management sub-device 1023.

[0091] The data reading operation may specifically include: S512: determining target information of the reading operation. Specifically, the target information may be, for example, pixel point information corresponding to the to-be-processed graphic, such as coordinate information.

[0092] S513: Determine a read operation address. Specifically, obtaining the read operation address may be, for example, obtaining a cache address corresponding to the pixel information in the target information as the read operation address based on a correspondence between the pixel information and the write cache address.

[0093] S514: Determine the storage unit and the address within the unit corresponding to the read operation.

[0094] S509: Polling arbitration. Specifically, polling arbitration determines whether a corresponding read operation or write operation can be performed. If the arbitration result is that the corresponding read operation or write operation can be performed, the cache write sub-device 1021 performs the corresponding write operation or the cache read sub-device 1022 performs the corresponding read operation. Conversely, if the arbitration result is that the corresponding read operation or write operation cannot be performed, the cache write sub-device 1021 suspends the corresponding write operation or the cache read sub-device 1022 suspends the corresponding read operation.

[0095] S515: Read the target information and release the corresponding read operation address.

[0096] The third embodiment of the present application relates to a computer-readable storage medium storing a computer program, which implements the above method embodiment when executed by a processor.

[0097] That is, those skilled in the art will understand that all or part of the steps in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a program, which is stored in a storage medium and includes a number of instructions for causing a device (which may be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps in the various embodiments of the present application. The aforementioned storage medium includes: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc., various media that can store program code.

[0098] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A graphics processing method, characterized in that: Applied to a graphics processing apparatus, the graphics processing apparatus comprises a graphics processing device and a memory, the graphics processing device comprises a plurality of graphics processing modules, the memory comprises a plurality of storage units, and the graphics processing method comprises: Acquire a to-be-processed graph, wherein the to-be-processed graph includes a plurality of sub-graphs; Using the multiple graphics processing modules to perform graphics processing on the multiple sub-graphics, each of the graphics processing modules processes at most one sub-graphic in one processing cycle; Acquire the storage space size required by each of the graphic processing modules for processing the sub-graphics; A corresponding number of storage units are allocated to each of the graphics processing modules according to the size of the storage space.

2. The graphics processing method according to claim 1, characterized in that: The allocating a corresponding number of storage units to each of the graphics processing modules according to the size of the storage space includes: Allocating corresponding cache addresses to each of the graphics processing modules according to the number of the storage units; A correspondence between the cache address and the serial number of the storage unit and the address within the unit is constructed, wherein the address within the unit is a storage address within the storage unit.

3. The graphics processing method according to claim 2, characterized in that: The using the multiple graphics processing modules to perform graphics processing on the multiple sub-graphics includes: Get write information and corresponding write cache address; Acquire the target number and the address in the target unit of the storage unit corresponding to the write cache address according to the corresponding relationship; The write information is written into a storage location corresponding to the target number and the address in the target unit.

4. The graphics processing method according to claim 2, characterized in that: The using the multiple graphics processing modules to perform graphics processing on the multiple sub-graphics includes: Get the read cache address; Acquire the target number and the address in the target unit of the storage unit corresponding to the read cache address according to the corresponding relationship; The target information is read back from the storage location corresponding to the target number and the address in the target unit.

5. The graphics processing method according to claim 4, characterized in that: After the target information is read back from the storage location corresponding to the target number and the address in the target unit, the graphics processing method further includes: The cache address corresponding to the target number and the address in the target unit is released.

6. The graphics processing method according to claim 1, characterized in that: The using the multiple graphics processing modules to perform graphics processing on the multiple sub-graphics includes: After each of the graphics processing modules completes the graphics processing on the sub-graphics, all storage units allocated to the graphics processing module are released.

7. The graphics processing method according to claim 1, characterized in that: The number of graphics to be processed is multiple, and the graphics processing method includes: The size of the storage unit is determined according to the graphic formats and resolutions of the plurality of graphics to be processed.

8. A graphics processing device, characterized in that: include: A graphics processing device and a memory, wherein the memory includes a plurality of storage units; The graphics processing device includes a graphics acquisition device, multiple graphics processing modules, and a storage unit allocation device. The graphics acquisition device is used to acquire a graphics to be processed, and the graphics to be processed include multiple sub-graphics. The multiple graphics processing modules are used to perform graphics processing on the multiple sub-graphics, and each of the graphics processing modules processes at most one sub-graphic in one processing cycle. The storage unit allocation device is used to acquire the storage space size required for each of the graphics processing modules to process the sub-graphics, and allocate a corresponding number of the storage units to each of the graphics processing modules according to the storage space size.

9. The graphics processing device according to claim 8, characterized in that: The graphics processing module further includes: a cache address management sub-device; The storage unit allocation device is used to allocate corresponding cache addresses to each of the graphics processing modules according to the number of the storage units, and the cache address management sub-device is used to establish a correspondence between the cache address and the number of the storage unit and the address within the unit, and the address within the unit is the storage address within the storage unit.

10. The graphics processing device according to claim 9, characterized in that: The graphics processing module further includes: a cache writing sub-device; The cache write sub-device is used to obtain write information and a corresponding write cache address, obtain the target number and the address within the target unit of the storage unit corresponding to the write cache address according to the corresponding relationship, and write the write information into the storage location corresponding to the target number and the address within the target unit.

11. The graphics processing device according to claim 9, characterized in that: The graphics processing module further includes: a cache reading sub-device; The cache reading sub-device is used to obtain a read cache address, obtain a target number and an address in the target unit corresponding to the read cache address according to the corresponding relationship, and read back target information from a storage location corresponding to the target number and the address in the target unit.

12. The graphics processing device according to claim 11, characterized in that: After the cache reading sub-device reads back the target information from the storage location corresponding to the target number and the address in the target unit, the cache address management sub-device is further used to: release the cache address corresponding to the target number and the address in the target unit.

13. The graphics processing device according to claim 8, characterized in that: After each of the graphics processing modules completes the graphics processing on the sub-graphics, the storage unit allocation device is further used to: release all storage units allocated to the graphics processing modules.

14. The graphics processing device according to claim 8, characterized in that: The number of the graphics to be processed is multiple, and the storage unit allocation device is further used to: determine the size of the storage unit according to the graphic formats and resolutions of the multiple graphics to be processed.

15. A computer-readable storage medium storing a computer program, characterized in that: The computer program is executed by a processor to implement the graphics processing method according to any one of claims 1 to 7.

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