Array substrate and display device

Abstract

An array substrate is provided. The array substrate comprises a plurality of pixel driving circuits; wherein each pixel driving circuit (PDC) in the plurality of pixel driving circuits comprises a driving transistor (Td), a first light emitting control transistor (T3) and a third reset transistor (Tr3); active layers (ACTd, ACT3 and ACTr3) of the driving transistor (Td), the first light-emitting control transistor (T3) and the third reset transistor (Tr3) are located on a first semiconductor material layer (SML1); a first electrode of the driving transistor (Td), a second electrode of the first light-emitting control transistor (T3) and a second electrode (D3) of the third reset transistor (Tr3) are located on the first semiconductor material layer (SML1); the first electrode (Sd) of the driving transistor (Td), the second electrode (D3) of the first light emission control transistor (T3), and the second electrode (Dr) of the third reset transistor (Tr3) are parts of an integral structure; and the first electrode (Sd) of the driving transistor (Td), the second electrode (D3) of the first light emission control transistor (T3), and the second electrode (Dr3) of the third reset transistor (Tr3) are connected to each other through one or more portions of the first semiconductor material layer (SML1).

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] Organic light emitting diode (OLED) display is one of the hot spots in the field of flat panel display research today. OLED is driven by a driving current that needs to be kept constant to control the brightness. The OLED display panel includes a plurality of pixel units configured with a pixel driving circuit arranged in multiple rows and columns. Summary of the invention

[0003] In a first aspect, the present disclosure provides an array substrate, comprising a plurality of pixel driving circuits; wherein each of the plurality of pixel driving circuits comprises a driving transistor, a first light-emitting control transistor and a third reset transistor; the active layers of the driving transistor, the first light-emitting control transistor and the third reset transistor are located in a first semiconductor material layer; the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor and the second electrode of the third reset transistor are located in the first semiconductor material layer; the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor and the second electrode of the third reset transistor are part of an overall structure; and the first electrode of the driving transistor, the second electrode of the first light-emitting control transistor and the second electrode of the third reset transistor are connected to each other through one or more parts of the first semiconductor material layer.

[0004] In some embodiments of the present disclosure, the array substrate also includes: a first light-emitting control electrode pad, which is located on the first semiconductor material layer; and a plurality of light-emitting control signal lines, which are located on a side of the first light-emitting control electrode pad away from the first semiconductor material layer; wherein the first light-emitting control electrode pad includes a gate of the first light-emitting control transistor; and each of the plurality of light-emitting control signal lines is connected to the first light-emitting control electrode pad through a via.

[0005] In some embodiments of the present disclosure, the array substrate also includes: a second light-emitting control electrode pad, which is located on the first semiconductor material layer; and a plurality of light-emitting control signal lines, which are located on a side of the second light-emitting control electrode pad away from the first semiconductor material layer; wherein each pixel driving circuit also includes a second light-emitting control transistor; the second light-emitting control electrode pad includes a gate of the second light-emitting control transistor; and each of the plurality of light-emitting control signal lines is connected to the second light-emitting control electrode pad through a via.

[0006] In some embodiments of the present disclosure, each pixel driving circuit also includes a storage capacitor, and the storage capacitor includes a first capacitor electrode and a second capacitor electrode; the first light-emitting control electrode pad and the first capacitor electrode are located in a first gate metal layer; the second capacitor electrode is located in a second gate metal layer, and the second gate metal layer is located on a side of the first gate metal layer away from the first semiconductor material layer; the multiple light-emitting control signal lines are located in a first signal line layer, and the first signal line layer is located on a side of the second gate metal layer away from the first gate metal layer.

[0007] In some embodiments of the present disclosure, each pixel driving circuit also includes a compensation transistor; the active layer of the compensation transistor is located in a second semiconductor material layer, and the second semiconductor material layer is located on a side of the second gate metal layer away from the first gate metal layer; at least a portion of the gate of the compensation transistor is located in a third gate metal layer, and the third gate metal layer is located on a side of the second semiconductor material layer away from the second gate metal layer; and the multiple light-emitting control signal lines are located in the first signal line layer, and the first signal line layer is located on a side of the third gate metal layer away from the second semiconductor material layer.

[0008] In some embodiments of the present disclosure, the array substrate also includes: a first voltage connection pad and a plurality of first voltage supply lines; wherein the active layer of the first light emitting control transistor, the first voltage connection pad and the plurality of first voltage supply lines are located at three different layers; and a corresponding first voltage supply line among the plurality of first voltage supply lines is connected to the first voltage connection pad, and the first voltage connection pad is connected to the first electrode of the first light emitting control transistor.

[0009] In some embodiments of the present disclosure, an orthographic projection of the second electrode of the third reset transistor on the substrate at least partially overlaps with an orthographic projection of the first voltage connection pad on the substrate.

[0010] In some embodiments of the present disclosure, the array substrate also includes: a plurality of light-emitting control signal lines; wherein each of the plurality of light-emitting control signal lines is configured to provide a light-emitting control signal to the gate of the first light-emitting control transistor; and the first voltage connection pad is located on the same layer as the plurality of light-emitting control signal lines.

[0011] In some embodiments of the present disclosure, the first voltage connection pad is connected to the first electrodes of the first light emission control transistors in two adjacent pixel driving circuits located in the same row.

[0012] In some embodiments of the present disclosure, each of the first voltage supply lines includes a main body and a plurality of extension portions extending in a direction away from the main body; each of the plurality of extension portions is connected to the first voltage connection pad; and the first voltage connection pad is connected to the first electrode of the first light emitting control transistor.

[0013] In some embodiments of the present disclosure, each pixel driving circuit also includes a compensation transistor; the active layer of the compensation transistor is located in a second semiconductor material layer, and the second semiconductor material layer is located on a side of the first semiconductor material layer away from the substrate; the orthographic projection of the main body on the substrate substantially covers the orthographic projection of the active layer of the compensation transistor on the substrate.

[0014] In some embodiments of the present disclosure, an orthographic projection of the body on the base substrate substantially covers an orthographic projection of the first electrode of the compensation transistor, the active layer, and the second electrode on the base substrate.

[0015] In some embodiments of the present disclosure, each pixel driving circuit also includes a first reset transistor and a second reset transistor; wherein, the array substrate also includes: a plurality of third reset signal lines, which are configured to provide a third reset signal to the first electrode of the third reset transistor in the plurality of pixel driving circuits; and a plurality of first reset signal lines, which are configured to provide a first reset signal to the first electrode of the first reset transistor in the plurality of pixel driving circuits, and / or a plurality of second reset signal lines, which are configured to provide a second reset signal to the first electrode of the second reset transistor in the plurality of pixel driving circuits; wherein the plurality of first reset signal lines, the plurality of second reset signal lines and the plurality of third reset signal lines extend along a direction substantially parallel to the first direction.

[0016] In some embodiments of the present disclosure, the array substrate also includes: a plurality of third reset signal lines, which are configured to provide a third reset signal to the first electrode of the third reset transistor in the plurality of pixel driving circuits; a plurality of first low-voltage supply lines; a plurality of fourth reset signal lines; a plurality of fifth reset signal lines; a plurality of sixth reset signal lines; and a plurality of second low-voltage supply lines; wherein the plurality of third reset signal lines and the plurality of first low-voltage signal lines extend in a direction substantially parallel to the first direction; the plurality of fourth reset signal lines, the plurality of fifth reset signal lines, the plurality of sixth reset signal lines and the plurality of second low-voltage supply lines extend in a direction substantially parallel to the second direction; the second direction is different from the first direction; and the plurality of fourth reset signal lines, the plurality of fifth reset signal lines, the plurality of sixth reset signal lines and the plurality of second low-voltage supply lines are located on the same layer, and are located on the side of the plurality of third reset signal lines and the plurality of first low-voltage signal lines away from the first semiconductor material layer.

[0017] In some embodiments of the present disclosure, the plurality of fourth reset signal lines, the plurality of fifth reset signal lines, the plurality of sixth reset signal lines, and the plurality of second low voltage supply lines are alternately arranged.

[0018] In some embodiments of the present disclosure, the plurality of pixel driving circuits are arranged into J columns, where J is a positive integer; the J columns include the (8j-7)th column among the J columns, the (8j-6)th column among the J columns, the (8j-5)th column among the J columns, the (8j-4)th column among the J columns, the (8j-3)th column among the J columns, the (8j-2)th column among the J columns, the (8j-1)th column among the J columns, and the (8j)th column among the J columns, where j is a positive integer, 1≤j≤(J / 8); a corresponding fourth reset signal line among the plurality of fourth reset signal lines, a corresponding fifth reset signal line among the plurality of fifth reset signal lines, a corresponding sixth reset signal line among the plurality of sixth reset signal lines, and a corresponding second low voltage supply line among the plurality of second low voltage supply lines. One of the corresponding fourth reset signal line, the corresponding fifth reset signal line, the corresponding sixth reset signal line and the corresponding second low-voltage supply line is located between the (8j-7)th column and the (8j-6)th column; another one of the corresponding fourth reset signal line, the corresponding fifth reset signal line, the corresponding sixth reset signal line and the corresponding second low-voltage supply line is located between the (8j-5)th column and the (8j-4)th column; another one of the corresponding fourth reset signal line, the corresponding fifth reset signal line, the corresponding sixth reset signal line and the corresponding second low-voltage supply line is located between the (8j-3)th column and the (8j-2)th column; and another one of the corresponding fourth reset signal line, the corresponding fifth reset signal line, the corresponding sixth reset signal line and the corresponding second low-voltage supply line is located between the (8j-1)th column and the (8j)th column.

[0019] In some embodiments of the present disclosure, the array substrate further includes: a first corresponding anode, a second corresponding anode, a third corresponding anode and a fourth corresponding anode; wherein the first corresponding anode is the anode of a sub-pixel of a first color, the second corresponding anode is the anode of a sub-pixel of a second color, and the third corresponding anode and the fourth corresponding anode are anodes of two sub-pixels of a third color; the orthographic projection of the third corresponding anode on the substrate substrate at least partially overlaps with the orthographic projections of two adjacent second voltage supply lines among the multiple second voltage supply lines on the substrate substrate, and at least partially overlaps with the orthographic projections of a corresponding fourth reset signal line, a corresponding fifth reset signal line, a corresponding sixth reset signal line and one of the corresponding second low voltage supply lines on the substrate substrate; and the orthographic projection of the fourth corresponding anode on the substrate substrate at least partially overlaps with the orthographic projections of two adjacent second voltage supply lines among the multiple second voltage supply lines on the substrate substrate, and at least partially overlaps with the orthographic projections of a corresponding fourth reset signal line, a corresponding fifth reset signal line, a corresponding sixth reset signal line and one of the corresponding second low voltage supply lines on the substrate substrate.

[0020] In some embodiments of the present disclosure, an orthographic projection of at least one of the first corresponding anode, the second corresponding anode, the third corresponding anode, or the fourth corresponding anode on the substrate at least partially overlaps with an orthographic projection of the second electrode of the third reset transistor on the substrate.

[0021] In a second aspect, the present disclosure provides an array substrate comprising a plurality of pixel driving circuits: wherein each of the plurality of pixel driving circuits comprises a second node connection line, a first light emission control transistor, a third reset transistor and a second node connection line; the second node connection line is connected to a second electrode of the first light emission control transistor and to a second electrode of the third reset transistor; and the second node connection line is located on the same layer as an active layer of the first light emission control transistor and the third reset transistor.

[0022] In some embodiments of the present disclosure, the array substrate also includes a plurality of light-emitting control signal lines; wherein each of the plurality of light-emitting control signal lines is configured to provide a control signal to the gate of the first light-emitting control transistor; and the plurality of light-emitting control signal lines are separated from the second node connection line by at least three insulating layers.

[0023] In some embodiments of the present disclosure, each pixel driving circuit also includes a first node connection line, a storage capacitor and a compensation transistor; the first node connection line is connected to the first capacitor electrode of the storage capacitor and to the first electrode of the compensation transistor; and the multiple light-emitting control signal lines and the first node connection line are located on the same layer.

[0024] In a third aspect, the present disclosure provides a display device, comprising the array substrate and one or more integrated circuits connected to the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0026] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0027] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0028] Figure 2B is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0029] Figure 3Ais a schematic diagram showing the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure.

[0030] Figure 3B It is shown Figure 3A Schematic diagram of the structure of the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the second semiconductor material layer, the third gate metal layer and the first signal line layer in the array substrate shown in FIG.

[0031] Figure 3C It is shown Figure 3A Schematic diagram of the arrangement of the pixel driving circuit of the array substrate shown in .

[0032] Figure 3D It is shown Figure 3A A schematic diagram of the structure of the first semiconductor material layer in the array substrate is shown in FIG.

[0033] Figure 3E It is shown Figure 3A A schematic diagram of the structure of the first gate metal layer in the array substrate is shown in FIG.

[0034] Figure 3F It is shown Figure 3A A schematic diagram of the structure of the second gate metal layer in the array substrate is shown in FIG.

[0035] Figure 3G It is shown Figure 3A A schematic diagram of the structure of the second semiconductor material layer in the array substrate is shown in FIG.

[0036] Figure 3H It is shown Figure 3A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in FIG.

[0037] Fig. 3I It is shown Figure 3A Schematic diagram of the structure of the passivation layer of the array substrate shown in FIG.

[0038] Figure 3J It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in the array substrate is shown in FIG.

[0039] Figure 3K It is shown Figure 3A A schematic diagram of the structure of the first planarization layer in the array substrate is shown in FIG.

[0040] Figure 3L It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate is shown in FIG.

[0041] Figure 3M It is shown Figure 3A Schematic diagram of the structure of the second planarization layer in the array substrate shown in FIG.

[0042] Figure 3N It is shown Figure 3A A schematic diagram of the structure of the third signal line layer in the array substrate is shown in FIG.

[0043] Fig.3O It is shown Figure 3A Schematic diagram of the structure of the anode layer in the array substrate shown in FIG.

[0044] Figure 4A is along Figure 3A Cross-sectional view along line A-A'.

[0045] Figure 4B is along Figure 3A Cross-sectional view along line BB'.

[0046] Figure 5 The diagram shows a voltage supply path in an array substrate according to some embodiments of the present disclosure.

[0047] Figure 6 is a schematic diagram showing the structure of corresponding first voltage supply lines in an array substrate according to some embodiments of the present disclosure.

[0048] Figure 7 It is shown Figure 3A A schematic diagram of the structure of the second semiconductor material layer and the corresponding first voltage supply line in the array substrate is shown.

[0049] Fig. 8A is a schematic diagram showing the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure.

[0050] Figure 8B It is shown Fig. 8A Schematic diagram of the arrangement of pixel driving circuits in an array substrate shown in FIG.

[0051] Figure 8C It is shown Fig. 8A A schematic diagram of the structure of the first semiconductor material layer in the array substrate is shown in FIG.

[0052] Fig.8D It is shown Fig. 8A A schematic diagram of the structure of the first gate metal layer in the array substrate is shown in FIG.

[0053] Fig. 8E It is shown Fig. 8A A schematic diagram of the structure of the second gate metal layer in the array substrate is shown in FIG.

[0054] Figure 8F It is shown Fig. 8A A schematic diagram of the structure of the second semiconductor material layer in the array substrate is shown in FIG.

[0055] Figure 8G It is shown Fig. 8A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in FIG.

[0056] Figure 8H It is shown Fig. 8A Schematic diagram of the structure of the passivation layer in the array substrate shown in FIG.

[0057] Figure 8I It is shown Fig. 8A A schematic diagram of the structure of the first signal line layer in the array substrate is shown in FIG.

[0058] Figure 8J It is shown Fig. 8A A schematic diagram of the structure of the first planarization layer in the array substrate is shown in FIG.

[0059] Figure 8K It is shown Fig. 8A A schematic diagram of the structure of the second signal line layer in the array substrate is shown in FIG.

[0060] Figure 8L It is shown Fig. 8A Schematic diagram of the structure of the second planarization layer in the array substrate shown in FIG.

[0061] Figure 8M It is shown Fig. 8A A schematic diagram of the structure of the third signal line layer in the array substrate is shown in FIG.

[0062] Figure 8N It is shown Fig. 8A Schematic diagram of the structure of the anode layer in the array substrate shown in FIG.

[0063] Fig.8O It is shown Fig. 8A Schematic diagram of the structure of the third signal line layer and the anode layer in the array substrate shown in FIG.

[0064] Figure 8P It is shown Fig. 8A Schematic diagram of the structure of the first semiconductor material layer and the anode layer in the array substrate shown in FIG.

[0065] Fig. 9A A first interconnected reset signal network is shown in accordance with some embodiments of the present disclosure.

[0066] Fig. 9B A first interconnected reset signal network is shown in accordance with some embodiments of the present disclosure.

[0067] Fig. 10AA second interconnected reset signal network is shown in accordance with some embodiments of the present disclosure.

[0068] Fig. 10B A second interconnected reset signal network is shown in accordance with some embodiments of the present disclosure.

[0069] Fig.11 A third interconnected reset signal network is shown in accordance with some embodiments of the present disclosure.

[0070] Fig.12 An interconnected low voltage supply network is shown in accordance with some embodiments of the present disclosure.

[0071] Fig.13 It is shown Figure 3A A schematic diagram of the structure of the first semiconductor material layer in the array substrate is shown in FIG. DETAILED DESCRIPTION

[0072] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0073] The present disclosure provides an array substrate and a display device, which substantially overcomes one or more problems caused by the limitations and shortcomings of the prior art. In one aspect, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of pixel drive circuits. Optionally, each of the plurality of pixel drive circuits includes a drive transistor, a data write transistor, a first light emission control transistor, and a third reset transistor. Optionally, the active layer of the drive transistor, the data write transistor, the first light emission control transistor, and the third reset transistor is located in the first semiconductor material layer. Optionally, the second electrode of the data write transistor, the first electrode of the drive transistor, the second electrode of the first light emission control transistor, and the second electrode of the third reset transistor are located in the first semiconductor material layer. Optionally, the second electrode of the data write transistor, the first electrode of the drive transistor, the second electrode of the first light emission control transistor, and the second electrode of the third reset transistor are parts of the overall structure. Optionally, the second electrode of the data write transistor, the first electrode of the drive transistor, the second electrode of the first light emission control transistor, and the second electrode of the third reset transistor are connected to each other through one or more parts of the first semiconductor material layer.

[0074] Various suitable pixel driving circuits can be used in the array substrate described in the present disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C and 8T2C. In some embodiments, each of the plurality of pixel driving circuits is an 8T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in the present disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0075] Figure 1 is a plan view of an array substrate in some embodiments of the present disclosure. Figure 1 , the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes an electronic component, for example, a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes a plurality of first gate lines (e.g., a corresponding first gate line GL1), a plurality of second gate lines (e.g., a corresponding second gate line GL2), a plurality of data lines (e.g., a corresponding data line DL), a plurality of high-voltage supply lines (e.g., a corresponding high-voltage supply line Vdd) and a plurality of low-voltage supply lines (e.g., a corresponding low-voltage supply line Vss). Each sub-pixel Sp emits light driven by a corresponding pixel driving circuit PDC. In one example, a high-voltage signal (e.g., a VDD signal) is input to a corresponding pixel driving circuit PDC connected to an anode of a light-emitting element through a corresponding high-voltage supply line Vdd in a plurality of high-voltage supply lines; a low-voltage signal (e.g., a VSS signal) is input to a cathode of a light-emitting element through a low-voltage supply line. The voltage difference between the high-voltage signal (e.g., a VDD signal) and the low-voltage signal (e.g., a VSS signal) is a driving voltage ΔV, which drives the light-emitting element to emit light.

[0076] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2AIn some embodiments, the pixel driving circuit includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a second reset transistor Tr2 having a gate connected to a corresponding second reset control signal line rst2 among a plurality of second reset control signal lines, a first electrode connected to a corresponding second reset signal line Vint2 among a plurality of second reset signal lines, and a second electrode connected to a second electrode of the driving transistor Td; a first transistor T1 having a gate connected to a corresponding first gate line GL1 among a plurality of first gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to the first electrode of the driving transistor Td; a third reset transistor Tr3 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding third reset signal line Vint3 among a plurality of third reset signal lines, and a second electrode connected to the first electrode of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding second gate line GL1 among a plurality of second gate lines, a first electrode connected to a corresponding data line DL among a plurality of data lines, and a second electrode connected to the first electrode of the driving transistor Td. A first capacitor electrode Ce1 connected to a storage capacitor Cst and a gate of a driving transistor Td, and a second electrode connected to a second electrode of the driving transistor Td; a third transistor T3 having a gate connected to a corresponding light emitting control signal line em among a plurality of light emitting control signal lines, a first electrode connected to a corresponding voltage supply line Vdd among a plurality of voltage supply lines, and a second electrode connected to a first electrode of the driving transistor Td and a second electrode of the first transistor T1; a fourth transistor T4 having a gate connected to a corresponding light emitting control signal line em among a plurality of light emitting control signal lines, a first electrode connected to the driving transistor Td and a second electrode of the second transistor T2, and a second electrode connected to an anode of the light emitting element LE; and a first reset transistor Tr1 having a gate connected to a corresponding first reset control signal line rst1 among a plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 among a plurality of first reset signal lines, and a second electrode connected to a second electrode of the fourth transistor T4 and an anode of the light emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the first electrode of the third transistor T3.

[0077] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a first transistor T1), a compensation transistor (e.g., a second transistor T2), two light emitting control transistors (e.g., a third transistor T3 and a fourth transistor T4), and three reset transistors (e.g., a first reset transistor Tr1, a second reset transistor Tr2, and a third reset transistor Tr3).

[0078] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, the first terminal and the second terminal being connected to an active layer of the transistor. The direction of the current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Therefore, depending on the direction of the current flowing through the transistor, in one example, the first electrode is configured to receive an input signal, and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal, and the first electrode is configured to output an output signal.

[0079] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3 and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1 and the first electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, the second electrode of the third reset transistor Tr3, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light emitting element LE.

[0080] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels include a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, the corresponding pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a S1-S2-S3 format repeating array, wherein S1 represents the corresponding first sub-pixel, S2 represents the corresponding second sub-pixel, and S3 represents the corresponding third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, and C3 represents the corresponding third sub-pixel of the third color. In another example, the C1-C2-C3 format is an RGB format, wherein the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, and the corresponding third sub-pixel is a blue sub-pixel.

[0081] In another example, the array of multiple sub-pixels includes a repeating array of the S1-S2-S3-S4 format, wherein S1 represents the corresponding first sub-pixel, S2 represents the corresponding second sub-pixel, S3 represents the corresponding third sub-pixel, and S4 represents the corresponding fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C4 represents the corresponding fourth sub-pixel of the fourth color. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2' format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C2' represents the corresponding fourth sub-pixel of the second color. In another example, the C1-C2-C3-C2′ format is an RGBG format, wherein the corresponding first subpixel is a red subpixel, the corresponding second subpixel is a green subpixel, the corresponding third subpixel is a blue subpixel, and the corresponding fourth subpixel is a green subpixel.

[0082] In some embodiments, the minimum repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the first sub-pixel, the second sub-pixel, and the third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, a driving transistor Td, and a storage capacitor Cst.

[0083] In an alternative embodiment, the minimum repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the respective first sub-pixels, the respective second sub-pixels, the respective third sub-pixels, and the respective fourth sub-pixels includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, a driving transistor Td, and a storage capacitor Cst.

[0084] The present disclosure may be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. Figure 2A, the second transistor T2 is an n-type transistor, such as a metal oxide transistor, and the other transistors are p-type transistors, such as polysilicon transistors. For a p-type transistor, a valid control signal (e.g., a turn-on control signal) is a low voltage signal, and an invalid control signal (e.g., a turn-off control signal) is a high voltage signal. For an n-type transistor, a valid control signal (e.g., a turn-on control signal) is a high voltage signal, and an invalid control signal (e.g., a turn-off control signal) is a low voltage signal.

[0085] Figure 2B is a timing diagram showing the operation of the pixel driving circuit in some embodiments according to the present disclosure. Figure 2A and Figure 2B During a frame of image, the operation of the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2 and a light emitting sub-stage t3. In the initial sub-stage t0, a cut-off reset control signal is provided to the gate of the second reset transistor Tr2 through the corresponding second reset control signal line rst2 to cut off the second reset transistor Tr2. A cut-off reset control signal is provided to the gate of the first reset transistor Tr1 and the gate of the third reset transistor Tr3 through the corresponding first reset control signal line rst1 to cut off the first reset transistor Tr1 and the third reset transistor Tr3. In the initial sub-stage t0, the corresponding first gate line GL1 is provided with a cut-off signal, so the first transistor T1 is cut off.

[0086] In the reset sub-phase t1, the on-reset control signal is provided to the gate of the first reset transistor Tr1 through the corresponding first reset control signal line rst1 to turn on the first reset transistor Tr1; the initialization voltage signal from the corresponding first reset signal line Vint1 is allowed to be transferred from the first electrode of the first reset transistor Tr1 to the second electrode of the first reset transistor Tr1; and to the node N4 in turn. The anode of the light-emitting element LE is initialized. The on-reset control signal is provided to the gate of the third reset transistor Tr3 through the corresponding first reset control signal line rst1 to turn on the third reset transistor Tr3; the initialization voltage signal from the corresponding third reset signal line Vint3 is allowed to be transferred from the first electrode of the third reset transistor Tr3 to the second electrode of the third reset transistor Tr3; and to the node N2 in turn. Node N2 is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding voltage supply line Vdd. As the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 increases, the first capacitor electrode Ce1 is charged in the reset sub-phase t1. In the reset sub-phase t1, the corresponding first gate line GL1 is provided with a cut-off signal, so the first transistor T1 is cut off. The corresponding light emitting control signal line em is supplied with a high voltage signal to turn off the third transistor T3 and the fourth transistor T4.

[0087] In the data writing sub-phase t2, a turn-on reset control signal is provided to the gate of the second reset transistor Tr2 through the second reset control signal line rst2 to turn on the second reset transistor Tr2; the initialization voltage signal from the corresponding second reset signal line Vint2 is allowed to be transmitted from the first electrode of the second reset transistor Tr2 to the second electrode of the second reset transistor Tr2, and then to the second electrode of the driving transistor Td. The second electrode of the driving transistor Td is initialized.

[0088] In the data writing sub-stage t2, the cut-off reset control signal is again provided to the gate of the first reset transistor Tr1 and the gate of the third reset transistor Tr3 through the corresponding first reset control signal line rst1 to cut off the first reset transistor Tr1 and the third reset transistor Tr3. The corresponding first gate line GL1 and the corresponding second gate line GL2 are respectively provided with a turn-on signal, so the first transistor T1 and the second transistor T2 are turned on. The first electrode of the driving transistor Td is connected to the second electrode of the second transistor T2. The gate of the driving transistor Td is electrically connected to the first electrode of the second transistor T2. Since the second transistor T2 is turned on in the data writing sub-stage t2, the gate of the driving transistor Td is connected and short-circuited with the second electrode, and only the PN junction between the gate of the driving transistor Td and the first electrode is effective, so that the driving transistor Td is in a diode connection mode. The first transistor T1 is turned on in the data writing sub-stage t2. The data voltage signal transmitted through the corresponding data line DL is received by the first electrode of the first transistor T1 and sequentially transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the first transistor T1. The node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate of the driving transistor Td and the first electrode is effective, in the data writing sub-phase t2, the voltage level of the N1 node gradually rises to (Vdata+Vth), where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 is reduced to a relatively small value, the storage capacitor Cst is discharged. The corresponding light emitting control signal line em is provided with a high voltage signal to turn off the third transistor T3 and the fourth transistor T4.

[0089] In the light-emitting sub-stage t3, a cut-off reset control signal is provided to the gate of the second reset transistor Tr2 through the corresponding second reset control signal line rst2 to cut off the second reset transistor Tr2. A cut-off reset control signal is provided to the gate of the first reset transistor Tr1 and the gate of the third reset transistor Tr3 through the corresponding first reset control signal line rst1 to cut off the first reset transistor Tr1 and the third reset transistor Tr3. The corresponding first gate line GL1 and the corresponding second gate line GL2 are respectively provided with a cut-off signal, and the first transistor T1 and the second transistor T2 are cut off. The corresponding light-emitting control signal line em is provided with a low voltage signal to turn on the third transistor T3 and the fourth transistor T4. In the light-emitting sub-stage t3, the voltage level of the node N1 is maintained at (Vdata+Vth), and the driving transistor Td is turned on by the voltage level and works in the saturation region. A path is formed, which passes through the third transistor T3, the driving transistor Td, and the fourth transistor T4 to the light-emitting element LE. The driving transistor Td generates a driving current for driving the light-emitting element LE to emit light. The voltage level at the node N3 connected to the second electrode of the driving transistor Td is equal to the light emitting voltage of the light emitting element LE.

[0090] Figure 3A is a schematic diagram showing the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. Figure 3B It is shown Figure 3A Schematic diagram of the structure of the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the second semiconductor material layer, the third gate metal layer and the first signal line layer in the array substrate shown in FIG. Figure 3C It is shown Figure 3A Schematic diagram of the arrangement of the pixel driving circuit of the array substrate shown in . Figures 3A to 3C A portion of the array substrate having two adjacent pixel driving circuits (including PDC1 and PDC2) is shown.

[0091] Figure 3D It is shown Figure 3A A schematic diagram of the structure of the first semiconductor material layer in the array substrate is shown in FIG. Figure 3E It is shown Figure 3A A schematic diagram of the structure of the first gate metal layer in the array substrate is shown in FIG. Figure 3F It is shown Figure 3A A schematic diagram of the structure of the second gate metal layer in the array substrate is shown in FIG. Figure 3G It is shown Figure 3A A schematic diagram of the structure of the second semiconductor material layer in the array substrate is shown in FIG. Figure 3H It is shown Figure 3A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in FIG. Fig. 3I It is shown Figure 3ASchematic diagram of the structure of the passivation layer of the array substrate shown in FIG. Figure 3J It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in the array substrate is shown in FIG. Figure 3K It is shown Figure 3A A schematic diagram of the structure of the first planarization layer in the array substrate is shown in FIG. Figure 3L It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate is shown in FIG. Figure 3M It is shown Figure 3A Schematic diagram of the structure of the second planarization layer in the array substrate shown in FIG. Figure 3N It is shown Figure 3A A schematic diagram of the structure of the third signal line layer in the array substrate is shown in FIG. Fig.3O It is shown Figure 3A Schematic diagram of the structure of the anode layer in the array substrate shown in FIG. Figure 4A is along Figure 3A Cross-sectional view along line A-A'. Figure 4B is along Figure 3A Cross-sectional view along line BB'.

[0092] refer to FIG. 3A to FIG. 3N , Figure 4A and Figure 4BIn some embodiments, the array substrate includes a substrate BS; a buffer layer BUF, which is located on the substrate BS; a first semiconductor material layer SML1, which is located on a side of the buffer layer BUF away from the substrate BS; a gate insulating layer GI, which is located on a side of the first semiconductor material layer SML1 away from the substrate BS; a first gate metal layer Gate1, which is located on a side of the gate insulating layer GI away from the first semiconductor material layer SML1; an insulating layer IN, which is located on a side of the first gate metal layer Gate1 away from the gate insulating layer GI; a second gate metal layer Gate2, which is located on a side of the insulating layer IN away from the first gate metal layer Gate1; a first interlayer dielectric layer ILD1, which is located on a side of the second gate metal layer Gate2 away from the insulating layer IN; a second semiconductor material layer SML2, which is located on a side of the first interlayer dielectric layer ILD1 away from the second gate metal layer SML2; a second interlayer dielectric layer ILD2, which is located on a side of the second semiconductor material layer SML2 away from the first interlayer dielectric layer ILD1 ; the third gate metal layer Gate3, which is located on the side of the second interlayer dielectric layer ILD2 away from the second semiconductor material layer SML2; the passivation layer PVX, which is located on the side of the third gate metal layer Gate3 away from the second interlayer dielectric layer ILD2; the first signal line layer SD1, which is located on the side of the passivation layer PVX away from the third gate metal layer Gate3; the first planarization layer PLN1, which is located on the side of the first signal line layer SD1 away from the passivation layer PVX; the second signal line layer SD2, which is located on the side of the first planarization layer PLN1 away from the first signal line layer SD1; the second planarization layer PLN2, which is located on the side of the second signal line layer SD2 away from the first planarization layer PLN1; the third signal line layer SD3, which is located on the side of the second planarization layer PLN2 away from the second signal line layer SD2; the third planarization layer PLN3, which is located on the side of the third signal line layer SD3 away from the second planarization layer PLN2; and the anode layer ADL, which is located on the side of the third planarization layer PLN3 away from the third signal line layer SD3.

[0093] Reference Figure 2A , Figure 3A , Figure 3D , Figure 4A and Figure 4BIn some embodiments, the first semiconductor material layer SML1 includes at least an active layer of multiple transistors (including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td) of a pixel driving circuit. Optionally, the first semiconductor material layer SML1 also includes at least corresponding portions of first electrodes of multiple transistors (including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td) of a pixel driving circuit. Optionally, the first semiconductor material layer SML1 also includes at least corresponding portions of second electrodes of multiple transistors (including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td) of a pixel driving circuit. Optionally, the first semiconductor material layer SML1 includes an active layer, a first electrode, and a second electrode of a plurality of transistors (including a first transistor T1, a third transistor T3, a fourth transistor T4, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a driving transistor Td) of a pixel driving circuit. Various suitable semiconductor materials can be used to manufacture the first semiconductor material layer SML1. Examples of semiconductor materials used to manufacture the first semiconductor material layer SML1 include silicon-based semiconductor materials, such as polycrystalline silicon, monocrystalline silicon, and amorphous silicon.

[0094] exist Figure 3D In, corresponding to Figure 3C The pixel driving circuit of PDC2 in is marked with a mark, which represents the components of each of the multiple transistors (T1, T3, T4, Tr1, Tr2, Tr3 and Td) in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1 and a second electrode D1. The third transistor T3 includes an active layer ACT3, a first electrode S3 and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4 and a second electrode D4. The first reset transistor Tr1 includes an active layer ACTr1, a first electrode Sr1 and a second electrode Dr1. The second reset transistor Tr2 includes an active layer ACTr2, a first electrode Sr2 and a second electrode Dr2. The third reset transistor Tr3 includes an active layer ACTr3, a first electrode Sr3 and a second electrode Dr3. The driving transistor Td includes an active layer ACTd, a first electrode Sd and a second electrode Dd.

[0095] Optionally, the active layers (ACT1, ACT3, ACT4, ACTr1, ACTr2, ACT3 and ACTd), the first electrodes (S1, S3, S4, Sr1, Sr2, Sr3 and Sd) and the second electrodes (D1, D3, D4, Dr1, Dr2, Dr3 and Dd) of each transistor (T1, T3, T4, Tr1, Tr2, Tr3 and Td) are located on the same layer.

[0096] In some embodiments, the active layers (ACT1, ACT3, ACT4, ACTr1, ACTr3, and ACTd) of the plurality of transistors (T1, T3, T4, Tr1, Tr3, and Td) in the pixel driving circuit, at least a portion of the first electrodes (S1, S3, S4, Sr1, Sr3, and Sd), and at least a portion of the second electrodes (D1, D3, D4, Dr1, Dr3, and Dd) are part of an integral structure. Optionally, in the same pixel driving circuit, a portion (ACTr2, Sr2, Dr2) of the second reset transistor Tr2 located in the first semiconductor material layer is spaced apart from the integral structure (T1, T3, T4, Tr1, and Td). Figure 3D As shown, in some embodiments, the active layers (ACT1, ACT3, ACT4, ACT1, ACT3 and ACTd) of multiple transistors (T1, T3, T4, Tr1, Tr3 and Td) in two adjacent pixel driving circuits, at least a portion of the first electrodes (S1, S3, S4, Sr1, Sr3 and Sd), and at least a portion of the second electrodes (D1, D3, D4, Dr1, Dr3 and Dd) are part of the overall structure.

[0097] Reference Figure 2A , Figure 3A , Figure 3E , Figure 4A as well as Figure 4B In some embodiments, the first gate metal layer Gate1 includes a plurality of first gate lines in a pixel driving circuit (e.g., a corresponding first gate line GL1), a plurality of first reset control signal lines (e.g., a corresponding first reset control signal line rst1), a plurality of second reset control signal lines (e.g., a corresponding second reset control signal line rst2), a first light-emitting control electrode pad emP1, a second light-emitting control electrode pad emP2, and a first capacitor electrode Ce1 of a storage capacitor Cst.

[0098] In some embodiments, the first light-emitting control electrode pad emP1 includes a gate G3 of a third transistor T3. Optionally, the first light-emitting control electrode pad emP1 includes a gate of a third transistor of a first adjacent pixel drive circuit and a second adjacent pixel drive circuit located in the same row. In some embodiments, the second light-emitting control electrode pad emP2 includes a gate G4 of a fourth transistor T4. Optionally, the second light-emitting control electrode pad emP2 includes a gate of a fourth transistor of a first adjacent pixel drive circuit and a third adjacent pixel drive circuit located in the same row. The third adjacent pixel drive circuit, the first adjacent pixel drive circuit and the second adjacent pixel drive circuit are arranged sequentially in the same row.

[0099] Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first gate metal layer Gate1. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first gate metal layer Gate1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, a plurality of first gate lines (e.g., corresponding first gate line GL1), a plurality of first reset control signal lines (e.g., corresponding first reset control signal line rst1), a plurality of second reset control signal lines (e.g., corresponding second reset control signal line rst2), a first light-emitting control electrode pad emP1, a second light-emitting control electrode pad emP2, and a first capacitor electrode Ce1 of a storage capacitor Cst in a pixel driving circuit are located in the same layer.

[0100] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when a plurality of first gate lines and a first capacitor electrode Ce1 are formed due to one or more steps of the same patterning process performed in the same material layer, the plurality of first gate lines and the first capacitor electrode Ce1 are located in the same layer. In another example, by simultaneously performing the steps of forming a plurality of first gate lines and the steps of forming the first capacitor electrode Ce1, a plurality of first gate lines and the first capacitor electrode Ce1 can be formed in the same layer. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in the cross-sectional view is the same.

[0101] In some embodiments, reference Figure 3A , Figure 3B , Figure 3E , Figure 3J and Figure 4A, the first light-emitting control electrode pad emP1 and the second light-emitting control electrode pad emP2 are connected to the corresponding light-emitting control signal line em among the multiple light-emitting control signal lines. Optionally, the first light-emitting control electrode pad emP1 and the second light-emitting control electrode pad emP2 are located in the first gate metal layer Gate1. Optionally, each light-emitting control signal line em is located in the first signal line layer SD1. In one example, the corresponding light-emitting control signal line em is connected to the first light-emitting control electrode pad emP1 through a via extending through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1 and the insulating layer IN. In another example, the corresponding light-emitting control signal line em is connected to the second light-emitting control electrode pad emP2 through a via extending through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1 and the insulating layer IN.

[0102] Reference Figure 2A , Figure 3A , Figure 3F , Figure 4A as well as Figure 4B In some embodiments, the second gate metal layer Gate2 includes at least part of a plurality of second gate lines in the pixel driving circuit (e.g., the corresponding second gate line first branch GL2-1), a plurality of second reset signal lines (e.g., the corresponding second reset signal line Vint2), and a second capacitor electrode Ce2 of the storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the second gate metal layer Gate2. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second gate metal layer Gate2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, at least part of a plurality of second gate lines in the pixel driving circuit (e.g., the corresponding second gate line first branch GL2-1), a plurality of second reset signal lines (e.g., the corresponding second reset signal line Vint2), and the second capacitor electrode Ce2 of the storage capacitor Cst are located in the same layer.

[0103] Reference Figure 2A , Figure 3A , Figure 3G , Figure 4A and Figure 4BIn some embodiments, the second semiconductor material layer SML2 includes at least an active layer ACT2 of a second transistor T2 in a pixel driving circuit. Optionally, the second semiconductor material layer SML2 also includes at least a portion of a first electrode S2 of a second transistor T2 in a pixel driving circuit. Optionally, the second semiconductor material layer SML2 also includes at least a portion of a second electrode D2 of a second transistor T2 in a pixel driving circuit. Optionally, the second semiconductor material layer SML2 includes an active layer ACT2, a first electrode S2, and a second electrode D2 of a second transistor T2. In the present array substrate, at least the active layer ACT2 of the second transistor T2 is located at a layer different from the active layers of at least other transistors in the pixel driving circuit. Various suitable semiconductor materials can be used to manufacture the second semiconductor material layer SML2. Examples of semiconductor materials used to manufacture the second semiconductor material layer SML2 include semiconductor materials based on metal oxides (e.g., indium gallium zinc oxide) and semiconductor materials based on metal oxynitrides (e.g., zinc oxynitride).

[0104] exist Figure 3G In, corresponding to Figure 3B The pixel driving circuit of PDC1 in the pixel driving circuit is marked with a mark indicating the components of the second transistor in the pixel driving circuit. For example, the second transistor T2 includes an active layer ACT2, a first electrode S2 and a second electrode D2. Optionally, the active layer ACT2, the first electrode S2 and the second electrode D2 of the second transistor T2 are located in the same layer.

[0105] refer to Figure 2A , Figure 3A , Figure 3H , Figure 4A and Figure 4B In some embodiments, the third gate metal layer Gate3 includes at least part of a plurality of second gate lines (e.g., the corresponding second gate line second branch GL2-2), a plurality of first reset signal lines (e.g., the corresponding first reset signal line Vint1) and a plurality of third reset signal lines (e.g., the corresponding third reset signal line Vint3). Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the third gate metal layer Gate3. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the third gate metal layer Gate3 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc.

[0106] Fig. 3I Show Figure 3A The array substrate is shown with vias extending through the passivation layer.

[0107] refer to Figure 2A , Figure 3A , Figure 3J , Figure 4A and Figure 4B In some embodiments, the first signal line layer SD1 includes a plurality of light-emitting control signal lines (e.g., corresponding light-emitting control signal lines em); a first voltage connection pad VCP1; a second voltage connection pad VCP2; a first data connection pad DCP1; a first node connection line Cln1; a third node connection line Cln3; a first relay electrode RE1; a first reset signal connection line Cli1; a second reset signal connection line Cli2; and a third reset signal connection line Cli3.

[0108] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first signal line layer SD1. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In some embodiments, the first signal line layer includes a plurality of sublayers stacked together. In one example, the first signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the first signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, a plurality of light-emitting control signal lines (e.g., corresponding light-emitting control signal lines em); a first voltage connection pad VCP1; a second voltage connection pad VCP2; a first data connection pad DCP1; a first node connection line Cln1; a third node connection line Cln3; a first relay electrode RE1; a first reset signal connection line Cli1; a second reset signal connection line Cli2; and a third reset signal connection line Cli3 are located in the same layer.

[0109] In some embodiments, the first node connection line Cln1 connects multiple components of the pixel driving circuit to the node N1. Figure 4A , the first node connection line Cln1 is connected to the first capacitor electrode Ce1 through the first via hole v1, and is connected to the second transistor T2 (eg, connected to the first electrode S2 of the second transistor T2) through the second via hole v2. Optionally, the first node connection line Cln1 corresponds to Figure 2A Node N1 described in .

[0110] In some embodiments, the orthographic projection of the second electrode Dr3 of the third reset transistor Tr3 on the substrate BS at least partially overlaps with the orthographic projection of the first voltage connection pad VCP1 on the substrate BS. The inventors of the present disclosure have found that by making the voltage at the first voltage connection pad VCP1 constant, this structure helps stabilize the voltage level at the node N2.

[0111] refer to Figure 2A , Figure 3A , Figure 3E , Figure 3F , Figure 4A and Figure 4B In some embodiments, in the hole region H, a portion of the second capacitor electrode Ce2 does not exist. Optionally, except for the hole region H where the portion of the second capacitor electrode Ce2 does not exist, the orthographic projection of the second capacitor electrode Ce2 on the substrate substrate BS substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99% or 100%) covers and is larger than the orthographic projection of the first capacitor electrode Ce1 on the substrate substrate BS. Optionally, the first via v1 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the hole region H and the insulating layer IN.

[0112] In some embodiments, the first node connection line Cln1 crosses a corresponding second gate line among the plurality of second gate lines. Figure 3A , Figure 3B and Figure 4A As shown, the first node connection line Cln1 crosses the corresponding second gate line first branch GL2-1 in the second gate metal layer Gate2 and the corresponding second gate line second branch GL2-2 in the third gate metal layer Gate3.

[0113] In some embodiments, reference Figure 4B The third node connection line Cln3 is connected to the second electrode Dr2 of the second reset transistor Tr2 through the third via hole v3, connected to the second electrode D2 of the second transistor T2 through the fourth via hole v4, and connected to the second electrode Dd of the driving transistor Td and the first electrode S4 of the fourth transistor T4 through the fifth via hole v5. Optionally, the third node connection line Cln3 corresponds to Figure 2A Optionally, the third node connection line Cln3 intersects with a corresponding second gate line in the plurality of second gate lines. Figure 3A , Figure 3B and Figure 4B As shown, the third node connection line Cln3 crosses the corresponding second gate line first branch GL2-1 in the second gate metal layer Gate2 and the corresponding second gate line second branch GL2-2 in the third gate metal layer Gate3.

[0114] In some embodiments, the positive projection of the third node connection line Cln3 on the substrate substrate BS overlaps at least partially (e.g., at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 98% or at least 99%) with the positive projection of the active layer ACT2 of the second transistor T2 on the substrate substrate. Optionally, the third node connection line Cln3 extends in a direction substantially parallel to the direction in which the active layer ACT2 of the second transistor T2 extends. Optionally, the positive projection of the third node connection line Cln3 on the substrate substrate BS overlaps at least partially with the positive projection of the first electrode S2 of the second transistor T2 on the substrate substrate. Optionally, the positive projection of the third node connection line Cln3 on the substrate substrate BS overlaps at least partially with the positive projection of the second electrode D2 of the second transistor T2 on the substrate substrate. As used herein, the term "substantially parallel" refers to an angle in the range of 0 degrees to about 45 degrees, for example, 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, 0 degrees to about 30 degrees.

[0115] In the present array substrate, the second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are located in the same layer, for example, located in the first semiconductor material layer SML1. In some embodiments, the second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are parts of an integral structure. In some embodiments, the second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are connected to each other in the first semiconductor material layer SML1. The second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are connected to each other through one or more parts of the first semiconductor material layer SML1, for example, there is no connection line in a layer different from the first semiconductor material layer SML1.

[0116] In some embodiments, a corresponding light emitting control signal line em among the plurality of light emitting control signal lines is connected to a first light emitting control electrode pad emP1 and a second light emitting control electrode pad emP2 in the first gate metal layer Gate1.

[0117] Figure 3K Show Figure 3A The array substrate is shown with vias extending through the first planarization layer.

[0118] refer to Figure 2A , Figure 3A , Figure 3B , Figure 3L , Figure 4A and Figure 4B In some embodiments, the second signal line layer SD2 includes a plurality of first voltage supply lines (e.g., corresponding first voltage supply lines Vddh), a plurality of first low voltage supply lines (e.g., corresponding first low voltage supply lines Vss1), a second relay electrode RE2, and a second data connection pad DCP2. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second signal line layer SD2. For example, the conductive material can be deposited on a substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second signal line layer SD2 include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, and the like. In one example, the second signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, a plurality of first voltage supply lines (e.g., corresponding first voltage supply lines Vddh), the second relay electrode RE2, and the second data connection pad DCP2 are located in the same layer.

[0119] Figure 3M Show Figure 3A The array substrate is shown with vias extending through the second planarization layer.

[0120] refer to Figure 2A , Figure 3A , Figure 3N , Figure 4A and Figure 4B In some embodiments, the third signal line layer SD3 includes a plurality of second voltage supply lines (e.g., corresponding second voltage supply lines Vddv), an anode contact pad ACP, a plurality of data lines (e.g., corresponding data lines DL), a plurality of fourth reset signal lines (e.g., corresponding fourth reset signal lines Vint4), a plurality of fifth reset signal lines (e.g., corresponding fifth reset signal lines Vint5), a plurality of sixth reset signal lines (e.g., corresponding sixth reset signal lines Vint6) and a plurality of second low voltage supply lines (e.g., corresponding second low voltage supply lines Vss2). In some embodiments, the corresponding first voltage supply line Vddh and the corresponding second voltage supply line Vddv are configured to provide a first reference voltage signal (e.g., a high reference voltage signal). Optionally, the corresponding low voltage supply line VSS is configured to provide a second reference voltage signal (e.g., a low reference voltage signal). Optionally, the first reference voltage signal is a constant voltage signal, the second reference voltage signal is a constant voltage signal, and the voltage level of the first reference voltage signal is higher than the voltage level of the second reference voltage signal.

[0121] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the third signal line layer SD3. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the third signal line layer SD3 include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In one example, the second signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. In another example, the second signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, multiple second voltage supply lines (e.g., corresponding second voltage supply lines Vddv), an anode contact pad ACP, multiple data lines (e.g., corresponding data lines DL), multiple fourth reset signal lines (e.g., corresponding fourth reset signal lines Vint4), multiple fifth reset signal lines (e.g., corresponding fifth reset signal lines Vint5), multiple sixth reset signal lines (e.g., corresponding sixth reset signal lines Vint6) and multiple low voltage supply lines (e.g., corresponding low voltage supply lines Vss) are located on the same layer.

[0122] Reference Figure 2A , Figure 3A , Fig.3O , Figure 4A and Figure 4B In some embodiments, the anode layer ADL includes a plurality of anodes AD.

[0123] refer to Figure 2A , Figure 3A , Figure 3B , Figure 3J , Figure 3L , Figure 3N , Figure 4A and Figure 4B In some embodiments, a plurality of first voltage supply lines and a plurality of second voltage supply lines are interconnected to form a voltage supply network. A corresponding first voltage supply line Vddh among the plurality of first voltage supply lines is connected to a first voltage connection pad VCP1, and the first voltage connection pad VCP1 is connected to a first electrode of the third transistor T3, thereby providing a voltage supply signal to the first electrode of the third transistor T3. Each first voltage supply line Vddh among the plurality of first voltage supply lines is connected to a second voltage connection pad VCP2, and the second voltage connection pad VCP2 is connected to a second capacitor electrode Ce2 of the storage capacitor Cst, thereby providing a voltage supply signal to the second capacitor electrode Ce2 of the storage capacitor Cst.

[0124] In some embodiments, the first reset signal connection line Cli1 connects a corresponding first reset signal line Vint1 of a plurality of first reset signal lines to the first electrode Sr1 of the first reset transistor Tr1. The first reset signal connection line Cli1 is configured to transmit a reset signal from the corresponding first reset signal line Vint1 to the first electrode Sr1 of the first reset transistor Tr1.

[0125] In some embodiments, the second reset signal connection line Cli2 connects a corresponding second reset signal line Vint2 of a plurality of second reset signal lines to the first electrode Sr2 of the second reset transistor Tr2. The second reset signal connection line Cli2 is configured to transmit a reset signal from the corresponding second reset signal line Vint2 to the first electrode Sr1 of the second reset transistor Tr2.

[0126] In some embodiments, the third reset signal connection line Cli3 connects a corresponding third reset signal line Vint3 among a plurality of third reset signal lines to a first electrode Sr3 of a third reset transistor Tr3. The third reset signal connection line Cli3 is configured to transmit a reset signal from a corresponding third reset signal line Vint3 to the first electrode Sr3 of the third reset transistor Tr3. In one example, the third reset signal connection line Cli3 is connected to the first electrode of the third reset transistor in two adjacent pixel driving circuits located in the same row, and is configured to transmit a reset signal from the corresponding third reset signal line Vint3 to the first electrode of the third reset transistor in two adjacent pixel driving circuits located in the same row.

[0127] In some embodiments, the first relay electrode RE1 is connected to the second electrode D4 of the fourth transistor T4 (and / or the second electrode Dr1 of the first reset transistor Tr1), and is connected to the second relay electrode RE2. The second relay electrode is connected to the first relay electrode RE1 and is connected to the anode contact pad ACP. In one example, the anode contact pad ACP is located in the third signal line layer SD3, the second relay electrode RE2 is located in the second signal line layer SD2, and the first relay electrode RE1 is located in the first signal line layer SD1. In another example, the anode contact pad ACP is connected to the second relay electrode RE2 through a via extending through the second planarization layer PLN2, the second relay electrode RE2 is connected to the first relay electrode RE1 through a via extending through the first planarization layer PLN1, and the first relay electrode RE1 is connected to the second electrode D4 of the fourth transistor T4 (and / or the second electrode Dr1 of the first reset transistor Tr1) through a via extending through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI.

[0128] In some embodiments, the first data connection pad DCP1 is connected to the first electrode S1 of the first transistor T1 and to the second data connection pad DCP2. The second data connection pad DCP2 is connected to the first data connection pad DCP1 and to the corresponding data line DL among the plurality of data lines. In one example, the first data connection pad DCP1 is located in the first signal line layer SD1, the second data connection pad DCP2 is located in the second signal line layer SD2, and the corresponding data line DL is located in the third signal line layer SD3. In another example, the corresponding data line DL is connected to the second data connection pad DCP2 through a via extending through the second planarization layer PLN2, the second data connection pad DCP2 is connected to the first data connection pad DCP1 through a via extending through the first planarization layer PLN1, and the first data connection pad DCP1 is connected to the first electrode S1 of the first transistor T1 through a via extending through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI.

[0129] In the present array substrate, each light emitting control signal line em is not located in the first gate metal layer, but in the first signal line layer. Figure 3A , Figure 3B and Figure 3D , the second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are located in the same layer, for example, in the first semiconductor material layer SML1. In some embodiments, the second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are part of an integral structure. In some embodiments, the second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are connected to each other in the first semiconductor material layer SML1. The second electrode D1 of the first transistor T1, the first electrode Sd of the driving transistor Td, the second electrode D3 of the third transistor T3, and the second electrode Dr3 of the third reset transistor Tr3 are connected to each other through one or more parts of the first semiconductor material layer SML1, for example, there is no connection line in a layer different from the first semiconductor material layer SML1.

[0130] The inventors of the present disclosure have discovered that the unique and complex structure of the array substrate significantly reduces the parasitic capacitance between components located in the first signal line layer and components located in the first gate metal layer, thereby greatly improving the display quality.

[0131] In some embodiments, reference FIG. 3A to FIG. 3N, the first pixel driving circuits (eg, Figure 3C The corresponding layer of the PDC1) and the second pixel driving circuit (eg, Figure 3C The corresponding layers of PDC2) in the array substrate, for example, have substantial (e.g., at least 80% symmetric, at least 85% symmetric, at least 90% symmetric, at least 95% symmetric, at least 98% symmetric, at least 99% symmetric, or completely symmetric) mirror symmetry relative to each other about a plane perpendicular to the major surface of the array substrate and substantially parallel to the plurality of data lines.

[0132] As used herein, the term "corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" is not intended to include layers that are not part of the pixel driving circuit. For example, the "corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" do not include an anode layer or a pixel defining layer. In some embodiments, the "corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" do not include a third signal line layer. In some embodiments, the "corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" do not include a second signal line layer. In some embodiments, the "corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" do not include a first signal line layer. In some embodiments, the "corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" do not include a third gate metal layer. In some embodiments, the "corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" do not include a second gate metal layer.

[0133] In one example, "the corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" refer to at least one conductive layer of the first pixel driving circuit and at least one conductive layer of the second pixel driving circuit. In a specific example, the "corresponding layer" includes at least one of the first semiconductor material layer, the first gate metal layer, the second gate metal layer, the second semiconductor material layer, the third gate metal layer, the first signal line layer, the second signal line layer, or the third signal line layer. In another specific example, the "corresponding layer" also includes at least one of the gate insulating layer, the insulating layer, the first interlayer dielectric layer, the second interlayer dielectric layer, the passivation layer, the first planarization layer, or the second planarization layer. In another specific example, the "corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" include the first semiconductor material layer. In another specific example, the "corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" include the first gate metal layer. In another specific example, the "corresponding layer of the first pixel driving circuit and the corresponding layer of the second pixel driving circuit" include the second semiconductor material layer.

[0134] In the relevant array substrate, a plurality of light-emitting control signal lines are generally located in the first gate metal layer, and a corresponding light-emitting control signal line among the plurality of light-emitting control signal lines generally includes the gates of the third transistor and the fourth transistor. The relevant array substrate generally includes a voltage connection line that crosses the corresponding light-emitting control signal line. The voltage connection line is connected to one or more voltage supply lines and is connected to the first electrode of the third transistor. The inventors of the present disclosure have found that in the relevant array substrate, there is a relatively large parasitic capacitance between the voltage connection line (for example, located in the first signal line layer) and the corresponding light-emitting control signal line located in the first gate metal layer, which adversely affects the display quality.

[0135] In the present array substrate, each light-emitting control signal line em is not located in the first gate metal layer, but in the first signal line layer. The first light-emitting control electrode pad emP1 and the second light-emitting control electrode pad emP2 are connected to the corresponding light-emitting control signal line em among the plurality of light-emitting control signal lines. Optionally, the first light-emitting control electrode pad emP1 and the second light-emitting control electrode pad emP2 are located in the first gate metal layer. Optionally, the corresponding light-emitting control signal line em is located in the first signal line layer. The inventors of the present disclosure have found that this unique and complex structure greatly reduces the parasitic capacitance between the first gate metal layer and the first signal line layer, thereby significantly improving the display quality.

[0136] Figure 5 FIG. 2 shows a voltage supply path in an array substrate according to some embodiments of the present disclosure. Figure 5 , Figure 3D , Figure 3J and Figure 3L In some embodiments, the array substrate includes a third transistor configured to receive a voltage supply signal; a first voltage connection pad VCP1; and a corresponding first voltage supply line Vddh among a plurality of first voltage supply lines; wherein the active layer of the third transistor, the first voltage connection pad VCP1 and the corresponding first voltage supply line Vddh are located at three different layers. Optionally, the active layer of the third transistor is located at the first semiconductor material layer; the first voltage connection pad VCP1 is located at the first signal line layer, and the corresponding first voltage supply line Vddh is located at the second signal line layer. In some embodiments, the corresponding first voltage supply line Vddh is connected to the first voltage connection pad VCP1, and the first voltage connection pad VCP1 is connected to the first electrode S3 of the third transistor.

[0137] In some embodiments, reference Figure 5 , Figure 3D , Figure 3J and Figure 3LThe array substrate further includes a corresponding light emitting control signal line em configured to provide a light emitting control signal to the gate of the third transistor. In some embodiments, the corresponding light emitting control signal line em and the first voltage connection pad VCP1 are located in the same layer.

[0138] In some embodiments, the first voltage connection pad VCP1 is connected to the first electrodes ( Figure 5 Indicated as S3 and S3').

[0139] Figure 6 Schematic diagram showing the structure of corresponding first voltage supply lines in an array substrate according to some embodiments of the present disclosure. Figure 6 In some embodiments, the corresponding first voltage supply line Vddh includes a main body MB and a plurality of extensions ET extending in a direction away from the main body MB. Optionally, the plurality of extensions ET extend in the same direction away from the main body MB. In some embodiments, a corresponding extension ET among the plurality of extensions ET is connected to a first voltage connection pad VCP1, and the first voltage connection pad VCP1 is connected to a first electrode S3 of a third transistor. Optionally, two adjacent extensions ET among the plurality of extensions ET are connected to the first voltage connection pad VCP1, and the first voltage connection pad VCP1 is connected to a first electrode S3 of a third transistor in two adjacent pixel driving circuits located in the same row. Figure 5 Indicated as S3 and S3').

[0140] Figure 7 It is shown Figure 3A Schematic diagram of the structure of the second semiconductor material layer and the corresponding first voltage supply line in the array substrate shown in FIG. Figure 7 In some embodiments, the orthographic projection of the main body MB on the substrate substantially covers (e.g., covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers) the orthographic projection of the active layer ACT2 of the second transistor T2 on the substrate. Optionally, the orthographic projection of the main body MB on the substrate substantially covers (e.g., covers at least 80%, covers at least 85%, covers at least 90%, covers at least 95%, covers at least 99%, or completely covers) the first electrode S2 of the second transistor T2, the active layer ACT2, and the orthographic projection of the second electrode D2 on the substrate. The inventors of the present disclosure have found that the unique and complex structure of the present array substrate helps to enhance the stability of the second transistor T2.

[0141] Fig. 8A is a schematic diagram showing the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. Figure 8B It is shown Fig. 8ASchematic diagram of the arrangement of pixel driving circuits in an array substrate shown in FIG. Figure 8C It is shown Fig. 8A A schematic diagram of the structure of the first semiconductor material layer in the array substrate is shown in FIG. Fig.8D It is shown Fig. 8A A schematic diagram of the structure of the first gate metal layer in the array substrate is shown in FIG. Fig. 8E It is shown Fig. 8A A schematic diagram of the structure of the second gate metal layer in the array substrate is shown in FIG. Figure 8F It is shown Fig. 8A A schematic diagram of the structure of the second semiconductor material layer in the array substrate is shown in FIG. Figure 8G It is shown Fig. 8A A schematic diagram of the structure of the third gate metal layer in the array substrate is shown in FIG. Figure 8H It is shown Fig. 8A Schematic diagram of the structure of the passivation layer in the array substrate shown in FIG. Figure 8I It is shown Fig. 8A A schematic diagram of the structure of the first signal line layer in the array substrate is shown in FIG. Figure 8J It is shown Fig. 8A A schematic diagram of the structure of the first planarization layer in the array substrate is shown in FIG. Figure 8K It is shown Fig. 8A A schematic diagram of the structure of the second signal line layer in the array substrate is shown in FIG. Figure 8L It is shown Fig. 8A Schematic diagram of the structure of the second planarization layer in the array substrate shown in FIG. Figure 8M It is shown Fig. 8A A schematic diagram of the structure of the third signal line layer in the array substrate is shown in FIG. Figure 8N It is shown Fig. 8A Schematic diagram of the structure of the anode layer in the array substrate shown in FIG. FIG. 8A to FIG. 8N A portion of an array substrate having twelve adjacent pixel driving circuits (including PDC1, PDC2, PDC3, PDC4, PDC5, PDC6, PDC7, PDC8, PDC9, PDC10, PDC11, and PDC12) is shown. Figure 8B PDC1 and PDC2 depicted in Figure 3C PDC1 and PDC2 are depicted in FIG.

[0142] Reference FIG. 8A to FIG. 8NIn some embodiments, the array substrate includes pixel driving circuits arranged in J columns, where J is a positive integer. The array substrate includes a plurality of fourth reset signal lines (e.g., corresponding fourth reset signal lines Vint4), a plurality of fifth reset signal lines (e.g., corresponding fifth reset signal lines Vint5), a plurality of sixth reset signal lines (e.g., corresponding sixth reset signal lines Vint6), and a plurality of second low voltage supply lines (e.g., corresponding second low voltage supply lines Vss2). In some embodiments, the J columns include the (8j-7)th column C(8j-7) among the J columns, the (8j-6)th column C(8j-6) among the J columns, the (8j-5)th column C(8j-5) among the J columns, the (8j-4)th column C(8j-4) among the J columns, the (8j-3)th column C(8j-3) among the J columns, the (8j-2)th column C(8j-2) among the J columns, the (8j-1)th column C(8j-1) among the J columns, and the (8j)th column C(8j) among the J columns, where J and j are positive integers, 1≤j≤J / 8.

[0143] In some embodiments, one of the corresponding fourth reset signal line Vint4, the corresponding fifth reset signal line Vint5, the corresponding sixth reset signal line Vint6 and the corresponding second low voltage supply line Vss2 is located between the (8j-7)th column C(8j-7) among the J columns and the (8j-6)th column C(8j-6) among the J columns; the other of the corresponding fourth reset signal line Vint4, the corresponding fifth reset signal line Vint5, the corresponding sixth reset signal line Vint6 and the corresponding second low voltage supply line Vss2 is located between the (8j-5)th column C(8j-5) among the J columns and the (8j-4)th column C(8j-6) among the J columns. 4); another one of the corresponding fourth reset signal line Vint4, the corresponding fifth reset signal line Vint5, the corresponding sixth reset signal line Vint6 and the corresponding second low voltage supply line Vss2 is located between the (8j-3)th column C(8j-3) among the J columns and the (8j-2)th column C(8j-2) among the J columns; and another one of the corresponding fourth reset signal line Vint4, the corresponding fifth reset signal line Vint5, the corresponding sixth reset signal line Vint6 and the corresponding second low voltage supply line Vss2 is located between the (8j-1)th column C(8j-1) among the J columns and the (8j)th column C(8j) among the J columns.

[0144] In such FIG. 8A to FIG. 8NIn one example shown, the corresponding sixth reset signal line Vint6 is located between the (8j-7)th column C(8j-7) among the J columns and the (8j-6)th column C(8j-6) among the J columns; the corresponding fourth reset signal line Vint4 is located between the (8j-5)th column C(8j-5) among the J columns and the (8j-4)th column C(8j-4) among the J columns; the corresponding second low voltage supply line Vss2 is located between the (8j-3)th column C(8j-3) among the J columns and the (8j-2)th column C(8j-2) among the J columns; and the corresponding fifth reset signal line Vint5 is located between the (8j-1)th column C(8j-1) among the J columns and the (8j)th column C(8j) among the J columns. The corresponding sixth reset signal line Vint6, the corresponding fourth reset signal line Vint4, the corresponding second low voltage supply line Vss2 and the corresponding fifth reset signal line Vint5 are arranged in sequence.

[0145] As used herein, the terms "column (8j-7)", "column (8j-6)", "column (8j-5)", "column (8j-4)", "column (8j-3)", "column (8j-2)", "column (8j-1)", "column (8j)" are used in the context of J columns. The array substrate may or may not include additional columns before the first column of the J columns and / or additional columns after the last column of the J columns. In the context of the array substrate, the terms "column (8j-7)", "column (8j-5)", "column (8j-3)", "column (8j-1)" do not necessarily represent odd columns, and the terms "column (8j-6)", "column (8j-4)", "column (8j-2)", "column (8j)" do not necessarily represent even columns. In one example, column (8j-7) is an odd column in the context of J columns, but may be an even column in the context of the array substrate. In another example, the (8j-7)th column is an odd column in the context of J columns, and is also an odd column in the context of the array substrate. In one example, the (8j-6)th column is an even column in the context of J columns, but can be an odd column in the context of the array substrate. In another example, the (8j-6)th column is an even column in the context of J columns, and is also an even column in the context of the array substrate. In one example, the (8j-5)th column is an odd column in the context of J columns, but can be an even column in the context of the array substrate. In another example, the (8j-5)th column is an odd column in the context of J columns, and is also an odd column in the context of the array substrate. In one example, the (8j-4)th column is an even column in the context of J columns, but can be an odd column in the context of the array substrate. In another example, the (8j-4)th column is an even column in the context of J columns, and is also an even column in the context of the array substrate. In one example, the (8j-3)th column is an odd column in the context of J columns, but may be an even column in the context of the array substrate. In another example, the (8j-3)th column is an odd column in the context of J columns, and may also be an odd column in the context of the array substrate. In one example, the (8j-2)th column is an even column in the context of J columns, but may be an odd column in the context of the array substrate. In another example, the (8j-2)th column is an even column in the context of J columns, and may also be an even column in the context of the array substrate. In one example, the (8j-1)th column is an odd column in the context of J columns, but may be an even column in the context of the array substrate. In another example, the (8j-1)th column is an odd column in the context of J columns, and may also be an odd column in the context of the array substrate. In one example, the (8j)th column is an even column in the context of J columns, but may be an odd column in the context of the array substrate. In another example, the (8j)th column is an even column in the context of J columns, and is also an even column in the context of the array substrate.

[0146] See also Figure 8N In some embodiments, the anode layer includes a first corresponding anode RAD1, a second corresponding anode RAD2, a third corresponding anode RAD3, and a fourth corresponding anode RAD4. In one example, the first corresponding anode RAD1 is an anode of a sub-pixel of a first color (e.g., a red sub-pixel), the second corresponding anode RAD2 is an anode of a sub-pixel of a second color (e.g., a blue sub-pixel), and the third corresponding anode RAD3 and the fourth corresponding anode RAD4 are anodes of two sub-pixels of a third color (e.g., two green sub-pixels). In some embodiments, the array of multiple sub-pixels in the array substrate includes a repeating array in the form of RGBG, where R represents a red sub-pixel, B represents a blue sub-pixel, and G represents a green sub-pixel.

[0147] In some embodiments, the first corresponding anode RAD1 includes a first main anode portion MAP1 and a first extension E1 extending in a direction away from the first main anode portion MAP1. The first extension E1 connects the first main anode portion MAP1 with the first corresponding anode connection pad. In some embodiments, the second corresponding anode RAD2 includes a second main anode portion MAP2 and a second extension E2 extending in a direction away from the second main anode portion MAP2. The second extension E2 connects the second main anode portion MAP2 with the second corresponding anode connection pad. In some embodiments, the third corresponding anode RAD3 includes a third main anode portion MAP3 and a third extension E3 extending in a direction away from the third main anode portion MAP3. The third extension E3 connects the third main anode portion MAP3 with the third corresponding anode connection pad. In some embodiments, the fourth corresponding anode RAD4 includes a fourth main anode portion MAP4 and a fourth extension E4 extending in a direction away from the fourth main anode portion MAP4. The fourth extension E4 connects the fourth main anode portion MAP4 with the fourth corresponding anode connection pad. Optionally, the first extension E1 extends in a direction substantially parallel to the first direction DR1 in a direction away from the first main anode portion MAP1. Optionally, the second extension portion E2 extends in a direction substantially parallel to the first direction DR1 in a direction away from the second main anode portion MAP2. Optionally, the third extension portion E3 extends in a direction substantially parallel to the second direction DR2 in a direction away from the third main anode portion MAP3. Optionally, the fourth extension portion E4 extends in a direction substantially parallel to the second direction DR2 in a direction away from the fourth main anode portion MAP4.

[0148] Fig.8O It is shown Fig. 8A Schematic diagram of the structure of the third signal line layer and the anode layer in the array substrate shown in FIG. Figure 8M , Figure 8N With Fig.8O , the orthographic projection of the first main anode portion MAP1 on the substrate substrate at least partially overlaps the orthographic projections of two adjacent data lines among the plurality of data lines on the substrate substrate. Optionally, the orthographic projection of the first main anode portion MAP1 on the substrate substrate at least partially overlaps the orthographic projections of two adjacent second voltage supply lines among the plurality of second voltage supply lines on the substrate substrate. In some embodiments, the orthographic projection of the second main anode portion MAP2 on the substrate substrate at least partially overlaps the orthographic projections of two adjacent data lines among the plurality of data lines on the substrate substrate. Optionally, the orthographic projection of the second main anode portion MAP2 on the substrate substrate at least partially overlaps the orthographic projections of two adjacent second voltage supply lines among the plurality of second voltage supply lines on the substrate substrate. Optionally, two adjacent data lines are configured to provide data signals to pixel driving circuits in the (8j - k1)-th column and the (8j - (k1 + 1))-th column, where j is a positive integer, 1 ≤ j ≤ (J / 8), k1 is a positive integer and 1 ≤ k1 < j. Optionally, two adjacent second voltage supply lines are configured to provide voltage supply signals to pixel driving circuits in the (8j - k1)-th column and the (8j - (k1 + 1))-th column, where J is a positive integer, 1 ≤ j ≤ (J / 8), k1 is an odd positive integer and 1 ≤ k1 < j. Examples of the (8j - k1)-th column and the (8j - (k1 + 1))-th column include the (8j - 1)-th column C(8j - 1) and the (8j - 2)-th column C(8j - 2), the (8j - 3)-th column C(8j - 3) and the (8j - 4)-th column C(8j - 4), the (8j - 5)-th column C(8j - 5) and the (8j - 6)-th column C(8j - 6).

[0149] In some embodiments, the orthographic projection of the first main anode portion MAP1 on the substrate substrate does not overlap at all with the orthographic projections of the plurality of fourth reset signal lines on the substrate substrate, does not overlap at all with the orthographic projections of the plurality of fifth reset signal lines on the substrate substrate, does not overlap at all with the orthographic projections of the plurality of sixth reset signal lines on the substrate substrate, and does not overlap at all with the orthographic projections of the plurality of second low voltage supply lines on the substrate substrate. In some embodiments, the orthographic projection of the second main anode portion MAP2 on the substrate substrate does not overlap at all with the orthographic projections of the plurality of fourth reset signal lines on the substrate substrate, does not overlap at all with the orthographic projections of the plurality of fifth reset signal lines on the substrate substrate, does not overlap at all with the orthographic projections of the plurality of sixth reset signal lines on the substrate substrate, and does not overlap at all with the orthographic projections of the plurality of second low voltage supply lines on the substrate substrate.

[0150] In some embodiments, the positive projection of the third main anode portion MAP3 on the substrate overlaps at least partially with the positive projections of two adjacent second voltage supply lines among the plurality of second voltage supply lines on the substrate, and also overlaps at least partially with the positive projection of one of the corresponding fourth reset signal line Vint4, the corresponding fifth reset signal line Vint5, the corresponding sixth reset signal line Vint6, and the corresponding second low-voltage supply line Vss2 on the substrate. In some embodiments, the positive projection of the fourth main anode portion MAP4 on the substrate overlaps at least partially with the positive projections of two adjacent second voltage supply lines among the plurality of second voltage supply lines on the substrate, and also overlaps at least partially with the positive projection of one of the corresponding fourth reset signal line Vint4, the corresponding fifth reset signal line Vint5, the corresponding sixth reset signal line Vint6, and the corresponding second low-voltage supply line Vss2 on the substrate. Optionally, two adjacent second voltage supply lines are configured to provide a voltage supply signal to the pixel driving circuits in the (8j - k2)-th column and the (8j - (k2 + 1))-th column, where j is a positive integer, 1 ≤ j ≤ (J / 8), k2 is zero or an even positive integer, and 0 ≤ k2 < j. Examples of the (8j - k2)-th column and the (8j - (k2 + 1))-th column include the (8j)-th column C(8j) and the (8j - 1)-th column C(8j - 1), the (8j - 2)-th column C(8j - 2) and the (8j - 3)-th column C(8j - 3), the (8j - 4)-th column C(8j - 4) and the (8j - 5)-th column C(8j - 5), the (8j - 6)-th column C(8j - 6) and the (8j - 7)-th column C(8j - 7).

[0151] Figure 8P is a schematic diagram showing Fig. 8A the structures of the first semiconductor material layer and the anode layer in the array substrate shown in. Refer to Figure 8C , Figure 8N , Figure 8P , Figure 3D and Fig.3O , the positive projection of the first main anode portion MAP1 on the substrate overlaps at least partially with the positive projection of the active layer of the third reset transistor in two adjacent columns of pixel driving circuits. Optionally, the two adjacent columns of pixel driving circuits include the (8j - k1)-th column and the (8j - (k1 + 1))-th column, where j is a positive integer, 1 ≤ j ≤ (J / 8), k1 is a positive integer, and 1 ≤ k1 < j. Examples of the (8j - k1)-th column and the (8j - (k1 + 1))-th column include the (8j - 1)-th column C(8j - 1) and the (8j - 2)-th column C(8j - 2), the (8j - 3)-th column C(8j - 3) and the (8j - 4)-th column C(8j - 4), the (8j - 5)-th column C(8j - 5) and the (8j - 6)-th column C(8j - 6).

[0152] In some embodiments, the orthographic projection of at least one of the first corresponding anode RAD1, the second corresponding anode RAD2, the third corresponding anode RAD3, or the fourth corresponding anode RAD4 on the substrate at least partially overlaps with the orthographic projection of the second electrode Dr3 of the third reset transistor Tr3 on the substrate.

[0153] Fig. 9A FIG. 2 shows a first interconnected reset signal network according to some embodiments of the present disclosure. Fig. 9A In some embodiments, the array substrate includes a first interconnected reset signal network, which is configured to provide a first reset signal to a plurality of pixel driving circuits. For example, the first interconnected reset signal network is configured to provide a first reset signal to a first electrode of a first reset transistor in a plurality of pixel driving circuits. In some embodiments, the first interconnected reset signal network includes a plurality of first reset signal lines extending in directions substantially parallel to the first direction DR1, respectively; and a plurality of fourth reset signal lines extending in directions substantially parallel to the second direction DR2; wherein the plurality of first reset signal lines intersect the plurality of fourth reset signal lines, respectively. As used herein, the term "substantially parallel" refers to an angle in the range of 0 degrees to about 45 degrees, for example, 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, 0 degrees to about 30 degrees.

[0154] Optionally, each of the plurality of first reset signal lines Vint1 is connected to at least a plurality of fourth reset signal lines; and each of the plurality of fourth reset signal lines Vint4 is connected to at least a plurality of first reset signal lines.

[0155] In some embodiments, each first reset signal line Vint1 includes a plurality of first portions P1 and a plurality of second portions P2 arranged alternately. Two adjacent second portions in the plurality of second portions P2 are connected by a first portion in the plurality of first portions P1. Two adjacent first portions in the plurality of first portions P1 are connected by a second portion in the plurality of second portions P2. A corresponding second portion in the plurality of second portions P2 is connected to a corresponding fourth reset signal line Vint4.

[0156] In some embodiments, the plurality of first portions P1, the plurality of second portions P2, and each fourth reset signal line Vint4 are located at three different layers, respectively. In a specific example, the plurality of first portions P1 are located at the third gate metal layer, the plurality of second portions P2 are located at the first signal line layer, and each fourth reset signal line Vint4 is located at the third signal line layer. The inventors of the present disclosure have found that the unique and complex structure of the first interconnected reset signal network optimizes the layout of the signal lines in the array substrate.

[0157] Fig. 9B FIG. 2 shows a first interconnected reset signal network according to some embodiments of the present disclosure. Fig. 9B , the corresponding first reset signal line Vint1 includes a first main line portion MLP1 and a plurality of second portions P2. The first main line portion MLP1 is a continuous line portion connected to the plurality of second portions P2. The corresponding second portion of the plurality of second portions P2 is connected to the corresponding fourth reset signal line Vint4.

[0158] Fig. 10A FIG. 2 shows a second interconnected reset signal network according to some embodiments of the present disclosure. Fig. 10A In some embodiments, the array substrate includes a second interconnected reset signal network, which is configured to provide a second reset signal to a plurality of pixel driving circuits. For example, the second interconnected reset signal network is configured to provide a second reset signal to a first electrode of a second reset transistor in a plurality of pixel driving circuits. In some embodiments, the second interconnected reset signal network includes a plurality of second reset signal lines extending in directions substantially parallel to the first direction DR1, respectively; and a plurality of fifth reset signal lines extending in directions substantially parallel to the second direction DR2, respectively; wherein the plurality of second reset signal lines cross the plurality of fifth reset signal lines, respectively.

[0159] Optionally, each second reset signal line Vint2 of the plurality of second reset signal lines is connected to at least a plurality of fifth reset signal lines; and each fifth reset signal line Vint5 of the plurality of fifth reset signal lines is connected to at least a plurality of the plurality of second reset signal lines.

[0160] In some embodiments, each second reset signal line Vint2 includes a plurality of third portions P3 and a plurality of fourth portions P4 arranged alternately. Two adjacent fourth portions in the plurality of fourth portions P4 are connected by a third portion in the plurality of third portions P3. Two adjacent third portions in the plurality of third portions P3 are connected by a fourth portion in the plurality of fourth portions P4. A corresponding fourth portion in the plurality of fourth portions P4 is connected to a corresponding fifth reset signal line Vint5.

[0161] In some embodiments, the plurality of third portions P3, the plurality of fourth portions P4, and each fifth reset signal line Vint5 are located at three different layers, respectively. In a specific example, the plurality of third portions P3 are located at the second gate metal layer, the plurality of fourth portions P4 are located at the first signal line layer, and each fifth reset signal line Vint5 is located at the third signal line layer. The inventors of the present disclosure have found that the unique and complex structure of the second interconnect reset signal network optimizes the layout of the signal lines in the array substrate.

[0162] Fig. 10BFIG. 2 shows a second interconnected reset signal network according to some embodiments of the present disclosure. Fig. 10B , the corresponding second reset signal line Vint2 includes a second main line portion MLP2 and a plurality of fourth portions P4. The second main line portion MLP2 is a continuous line portion connected to the plurality of fourth portions P4. The corresponding fourth portion of the plurality of fourth portions P4 is connected to the corresponding fifth reset signal line Vint5.

[0163] Fig.11 FIG. 2 shows a third interconnected reset signal network in some embodiments according to the present disclosure. Fig.11 In some embodiments, the array substrate includes a third interconnected reset signal network, which is configured to provide a third reset signal to a plurality of pixel driving circuits. For example, the third interconnected reset signal network is configured to provide a third reset signal to a first electrode of a third reset transistor in a plurality of pixel driving circuits. In some embodiments, the third interconnected reset signal network includes a plurality of third reset signal lines extending in directions substantially parallel to the first direction DR1, respectively; and a plurality of sixth reset signal lines extending in directions substantially parallel to the second direction DR2, respectively; wherein the plurality of third reset signal lines cross the plurality of sixth reset signal lines, respectively.

[0164] Optionally, each of the plurality of third reset signal lines Vint3 is connected to at least a plurality of sixth reset signal lines; and each of the plurality of sixth reset signal lines Vint6 is connected to at least a plurality of third reset signal lines.

[0165] In some embodiments, the array substrate further includes a plurality of reset connection pads RCP, each of which is connected to an individual third reset signal line among the plurality of third reset signal lines and to an individual sixth reset signal line among the plurality of sixth reset signal lines.

[0166] In some embodiments, each third reset signal line Vint3, each sixth reset signal line Vint6 and each reset connection pad RCP are respectively located in three different layers. In a specific example, each third reset signal line Vint3 is located in the third gate metal layer, each reset connection pad RCP is located in the first signal line layer, and each sixth reset signal line Vint6 is located in the third signal line layer.

[0167] Fig.12 An interconnected low voltage supply network is shown in some embodiments according to the present disclosure. Fig.12In some embodiments, the array substrate includes an interconnected low-voltage supply network configured to provide a low-voltage supply signal to a plurality of pixel driving circuits. For example, the interconnected low-voltage supply network is configured to provide a low-voltage supply signal to cathodes in a plurality of pixel driving circuits. In some embodiments, the interconnected low-voltage supply network includes a plurality of first low-voltage supply lines extending in directions substantially parallel to the first direction DR1, and a plurality of second low-voltage supply lines extending in directions substantially parallel to the second direction DR2, wherein the plurality of first low-voltage supply lines intersect with the plurality of second low-voltage supply lines, respectively.

[0168] Optionally, each of the plurality of first low pressure supply lines Vss1 is connected to at least a plurality of the plurality of second low pressure supply lines; and each of the plurality of second low pressure supply lines Vss2 is connected to at least a plurality of the plurality of first low pressure supply lines.

[0169] In some embodiments, each first low voltage supply line Vss1 and each second low voltage supply line Vss2 are located at two different layers. In a specific example, each first low voltage supply line Vss1 is located at the second signal line layer, and each second low voltage supply line Vss2 is located at the third signal line layer.

[0170] In the relevant array substrate, the reset signal line along the second direction is usually located in the first signal line layer, which is close to the first gate metal layer. The proximity of the reset signal line along the second direction to the gate line located in the first gate metal layer results in a relatively large parasitic capacitance, which in turn results in an increased load in the gate line. The increased load in the gate line requires an increased drive load of the gate scanning circuit (e.g., the gate circuit on the array). The inventors of the present disclosure have found that by arranging the reset signal line along the second direction in a third signal line layer spaced apart from the first gate metal layer by several layers, the drive load requirement for the gate scanning circuit can be reduced.

[0171] In some embodiments, the array substrate includes a plurality of first gate lines configured to provide gate scanning signals to gates of first transistors in a plurality of pixel driving circuits; a plurality of first voltage supply lines located on a side of the plurality of first gate lines away from the substrate, the plurality of first voltage supply lines configured to provide voltage supply signals to first electrodes of third transistors and fourth transistors in the plurality of pixel driving circuits; and a plurality of fourth reset signal lines, a plurality of fifth reset signal lines, or a plurality of sixth reset signal lines located on a side of the plurality of first voltage supply lines away from the plurality of first gate lines. The plurality of fourth reset signal lines, the plurality of fifth reset signal lines, or the plurality of sixth reset signal lines extend along the second direction.

[0172] In the relevant array substrate, the reset signal lines (e.g., a plurality of fourth reset signal lines, a plurality of fifth reset signal lines, or a plurality of sixth reset signal lines) along the second direction are arranged alternately, and the reset signal lines along the second direction are generally located on one side of the plurality of first voltage supply lines close to the plurality of first gate lines, for example, generally located in the first signal line layer. The layout of the reset signal lines along the second direction in the relevant array substrate results in different capacitances of nodes (e.g., node N1, node N2, or node N3) in the pixel driving circuits of different columns, resulting in uneven display in the array substrate. The inventors of the present disclosure have found that by spacing the reset signal lines along the second direction from the plurality of first gate lines, the plurality of first voltage supply lines shield the nodes from the reset signal lines along the second direction, thereby significantly improving display uniformity.

[0173] In the relevant array substrate, a plurality of light-emitting control signal lines are usually located in the first gate metal layer, and each of the plurality of light-emitting control signal lines usually includes the gates of the third transistor and the fourth transistor. The relevant array substrate usually includes a second node connection line (for example, located in the first signal line layer), which connects the second electrode D3 of the third transistor T3 to the second electrode Dr3 of the third reset transistor Tr3. The inventor of the present disclosure found that in the relevant array substrate, the presence of the second node connection line causes the parasitic capacitance between the second node connection line located in the first signal line layer and each light-emitting control signal line located in the first gate metal layer to be relatively large, thereby adversely affecting the display quality. In addition, the relevant array substrate requires a relatively large number of vias to connect the second node connection line located in the first signal line layer and the element located in the first semiconductor material layer, which affects the layout of the signal lines in the relevant array substrate.

[0174] Fig.13 It is shown Figure 3A Schematic diagram of the structure of the first semiconductor material layer in the array substrate shown in FIG. Fig.13 In some embodiments, each of the plurality of pixel driving circuits includes a second node connection line Cln2 connected to the second electrode D3 of the first light emission control transistor T3 and to the second electrode Dr3 of the third reset transistor Tr3. In the present array substrate, the second node connection line Cln2 is located at the same layer as the active layers of the first light emission control transistor T3 and the third reset transistor Tr3.

[0175] In some embodiments, reference Figure 4A and Fig.13, the plurality of light-emitting control signal lines em are separated from the second node connection line Cln2 by at least three insulating layers, for example, three insulating layers, four insulating layers or five insulating layers. In some embodiments, the plurality of light-emitting control signal lines em are separated from the second node connection line Cln2 by at least three of the gate insulating layer GI, the insulating layer IN, the first interlayer dielectric layer ILD1, the second interlayer dielectric layer ILD2 or the passivation layer PVX. In one example, the plurality of light-emitting control signal lines em are separated from the second node connection line Cln2 by the gate insulating layer GI, the insulating layer IN, the first interlayer dielectric layer ILD1, the second interlayer dielectric layer ILD2 and the passivation layer PVX.

[0176] The inventors of the present disclosure have found that by spacing the plurality of light emitting control signal lines em from the second node connection line Cln2 by at least three insulating layers, parasitic capacitance between the second node connection line Cln2 and the plurality of light emitting control signal lines em can be significantly reduced, thereby achieving improved display quality.

[0177] In some embodiments, reference Figure 4A , the plurality of light emitting control signal lines em and the first node connection line Cln1 are located in the same layer. Figure 4A and Fig.13 , the first node connection line Cln1 is separated from the second node connection line Cln2 by at least three insulating layers, for example, three insulating layers, four insulating layers, or five insulating layers. In some embodiments, the first node connection line Cln1 is separated from the second node connection line Cln2 by at least three of the gate insulating layer GI, the insulating layer IN, the first interlayer dielectric layer ILD1, the second interlayer dielectric layer ILD2, or the passivation layer PVX. In one example, the first node connection line Cln1 is separated from the second node connection line Cln2 by the gate insulating layer GI, the insulating layer IN, the first interlayer dielectric layer ILD1, the second interlayer dielectric layer ILD2, and the passivation layer PVX.

[0178] In another aspect, the present invention provides a display device, comprising an array substrate as described herein or manufactured by the method described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light emitting diode display device. Optionally, the display device is a micro light emitting diode display device. Optionally, the display device is a mini light emitting diode display device.

[0179] On the other hand, the present disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a plurality of pixel drive circuits. Optionally, forming each of the plurality of pixel drive circuits includes forming a drive transistor, forming a data write transistor, forming a first light emission control transistor, and forming a third reset transistor. Optionally, the active layer of the drive transistor, the data write transistor, the first light emission control transistor, and the third reset transistor is formed in a first semiconductor material layer. Optionally, the second electrode of the data write transistor, the first electrode of the drive transistor, the second electrode of the first light emission control transistor, and the second electrode of the third reset transistor are formed in the first semiconductor material layer. Optionally, the second electrode of the data write transistor, the first electrode of the drive transistor, the second electrode of the first light emission control transistor, and the second electrode of the third reset transistor are formed as part of the overall structure. Optionally, the second electrode of the data write transistor, the first electrode of the drive transistor, the second electrode of the first light emission control transistor, and the second electrode of the third reset transistor are connected to each other through one or more parts of the first semiconductor material layer.

[0180] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. An array substrate comprising a plurality of pixel driving circuits; in, Each pixel driving circuit of the plurality of pixel driving circuits comprises a driving transistor, a first light emission control transistor and a third reset transistor; The active layers of the driving transistor, the first light emission control transistor and the third reset transistor are located in the first semiconductor material layer; The first electrode of the driving transistor, the second electrode of the first light emission control transistor and the second electrode of the third reset transistor are located in the first semiconductor material layer; The first electrode of the driving transistor, the second electrode of the first light emission control transistor and the second electrode of the third reset transistor are parts of an integral structure; as well as The first electrode of the driving transistor, the second electrode of the first light emission control transistor, and the second electrode of the third reset transistor are connected to each other through one or more portions of the first semiconductor material layer.

2. The array substrate according to claim 1, further comprising: include: A first light-emitting control electrode pad, which is located on the first semiconductor material layer; as well as a plurality of light-emitting control signal lines, which are located on a side of the first light-emitting control electrode pad away from the first semiconductor material layer; Wherein, the first light emitting control electrode pad includes a gate of the first light emitting control transistor; and Each of the plurality of light emission control signal lines is connected to the first light emission control electrode pad through a via hole.

3. The array substrate according to claim 1, further comprising: include: A second light-emitting control electrode pad, which is located on the first semiconductor material layer; as well as a plurality of light emitting control signal lines, which are located at a side of the second light emitting control electrode pad away from the first semiconductor material layer; Wherein, each pixel driving circuit further includes a second light emitting control transistor; The second light emission control electrode pad includes a gate of the second light emission control transistor; and Each of the plurality of light emission control signal lines is connected to the second light emission control electrode pad through a via hole.

4. The array substrate according to claim 2 or 3, in, Each pixel driving circuit further includes a storage capacitor, wherein the storage capacitor includes a first capacitor electrode and a second capacitor electrode; The first light emitting control electrode pad and the first capacitor electrode are located in a first gate metal layer; The second capacitor electrode is located at a second gate metal layer, and the second gate metal layer is located at a side of the first gate metal layer away from the first semiconductor material layer; The plurality of light emitting control signal lines are located in a first signal line layer, and the first signal line layer is located on a side of the second gate metal layer away from the first gate metal layer.

5. The array substrate according to claim 4, in, Each pixel driving circuit further includes a compensation transistor; The active layer of the compensation transistor is located in a second semiconductor material layer, and the second semiconductor material layer is located on a side of the second gate metal layer away from the first gate metal layer; At least a portion of the gate of the compensation transistor is located on a third gate metal layer, and the third gate metal layer is located on a side of the second semiconductor material layer away from the second gate metal layer; as well as The plurality of light emitting control signal lines are located in the first signal line layer, and the first signal line layer is located on a side of the third gate metal layer away from the second semiconductor material layer.

6. The array substrate according to any one of claims 1 to 5, further comprising a first voltage connection pad and a plurality of first voltage supply lines; in, The active layer of the first light emission control transistor, the first voltage connection pad and the plurality of first voltage supply lines are located at three different layers; as well as A corresponding first voltage supply line of the plurality of first voltage supply lines is connected to the first voltage connection pad, and the first voltage connection pad is connected to the first electrode of the first light emission control transistor.

7. The array substrate according to claim 6, in, An orthographic projection of the second electrode of the third reset transistor on the substrate at least partially overlaps with an orthographic projection of the first voltage connection pad on the substrate.

8. The array substrate according to claim 6, further comprising a plurality of light emitting control signal lines; in, Each of the plurality of light emission control signal lines is configured to provide a light emission control signal to a gate of the first light emission control transistor; as well as The first voltage connection pad and the plurality of light emitting control signal lines are located at a same layer.

9. The array substrate according to claim 6, in, The first voltage connection pad is connected to first electrodes of first light emission control transistors in two adjacent pixel driving circuits located in the same row.

10. The array substrate according to claim 6, in, Each of the first voltage supply lines includes a main body and a plurality of extensions extending in a direction away from the main body; Each of the plurality of extensions is connected to the first voltage connection pad; and The first voltage connection pad is connected to the first electrode of the first light emission control transistor.

11. The array substrate according to claim 10, in, Each pixel driving circuit further includes a compensation transistor; The active layer of the compensation transistor is located in the second semiconductor material layer, and the second semiconductor material layer is located on a side of the first semiconductor material layer away from the substrate; The orthographic projection of the body on the base substrate substantially covers the orthographic projection of the active layer of the compensation transistor on the base substrate.

12. The array substrate according to claim 11, in, The orthographic projection of the body on the base substrate substantially covers the orthographic projections of the first electrode of the compensation transistor, the active layer, and the second electrode on the base substrate.

13. The array substrate according to any one of claims 1 to 12, in, Each pixel driving circuit further includes a first reset transistor and a second reset transistor; Wherein, the array substrate further includes: a plurality of third reset signal lines configured to provide a third reset signal to first electrodes of third reset transistors in the plurality of pixel driving circuits; and a plurality of first reset signal lines configured to provide a first reset signal to a first electrode of a first reset transistor in the plurality of pixel driving circuits, and / or a plurality of second reset signal lines configured to provide a second reset signal to a first electrode of a second reset transistor in the plurality of pixel driving circuits; The plurality of first reset signal lines, the plurality of second reset signal lines and the plurality of third reset signal lines extend along a direction substantially parallel to the first direction.

14. The array substrate according to any one of claims 1 to 12, in, The array substrate further includes: a plurality of third reset signal lines configured to provide a third reset signal to first electrodes of third reset transistors in the plurality of pixel driving circuits; a plurality of first low pressure supply lines; a plurality of fourth reset signal lines; a plurality of fifth reset signal lines; a plurality of sixth reset signal lines; and a plurality of second low pressure supply lines; wherein the plurality of third reset signal lines and the plurality of first low voltage signal lines extend along a direction substantially parallel to the first direction; The plurality of fourth reset signal lines, the plurality of fifth reset signal lines, the plurality of sixth reset signal lines, and the plurality of second low voltage supply lines extend along a direction substantially parallel to the second direction; The second direction is different from the first direction; and The plurality of fourth reset signal lines, the plurality of fifth reset signal lines, the plurality of sixth reset signal lines and the plurality of second low voltage supply lines are located in the same layer and on a side of the plurality of third reset signal lines and the plurality of first low voltage signal lines away from the first semiconductor material layer.

15. The array substrate according to claim 14, in, The plurality of fourth reset signal lines, the plurality of fifth reset signal lines, the plurality of sixth reset signal lines, and the plurality of second low voltage supply lines are alternately arranged.

16. The array substrate according to claim 14, in, The plurality of pixel driving circuits are arranged into J columns, where J is a positive integer; The J columns include the (8j-7)th column among the J columns, the (8j-6)th column among the J columns, the (8j-5)th column among the J columns, the (8j-4)th column among the J columns, the (8j-3)th column among the J columns, the (8j-2)th column among the J columns, the (8j-1)th column among the J columns, and the (8j)th column among the J columns, where j is a positive integer, 1≤j≤(J / 8); a corresponding fourth reset signal line among the plurality of fourth reset signal lines, a corresponding fifth reset signal line among the plurality of fifth reset signal lines, a corresponding sixth reset signal line among the plurality of sixth reset signal lines, and a corresponding second low voltage supply line among the plurality of second low voltage supply lines, located between the (8j-7)th column and the (8j-6)th column; the other of the corresponding fourth reset signal line, the corresponding fifth reset signal line, the corresponding sixth reset signal line and the corresponding second low voltage supply line is located between the (8j-5)th column and the (8j-4)th column; Another one of the corresponding fourth reset signal line, the corresponding fifth reset signal line, the corresponding sixth reset signal line and the corresponding second low voltage supply line is located between the (8j-3)th column and the (8j-2)th column; and Another one of the corresponding fourth reset signal line, the corresponding fifth reset signal line, the corresponding sixth reset signal line, and the corresponding second low voltage supply line is located between the (8j-1)th column and the (8j)th column.

17. The array substrate according to any one of claims 1 to 16, further comprising a first corresponding anode, a second corresponding anode, a third corresponding anode and a fourth corresponding anode; in, The first corresponding anode is an anode of a sub-pixel of a first color, the second corresponding anode is an anode of a sub-pixel of a second color, and the third corresponding anode and the fourth corresponding anode are anodes of two sub-pixels of a third color; The orthographic projection of the third corresponding anode on the substrate substrate at least partially overlaps with the orthographic projections of two adjacent second voltage supply lines among the plurality of second voltage supply lines on the substrate substrate, and at least partially overlaps with the orthographic projections of one of the corresponding fourth reset signal line, the corresponding fifth reset signal line, the corresponding sixth reset signal line and the corresponding second low voltage supply line on the substrate substrate; as well as The orthographic projection of the fourth corresponding anode on the substrate substrate at least partially overlaps with the orthographic projections of two adjacent second voltage supply lines among the multiple second voltage supply lines on the substrate substrate, and at least partially overlaps with the orthographic projections of the corresponding fourth reset signal line, the corresponding fifth reset signal line, the corresponding sixth reset signal line and one of the corresponding second low voltage supply lines on the substrate substrate.

18. The array substrate according to claim 17, in, An orthographic projection of at least one of the first corresponding anode, the second corresponding anode, the third corresponding anode, or the fourth corresponding anode on the substrate at least partially overlaps with an orthographic projection of the second electrode of the third reset transistor on the substrate.

19. An array substrate comprising a plurality of pixel driving circuits: in, Each pixel driving circuit of the plurality of pixel driving circuits comprises a second node connection line, a first light emission control transistor, and a third reset transistor; The second node connection line is connected to the second electrode of the first light emission control transistor and is connected to the second electrode of the third reset transistor; as well as The second node connection line is located at the same layer as active layers of the first light emission control transistor and the third reset transistor.

20. The array substrate according to claim 19, further comprising a plurality of light emitting control signal lines; in, Each of the plurality of light emission control signal lines is configured to provide a control signal to a gate of the first light emission control transistor; as well as The plurality of light emitting control signal lines are spaced apart from the second node connecting line by at least three insulating layers.

21. The array substrate according to claim 20, in, Each pixel driving circuit further includes a first node connection line, a storage capacitor and a compensation transistor; The first node connection line is connected to a first capacitor electrode of the storage capacitor and to a first electrode of the compensation transistor; as well as The plurality of light emission control signal lines and the first node connection line are located in the same layer.

22. A display device comprising the array substrate according to any one of claims 1 to 21 and one or more integrated circuits connected to the array substrate.

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