Display substrate, driving method thereof and display device

Abstract

The invention discloses a display substrate, a driving method thereof and a display device. The display substrate comprises a plurality of circuit units, and at least one circuit unit at least comprises a pixel driving circuit and a light-emitting signal line. In at least one circuit unit, the pixel driving circuit at least comprises a third transistor (T3), a fifth transistor (T5) and a sixth transistor (T6), the second pole of the fifth transistor (T5) is connected with the first pole of the third transistor (T3), and the first pole of the sixth transistor (T6) is connected with the second pole of the third transistor (T3); in at least one pixel driving circuit of at least one unit row, the fifth transistor (T5) is connected with the light-emitting signal line in the previous unit row, and the sixth transistor (T6) is connected with the light-emitting signal line in the unit row.

Description

Display substrate, driving method thereof, and display device

[0001] This application claims priority to PCT application No. PCT / CN2023 / 120988, filed on September 25, 2023, with application number PCT / CN2023 / 120988 and invention name “Display substrate, driving method thereof, and display device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, and specifically to a display substrate and a driving method thereof, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] On the one hand, the present disclosure provides a display substrate, comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising at least a pixel driving circuit and a light-emitting signal line, the pixel driving circuit being configured to output a driving current to the connected light-emitting device, and the light-emitting signal line being configured to provide a light-emitting control signal to the pixel driving circuit; in at least one circuit unit, the pixel driving circuit comprising at least a third transistor as a driving transistor, a fifth transistor as a first light-emitting control transistor, and a sixth transistor as a second light-emitting control transistor, the first electrode of the fifth transistor being connected to the first power line, the second electrode of the fifth transistor being connected to the first electrode of the third transistor, the first electrode of the sixth transistor being connected to the second electrode of the third transistor, and the second electrode of the sixth transistor being connected to the light-emitting device; in at least one pixel driving circuit of at least one unit row, the fifth transistor being connected to the light-emitting signal line in the previous unit row, and the sixth transistor being connected to the light-emitting signal line in the current unit row.

[0007] In an exemplary embodiment, in at least one pixel driving circuit, the fifth transistor and the sixth transistor are respectively disposed on both sides of the third transistor unit in a column direction.

[0008] In an exemplary embodiment, the fifth transistor includes at least a fifth active layer, and the sixth transistor includes at least a sixth active layer; in at least one pixel driving circuit of at least one unit row, the fifth active layer is arranged in the circuit unit of the previous unit row, and the sixth active layer is arranged in the circuit unit of the current unit row.

[0009] In an exemplary embodiment, in at least one pixel driving circuit of at least one unit row, the fifth active layer is disposed on one side of the sixth active layer of the pixel driving circuit in the previous unit row in the unit row direction.

[0010] In an exemplary embodiment, the pixel driving circuit further includes a storage capacitor and a power connection electrode, the storage capacitor includes a first plate and a second plate, the orthographic projection of the first plate on the plane of the display substrate at least partially overlaps with the orthographic projection of the second plate on the plane of the display substrate; in at least one pixel driving circuit of at least one unit row, the first end of the power connection electrode is connected to the first area of ​​the fifth active layer of the pixel driving circuit in the next unit row, and the second end of the power connection electrode is connected to the second plate of the pixel driving circuit in this unit row.

[0011] In an exemplary embodiment, at least one circuit unit further includes a scan signal line, which is configured to provide a scan signal to the pixel driving circuit; the pixel driving circuit further includes a fourth transistor serving as a data writing transistor and a seventh transistor serving as a second initialization transistor, the first electrode of the fourth transistor being connected to the data signal line, the second electrode of the fourth transistor being connected to the first electrode of the third transistor, the first electrode of the seventh transistor being connected to the second initial signal line, and the second electrode of the seventh transistor being connected to the second electrode of the sixth transistor; in at least one pixel driving circuit of at least one unit row, the fourth transistor is connected to the scan signal line in the previous unit row, and the seventh transistor is connected to the scan signal line in the current unit row.

[0012] In an exemplary embodiment, in at least one pixel driving circuit, the fourth transistor and the seventh transistor are respectively disposed on both sides of the third transistor unit in a column direction.

[0013] In an exemplary embodiment, the fourth transistor includes at least a fourth active layer, and the seventh transistor includes at least a seventh active layer; in at least one pixel driving circuit of at least one unit row, the fourth active layer is arranged in a circuit unit of the previous unit row, and the seventh active layer is arranged in a circuit unit of the current unit row.

[0014] In an exemplary embodiment, in at least one pixel driving circuit of at least one unit row, the fourth active layer is disposed on one side of the seventh active layer of the pixel driving circuit in the previous unit row in the unit row direction.

[0015] In an exemplary embodiment, the pixel driving circuit further includes a first transistor serving as a first initialization transistor, a second transistor serving as a compensation transistor, a fourth transistor serving as a data writing transistor, and a seventh transistor serving as a second initialization transistor, the first electrode of the first transistor being connected to the first initial signal line, the first electrode of the fourth transistor being connected to the data signal line, the first electrode of the seventh transistor being connected to the second initial signal line, the second electrode of the first transistor and the first electrode of the second transistor being connected to the gate electrode of the third transistor through a first node electrode, and the first electrode of the third transistor, the second electrode of the fourth transistor, and the second electrode of the fifth transistor being connected to each other through a second node electrode.

[0016] In an exemplary embodiment, an orthographic projection of the first power line on the display substrate plane at least partially overlaps with an orthographic projection of the first node electrode on the display substrate plane.

[0017] In an exemplary embodiment, the orthographic projection of the second node electrode on the display substrate plane at least partially overlaps with the orthographic projection of the first initial signal line on the display substrate plane, and / or the orthographic projection of the second node electrode on the display substrate plane at least partially overlaps with the orthographic projection of the second initial signal line on the display substrate plane.

[0018] In an exemplary embodiment, the gate electrode of the first transistor is connected to a fourth scan signal line, and an orthographic projection of the second node electrode on a display substrate plane at least partially overlaps with an orthographic projection of the fourth scan signal line on the display substrate plane.

[0019] In an exemplary embodiment, the gate electrode of the second transistor is connected to a third scan signal line, and an orthographic projection of the second node electrode on a display substrate plane at least partially overlaps with an orthographic projection of the third scan signal line on the display substrate plane.

[0020] In an exemplary embodiment, the first initial signal line is connected to a first shielding electrode, and an orthographic projection of the first shielding electrode on the display substrate plane at least partially overlaps an orthographic projection of a node between two gate electrodes of the second transistor on the display substrate plane.

[0021] In an exemplary embodiment, the second initial signal line is connected to a second shielding electrode, and an orthographic projection of the second shielding electrode on the display substrate plane at least partially overlaps an orthographic projection of a node between two gate electrodes of the first transistor on the display substrate plane.

[0022] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0023] On the other hand, the present disclosure also provides a driving method for a display substrate, wherein the display substrate includes multiple circuit units constituting multiple unit rows and multiple unit columns, at least one circuit unit includes at least a pixel driving circuit and a light-emitting signal line, the pixel driving circuit is configured to output a driving current to the connected light-emitting device, and the light-emitting signal line is configured to provide a light-emitting control signal to the pixel driving circuit; in at least one circuit unit, the pixel driving circuit includes at least a third transistor as a driving transistor, a fifth transistor as a first light-emitting control transistor, and a sixth transistor as a second light-emitting control transistor, the first electrode of the fifth transistor is connected to the first power line, the second electrode of the fifth transistor is connected to the first electrode of the third transistor, the first electrode of the sixth transistor is connected to the second electrode of the third transistor, and the second electrode of the sixth transistor is connected to the light-emitting device; the driving method includes at least a light-emitting stage, in which, in at least one pixel driving circuit of at least one unit row, the conduction and disconnection of the fifth transistor are controlled by the light-emitting signal line in the previous unit row, and the conduction and disconnection of the sixth transistor are controlled by the light-emitting signal line in the current unit row.

[0024] In an exemplary embodiment, at least one circuit unit further includes a scan signal line, which is configured to provide a scan signal to the pixel driving circuit; the pixel driving circuit further includes a fourth transistor serving as a data writing transistor and a seventh transistor serving as a second initialization transistor, the first electrode of the fourth transistor being connected to the data signal line, the second electrode of the fourth transistor being connected to the first electrode of the third transistor, the first electrode of the seventh transistor being connected to the second initialization signal line, and the second electrode of the seventh transistor being connected to the second electrode of the sixth transistor; the driving method further includes a data writing phase and a reset phase, and in at least one pixel driving circuit of at least one unit row, in the data writing phase, the conduction and disconnection of the fourth transistor are controlled by the scan signal line in the previous unit row, and in the reset phase, the conduction and disconnection of the seventh transistor are controlled by the scan signal line in the current unit row.

[0025] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0027] FIG1 is a schematic structural diagram of a display device;

[0028] FIG2 is a schematic diagram of a planar structure of a display substrate;

[0029] FIG3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0030] FIG4 is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0031] FIG5 is a driving timing diagram of the pixel driving circuit shown in FIG4 ;

[0032] FIG6 is a schematic diagram of an equivalent circuit of a cascade of pixel driving circuits according to an exemplary embodiment of the present disclosure;

[0033] FIG7 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0034] FIG8 is a schematic diagram of a display substrate after a semiconductor layer pattern is formed according to the present disclosure;

[0035] 9A and 9B are schematic diagrams of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0036] 10A and 10B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0037] FIG11 is a schematic diagram of a display substrate after a fourth insulating layer pattern is formed according to the present disclosure;

[0038] 12A and 12B are schematic diagrams of a display substrate after a third conductive layer pattern is formed thereon according to the present disclosure;

[0039] FIG13 is a schematic diagram of a display substrate after forming a first flat layer pattern according to the present disclosure;

[0040] 14A and 14B are schematic diagrams of a display substrate after a fourth conductive layer pattern is formed thereon according to the present disclosure.

[0041] Explanation of Reference Numerals: 11—first active layer; 12—second active layer; 13—third active layer; 14—fourth active layer; 15—fifth active layer; 16—sixth active layer; 17—seventh active layer; 21—first scanning signal line; 22—second scanning signal line; 23—third scanning signal line; 24—fourth scanning signal line; 25—first light-emitting signal line; 26—second light-emitting signal line; 31—first electrode plate; 32—second electrode plate; 33—opening; 34—plate connecting block; 41—first initial signal line; 42—second initial signal line; 43—first shielding electrode; 44—second shielding electrode; 51—first connecting electrode; 52—second connecting electrode; 53—third connecting electrode; 54—fourth connecting electrode; 55—fifth connecting electrode; 56—sixth connecting electrode; 57—seventh connecting electrode; 61—first power line; 62—data signal line; 63—anode connection electrode; 101—substrate; 102—driving circuit layer; 103—light-emitting structure layer; 104—encapsulation structure layer. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0043] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0044] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0045] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0046] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0047] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0048] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0049] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0050] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0051] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0052] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0053] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0054] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number. In an exemplary embodiment, the pixel array may be provided on a display substrate.

[0055] FIG2 is a schematic diagram of a planar structure of a display substrate. As shown in FIG2 , the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit may include a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0056] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a green subpixel (G) that emits green light, and the third subpixel P3 may be a blue subpixel (B) that emits blue light. In an exemplary embodiment, the subpixels may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three subpixels may be arranged horizontally, vertically, or in a triangular pattern, although this disclosure is not limited thereto.

[0057] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.

[0058] Figure 3 is a schematic cross-sectional view of a display substrate, illustrating the structure of three sub-pixels in the display area. As shown in Figure 3, in a plane perpendicular to the display substrate, the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the drive circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in this disclosure.

[0059] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include a light-emitting device, which may include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0060] The exemplary embodiments of the present disclosure provide a display substrate. In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate. On a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one of the circuit units may include a pixel driving circuit, and the pixel driving circuit is configured to output a corresponding current to the connected light-emitting device. The light-emitting structure layer may include a plurality of light-emitting units, at least one of the light-emitting units may include a light-emitting device, the light-emitting device being connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device being configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.

[0061] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position and shape of the orthographic projection of the light-emitting unit on the substrate may correspond to the position and shape of the orthographic projection of the circuit unit on the substrate, or the position and shape of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position and shape of the orthographic projection of the circuit unit on the substrate.

[0062] In an exemplary embodiment, the display substrate of the present disclosure may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit including at least a pixel driving circuit and a light-emitting signal line, the pixel driving circuit being configured to output a driving current to the connected light-emitting device, and the light-emitting signal line being configured to provide a light-emitting control signal to the pixel driving circuit; in at least one circuit unit, the pixel driving circuit includes at least a third transistor as a driving transistor, a fifth transistor as a first light-emitting control transistor, and a sixth transistor as a second light-emitting control transistor, the first electrode of the fifth transistor being connected to the first power line, the second electrode of the fifth transistor being connected to the first electrode of the third transistor, the first electrode of the sixth transistor being connected to the second electrode of the third transistor, and the second electrode of the sixth transistor being connected to the light-emitting device; in at least one pixel driving circuit of at least one unit row, the fifth transistor is connected to the light-emitting signal line in the previous unit row, and the sixth transistor is connected to the light-emitting signal line in the current unit row.

[0063] In an exemplary embodiment, at least one circuit unit further includes a scan signal line, which is configured to provide a scan signal to the pixel driving circuit; the pixel driving circuit further includes a fourth transistor serving as a data writing transistor and a seventh transistor serving as a second initialization transistor, the first electrode of the fourth transistor being connected to the data signal line, the second electrode of the fourth transistor being connected to the first electrode of the third transistor, the first electrode of the seventh transistor being connected to the second initial signal line, and the second electrode of the seventh transistor being connected to the second electrode of the sixth transistor; in at least one pixel driving circuit of at least one unit row, the fourth transistor is connected to the scan signal line in the previous unit row, and the seventh transistor is connected to the scan signal line in the current unit row.

[0064] The display substrate of the exemplary embodiments of the present disclosure will be described below with reference to some examples.

[0065] Figure 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 4, the pixel driving circuit has a 7T1C structure and may include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C. Each pixel driving circuit is connected to ten signal lines (a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, a first light-emitting signal line EM1, a second light-emitting signal line EM2, a first initial signal line INIT1, a second initial signal line INIT2, a data signal line DATA, and a first power line VDD).

[0066] In an exemplary embodiment, each pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is respectively connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, the second node N2 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, and the fourth node N4 is respectively connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0067] In an exemplary embodiment, a first end of the storage capacitor C in the pixel driving circuit is connected to the first node N1 , and a second end of the storage capacitor C is connected to the first power line VDD.

[0068] In an exemplary embodiment, the first transistor T1 may be referred to as a first initialization transistor, a gate electrode of the first transistor T1 is connected to the fourth scan signal line S4 , a first electrode of the first transistor T1 is connected to the first initial signal line INIT1 , and a second electrode of the first transistor T1 is connected to the first node N1 .

[0069] In an exemplary embodiment, the second transistor T2 may be referred to as a compensation transistor, a gate electrode of the second transistor T2 is connected to the third scan signal line S3 , a first electrode of the second transistor T2 is connected to the first node N1 , and a second electrode of the second transistor T2 is connected to the third node N3 .

[0070] In an exemplary embodiment, the third transistor T3 may be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1 , a first electrode of the third transistor T3 is connected to the second node N2 , and a second electrode of the third transistor T3 is connected to the third node N3 .

[0071] In an exemplary embodiment, the fourth transistor T4 may be referred to as a data writing transistor, a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1 , a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2 .

[0072] In an exemplary embodiment, the fifth transistor T5 may be referred to as a first light emission control transistor, a gate electrode of the fifth transistor T5 is connected to the first light emission signal line EM1, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.

[0073] In an exemplary embodiment, the sixth transistor T6 may be referred to as a second light emission control transistor, a gate electrode of the sixth transistor T6 is connected to the second light emission signal line EM2 , a first electrode of the sixth transistor T6 is connected to the third node N3 , and a second electrode of the sixth transistor T6 is connected to the fourth node N4 .

[0074] In an exemplary embodiment, the seventh transistor T7 may be referred to as a second initialization transistor, a gate electrode of the seventh transistor T7 is connected to the second scan signal line S1, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0075] In an exemplary embodiment, a first electrode of the light-emitting device EL is connected to the fourth node N4, and a second electrode of the light-emitting device EL is connected to the second power supply line VSS. The light-emitting device EL may be an OLED including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode, a quantum dot light-emitting layer, and a second electrode.

[0076] In an exemplary embodiment, the signal of the first power line VDD is a continuously provided high level signal, and the signal of the second power line VSS is a continuously provided low level signal.

[0077] In an exemplary embodiment, the first to second transistors T1 to T2 and the fourth to seventh transistors T4 to T7 are switching transistors, and the third transistor T3 is a driving transistor.

[0078] In an exemplary embodiment, the first to seventh transistors T1 to T7 in the pixel driving circuit may be P-type transistors or N-type transistors. In other possible exemplary embodiments, the first to seventh transistors T1 to T7 in the pixel driving circuit may include P-type transistors and N-type transistors.

[0079] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 in the pixel driving circuit may be low-temperature polysilicon transistors, or oxide transistors, or both. The active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), while the active layer of the oxide transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and oxide transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0080] FIG5 is a driving timing diagram of the pixel driving circuit shown in FIG4. As shown in FIG5, in an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0081] The first phase A1 can be referred to as a reset phase for the first node N1. The signal on the fourth scan signal line S4 is a low-level signal, while the signals on the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals, turning on the first transistor T1 and turning off the other switching transistors.

[0082] The first transistor T1 is turned on so that the signal of the first initial signal line INIT1 is provided to the first node N1, thereby initializing (resetting) the first node N1 and clearing the original charge in the first node N1.

[0083] The second phase A2 can be called a data writing phase. The signals on the first scan signal line S1 and the third scan signal line S3 are low-level signals, while the signals on the second scan signal line S2, the fourth scan signal line S4, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals. This turns on the second transistor T2 and the fourth transistor T4, and turns off the other switching transistors.

[0084] The second transistor T2 is turned on, so that the first node N1 and the third node N3 are turned on. Since the third transistor T3 is continuously turned on during this stage, the fourth transistor T4 is turned on, so that the data signal output by the data signal line DATA is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line DATA and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage of the first node N1 is Vd1-|Vth|, where Vd is the data voltage output by the data signal line DATA and Vth is the threshold voltage of the third transistor T3.

[0085] The third phase A3 can be referred to as a phase where the third node N3 is reset. The signals on the second scan signal line S2 and the third scan signal line S3 are low-level signals, while the signals on the first scan signal line S1, the fourth scan signal line S4, the first light-emitting signal line EM1, and the second light-emitting signal line EM2 are high-level signals. This turns on the second transistor T2 and the seventh transistor T7, while turning off the other switching transistors.

[0086] The second transistor T2 is turned on, connecting the first node N1 and the third node N3. The data voltage held in the parasitic capacitance of the second node N2 is continuously supplied to the first node N1 via the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. This prolongs the compensation time for the threshold voltage of the third transistor T3 and improves the uneven display caused by insufficient compensation. The seventh transistor T7 is turned on, supplying the signal of the second initial signal line INIT2 to the fourth node N4, initializing (resetting) the first electrode of the light-emitting device EL and clearing the original charge in the first electrode of the light-emitting device EL.

[0087] The fourth phase A4 is called a buffer phase. The signals of the first scanning signal line S1, the second scanning signal line S2, the third scanning signal line S3, the fourth scanning signal line S4, the first light emitting signal line EM1 and the second light emitting signal line EM2 are all high level signals, and all switching transistors are turned off.

[0088] The fifth stage A5 can be referred to as a reset stage for the second node N2 and the third node N3. The signal on the first light-emitting signal line EM1 is a low-level signal, and the signals on the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the fourth scan signal line S4, and the second light-emitting signal line EM2 are all high-level signals, turning on the fifth transistor T5 and turning off the other switching transistors.

[0089] The fifth transistor T5 is turned on so that the power signal output from the first power line VDD is provided to the third node N3 through the turned-on fifth transistor T5, the second node N2, and the turned-on third transistor T3, thereby resetting the second node N2 and the third node N3.

[0090] The sixth phase A6 can be called the light-emitting phase. The signals on the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are low-level signals, and the signals on the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, and the fourth scan signal line S4 are all high-level signals, turning on the fifth transistor T5 and the sixth transistor T6, and turning off the other switching transistors.

[0091] The fifth transistor T5 and the sixth transistor T6 are turned on, causing the power signal output from the first power line VDD to provide a driving voltage to the first electrode of the light-emitting device EL via the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on sixth transistor T6, thereby driving the light-emitting device EL to emit light. Because the fifth transistor T5 is turned on early in the fifth phase A5, the power signal is written to the third node N3. After the sixth transistor T6 is turned on, the charge at the third node N3 is quickly transferred to the fourth node N4. This allows the light-emitting device EL to turn on faster, which is particularly important for low grayscale lighting.

[0092] During the pixel driving circuit driving process, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0093] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting device EL, K is a constant related to process and design, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, and Vdd is the voltage of the power signal output by the first power line.

[0094] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 of each pixel driving circuit is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0095] Figure 6 is a schematic diagram of an equivalent circuit of a cascade of pixel driving circuits of an exemplary embodiment of the present disclosure, illustrating the pixel driving circuits of the n-1th unit row and the nth unit row. The structures of the pixel driving circuits of the n-1th unit row and the nth unit row are basically the same as those shown in Figure 4, where n is a positive integer greater than 1.

[0096] As shown in FIG6 , the second light-emitting signal line EM2(n-1) of the n-1th unit row can also serve as the first light-emitting signal line EM1(n) of the n-1th unit row, that is, the second light-emitting signal line EM2(n-1) of the n-1th unit row and the first light-emitting signal line EM1(n) of the n-1th unit row are the same light-emitting signal line, and the sixth transistor T6 of the n-1th unit row and the fifth transistor T5 of the n-1th unit row share the same light-emitting signal line. The second scan signal line S2(n-1) of the n-1th unit row can also serve as the first scan signal line S1(n) of the n-1th unit row, that is, the second scan signal line S2(n-1) of the n-1th unit row and the first scan signal line S1(n) of the n-1th unit row are the same scan signal line, and the seventh transistor T7 of the n-1th unit row and the fourth transistor T4 of the n-1th unit row share the same scan signal line.

[0097] Figure 7 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of nine circuit units (three unit rows and three unit columns). In this exemplary embodiment, the display substrate may include multiple circuit units, which may form multiple unit rows and multiple unit columns. The multiple circuit units in each unit row are arranged sequentially along a first direction X, and the multiple unit rows are arranged sequentially along a second direction Y, forming an array of circuit units arranged in an array, with the first direction X intersecting the second direction Y.

[0098] As shown in FIG7 , at least one circuit unit may include a pixel driving circuit, and a scan signal line, a third scan signal line 23, a fourth scan signal line 24, a light emitting signal line, a first initial signal line 41, a second initial signal line 42, a first power supply line 61, and a data signal line 62 connected to the pixel driving circuit. In an exemplary embodiment, the scan signal line, the third scan signal line 23, the fourth scan signal line 24, the light emitting signal line, the first initial signal line 41, and the second initial signal line 42 may be in the shape of a straight line or a zigzag line with a main portion extending along the first direction X, and the first power supply line 61 and the data signal line 62 may be in the shape of a straight line or a zigzag line with a main portion extending along the second direction Y.

[0099] In this disclosure, "A extends along direction B" means that A can include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B."

[0100] In an exemplary embodiment, at least one pixel driving circuit may include at least a storage capacitor and multiple transistors. The storage capacitor may include a stacked first plate and a second plate. The multiple transistors may include a first transistor T1 serving as a first initialization transistor, a second transistor T2 serving as a compensation transistor, a third transistor T3 serving as a drive transistor, a fourth transistor T4 serving as a data writing transistor, a fifth transistor T5 serving as a first emission control transistor, a sixth transistor T6 serving as a second emission control transistor, and a seventh transistor T7 serving as a second initialization transistor. The first to seventh transistors T1 to T7 may be low-temperature polysilicon transistors.

[0101] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the fourth scan signal line 24, the first electrode of the first transistor T1 is connected to the first initial signal line 41, the second electrode of the first transistor T1 and the first electrode of the second transistor T2 are connected to the gate electrode of the third transistor T3 (the first electrode plate of the storage capacitor), the gate electrode of the second transistor T2 is connected to the third scan signal line 23, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 are connected to each other, the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5 are connected to each other, the first electrode of the fourth transistor T4 is connected to the data signal line 62, the first electrode of the fifth transistor T5 is connected to the first power line 61, the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 42.

[0102] In an exemplary embodiment, the light-emitting signal line of at least one unit row can, on the one hand, serve as the second light-emitting signal line 26 of the pixel driving circuit in the unit row, and, on the other hand, serve as the first light-emitting signal line 25 of the pixel driving circuit in the next unit row. That is, the first light-emitting signal line 25 of the pixel driving circuit in the unit row and the second light-emitting signal line 26 of the pixel driving circuit in the previous unit row are the same light-emitting signal line, or the second light-emitting signal line 26 of the pixel driving circuit in the unit row and the first light-emitting signal line 25 of the pixel driving circuit in the next unit row are the same light-emitting signal line. For example, the light-emitting signal line of the n-1th unit row can, on the one hand, serve as the second light-emitting signal line 26(n-1) of the pixel driving circuit in the n-1th unit row, and, on the other hand, serve as the first light-emitting signal line 25(n) of the pixel driving circuit in the nth unit row. For another example, the light-emitting signal line of the nth unit row can, on the one hand, serve as the second light-emitting signal line 26(n) of the pixel driving circuit in the nth unit row, and, on the other hand, serve as the first light-emitting signal line 25(n+1) of the pixel driving circuit in the n+1th unit row. For another example, the light-emitting signal line of the n+1th unit row serves as the second light-emitting signal line 26(n+1) of the pixel driving circuit in the n+1th unit row on the one hand, and serves as the first light-emitting signal line 25(n+2) of the pixel driving circuit in the n+2th unit row on the other hand.

[0103] In an exemplary embodiment, in at least one pixel driving circuit in at least one unit row, the gate electrode of the fifth transistor T5 is connected to the light emitting signal line in the previous unit row, and the gate electrode of the sixth transistor T6 is connected to the light emitting signal line in the current unit row. The gate electrode of the fifth transistor T5 in the pixel driving circuit in the current unit row and the gate electrode of the sixth transistor T6 in the pixel driving circuit in the previous unit row are connected to the same light emitting signal line, or the gate electrode of the sixth transistor T6 in the pixel driving circuit in the current unit row and the gate electrode of the fifth transistor T5 in the pixel driving circuit in the next unit row are connected to the same light emitting signal line. For example, the gate electrode of the sixth transistor T6 in the pixel driving circuit in the n-1th unit row and the gate electrode of the fifth transistor T5 in the pixel driving circuit in the n-th unit row are simultaneously connected to the light emitting signal line in the n-1th unit row, and the light emitting signal line serves as both the second light emitting signal line 26(n-1) of the pixel driving circuit in the n-1th unit row and the first light emitting signal line 25(n) of the pixel driving circuit in the n-th unit row. For another example, the gate electrode of the sixth transistor T6 of the pixel driving circuit in the nth unit row and the gate electrode of the fifth transistor T5 of the pixel driving circuit in the n+1th unit row are simultaneously connected to the light-emitting signal line in the nth unit row. This light-emitting signal line serves as both the second light-emitting signal line 26(n) of the pixel driving circuit in the nth unit row and the first light-emitting signal line 25(n+1) of the pixel driving circuit in the n+1th unit row. For another example, the gate electrode of the sixth transistor T6 of the pixel driving circuit in the n+1th unit row and the gate electrode of the fifth transistor T5 of the pixel driving circuit in the n+2th unit row are simultaneously connected to the light-emitting signal line in the n+1th unit row. This light-emitting signal line serves as both the second light-emitting signal line 26(n+1) of the pixel driving circuit in the n+1th unit row and the first light-emitting signal line 25(n+2) of the pixel driving circuit in the n+2th unit row.

[0104] In an exemplary embodiment, the scan signal line of at least one unit row can serve as the second scan signal line 22 of the pixel driving circuit in the current unit row and the first scan signal line 21 of the pixel driving circuit in the next unit row. That is, the first scan signal line 21 of the pixel driving circuit in the current unit row and the second scan signal line 22 of the pixel driving circuit in the previous unit row are the same scan signal line, or the second scan signal line 22 of the pixel driving circuit in the current unit row and the first scan signal line 21 of the pixel driving circuit in the next unit row are the same scan signal line. For example, the scan signal line of the n-1th unit row can serve as the second scan signal line 22(n-1) of the pixel driving circuit in the n-1th unit row and the first scan signal line 21(n) of the pixel driving circuit in the nth unit row. For another example, the scan signal line of the nth unit row can serve as the second scan signal line 22(n) of the pixel driving circuit in the nth unit row and the first scan signal line 21(n+1) of the pixel driving circuit in the n+1th unit row. For another example, the scanning signal line of the n+1th unit row serves as the second scanning signal line 22(n+1) of the pixel driving circuit in the n+1th unit row on the one hand, and serves as the first scanning signal line 21(n+2) of the pixel driving circuit in the n+2th unit row on the other hand.

[0105] In an exemplary embodiment, in at least one pixel driving circuit in at least one unit row, the gate electrode of the fourth transistor T4 is connected to the scan signal line in the previous unit row, and the gate electrode of the seventh transistor T7 is connected to the scan signal line in the current unit row. The gate electrode of the fourth transistor T4 in the pixel driving circuit in the current unit row and the gate electrode of the seventh transistor T7 in the pixel driving circuit in the previous unit row are connected to the same scan signal line, or the gate electrode of the seventh transistor T7 in the pixel driving circuit in the current unit row and the gate electrode of the fourth transistor T4 in the pixel driving circuit in the next unit row are connected to the same scan signal line. For example, the gate electrode of the seventh transistor T7 in the pixel driving circuit in the n-1th unit row and the gate electrode of the fourth transistor T4 in the pixel driving circuit in the n-th unit row are simultaneously connected to the scan signal line in the n-1th unit row, and the scan signal line serves as both the second scan signal line 22(n-1) of the pixel driving circuit in the n-1th unit row and the first scan signal line 21(n) of the pixel driving circuit in the n-th unit row. For another example, the gate electrode of the seventh transistor T7 of the pixel driving circuit in the nth unit row and the gate electrode of the fourth transistor T4 of the pixel driving circuit in the n+1th unit row are simultaneously connected to the scanning signal line in the nth unit row. This scanning signal line serves as both the second scanning signal line 22(n) of the pixel driving circuit in the nth unit row and the first scanning signal line 21(n+1) of the pixel driving circuit in the n+1th unit row. For another example, the gate electrode of the seventh transistor T7 of the pixel driving circuit in the n+1th unit row and the gate electrode of the fourth transistor T4 of the pixel driving circuit in the n+2th unit row are simultaneously connected to the scanning signal line in the n+1th unit row. This scanning signal line serves as both the second scanning signal line 22(n+1) of the pixel driving circuit in the n+1th unit row and the first scanning signal line 21(n+2) of the pixel driving circuit in the n+2th unit row.

[0106] In an exemplary embodiment, in at least one pixel driving circuit, the fifth transistor T5 and the sixth transistor T6 may be respectively disposed on both sides of the third transistor T3 in the second direction Y (unit column direction). For example, in a pixel driving circuit in the nth unit row, the fifth transistor T5 may be disposed on a side opposite to the second direction Y of the third transistor T3, and the sixth transistor T6 may be disposed on a side of the third transistor T3 in the second direction Y.

[0107] In an exemplary embodiment, in at least one pixel driving circuit, the fourth transistor T4 and the seventh transistor T7 may be respectively disposed on both sides of the third transistor T3 in the second direction Y (unit column direction). For example, in a pixel driving circuit in the nth unit row, the fourth transistor T4 may be disposed on a side opposite to the second direction Y of the third transistor T3, and the seventh transistor T7 may be disposed on a side of the third transistor T3 in the second direction Y.

[0108] In an exemplary embodiment, the fifth transistor T5 may include at least a fifth active layer, and the sixth transistor T6 may include at least a sixth active layer. In at least one pixel driving circuit of at least one unit row, the fifth active layer may be provided in a circuit unit of the previous unit row, and the sixth active layer may be provided in a circuit unit of the current unit row. For example, in a pixel driving circuit of the nth unit row, the fifth active layer may be provided in a circuit unit of the (n-1)th unit row, and the sixth active layer may be provided in a circuit unit of the nth unit row.

[0109] In an exemplary embodiment, the fourth transistor T4 may include at least a fourth active layer, and the seventh transistor T7 may include at least a seventh active layer. In at least one pixel driving circuit of at least one unit row, the fourth active layer may be provided in a circuit unit of the previous unit row, and the seventh active layer may be provided in a circuit unit of the current unit row. For example, in a pixel driving circuit of the nth unit row, the fourth active layer may be provided in a circuit unit of the (n-1)th unit row, and the seventh active layer may be provided in a circuit unit of the nth unit row.

[0110] In an exemplary embodiment, in at least one pixel driving circuit of at least one unit row, the fifth active layer may be disposed on one side of the first direction X (unit row direction) of the sixth active layer of the pixel driving circuit in the previous unit row. For example, in a pixel driving circuit in the nth unit row, the fifth active layer may be disposed on one side of the first direction X of the sixth active layer of the pixel driving circuit in the (n-1)th unit row.

[0111] In an exemplary embodiment, in at least one pixel driving circuit of at least one unit row, the fourth active layer may be disposed on one side of the first direction X (unit row direction) of the seventh active layer of the pixel driving circuit in the previous unit row. For example, in a pixel driving circuit in the nth unit row, the fourth active layer may be disposed on one side of the first direction X of the seventh active layer of the pixel driving circuit in the (n-1)th unit row.

[0112] In an exemplary embodiment, the pixel driving circuit may further include a storage capacitor and a fourth connecting electrode 54, and the fourth connecting electrode 54 may serve as a power connection electrode of the present disclosure. The storage capacitor may include a first plate 31 and a second plate 32, and the orthographic projection of the first plate 31 on the display substrate plane at least partially overlaps with the orthographic projection of the second plate 32 on the display substrate plane. In at least one pixel driving circuit of at least one unit row, the first end of the fourth connecting electrode 54 is connected to the first area of ​​the fifth active layer of the pixel driving circuit in the next unit row, and the second end of the fourth connecting electrode 54 is connected to the second plate 32 of the pixel driving circuit in the current unit row. For example, in a pixel driving circuit of the nth unit row, the first end of the fourth connecting electrode 54 is connected to the first area of ​​the fifth active layer of the pixel driving circuit in the n+1th unit row, and the second end of the fourth connecting electrode 54 is connected to the second plate 32 of the pixel driving circuit in the nth unit row. For another example, in a pixel driving circuit in the n+1th unit row, the first end of the fourth connecting electrode 54 is connected to the first area of ​​the fifth active layer of the pixel driving circuit in the n+2th unit row, and the second end of the fourth connecting electrode 54 is connected to the second electrode 32 of the pixel driving circuit in the n+1th unit row.

[0113] In an exemplary embodiment, the second electrode of the first transistor T1 and the first electrode of the second transistor T2 may be connected to the first electrode plate 31 (the gate electrode of the third transistor T3 ) through the first connection electrode 51 , which may serve as a first node electrode of the present disclosure.

[0114] In an exemplary embodiment, an orthographic projection of the first power line 61 on the display substrate plane at least partially overlaps with an orthographic projection of the first connection electrode 51 on the display substrate plane.

[0115] In an exemplary embodiment, the first electrode of the third transistor T3 , the second electrode of the fourth transistor T4 , and the second electrode of the fifth transistor T5 may be connected to each other through the second connection electrode 52 , which may serve as a second node electrode of the present disclosure.

[0116] In an exemplary embodiment, the orthographic projection of the second connecting electrode 52 on the display substrate plane at least partially overlaps with the orthographic projection of the first initial signal line 41 on the display substrate plane, and / or the orthographic projection of the second connecting electrode 52 on the display substrate plane at least partially overlaps with the orthographic projection of the second initial signal line 42 on the display substrate plane.

[0117] In an exemplary embodiment, an orthographic projection of the second connection electrode 52 on the display substrate plane at least partially overlaps with an orthographic projection of the third scan signal line 23 on the display substrate plane.

[0118] In an exemplary embodiment, an orthographic projection of the second connection electrode 52 on the display substrate plane at least partially overlaps with an orthographic projection of the fourth scan signal line 24 on the display substrate plane.

[0119] In an exemplary embodiment, the first initial signal line 41 is connected to a first shielding electrode, and an orthographic projection of the first shielding electrode on the display substrate plane at least partially overlaps an orthographic projection of a node between two gate electrodes of the second transistor T2 on the display substrate plane.

[0120] In an exemplary embodiment, the second initial signal line 42 is connected to a second shielding electrode, and an orthographic projection of the second shielding electrode on the display substrate plane at least partially overlaps an orthographic projection of a node between two gate electrodes of the first transistor T1 on the display substrate plane.

[0121] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include a semiconductor layer disposed on a substrate, a first conductive layer disposed on a side of the semiconductor layer away from the substrate, a second conductive layer disposed on a side of the first conductive layer away from the substrate, a third conductive layer disposed on a side of the second conductive layer away from the substrate, and a fourth conductive layer disposed on a side of the third conductive layer away from the substrate. The semiconductor layer may include at least an active layer of the first to seventh transistors T1 to T7. The first conductive layer may include at least a scan signal line, a third scan signal line 23, a fourth scan signal line 24, a light emitting signal line, and a first plate 31 of a storage capacitor. The second conductive layer may include at least a first initial signal line 41, a second initial signal line 42, and a second plate 32 of a storage capacitor. The third conductive layer may include at least a plurality of connection electrodes. The fourth conductive layer may include at least a first power line 61 and a data signal line 62.

[0122] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes the deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes the coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0123] In an exemplary embodiment, taking 9 circuit units (three unit rows and three unit columns) as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0124] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process to form a first insulating layer disposed on the substrate, and a semiconductor layer pattern disposed on the first insulating layer, as shown in FIG8 .

[0125] In an exemplary embodiment, the semiconductor layer pattern in each circuit unit may include at least the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, and the first active layer 11, the second active layer 12, the third active layer 13, the sixth active layer 16 and the seventh active layer 17 are an integrated structure connected to each other, and the fourth active layer 14 and the fifth active layer 15 are separately provided.

[0126] In an exemplary embodiment, in the pixel driving circuit of the present circuit unit, in the first direction X, the fourth active layer 14 and the fifth active layer 15 may be located on one side of the third active layer 13 in the present circuit unit in the first direction X, and the sixth active layer 16 and the seventh active layer 17 may be located on the side of the third active layer 13 in the present circuit unit opposite to the first direction X. In the second direction Y, the sixth active layer 16 and the seventh active layer 17 may be located on one side of the third active layer 13 in the present circuit unit in the second direction Y, and the first active layer 11, the second active layer 12, the fourth active layer 14, and the fifth active layer 15 may be located on the side of the third active layer 13 in the present circuit unit opposite to the second direction Y.

[0127] In an exemplary embodiment, the third active layer 13 may have an inverted "Ω" shape, the first active layer 11 may have an inverted "n" shape, the second active layer 12 and the fourth active layer 14 may have an "L" shape, and the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 may have an inverted "I" shape.

[0128] In example embodiments, the first to seventh active layers 11 to 17 may each include a first region, a second region, and a channel region between the first and second regions.

[0129] In an exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be connected to each other, and the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer. The second region 12-2 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer may be connected to each other, and the second region 12-2 of the second active layer may serve as both the second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer may be connected to each other, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the first region 13-1 of the third active layer, the first region 14-1 of the fourth active layer, the second region 14-2 of the fourth active layer, the first region 15-1 of the fifth active layer, the second region 15-2 of the fifth active layer, and the first region 17-1 of the seventh active layer can be set separately.

[0130] In an exemplary embodiment, in a unit column, the fourth active layer 14 and the fifth active layer 15 of the pixel driving circuit in the present circuit unit can be set in the circuit unit of the previous unit row, and the first active layer 11, the second active layer 12, the third active layer 13, the sixth active layer 16 and the seventh active layer 17 can be set in the present circuit unit.

[0131] In an exemplary embodiment, the fifth active layer 15 of the pixel driving circuit in the circuit unit of the current unit row can be located on one side of the sixth active layer 16 of the pixel driving circuit in the circuit unit of the previous unit row in the first direction X, so that the fifth active layer 15 and the sixth active layer 16 of the pixel driving circuit in the circuit unit of the previous unit row can share a light-emitting signal line, and the light-emitting signal line can simultaneously control the conduction and disconnection of the sixth transistor T6 of the current unit row and the fifth transistor T5 of the next unit row. For example, the fifth active layer 15 of the pixel driving circuit in the nth unit row is disposed in the circuit unit of the n-1th unit row, so that the fifth active layer 15 of the pixel driving circuit in the nth unit row and the sixth active layer 16n-1 of the pixel driving circuit in the n-1th unit row can share a light-emitting signal line, and the light-emitting signal line can simultaneously control the conduction and disconnection of the fifth transistor T5 of the nth unit row and the sixth transistor T6 of the n-1th unit row. For another example, the fifth active layer 15n+1 of the pixel driving circuit in the n+1th unit row is arranged in the circuit unit of the nth unit row, so that the fifth active layer 15n+1 of the pixel driving circuit in the n+1th unit row and the sixth active layer 16 of the pixel driving circuit in the nth unit row can share a light-emitting signal line, and the one light-emitting signal line can simultaneously control the conduction and disconnection of the fifth transistor T5 of the n+1th unit row and the sixth transistor T6 of the nth unit row.

[0132] In an exemplary embodiment, the fourth active layer 14 of the pixel driving circuit in the circuit unit of the current unit row can be located on one side of the seventh active layer 17 of the pixel driving circuit in the circuit unit of the previous unit row in the first direction X, so that the fourth active layer 14 and the seventh active layer 17 of the pixel driving circuit in the circuit unit of the previous unit row can share a scan signal line, and the scan signal line can simultaneously control the conduction and disconnection of the seventh transistor T7 of the current unit row and the fourth transistor T4 of the next unit row. For example, the fourth active layer 14 of the pixel driving circuit in the n-th unit row is disposed in the circuit unit of the n-1-th unit row, so that the fourth active layer 14 of the pixel driving circuit in the n-th unit row and the seventh active layer 17n-1 of the pixel driving circuit in the n-1-th unit row can share a scan signal line, and the scan signal line can simultaneously control the conduction and disconnection of the seventh transistor T7 of the n-1-th unit row and the fourth transistor T4 of the n-th unit row. For another example, the fourth active layer 14n+1 of the pixel driving circuit in the n+1th unit row is arranged in the circuit unit of the nth unit row, so that the fourth active layer 14n+1 of the pixel driving circuit in the n+1th unit row and the seventh transistor T7 of the pixel driving circuit in the nth unit row can share a scanning signal line, and the one scanning signal line can simultaneously control the conduction and disconnection of the seventh transistor T7 of the nth unit row and the fourth transistor T4 of the n+1th unit row.

[0133] In an exemplary embodiment, the semiconductor layer may be made of polycrystalline silicon (p-Si), i.e., the first transistor T1 to the seventh transistor T7 are LTPS transistors. In an exemplary embodiment, patterning the semiconductor film through a patterning process may include: first forming an amorphous silicon (a-Si) film on a first insulating film, performing a dehydrogenation treatment on the amorphous silicon film, and then crystallizing the dehydrogenated amorphous silicon film to form a polycrystalline silicon film. Subsequently, patterning the polycrystalline silicon film to form a semiconductor layer pattern.

[0134] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG9A and FIG9B , FIG9B being a planar schematic diagram of the first conductive layer in FIG9A . In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0135] In an exemplary embodiment, the first conductive layer pattern of each circuit unit may include at least a scan signal line, a third scan signal line 23 , a fourth scan signal line 24 , a light emitting signal line, and a first plate 31 of a storage capacitor.

[0136] In an exemplary embodiment, the first electrode plate 31 may be rectangular, with chamfered or grooved corners. The orthographic projection of the first electrode plate 31 on the substrate at least partially overlaps the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 31 may serve as both a plate of the storage capacitor and a gate electrode of the third transistor T3.

[0137] In an exemplary embodiment, the shape of the scan signal line can be a straight line or a broken line with the main portion extending along the first direction X. The scan signal line can be located on one side of the first electrode 31 in the second direction Y. The area where the scan signal line overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4, and the area where the scan signal line overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7.

[0138] In an exemplary embodiment, a scan signal line can simultaneously serve as the second scan signal line 22 of the pixel driving circuit in the current unit row and the first scan signal line 21 of the pixel driving circuit in the next unit row. For example, the scan signal line of the n-1th unit row can serve as the second scan signal line 22(n-1) of the pixel driving circuit in the n-1th unit row, and can also serve as the first scan signal line 21(n) of the pixel driving circuit in the nth unit row. For another example, the scan signal line of the nth unit row can serve as the second scan signal line 22(n) of the pixel driving circuit in the nth unit row, and can also serve as the first scan signal line 21(n+1) of the pixel driving circuit in the n+1th unit row. For another example, the scan signal line of the n+1th unit row can serve as the second scan signal line 22(n+1) of the pixel driving circuit in the n+1th unit row, and can also serve as the first scan signal line 21(n+2) of the pixel driving circuit in the n+2th unit row.

[0139] In an exemplary embodiment, the third scan signal line 23 may be shaped as a straight line or a zigzag line, with the main portion extending along the first direction X. The third scan signal line 23 may be located on a side of the first electrode plate 31 opposite to the second direction Y. A third gate block 23-1 is disposed on the third scan signal line 23. The third gate block 23-1 may be shaped as a bar extending along the second direction Y. A first end of the third gate block 23-1 is connected to a side of the third scan signal line 23 away from the first electrode plate 31, and a second end of the third gate block 23-1 extends away from the first electrode plate 31. The region where the third scan signal line 23 and the third gate block 23-1 overlap with the second active layer may serve as the gate electrode of the second transistor T2 of the dual-gate structure.

[0140] In an exemplary embodiment, the shape of the fourth scan signal line 24 can be a straight line or a broken line with the main portion extending along the first direction X. The fourth scan signal line 24 can be located on the side of the third scan signal line 23 away from the first electrode plate 31. The area where the fourth scan signal line 24 overlaps with the first active layer can serve as the gate electrode of the first transistor T1 of the dual-gate structure.

[0141] In an exemplary embodiment, the shape of the light-emitting signal line can be a straight line or a broken line with the main part extending along the first direction X. The light-emitting signal line can be located on one side of the first electrode 31 in the second direction Y. The area where the light-emitting signal line overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5, and the area where the light-emitting signal line overlaps with the sixth active layer can serve as the gate electrode of the sixth transistor T6.

[0142] In an exemplary embodiment, a light-emitting signal line can simultaneously serve as the second light-emitting signal line 26 of the pixel driving circuit in the current unit row and the first light-emitting signal line 25 of the pixel driving circuit in the next unit row. For example, the light-emitting signal line of the n-1th unit row can serve as the second light-emitting signal line 26(n-1) of the pixel driving circuit in the n-1th unit row, and can also serve as the first light-emitting signal line 25(n) of the pixel driving circuit in the n-1th unit row. For another example, the light-emitting signal line of the nth unit row can serve as the second light-emitting signal line 26(n) of the pixel driving circuit in the nth unit row, and can also serve as the first light-emitting signal line 25(n+1) of the pixel driving circuit in the n+1th unit row. For another example, the light-emitting signal line of the n+1th unit row can serve as the second light-emitting signal line 26(n+1) of the pixel driving circuit in the n+1th unit row, and can also serve as the first light-emitting signal line 25(n+2) of the pixel driving circuit in the n+2th unit row.

[0143] In an exemplary embodiment, the scanning signal line, the third scanning signal line 23, the fourth scanning signal line 24 and the light-emitting signal line can be designed with non-equal widths, and the width is the dimension in the second direction Y, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0144] In an exemplary embodiment, the scan signal line, the third scan signal line 23, the fourth scan signal line 24 and the light emitting signal line may include an area overlapping with the semiconductor layer and an area not overlapping with the semiconductor layer, and the width of the signal line in the area overlapping with the semiconductor layer may be greater than the width of the signal line in the area not overlapping with the semiconductor layer.

[0145] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the first active layer 11 to the seventh active layer 17 are both conductorized.

[0146] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG10A and FIG10B , where FIG10B is a plan view schematic diagram of the second conductive layer in FIG10A . In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0147] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least a second plate 32 of the storage capacitor, a first initial signal line 41 , a second initial signal line 42 , a first shielding electrode 43 , and a second shielding electrode 44 .

[0148] In an exemplary embodiment, the outline of the second electrode plate 32 can be rectangular, and the corners of the rectangle can be chamfered or grooved. The orthographic projection of the second electrode plate 32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 31 on the substrate. The second electrode plate 32 can serve as another electrode plate of the storage capacitor, and the first electrode plate 31 and the second electrode plate 32 constitute the storage capacitor of the pixel driving circuit.

[0149] In an exemplary embodiment, the second electrode plate 32 is provided with an opening 33. The opening 33 can be rectangular and located in the central region of the second electrode plate 32, forming an annular structure. The opening 33 exposes the third insulating layer covering the first electrode plate 31, and the orthographic projection of the first electrode plate 31 on the substrate includes the orthographic projection of the opening 33 on the substrate. In an exemplary embodiment, the opening 33 is configured to accommodate a tenth via hole to be formed later. The tenth via hole is located within the opening 33 and exposes the first electrode plate 31, allowing the first connecting electrode to be formed later to be connected to the first electrode plate 31 through the via hole.

[0150] In an exemplary embodiment, a plate connection block 34 may be provided on the second plate 32. The plate connection block 34 may be in the shape of a strip extending along the first direction X and may be provided on one side of the second plate 32 in the first direction X or on a side opposite to the first direction X. The first end of the plate connection block 34 is connected to the second plate 32 of the circuit unit in question. The plate connection block 34 is also connected to the second plate 32 of the circuit unit adjacent to the circuit unit in the first direction X, so that the second plates 32 of adjacent circuit units in a unit row form an interconnected, integrated structure. Since the second plate 32 in each circuit unit is connected to a subsequently formed first power line, by forming the second plates 32 of adjacent circuit units into an interconnected, integrated structure, the second plates of the integrated structure can be reused as power signal lines. This ensures that multiple second plates in a unit row have the same potential, which helps improve panel uniformity, avoid display defects on the display substrate, and ensure the display quality of the display substrate.

[0151] In an exemplary embodiment, the shape of the first initial signal line 41 can be a straight line or a broken line with the main portion extending along the first direction X. The first initial signal line 41 can be located between the third scanning signal line 23 and the fourth scanning signal line 24. The first initial signal line 41 is configured to be connected to the first region of the first active layer through a sixth connecting electrode formed subsequently.

[0152] In an exemplary embodiment, a first preliminary connection block 41-1 may be provided on the first preliminary signal line 41. The first preliminary connection block 41-1 may be block-shaped (e.g., rectangular) and connected to the first preliminary signal line 41. The first preliminary connection block 41-1 is configured to be connected to the first region of the first active layer via a sixth connection electrode formed subsequently.

[0153] In an exemplary embodiment, the first shielding electrode 43 may be in the shape of a block (such as a rectangle), and may be disposed on a side of the first initial signal line 41 close to the second electrode plate 32 and connected to the first initial signal line 41. The orthographic projection of the first shielding electrode 43 on the substrate at least partially overlaps with the orthographic projection of the second active layer between the two gate electrodes in the second transistor T2 on the substrate. The first shielding electrode 34 is configured to shield the influence of the data voltage jump on the second transistor T2, thereby preventing the data voltage jump from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0154] In an exemplary embodiment, in one unit row, the first preliminary signal line 41 , the first preliminary connection block 41 - 1 , and the first shielding electrode 43 may be an integral structure connected to each other.

[0155] In an exemplary embodiment, the shape of the second initial signal line 42 can be a straight line or a broken line with the main portion extending along the first direction X. The second initial signal line 42 can be located on the side of the scanning signal line away from the second electrode 32. The second initial signal line 42 is configured to be connected to the first region of the seventh active layer through a seventh connecting electrode formed subsequently.

[0156] In an exemplary embodiment, a second initial connection block 42-1 may be provided on the second initial signal line 42. The second initial connection block 42-1 may be block-shaped (e.g., rectangular) and may be provided on a side of the second initial signal line 42 close to the second electrode plate 32 and connected to the second initial signal line 42. The second initial signal line 42 is configured to be connected to the first region of the first active layer via a subsequently formed seventh connection electrode.

[0157] In an exemplary embodiment, the second shielding electrode 44 may be in a block shape (e.g., rectangular) and may be disposed on a side of the second initial signal line 42 close to the second electrode plate 32 and connected to the second initial signal line 42. The orthographic projection of the second shielding electrode 44 on the substrate at least partially overlaps with the orthographic projection of the first active layer between the two gate electrodes in the first transistor T1 on the substrate. The second shielding electrode 44 is configured to shield the influence of the data voltage jump on the first transistor T1, thereby preventing the data voltage jump from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0158] In an exemplary embodiment, in one cell row, the second preliminary signal line 42 , the second preliminary connection block 42 - 1 , and the second shielding electrode 44 may be an integral structure connected to each other.

[0159] (4) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fifth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of vias are provided on the fourth insulating layer, as shown in FIG. 11 .

[0160] In an exemplary embodiment, the multiple vias of each circuit unit include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12 and a thirteenth via V13.

[0161] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a subsequently formed sixth connecting electrode to the first region of the first active layer through the via hole.

[0162] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second area of ​​the first active layer (also the first area of ​​the second active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second area of ​​the first active layer (also the first area of ​​the second active layer), and the second via hole V2 is configured to connect the subsequently formed first connecting electrode to the second area of ​​the first active layer (also the first area of ​​the second active layer) through the via hole.

[0163] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the third active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first area of ​​the third active layer, and the third via hole V3 is configured to connect a subsequently formed second connecting electrode to the first area of ​​the third active layer through the via hole.

[0164] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the fourth via hole V4 are etched away to expose the surface of the first region of the fourth active layer, and the fourth via hole V4 is configured to connect a subsequently formed third connecting electrode to the first region of the fourth active layer through the via hole.

[0165] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the second region of the fourth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the fifth via hole V5 are etched away to expose the surface of the second region of the fourth active layer, and the fifth via hole V5 is configured to connect a subsequently formed second connecting electrode to the second region of the fourth active layer through the via hole.

[0166] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the first region of the fifth active layer, and the sixth via hole V6 is configured to connect a subsequently formed fourth connecting electrode to the first region of the fifth active layer through the via hole.

[0167] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the second region of the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the second region of the fifth active layer, and the seventh via hole V7 is configured to connect a subsequently formed second connecting electrode to the second region of the fifth active layer through the via hole.

[0168] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the eighth via V8 are etched away to expose the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the eighth via V8 is configured to connect the subsequently formed fifth connecting electrode to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the via hole.

[0169] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via hole V9 are etched away to expose the surface of the first region of the seventh active layer, and the ninth via hole V9 is configured to connect the subsequently formed seventh connecting electrode to the first region of the seventh active layer through the via hole.

[0170] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the opening 33 on the substrate, the fourth insulating layer and the third insulating layer in the tenth via hole V10 are etched away, exposing the surface of the first electrode 31, and the tenth via hole V10 is configured to connect the subsequently formed first connecting electrode to the first electrode 31 through the via hole.

[0171] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the second electrode plate 32 on the substrate, the fourth insulating layer in the eleventh via hole V11 is etched away to expose the surface of the second electrode plate 32, and the eleventh via hole V11 is configured to connect the subsequently formed fourth connecting electrode to the second electrode plate 32 through the via hole.

[0172] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the first initial connection block 41-1 of the first initial signal line 41 on the substrate, the fourth insulating layer in the twelfth via V12 is etched away, exposing the surface of the first initial connection block 41-1, and the twelfth via V12 is configured to connect the subsequently formed sixth connection electrode to the first initial connection block 41-1 through the via.

[0173] In an exemplary embodiment, the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the second initial connection block 42-1 of the second initial signal line 42 on the substrate, the fourth insulating layer in the thirteenth via hole V13 is etched away, exposing the surface of the second initial connection block 42-1, and the thirteenth via hole V13 is configured to connect the subsequently formed seventh connection electrode to the second initial connection block 42-1 through the via hole.

[0174] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the fourth insulating layer, as shown in FIG12A and FIG12B , where FIG12B is a plan view schematic diagram of the third conductive layer in FIG12A . In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0175] In an exemplary embodiment, the third conductive layer of each circuit unit includes at least first, second, third, fourth, fifth, sixth, and seventh connection electrodes 51, 52, 53, 54, 55, 56, 57, and 58.

[0176] In an exemplary embodiment, the first connection electrode 51 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the first connection electrode 51 is connected to the second region of the first active layer (also the first region of the second active layer) via a second via hole V2, and a second end of the first connection electrode 51 is connected to the first electrode plate 31 via a tenth via hole V10. In an exemplary embodiment, because the first electrode plate 31 also serves as the gate electrode of the third transistor T3, the first connection electrode 51 causes the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 31 to have the same potential, forming a first node N1 of the pixel driving circuit.

[0177] In an exemplary embodiment, the second connection electrode 52 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the second connection electrode 52 is connected to the first region of the third active layer via a third via hole V3, a second end of the second connection electrode 52 is connected to the second region of the fifth active layer via a seventh via hole V7, and a portion between the first and second ends is connected to the second region of the fourth active layer via a fifth via hole V5. In an exemplary embodiment, the second connection electrode 52 causes the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5 to have the same potential, forming a second node N2 of the pixel driving circuit.

[0178] In an exemplary embodiment, since the fourth and fifth active layers of the pixel driver circuit in the current unit row are disposed in the circuit cells of the previous unit row, the second connection electrode 52 in the current unit row spans the circuit cells of two unit rows. The via hole connecting the second connection electrode 52 to the second region of the fourth active layer and the second region of the fifth active layer is located in the circuit cell of the previous unit row, while the via hole connecting the second connection electrode 52 to the first region of the third active layer is located in the circuit cell of the current unit row. For example, the second connection electrode 52 of the pixel driver circuit in the nth unit row has a via hole connecting the second region of the fourth active layer and the second region of the fifth active layer of the pixel driver circuit in the nth unit row in the circuit cell of the (n-1)th unit row, and a via hole connecting the second connection electrode 52 to the first region of the third active layer of the pixel driver circuit in the nth unit row in the circuit cell of the nth unit row. For another example, the fifth connecting electrode 55 in the n+1th unit row has a via position connecting it to the second area of ​​the fourth active layer and the second area of ​​the fifth active layer of the pixel driving circuit in the n+1th unit row, which is located in the circuit unit of the nth unit row; and a via position connecting it to the first area of ​​the third active layer of the pixel driving circuit in the n+1th unit row, which is located in the circuit unit of the n+1th unit row.

[0179] In an exemplary embodiment, the positive projection of the second connecting electrode 52 (the second node N2 of the pixel driving circuit) on the substrate at least partially overlaps with the positive projection of the first initial signal line 41 and the second initial signal line 42 on the substrate, so that the first initial signal line 41 and the second initial signal line 42 with a constant potential can effectively stabilize the potential of the second node N2.

[0180] In an exemplary embodiment, the orthographic projection of the second connection electrode 52 on the substrate at least partially overlaps with the orthographic projections of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the fourth scan signal line 24. Because the power signal output from the first power line is provided to the second node N2 during the fifth phase of the driving sequence of the pixel driving circuit, the influence of the scan lines on the second node N2 can be reset, thereby improving the light emission stability during the light emission phase.

[0181] In an exemplary embodiment, the third connection electrode 53 may be in a block shape (eg, rectangular), connected to the first region of the fourth active layer through a fourth via hole V4, and configured to be connected to a subsequently formed data signal line.

[0182] In an exemplary embodiment, the fourth connection electrode 54 may be in an "L" shape. A first end of the fourth connection electrode 54 is connected to the first region of the fifth active layer via a sixth via hole V6, and a second end of the fourth connection electrode 54 is connected to the second electrode plate 32 via an eleventh via hole V11. This ensures that the first electrode of the fifth transistor T5 and the second electrode plate 32 of the storage capacitor have the same potential. In an exemplary embodiment, the fourth connection electrode 54 is configured to be connected to a first power line formed later.

[0183] In an exemplary embodiment, since the fifth active layer of the pixel driving circuit in the current unit row is disposed in the circuit unit of the previous unit row, the first end of the fourth connecting electrode 54 in the current unit row is connected to the first region of the fifth active layer of the pixel driving circuit in the next unit row, and the second end of the fourth connecting electrode 54 is connected to the second electrode plate 32 of the pixel driving circuit in the current unit row. For example, the fourth connecting electrode 54 of the pixel driving circuit in the nth unit row has a first end connected to the first region of the fifth active layer of the pixel driving circuit in the n+1th unit row, and a second end connected to the second electrode plate 32 of the pixel driving circuit in the nth unit row. For another example, the fourth connecting electrode 54 in the n+1th unit row has a first end connected to the first region of the fifth active layer of the pixel driving circuit in the n+2th unit row, and a second end connected to the second electrode plate 32 of the pixel driving circuit in the n+1th unit row.

[0184] In an exemplary embodiment, the shape of the fifth connecting electrode 55 can be a block shape (such as a rectangle), the fifth connecting electrode 55 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the eighth via V8, and the sixth connecting electrode 56 is configured to be connected to the subsequently formed anode connecting electrode.

[0185] In an exemplary embodiment, the sixth connection electrode 56 may be in the shape of a strip extending along the second direction Y. A first end of the sixth connection electrode 56 is connected to the first region of the first active layer via a first via hole V1, and a second end of the sixth connection electrode 56 is connected to the first initial connection block 41-1 via a twelfth via hole V12. In an exemplary embodiment, because the first initial connection block 41-1 is connected to the first initial signal line 41, the sixth connection electrode 56 connects the first initial signal line 41 to the first electrode of the first transistor T1. The first initial signal line 41 can write the first initial signal to the first electrode of the first transistor T1.

[0186] In an exemplary embodiment, the seventh connection electrode 57 may be in the shape of a strip extending along the first direction X. A first end of the seventh connection electrode 57 is connected to the first region of the seventh active layer via a ninth via hole V9, and a second end of the seventh connection electrode 57 is connected to the second initial connection block 42-1 via a thirteenth via hole V13. In an exemplary embodiment, because the second initial connection block 42-1 is connected to the second initial signal line 42, the seventh connection electrode 57 connects the second initial signal line 42 to the first electrode of the seventh transistor T7. The second initial signal line 42 can write the second initial signal into the first electrode of the seventh transistor T7.

[0187] (6) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate having the aforementioned pattern formed thereon, patterning the first planar film using a patterning process to form a first planar layer covering the third conductive layer pattern, wherein a plurality of vias are provided on the first planar layer, as shown in FIG. 13 .

[0188] In an exemplary embodiment, the plurality of vias in each circuit unit includes at least a twenty-first via V21 , a twenty-second via V22 , and a twenty-third via V23 .

[0189] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the fourth connecting electrode 54 on the substrate, the first flat layer within the twenty-first via hole V21 is etched away to expose the surface of the fourth connecting electrode 54, and the twenty-first via hole V21 is configured to connect a subsequently formed first power line to the fourth connecting electrode 54 through the via hole.

[0190] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the third connecting electrode 53 on the substrate, the first flat layer in the twenty-second via hole V22 is etched away to expose the surface of the third connecting electrode 53, and the twenty-second via hole V22 is configured to connect a subsequently formed data signal line to the third connecting electrode 53 through the via hole.

[0191] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the fifth connecting electrode 55 on the substrate, the first flat layer within the twenty-third via hole V23 is etched away to expose the surface of the fifth connecting electrode 55, and the twenty-third via hole V23 is configured to connect the subsequently formed anode connecting electrode to the fifth connecting electrode 55 through the via hole.

[0192] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the first flat layer, as shown in FIG. 14A and FIG. 14B , where FIG. 14B is a planar schematic diagram of the fourth conductive layer in FIG. 14A . In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0193] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least a first power line 61 , a data signal line 62 , and an anode connection electrode 63 .

[0194] In an exemplary embodiment, the first power line 61 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The first power line 61 is connected to the fourth connection electrode 54 through the twenty-first via hole V21. Since the fourth connection electrode 54 is respectively connected to the first electrode of the fifth transistor T5 and the second plate 32 of the storage capacitor, the first power line 61 writes the power signal to the fifth transistor T5 and the second plate 32 of the storage capacitor.

[0195] In an exemplary embodiment, the first power line 61 may be a zigzag line with unequal width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power line and the data signal line.

[0196] In an exemplary embodiment, the orthographic projection of the first power line 61 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate. The first power line 61 having a constant potential can effectively shield the influence of data voltage jumps and other signals on the first node N1 in the pixel driving circuit, thereby preventing the data voltage jumps and other signals from affecting the potential of the first node N1, thereby improving the driving performance of the pixel driving circuit.

[0197] In an exemplary embodiment, the data signal line 62 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y. The data signal line 62 is connected to the third connection electrode 53 through the twenty-second via hole V22. Since the third connection electrode 53 is connected to the first region of the fourth active layer through the via hole, the data signal line 62 is connected to the first electrode of the fourth transistor T4. The data signal line 62 can write a data signal to the first electrode of the fourth transistor T4.

[0198] In an exemplary embodiment, the anode connection electrode 63 may be in a block shape (e.g., a rectangular shape). The anode connection electrode 63 is connected to the fifth connection electrode 55 via a twenty-third via hole V23. The anode connection electrode 63 is configured to be connected to a subsequently formed anode. Since the fifth connection electrode 55 is connected to the second region of the sixth active layer and the second region of the seventh active layer via the via hole, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting device to emit light.

[0199] The subsequent process may include forming a second flat layer covering the fourth conductive layer pattern, wherein the second flat layer is provided with an anode via hole, the anode via hole exposing the anode connection electrode, and the anode via hole is configured to connect the subsequently formed anode to the anode connection electrode through the via hole.

[0200] At this point, the drive circuit layer is completed on the substrate. Within a plane parallel to the display substrate, the drive circuit layer may include multiple circuit units, each of which may include a pixel drive circuit, as well as a scan signal line, a third scan signal line, a fourth scan signal line, a light-emitting signal line, a first initial signal line, a second initial signal line, a first power line, and a data signal line connected to the pixel drive circuit. Within a plane perpendicular to the display substrate, the drive circuit layer may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first planar layer, a fourth conductive layer, and a second planar layer, sequentially disposed on the substrate. The semiconductor layer may include at least the active layer of the first transistor T1 to the seventh transistor T7; the first conductive layer may include at least the scan signal line, the third scan signal line, the fourth scan signal line, the light-emitting signal line, and the first plate of the storage capacitor; the second conductive layer may include at least the first initial signal line, the second initial signal line, and the second plate of the storage capacitor; the third conductive layer may include at least a plurality of connection electrodes; and the fourth conductive layer may include at least the first power line, the data signal line, and the anode connection electrode.

[0201] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).

[0202] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The first planarizing layer and the second planarizing layer can be made of an organic material, such as a resin.

[0203] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer may be prepared on the driving circuit layer first, and then an encapsulation structure layer may be prepared on the light emitting structure layer, which will not be described in detail here.

[0204] A pixel driver circuit in a display substrate uses a 7T1C structure. Each circuit unit's pixel driver circuit is connected to four scan signal lines (first to fourth scan signal lines) and two light-emitting signal lines (first and second light-emitting signal lines). The large number of signal lines not only increases the occupied area but also requires the corresponding transistors to be staggered, increasing the complexity of the pixel driver circuit structure. This makes it difficult to reduce the size of the circuit units and improve the display device's pixel per inch (PPI) resolution. Furthermore, the large number of scan signal lines and light-emitting signal lines increases the number of corresponding gate driver circuits in the border area, increasing the gate driver circuitry and occupied area, making it difficult to achieve a narrow border.

[0205] The display substrate provided by the exemplary embodiments of the present disclosure employs a staggered arrangement and signal borrowing between pixel driving circuits in two adjacent unit rows. The fifth transistor T5 of the pixel driving circuit in the current unit row and the sixth transistor T6 of the pixel driving circuit in the previous unit row share a common light-emitting signal line, and are controlled to be turned on and off by the same light-emitting signal line. Furthermore, the fourth transistor T4 of the pixel driving circuit in the current unit row and the seventh transistor T7 of the pixel driving circuit in the previous unit row share a common scanning signal line, and are controlled to be turned on and off by the same scanning signal line. This effectively reduces the number of signal lines and avoids the additional space required by more signal lines. This optimizes the layout of the pixel driving circuit, effectively reduces the size of the circuit units, and effectively improves the resolution of the display device.

[0206] The display substrate disclosed herein arranges the sixth transistor T6 of the pixel driving circuit in the previous unit row and the fifth transistor T5 of the pixel driving circuit in the current unit row in the circuit unit of the previous unit row. The fifth transistor T5 and the sixth transistor T6 are simultaneously connected to the light-emitting signal line of the previous unit row. That is, the fifth transistor T5 of the pixel driving circuit in the current unit row and the sixth transistor T6 of the pixel driving circuit in the previous unit row share the same light-emitting signal line. This light-emitting signal line serves as both the second light-emitting signal line of the pixel driving circuit in the previous unit row and the first light-emitting signal line of the pixel driving circuit in the current unit row. This enables the fifth transistor T5 of the current unit row to borrow the control signal of the sixth transistor T6 of the previous unit row. Compared to the existing structure in which each unit row is provided with a first light-emitting signal line for controlling the fifth transistor T5 and a second light-emitting signal line for controlling the sixth transistor T6, the present disclosure adopts the staggered arrangement of transistors in adjacent unit rows and signal borrowing, thereby providing only one light-emitting signal line in each unit row. This not only reduces the number of signal lines and the occupied area, but also reduces the complexity of the pixel driving circuit structure, effectively reducing the size of the circuit unit and effectively improving the resolution of the display device.

[0207] The present disclosure separately controls the fifth transistor and the sixth transistor, connects the fifth transistor T5 of the current unit row to the light-emitting signal line of the previous unit row, and connects the sixth transistor T6 to the light-emitting signal line of the current unit row. The light-emitting signal lines of the two unit rows jointly adjust the duty cycle of the pulse width modulation (PWM), thereby achieving ultra-high frequency and higher precision pulse width modulation, light-emitting signal duty cycle compensation, low grayscale compensation, and improved afterimage.

[0208] The display substrate disclosed herein arranges the seventh transistor T7 of the pixel driving circuit in the previous unit row and the fourth transistor T4 of the pixel driving circuit in the current unit row in the circuit unit of the previous unit row. The fourth transistor T4 and the seventh transistor T7 are simultaneously connected to the scan signal line of the previous unit row. That is, the fourth transistor T4 of the pixel driving circuit in the current unit row and the seventh transistor T7 of the pixel driving circuit in the previous unit row share the same scan signal line. This scan signal line serves as both the second scan signal line of the pixel driving circuit in the previous unit row and the first scan signal line of the pixel driving circuit in the current unit row. This enables the fourth transistor T4 in the current unit row to borrow the control signal of the seventh transistor T7 in the previous unit row. Compared to the existing structure in which each unit row is provided with a first scan signal line for controlling the fourth transistor T4 and a second scan signal line for controlling the seventh transistor T7, the present disclosure adopts a staggered arrangement of transistors in adjacent unit rows and uses signals for borrowing, thereby providing only one scan signal line in each unit row. This not only reduces the number of signal lines and the occupied area, but also reduces the complexity of the pixel driving circuit structure, effectively reducing the size of the circuit unit and improving the resolution of the display device.

[0209] The present disclosure optimizes space utilization by reducing the number of light-emitting signal lines and scanning signal lines in a unit row, making the layout more reasonable, ensuring the distance between nodes within the pixel driving circuit and the distance between each node and the signal line, effectively avoiding crosstalk, effectively improving the display quality of the display device, effectively improving the product yield, and reducing production costs.

[0210] The present disclosure reduces the number of light-emitting signal lines and scanning signal lines in the unit row, so that the number of corresponding gate drive circuits in the border area can be reduced exponentially, effectively reducing the occupied area of ​​the gate drive circuit, which is conducive to achieving a narrow border and improving product advantages.

[0211] By providing a first power line covering the first connection electrode, the present disclosure can effectively shield the impact of data voltage jumps and other signals on the first node in the pixel driving circuit, thereby preventing the data voltage jumps and other signals from affecting the potential of the first node and effectively preventing crosstalk from worsening. The disclosed manufacturing process is well compatible with existing manufacturing processes, is simple to implement, and has high production efficiency, low production costs, and a high yield rate.

[0212] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0213] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0214] The present disclosure also provides a method for driving a display substrate to drive the display substrate provided in the above embodiment. In an exemplary embodiment, the display substrate includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit including at least a pixel driving circuit and a light-emitting signal line, the pixel driving circuit being configured to output a driving current to a connected light-emitting device, and the light-emitting signal line being configured to provide a light-emitting control signal to the pixel driving circuit; in at least one circuit unit, the pixel driving circuit includes at least a third transistor as a driving transistor, a fifth transistor as a first light-emitting control transistor, and a sixth transistor as a second light-emitting control transistor, the first electrode of the fifth transistor being connected to a first power line, the second electrode of the fifth transistor being connected to the first electrode of the third transistor, the first electrode of the sixth transistor being connected to the second electrode of the third transistor, and the second electrode of the sixth transistor being connected to the light-emitting device; the driving method includes at least a light-emitting phase, in which, in at least one pixel driving circuit of at least one unit row, the conduction and disconnection of the fifth transistor are controlled by the light-emitting signal line in the previous unit row, and the conduction and disconnection of the sixth transistor are controlled by the light-emitting signal line in the current unit row.

[0215] In an exemplary embodiment, at least one circuit unit further includes a scan signal line, which is configured to provide a scan signal to the pixel driving circuit; the pixel driving circuit further includes a fourth transistor serving as a data writing transistor and a seventh transistor serving as a second initialization transistor, the first electrode of the fourth transistor being connected to the data signal line, the second electrode of the fourth transistor being connected to the first electrode of the third transistor, the first electrode of the seventh transistor being connected to the second initialization signal line, and the second electrode of the seventh transistor being connected to the second electrode of the sixth transistor; the driving method further includes a data writing phase and a reset phase, and in at least one pixel driving circuit of at least one unit row, in the data writing phase, the conduction and disconnection of the fourth transistor are controlled by the scan signal line in the previous unit row, and in the reset phase, the conduction and disconnection of the seventh transistor are controlled by the scan signal line in the current unit row.

[0216] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0217] While the embodiments disclosed herein are as described above, it should be noted that the embodiments described above are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising at least a pixel driving circuit and a light-emitting signal line, the pixel driving circuit being configured to output a driving current to a connected light-emitting device, and the light-emitting signal line being configured to provide a light-emitting control signal to the pixel driving circuit; in at least one circuit unit, the pixel driving circuit comprising at least a third transistor as a driving transistor, a fifth transistor as a first light-emitting control transistor, and a sixth transistor as a second light-emitting control transistor, a first electrode of the fifth transistor being connected to a first power supply line, a second electrode of the fifth transistor being connected to a first electrode of the third transistor, a first electrode of the sixth transistor being connected to a second electrode of the third transistor, and a second electrode of the sixth transistor being connected to the light-emitting device; in at least one pixel driving circuit of at least one unit row, the fifth transistor being connected to the light-emitting signal line in a previous unit row, and the sixth transistor being connected to the light-emitting signal line in the current unit row.

2. The display substrate according to claim 1, wherein: In at least one pixel driving circuit, the fifth transistor and the sixth transistor are respectively arranged on both sides of the third transistor unit in a column direction.

3. The display substrate according to claim 2, wherein: The fifth transistor includes at least a fifth active layer, and the sixth transistor includes at least a sixth active layer; in at least one pixel driving circuit of at least one unit row, the fifth active layer is arranged in a circuit unit of a previous unit row, and the sixth active layer is arranged in a circuit unit of the current unit row.

4. The display substrate according to claim 3, wherein: In at least one pixel driving circuit of at least one unit row, the fifth active layer is arranged on one side of the sixth active layer unit row direction of the pixel driving circuit in the previous unit row.

5. The display substrate according to claim 3, wherein: The pixel driving circuit further includes a storage capacitor and a power connection electrode, the storage capacitor includes a first electrode plate and a second electrode plate, and the orthographic projection of the first electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the second electrode plate on the display substrate plane; In at least one pixel driving circuit of at least one unit row, the first end of the power connection electrode is connected to the first area of ​​the fifth active layer of the pixel driving circuit in the next unit row, and the second end of the power connection electrode is connected to the second electrode plate of the pixel driving circuit in the current unit row.

6. The display substrate according to claim 1, wherein: At least one circuit unit also includes a scan signal line, which is configured to provide a scan signal to the pixel driving circuit; the pixel driving circuit also includes a fourth transistor as a data writing transistor and a seventh transistor as a second initialization transistor, the first electrode of the fourth transistor is connected to the data signal line, the second electrode of the fourth transistor is connected to the first electrode of the third transistor, the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the second electrode of the sixth transistor; in at least one pixel driving circuit of at least one unit row, the fourth transistor is connected to the scan signal line in the previous unit row, and the seventh transistor is connected to the scan signal line in the current unit row.

7. The display substrate according to claim 6, wherein: In at least one pixel driving circuit, the fourth transistor and the seventh transistor are respectively arranged on both sides of the third transistor unit in a column direction.

8. The display substrate according to claim 7, wherein: The fourth transistor includes at least a fourth active layer, and the seventh transistor includes at least a seventh active layer; in at least one pixel driving circuit of at least one unit row, the fourth active layer is arranged in a circuit unit of a previous unit row, and the seventh active layer is arranged in a circuit unit of the current unit row.

9. The display substrate according to claim 8, wherein: In at least one pixel driving circuit of at least one unit row, the fourth active layer is arranged on one side of the seventh active layer unit row direction of the pixel driving circuit in the previous unit row.

10. The display substrate according to any one of claims 1 to 9, wherein: The pixel driving circuit also includes a first transistor as a first initialization transistor, a second transistor as a compensation transistor, a fourth transistor as a data writing transistor and a seventh transistor as a second initialization transistor, the first electrode of the first transistor is connected to the first initial signal line, the first electrode of the fourth transistor is connected to the data signal line, the first electrode of the seventh transistor is connected to the second initial signal line, the second electrode of the first transistor and the first electrode of the second transistor are connected to the gate electrode of the third transistor through a first node electrode, and the first electrode of the third transistor, the second electrode of the fourth transistor and the second electrode of the fifth transistor are mutually connected through a second node electrode.

11. The display substrate according to claim 10, wherein: An orthographic projection of the first power line on the display substrate plane at least partially overlaps with an orthographic projection of the first node electrode on the display substrate plane.

12. The display substrate according to claim 10, wherein: The orthographic projection of the second node electrode on the display substrate plane at least partially overlaps with the orthographic projection of the first initial signal line on the display substrate plane, and / or the orthographic projection of the second node electrode on the display substrate plane at least partially overlaps with the orthographic projection of the second initial signal line on the display substrate plane.

13. The display substrate according to claim 10, wherein: The gate electrode of the first transistor is connected to a fourth scanning signal line, and an orthographic projection of the second node electrode on a display substrate plane at least partially overlaps with an orthographic projection of the fourth scanning signal line on the display substrate plane.

14. The display substrate according to claim 10, wherein: The gate electrode of the second transistor is connected to the third scanning signal line, and the orthographic projection of the second node electrode on the plane of the display substrate at least partially overlaps with the orthographic projection of the third scanning signal line on the plane of the display substrate.

15. The display substrate according to claim 10, wherein: The first initial signal line is connected to a first shielding electrode, and an orthographic projection of the first shielding electrode on the display substrate plane at least partially overlaps with an orthographic projection of a node between two gate electrodes in the second transistor on the display substrate plane.

16. The display substrate according to claim 10, wherein: The second initial signal line is connected to a second shielding electrode, and an orthographic projection of the second shielding electrode on the display substrate plane at least partially overlaps with an orthographic projection of a node between two gate electrodes in the first transistor on the display substrate plane.

17. A display device comprising the display substrate according to any one of claims 1 to 16.

18. A method for driving a display substrate, the display substrate comprising a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising at least a pixel driving circuit and a light-emitting signal line, the pixel driving circuit being configured to output a driving current to a connected light-emitting device, and the light-emitting signal line being configured to provide a light-emitting control signal to the pixel driving circuit; in at least one circuit unit, the pixel driving circuit comprising at least a third transistor as a driving transistor, a fifth transistor as a first light-emitting control transistor, and a sixth transistor as a second light-emitting control transistor, the first electrode of the fifth transistor being connected to a first power supply line, the second electrode of the fifth transistor being connected to the first electrode of the third transistor, the first electrode of the sixth transistor being connected to the second electrode of the third transistor, and the second electrode of the sixth transistor being connected to the light-emitting device; the driving method comprising at least a light-emitting stage, in which, in at least one pixel driving circuit of at least one unit row, the conduction and disconnection of the fifth transistor are controlled by the light-emitting signal line in the previous unit row, and the conduction and disconnection of the sixth transistor are controlled by the light-emitting signal line in the current unit row.

19. The driving method according to claim 18, wherein: At least one circuit unit also includes a scan signal line, which is configured to provide a scan signal to the pixel driving circuit; the pixel driving circuit also includes a fourth transistor as a data writing transistor and a seventh transistor as a second initialization transistor, the first electrode of the fourth transistor is connected to the data signal line, the second electrode of the fourth transistor is connected to the first electrode of the third transistor, the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the second electrode of the sixth transistor; the driving method also includes a data writing phase and a reset phase, in at least one pixel driving circuit of at least one unit row, in the data writing phase, the conduction and disconnection of the fourth transistor are controlled by the scan signal line in the previous unit row, and in the reset phase, the conduction and disconnection of the seventh transistor are controlled by the scan signal line in the current unit row.

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