Source driving circuit and driving method thereof, display panel and display device

Abstract

The invention discloses a source electrode driving circuit, a driving method thereof, a display panel and a display device. The source electrode driving circuit comprises a plurality of driving units (1). The driving unit (1) includes: n voltage conversion circuits (101), where n is an integer greater than or equal to 1; each voltage conversion circuit (101) comprises a first switching circuit (1011) and a second switching circuit (1012); the control end of the first switching circuit (1011) and the control end of the second switching circuit (1012) are used for inputting control signals (B), and the control signals (B) comprise a first control signal and a second control signal; the second switching circuit (1012) is switched off in response to a first control signal, and the first switching circuit (1011) is switched on in response to the first control signal and outputs a first voltage signal (V1) and a first fixed voltage signal (Vc1) in sequence; the first switching circuit (1011) is turned off in response to a second control signal, and the second switching circuit (1012) is turned on in response to the second control signal and sequentially outputs a second voltage signal (V2) and a first fixed voltage signal (Vc2); the polarity of the first voltage signal (V1) is opposite to the polarity of the second voltage signal (V2).

Description

Source driving circuit and driving method thereof, display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a source driving circuit and a driving method thereof, a display panel, and a display device. Background Art

[0002] As the resolution of display panels increases, the required display data also increases accordingly, and the source driver chip becomes increasingly complex. For liquid crystal display panels, since the polarity of the liquid crystal needs to be reversed, the voltage resistance performance of the components in the source driver chip needs to meet the requirements to prevent the voltage change caused by polarity reversal from exceeding the upper voltage limit of the components. High-voltage components have a higher upper voltage resistance limit, but they are usually larger in size. For high-resolution display panels, the use of high-voltage components will result in a larger source driver chip, which is not conducive to achieving narrow-frame display.

[0003] Summary of the Invention

[0004] An embodiment of the present disclosure provides a source driving circuit, the source driving circuit comprising: a plurality of driving units;

[0005] The driving unit includes: n voltage conversion circuits; wherein n is an integer greater than or equal to 1;

[0006] Each voltage conversion circuit includes: a first switching circuit and a second switching circuit; the control end of the first switching circuit and the control end of the second switching circuit are used to input control signals, and the control signals include a first control signal and a second control signal; the second switching circuit is turned off in response to the first control signal, and the first switching circuit is turned on in response to the first control signal and outputs a first voltage signal and a first fixed voltage signal in sequence; the first switching circuit is turned off in response to the second control signal, and the second switching circuit is turned on in response to the second control signal and outputs a second voltage signal and a first fixed voltage signal in sequence; the polarity of the first voltage signal is opposite to the polarity of the second voltage signal.

[0007] In some embodiments, the voltage conversion circuit further includes: a control circuit;

[0008] The output end of the control circuit is electrically connected to the control end of the first switch circuit and the control end of the second switch circuit;

[0009] The control circuit is used to output a control signal.

[0010] In some embodiments, the control circuit includes a first inverter;

[0011] The input terminal of the first inverter is used to input a second fixed voltage signal;

[0012] The first power signal input terminal of the first inverter is used to input a first power signal, and the second power signal input terminal of the first inverter is used to input a second power signal;

[0013] The output end of the first inverter is electrically connected to the control end of the first switch circuit and / or the control end of the second switch circuit, and is used to output a control signal.

[0014] In some embodiments, the voltage of the second fixed voltage signal is 0V.

[0015] In some embodiments, the voltage of the first voltage signal is greater than 0 volts and less than or equal to a volts, and the voltage of the second voltage signal is greater than 0 volts and less than or equal to -a volts; a is a positive number;

[0016] The voltage of one of the first power signal and the second power signal is 0 volts, and the voltage of one of the first power signal and the second power signal is b volts; or, the voltage of one of the first power signal and the second power signal is 0 volts, and the voltage of one of the first power signal and the second power signal is -b volts; b is a positive number less than or equal to a.

[0017] In some embodiments, the first switching circuit and the second switching circuit include transmission gate switches.

[0018] In some embodiments, the transmission gate switch includes a P-type transistor and / or an N-type transistor.

[0019] In some embodiments, the transmission gate switch includes a P-type transistor and an N-type transistor; an input terminal of the P-type transistor is electrically connected to an input terminal of the N-type transistor, and an output terminal of the P-type transistor is electrically connected to an output terminal of the N-type transistor;

[0020] The transmission gate switch further includes: a second inverter;

[0021] In the first switching circuit, the input end of the second inverter is electrically connected to the control end of the N-type transistor, the output end of the second inverter is electrically connected to the control end of the P-type transistor, the input end of the P-type transistor and the input end of the N-type transistor are used to input the first voltage signal or the first fixed voltage signal, and the output end of the P-type transistor and the output end of the N-type transistor are used to output the first voltage signal or the first fixed voltage signal;

[0022] In the second switching circuit, the output end of the second inverter is electrically connected to the control end of the N-type transistor, the input end of the second inverter is electrically connected to the control end of the P-type transistor, the input end of the P-type transistor and the input end of the N-type transistor are used to input the second voltage signal or the first fixed voltage signal, and the output end of the P-type transistor and the output end of the N-type transistor are used to output the second voltage signal or the first fixed voltage signal.

[0023] In some embodiments, the driving unit further includes: a switch group; the switch group includes n third switch circuits, n fourth switch circuits, n fifth switch circuits, and n sixth switch circuits;

[0024] The output ends of the n third switch circuits are electrically connected to the input ends of the first switch circuits in the n voltage conversion circuits respectively; the input ends of the third switch circuits are used to input the first voltage signal;

[0025] The output ends of the n fourth switch circuits are electrically connected to the input ends of the second switch circuits in the n voltage conversion circuits respectively; the input ends of the fourth switch circuits are used to input the second voltage signal;

[0026] The output ends of the n fifth switching circuits are respectively electrically connected to the input ends of the first switching circuit in the n voltage conversion circuits, and the output ends of the n sixth switching circuits are respectively electrically connected to the input ends of the second switching circuit in the n voltage conversion circuits; the input ends of the fifth switching circuit and the input ends of the sixth switching circuit are used to input the first fixed voltage signal.

[0027] In some embodiments, the third switch circuit, the fourth switch circuit, the fifth switch circuit, and the sixth switch circuit each include a transmission gate switch.

[0028] In some embodiments, the transmission gate switch included in each of the third switch circuit, the fourth switch circuit, the fifth switch circuit, and the sixth switch circuit includes a P-type transistor and an N-type transistor, an input terminal of the P-type transistor is electrically connected to an input terminal of the N-type transistor, and an output terminal of the P-type transistor is electrically connected to an output terminal of the N-type transistor;

[0029] The transmission gate switches included in the third switch circuit, the fourth switch circuit, the fifth switch circuit, and the sixth switch circuit further include: a third inverter; an input end of the third inverter is electrically connected to the control end of the N-type transistor, and an output end of the third inverter is electrically connected to the control end of the P-type transistor;

[0030] The input end of the P-type transistor and the input end of the N-type transistor included in the third switch circuit are used to input the first voltage signal, and the output end of the P-type transistor and the input end of the N-type transistor included in the third switch circuit are electrically connected to the input end of the first switch circuit;

[0031] The input end of the P-type transistor and the input end of the N-type transistor included in the fourth switch circuit are used to input the second voltage signal, and the output end of the P-type transistor and the input end of the N-type transistor included in the fourth switch circuit are electrically connected to the input end of the second switch circuit;

[0032] The input end of the P-type transistor and the input end of the N-type transistor included in the fifth switch circuit are used to input the first fixed voltage signal, and the output end of the P-type transistor and the input end of the N-type transistor included in the fifth switch circuit are electrically connected to the input end of the first switch circuit;

[0033] The input end of the P-type transistor and the input end of the N-type transistor included in the sixth switch circuit are used to input the first fixed voltage signal, and the output end of the P-type transistor and the input end of the N-type transistor included in the sixth switch circuit are electrically connected to the input end of the second switch circuit.

[0034] In some embodiments, the substrate of the N-type transistor is electrically connected to the third power signal terminal, the substrate of the P-type transistor is electrically connected to the fourth power signal terminal, the signal at the third power signal terminal is a third power signal, and the signal at the fourth power signal terminal is a fourth power signal; the voltage of the third power signal is greater than the voltage of the fourth power signal;

[0035] The voltage of the third power supply signal of the third switch circuit and the fifth switch circuit is a volt, and the voltage of the fourth power supply signal of the third switch circuit and the fifth switch circuit is 0 volt; the voltage of the third power supply signal of the fourth switch circuit and the sixth switch circuit is 0 volt, and the voltage of the fourth power supply signal of the fourth switch circuit and the sixth switch circuit is -a volt.

[0036] In some embodiments, the driving unit further includes: n data selection circuits;

[0037] The data selection circuit includes m data selection switches, where m is an integer greater than 1;

[0038] Input terminals of the m data selection switches are electrically connected to the output terminal of the voltage conversion circuit.

[0039] In some embodiments, the voltage of the first fixed voltage signal is greater than or equal to −0.7 volts and less than or equal to 0.7 volts.

[0040] In some embodiments, n=1 or n=2.

[0041] An embodiment of the present disclosure provides a driving method for a source driver circuit, comprising:

[0042] Determine an output voltage signal corresponding to each voltage conversion circuit in each driving unit in the current frame; the output voltage signal is a first voltage signal or a second voltage signal, and the polarity of the first voltage signal is opposite to the polarity of the second voltage signal;

[0043] A control signal is loaded onto the voltage conversion circuit according to the output voltage signal, so that the second switch circuit in the voltage conversion circuit is turned off in response to the first control signal and the first switch circuit is turned on in response to the first control signal, and the first voltage signal is output through the first switch circuit in the data writing phase of the current frame, and the first fixed voltage signal is output through the first switch circuit in the charge sharing phase after the data writing phase; or, the first opening circuit in the voltage conversion circuit is turned off in response to the second control signal and the second switch circuit is turned off and on in response to the second control signal, and the second voltage signal is output through the second switch circuit in the data writing phase of the current frame, and the first fixed voltage signal is output through the second switch circuit in the charge sharing phase after the data writing phase.

[0044] In some embodiments, the voltage conversion circuit further includes: a control circuit, the control circuit including a first inverter; and a control signal for the voltage conversion circuit, specifically including:

[0045] A second fixed voltage signal is loaded onto the input terminal of the first inverter, a first power signal is loaded onto the first power signal input terminal of the first inverter, and a second power signal is loaded onto the second power signal input terminal of the first inverter, so that the output terminal of the first inverter outputs a control signal to the control terminals of the first switching circuit and the second switching circuit.

[0046] In some embodiments, n=1; applying a control signal to the voltage conversion circuit specifically includes:

[0047] The same first power signal and the same second power signal are applied to each first inverter, so that the output terminal of each first inverter outputs the first control signal or the second control signal.

[0048] In some embodiments, n=2; applying the control signal to the voltage conversion circuit specifically includes:

[0049] For each driving circuit, a first power supply signal of b volts and a second power supply signal of 0 volts are loaded onto the first inverter included in one of the two voltage conversion circuits, so that the output end of the first inverter outputs a first control signal; and a first power supply signal of 0 volts and a second power supply signal of -b volts are loaded onto the first inverter included in the other of the two voltage conversion circuits, so that the output end of the first inverter outputs a second control signal.

[0050] In some embodiments, the driving unit further includes: n third switching circuits, n fourth switching circuits, n fifth switching circuits, and n sixth switching circuits. After determining the voltage signal corresponding to each voltage conversion circuit in each driving unit in the current frame, the method further includes:

[0051] For each voltage conversion circuit, if it is determined that the voltage signal corresponding to the voltage conversion circuit is the first voltage signal, controlling a third switch circuit electrically connected to the voltage conversion circuit to be conductive during a data writing phase to input the first voltage signal, and controlling a fifth switch circuit electrically connected to the voltage conversion circuit to be conductive during a charge sharing phase to input the first fixed voltage signal;

[0052] For each voltage conversion circuit, if it is determined that the voltage signal corresponding to the voltage conversion circuit is the second voltage signal, the fourth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on during the data writing phase, and the second voltage signal is input; and the sixth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on during the charge sharing phase, and the first fixed voltage signal is input.

[0053] In some embodiments, n=1; for each driving unit, the method further includes:

[0054] In the data writing phase, the third switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on and the fifth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned off; in the charge sharing phase, the fifth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on and the third switch circuit electrically connected to the voltage conversion circuit is controlled to be turned off;

[0055] Alternatively, in the data writing stage, the fourth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on and the sixth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned off; in the charge sharing stage, the sixth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on and the fourth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned off.

[0056] In some embodiments, n=2; for each driving unit, the method further includes:

[0057] During the data writing phase, the third switch circuit electrically connected to one of the two voltage conversion circuits is controlled to be turned on and the fourth switch circuit is turned off, and the third switch circuit electrically connected to the other of the two voltage conversion circuits is controlled to be turned off and the fourth switch circuit is controlled to be turned on;

[0058] In the charge sharing stage, the fifth switch circuit electrically connected to one of the two voltage conversion circuits is controlled to be turned on and the sixth switch circuit is controlled to be turned off, and the fifth switch electrically connected to the other of the two voltage conversion circuits is controlled to be turned off and the sixth switch circuit is controlled to be turned on.

[0059] In some embodiments, the driving unit further includes: n data selection circuits; and the method further includes:

[0060] The m data selection switches in each data selection circuit are controlled to be turned on in sequence, outputting a first voltage signal or a second voltage signal in a data writing phase, and outputting a first fixed voltage signal in a charge sharing phase.

[0061] An embodiment of the present disclosure provides a display panel, which includes the source driving circuit provided by the embodiment of the present disclosure.

[0062] In some embodiments, the display panel specifically includes: an array substrate and an opposite substrate disposed opposite to each other, and a liquid crystal layer located between the array substrate and the opposite substrate;

[0063] The array substrate includes a plurality of data lines, and the plurality of data lines are electrically connected to the source driving circuit.

[0064] An embodiment of the present disclosure provides a display device, which includes the display panel provided by the embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0066] FIG1 is a schematic structural diagram of a source driver circuit provided by an embodiment of the present disclosure;

[0067] FIG2 is a schematic structural diagram of another source driver circuit provided by an embodiment of the present disclosure;

[0068] FIG3 is a schematic structural diagram of another source driver circuit provided by an embodiment of the present disclosure;

[0069] FIG4 is a schematic structural diagram of another source driver circuit provided by an embodiment of the present disclosure;

[0070] FIG5 is a schematic structural diagram of another source driver circuit provided by an embodiment of the present disclosure;

[0071] FIG6 is a schematic structural diagram of another source driver circuit provided by an embodiment of the present disclosure;

[0072] FIG7 is a schematic structural diagram of another source driver circuit provided by an embodiment of the present disclosure;

[0073] FIG8 is a schematic structural diagram of another source driver circuit provided by an embodiment of the present disclosure;

[0074] FIG9 is a timing diagram of a source driver circuit provided in an embodiment of the present disclosure;

[0075] FIG10 is a schematic structural diagram of another source driver circuit provided by an embodiment of the present disclosure;

[0076] FIG11 is a timing diagram of another source driving circuit provided by an embodiment of the present disclosure;

[0077] FIG12 is a schematic structural diagram of another source driver circuit provided by an embodiment of the present disclosure;

[0078] FIG13 is a timing diagram of another source driving circuit provided by an embodiment of the present disclosure;

[0079] FIG14 is a schematic flow chart of a driving method of a source driver circuit provided by an embodiment of the present disclosure;

[0080] FIG15 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0081] FIG16 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0082] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0083] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0084] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0085] It should be noted that for liquid crystal displays, the polarity of the liquid crystal needs to be reversed. Specifically, the source driver chip needs to switch the voltage polarity. For frame inversion, within a frame, the positive polarity voltage output range is 0 volts (V) to AVDD V, and the negative polarity voltage output range is -AVDD V to 0V, where AVDD is the maximum data voltage. Typically, the withstand voltage variation of high-voltage devices is 32V, the withstand voltage variation of medium-voltage devices is 6 or 8V, and the withstand voltage variation of low-voltage devices is 1.2V. When AVDD is 6V, the maximum variation of voltage polarity switching is 12V. This maximum variation is within the withstand voltage variation of high-voltage devices, so using source driver chips with high-voltage devices will not cause withstand voltage issues. However, high-voltage devices are larger, occupying approximately five times the area of ​​medium-voltage devices. For high-resolution display panels, using high-voltage devices will result in a larger source driver chip, which is not conducive to achieving narrow-frame displays. If a medium-voltage device is selected to reduce device size without changing AVDD, there is a risk of device damage because the maximum voltage variation exceeds the withstand voltage variation of the medium-voltage device.

[0086] An embodiment of the present disclosure provides a source driving circuit, as shown in FIG1 , the source driving circuit includes: a plurality of driving units 1;

[0087] The driving unit 1 includes: n voltage conversion circuits 101; wherein n is an integer greater than or equal to 1;

[0088] Each voltage conversion circuit 101 includes: a first switching circuit 1011 and a second switching circuit 1012; the control end of the first switching circuit 1011 and the control end of the second switching circuit 1012 are used to input a control signal B, and the control signal includes a first control signal B1 (not shown) and a second control signal B2 (not shown); the second switching circuit 1012 is turned off in response to the first control signal B1, and the first switching circuit 1011 is turned on in response to the first control signal B1 and sequentially outputs a first voltage signal V1 and a first fixed voltage signal Vc1; the first switching circuit 1011 is turned off in response to the second control signal B2, and the second switching circuit 1012 is turned on in response to the second control signal B2 and sequentially outputs a second voltage signal V2 and a first fixed voltage signal Vc1; the polarity of the first voltage signal V1 is opposite to that of the second voltage signal V2.

[0089] It should be noted that FIG1 only shows one voltage conversion circuit 101 .

[0090] It should be noted that the source driver circuit provided in the embodiments of the present disclosure is applied to a liquid crystal display. As shown in FIG1 , the output end of the voltage conversion circuit 101 is electrically connected to the data line dt of the liquid crystal display panel. Thus, the source driver circuit is used to provide data signals to the data lines and implement voltage polarity switching of the data signals. For example, for a voltage conversion circuit 101, if the first voltage signal V1 is required to be written to the data line dt in the i-th frame, the polarity needs to be switched, that is, the second voltage signal V2 is required to be written to the data line dt in the i+1th frame. In the i-th frame, the second switch circuit 1012 of the control voltage conversion circuit 101 is turned off and the first switch circuit 1011 is turned on. The first switch circuit 1011 first outputs the first voltage signal V1 and then outputs the first fixed voltage signal Vc1, i.e., charge sharing is performed to pull the output voltage of the voltage conversion circuit from the first voltage signal V1 to the first fixed voltage signal Vc1. Then, in the (i+1) frame, the first switch circuit 1011 of the control voltage conversion circuit 101 is turned off and the second switch circuit 1012 is turned on. The second switch circuit 1012 first outputs the second voltage signal V2 and then outputs the first fixed voltage signal Vc1, i.e., charge sharing is performed to pull the output voltage of the voltage conversion circuit from the second voltage signal V2 to the first fixed voltage signal Vc1. That is, using the source driver circuit provided by the embodiment of the present disclosure, the output voltage needs to be pulled to the first fixed voltage signal Vc1 before the next frame of data is written. If charge sharing is not performed and the first voltage signal V1 is directly converted into the second voltage signal V2, the voltage change is |V1-V2|. However, in the embodiment of the present disclosure, the output voltage is pulled to the first fixed voltage signal Vc1. The voltage change of the voltage conversion is |V1-Vc1| or |V2-Vc1|, both of which are smaller than |V1-V2|.

[0091] The source driving circuit provided by the embodiment of the present disclosure can realize the conversion of a first voltage signal and a second voltage signal of opposite polarity by using a driving unit including a voltage conversion circuit. In addition, before the conversion of the voltage signals of opposite polarity, charge sharing is required to pull the output voltage to the first fixed voltage signal, which can reduce the voltage change of the voltage signal polarity conversion while realizing the voltage signal polarity conversion, avoid the voltage change exceeding the withstand voltage change of the voltage conversion circuit, and thus avoid damage to the voltage conversion circuit. It is conducive to reducing the size of the first switching circuit and the second switching circuit included in the voltage conversion circuit. Compared with the prior art that uses high-voltage devices to realize voltage conversion, the size of the driving unit of the source driving circuit disclosed in the present disclosure is greatly reduced. When the source driving circuit is applied to high-resolution display products, even if the required number of driving units is large, narrow-border display can still be achieved due to the greatly reduced size of the driving unit.

[0092] In a specific implementation, the first switch circuit and the second switch circuit of the voltage conversion circuit provided in the embodiment of the present disclosure may use medium voltage devices, wherein the withstand voltage variation of the medium voltage devices is 6V to 8V.

[0093] In some embodiments, as shown in FIG2 , the voltage conversion circuit 101 further includes: a control circuit 1013 ;

[0094] An output terminal of the control circuit 1013 is electrically connected to a control terminal of the first switch circuit 1011 and a control terminal of the second switch circuit 1012;

[0095] The control circuit 1013 is configured to output a control signal B.

[0096] In a specific implementation, as shown in FIG2 , the control circuit 1013 outputs the same control signal B to the control terminal of the first switch circuit 1011 and the control terminal of the second switch circuit 1012. That is, under the control of the same control signal B, only one of the first switch circuit 1011 and the second switch circuit 1012 is turned on while the other is turned off. Specifically, when the control circuit 1013 outputs the first control signal B1, the first switch circuit 1011 is turned on while the second switch circuit 1012 is turned off. When the control circuit 1013 outputs the second control signal B2, the first switch circuit 1011 is turned off while the second switch circuit 1012 is turned on.

[0097] In some embodiments, as shown in FIG3 and FIG4 , the control circuit 1013 includes a first inverter 10131 ;

[0098] The input terminal of the first inverter 10131 is used to input the second fixed voltage signal Vc2;

[0099] The first power signal input terminal of the first inverter 10131 is used to input the first power signal Vp1, and the second power signal input terminal of the first inverter 10131 is used to input the second power signal Vp2;

[0100] An output terminal of the first inverter 10131 is electrically connected to a control terminal of the first switch circuit 1011 and / or a control terminal of the second switch circuit 1012 for outputting a control signal.

[0101] In some embodiments, as shown in FIG3 , the control circuit 1013 includes only a first inverter 10131 , the output of which is electrically connected to the control terminal of the first switch circuit 1011 and the control terminal of the second switch circuit 1012 , thereby saving wiring space and cost.

[0102] Of course, in a specific implementation, if there is sufficient wiring space, it can also be as shown in Figure 4, where the control circuit 1013 includes two first inverters 10131 electrically connected to the control end of the first switch circuit 1011 and the control end of the second switch circuit 1012, respectively. The reference numerals of the two first inverters 10131 are 10131-1 and 10131-2, respectively. The output end of the first inverter 10131-1 is electrically connected to the control end of the first switch circuit 1011, and the output end of the first inverter 10131-2 is electrically connected to the control end of the second switch circuit 1012. When the control circuit 1013 includes two first inverters 10131, the second fixed voltage signals Vc2 input to the input terminals of the two first inverters 10131 are the same, the first power supply signals Vp1 input to the first power supply signal input terminals of the two first inverters 10131 are the same, the second power supply signals Vp2 input to the second power supply signal input terminals of the two first inverters 10131 are the same, and the control signals output from the output terminals of the first inverters 10131 are the same.

[0103] In some embodiments, the voltage of the second constant voltage signal Vc2 is 0V.

[0104] In some embodiments, the voltage of the first voltage signal V1 is greater than or equal to 0V and less than or equal to a V, and the voltage of the second voltage signal V2 is less than or equal to 0V and greater than or equal to -a V; a is a positive number.

[0105] It should be noted that the embodiment of the present disclosure considers the first voltage signal V1 to be a positive voltage and the second voltage signal V2 to be a negative voltage. That is, during the data writing phase, the first switch circuit is used to output a positive voltage and the second switch circuit is used to output a negative voltage.

[0106] In a specific implementation, a is, for example, the maximum absolute value of the gamma voltage of the liquid crystal display device. The voltage conversion circuit, the first switch circuit, and the second switch circuit in the voltage conversion circuit have a withstand voltage variation greater than or equal to a V.

[0107] In some embodiments, the voltage of one of the first power signal Vp1 and the second power signal Vp2 is 0V, and the voltage of the other of the first power signal Vp1 and the second power signal Vp2 is b V; or, the voltage of one of the first power signal Vp1 and the second power signal Vp2 is 0V, and the voltage of the other of the first power signal Vp1 and the second power signal Vp2 is -b V; b is a positive number less than or equal to a.

[0108] In some embodiments, the voltage of the first power signal Vp1 is greater than the voltage of the second power signal Vp2. That is, the voltage of the first power signal Vp1 is bV and the voltage of the second power signal Vp2 is 0V; or, the voltage of the first power signal Vp1 is 0V and the voltage of the second power signal Vp2 is -bV.

[0109] In some embodiments, b=a.

[0110] In some embodiments, the voltage of the first power signal Vp1 is bV, the voltage of the second power signal Vp2 is 0V, and the control signal B outputted from the output terminal of the first inverter is the first control signal B1. When b=a, the voltage value of the first control signal B1 is b=a. When the voltage of the first power signal Vp1 is 0V and the voltage of the second power signal Vp2 is -bV, the control signal B outputted from the output terminal of the first inverter is the second control signal B2. When b=a, the voltage value of the second control signal B2 is -b=-a. That is, the first control signal B1 is a high voltage signal and the second control signal B2 is a low voltage signal. Under the control of the high voltage signal, the first switch circuit is turned on and the second switch circuit is turned off. Under the control of the low voltage signal, the first switch circuit is turned off and the second switch circuit is turned on.

[0111] In the source driver circuit provided by the embodiment of the present disclosure, a second fixed voltage signal is input to the input end of the first inverter, so that by adjusting the voltages of the first power supply signal and the second power supply signal, the output end of the first inverter can output signals of different voltages as control signals for the first switching circuit and the second switching circuit.

[0112] In some embodiments, the first switching circuit and the second switching circuit include transmission gate switches.

[0113] In some embodiments, the transmission gate switch includes a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), hereinafter referred to as a MOS transistor.

[0114] In some embodiments, the transmission gate switch includes a P-type transistor, ie, a PMOS transistor, and / or an N-type transistor, ie, an NMOS transistor.

[0115] In some embodiments, as shown in FIG5 , one of the first switch circuit 1011 and the second switch circuit 1012 includes a PMOS transistor, and the other of the first switch circuit 1011 and the second switch circuit 1012 includes an NMOS transistor. FIG5 illustrates an example in which the first switch circuit 1011 includes an NMOS transistor and the second switch circuit 1012 includes a PMOS transistor. Accordingly, when the first control signal is a high voltage signal and the second control signal is a low voltage signal, the NMOS transistor is turned on and the PMOS transistor is turned off under the control of the high voltage signal, and the NMOS transistor is turned off and the PMOS transistor is turned on under the control of the low voltage signal. In a specific implementation, the substrate of the NMOS transistor is electrically connected to the first power signal terminal, and the substrate of the PMOS transistor is electrically connected to the second power signal terminal. The first power signal terminal outputs a first power signal Vp1, and the second power signal terminal outputs a second power signal Vp2.

[0116] Alternatively, in some embodiments, the transmission gate switch is a complementary metal oxide semiconductor (CMOS) field effect transistor. CMOS includes an NMOS transistor and a PMOS transistor, wherein the input terminal of the PMOS transistor is electrically connected to the input terminal of the NMOS transistor, and the output terminal of the PMOS transistor is electrically connected to the output terminal of the NMOS transistor. As shown in FIG6 , the first switch circuit 1011 and the second switch circuit 1012 both include an NMOS transistor and a PMOS transistor; the substrate of the NMOS transistor is electrically connected to the first power signal terminal, and the substrate of the PMOS transistor is electrically connected to the second power signal terminal. The first power signal terminal outputs a first power signal Vp1, and the second power signal terminal outputs a second power signal Vp2, where Vp1 is bV and Vp2 is 0V, or Vp1 is 0V and Vp2 is -bV. The first switch circuit 1011 and the second switch circuit 1012 further include a second inverter 2. The first control signal is a high voltage signal, that is, under the control of the high voltage signal, the NMOS transistor and the PMOS transistor in the first switch circuit are both turned on and the NMOS transistor and the PMOS transistor in the second switch circuit are both turned off; under the control of the low voltage signal, the NMOS transistor and the PMOS transistor in the first switch circuit are both turned off and the NMOS transistor and the PMOS transistor in the second switch circuit are both turned on. As shown in FIG6 , in the first switch circuit 1011, the input end of the second inverter 2 is electrically connected to the control stage of the NMOS transistor, and the output end of the second inverter 2 is electrically connected to the control stage of the PMOS transistor. In the second switch circuit 1012, the input end of the second inverter 2 is electrically connected to the control stage of the PMOS transistor, and the output end of the second inverter 2 is electrically connected to the control stage of the NMOS transistor.

[0117] In some embodiments, in the first switch circuit, the input end of the PMOS transistor and the input end of the NMOS transistor are used to input the first voltage signal or the first fixed voltage signal, and the output end of the PMOS transistor and the output end of the NMOS transistor are used to output the first voltage signal or the first fixed voltage signal;

[0118] In the second switch circuit, the input end of the PMOS tube and the input end of the NMOS tube are used to input the second voltage signal or the first fixed voltage signal, and the output end of the PMOS tube and the output end of the NMOS tube are used to output the second voltage signal or the first fixed voltage signal.

[0119] In some embodiments, as shown in FIG7 , the driving unit 1 further includes: a switch group 102 ; the switch group 102 includes n third switch circuits 1021 , n fourth switch circuits 1022 , n fifth switch circuits 1023 , and n sixth switch circuits 1024 ;

[0120] The output terminals of the n third switch circuits 1021 are electrically connected to the input terminals of the first switch circuits 1011 in the n voltage conversion circuits 101 respectively; the input terminals of the third switch circuits 1021 are used to input the first voltage signal V1;

[0121] The output terminals of the n fourth switch circuits 1022 are electrically connected to the input terminals of the second switch circuits 1012 in the n voltage conversion circuits 101 respectively; the input terminals of the fourth switch circuits 1022 are used to input the second voltage signal V2;

[0122] The output ends of the n fifth switch circuits 1023 are respectively electrically connected to the input ends of the first switch circuit 1011 in the n voltage conversion circuits 101, and the output ends of the n sixth switch circuits 1024 are respectively electrically connected to the input ends of the second switch circuit 1012 in the n voltage conversion circuits 101; the input end 1023 of the fifth switch circuit and the input end of the sixth switch circuit 1024 are used to input the first fixed voltage signal Vc1.

[0123] In a specific implementation, when the third switch circuit 1021 is turned on, the fifth switch circuit 1023 is turned off, the first switch circuit 1011 is turned on, and the second switch circuit 1012 is turned off, the output end of the voltage conversion circuit 101 outputs the first voltage signal V1; when the third switch circuit 1021 is turned off, the fifth switch circuit 1023 is turned on, the first switch circuit 1011 is turned on, and the second switch circuit 1012 is turned off, the output end of the voltage conversion circuit 101 outputs the first fixed voltage signal Vc1; when the fourth switch circuit 1022 is turned on, the sixth switch circuit 1024 is turned off, the second switch circuit 1012 is turned on, and the first switch circuit 1011 is turned off, the output end of the voltage conversion circuit 101 outputs the second voltage signal V2; when the sixth switch circuit 1024 is turned on, the fourth switch circuit 1022 is turned off, the second switch circuit 1012 is turned on, and the first switch circuit 1011 is turned off, the output end of the voltage conversion circuit 101 outputs the first fixed voltage signal Vc1.

[0124] In some embodiments, the third switch circuit, the fourth switch circuit, the fifth switch circuit, and the sixth switch circuit each include a transmission gate switch.

[0125] In some embodiments, the transmission gate switches included in the third switch circuit, the fifth switch circuit, the fourth switch circuit, and the sixth switch circuit are NMOS transistors or PMOS transistors.

[0126] Alternatively, in some embodiments, the transmission gate switch is a CMOS tube transmission gate. As shown in FIG8 , the third switch circuit 1021, the fourth switch circuit 1022, the fifth switch circuit 1023, and the sixth switch circuit 1024 each include: a third inverter 3, an NMOS tube, and a PMOS tube; the input end of the PMOS tube is electrically connected to the input end of the NMOS tube, and the output end of the PMOS tube is electrically connected to the output end of the NMOS tube. In the CMOS tube transmission gate shown in FIG8 , the input end of the third inverter 3 is electrically connected to the control stage of the NMOS tube, and the output end of the third inverter 3 is electrically connected to the control stage of the PMOS tube. The control signal input to the control end of the first CMOS tube transmission gate is SW. When SW is high, both the NMOS tube and the PMOS tube are turned on.

[0127] In some embodiments, the input end of the P-type transistor (PMOS) and the input end of the N-type transistor (NMOS) included in the third switch circuit are used to input the first voltage signal, and the output end of the P-type transistor and the input end of the N-type transistor included in the third switch circuit are electrically connected to the input end of the first switch circuit;

[0128] The input end of the P-type transistor and the input end of the N-type transistor included in the fourth switch circuit are used to input the second voltage signal, and the output end of the P-type transistor and the input end of the N-type transistor included in the fourth switch circuit are electrically connected to the input end of the second switch circuit;

[0129] The input end of the P-type transistor and the input end of the N-type transistor included in the fifth switch circuit are used to input the first fixed voltage signal, and the output end of the P-type transistor and the input end of the N-type transistor included in the fifth switch circuit are electrically connected to the input end of the first switch circuit;

[0130] The input end of the P-type transistor and the input end of the N-type transistor included in the sixth switch circuit are used to input the first fixed voltage signal, and the output end of the P-type transistor and the input end of the N-type transistor included in the sixth switch circuit are electrically connected to the input end of the second switch circuit.

[0131] In some embodiments, as shown in FIG8 , the substrate of the NMOS transistor is electrically connected to the third power signal terminal, the substrate of the PMOS transistor is electrically connected to the fourth power signal terminal, the signal at the third power signal terminal is a third power signal Vp3, and the signal at the fourth power signal terminal is a fourth power signal Vp4. The voltage of the third power signal Vp3 is greater than the voltage of the fourth power signal Vp4.

[0132] In a specific implementation, the input end of the third switching circuit inputs a first voltage signal, that is, a positive polarity voltage signal, that is, the voltage input to the input end of the third switching circuit is greater than or equal to 0V and less than or equal to aV; and the input end of the fourth switching circuit inputs a second voltage signal, that is, a negative polarity voltage signal, that is, the voltage input to the input end of the fourth switching circuit is greater than or equal to -aV and less than or equal to 0V.

[0133] In some embodiments, the voltage of the third power signal Vp3 of the third switch circuit and the fifth switch circuit is aV, and the voltage of the fourth power signal Vp4 of the third switch circuit and the fifth switch circuit is 0V; the voltage of the third power signal Vp3 of the fourth switch circuit and the sixth switch circuit is 0V, and the voltage of the fourth power signal Vp4 of the fourth switch circuit and the sixth switch circuit is -aV.

[0134] In a specific implementation, the voltage variation of the third, fourth, fifth, and sixth switch circuits will not exceed aV. Therefore, the withstand voltage variation of the third, fourth, fifth, and sixth switch circuits in the switch group provided by the embodiment of the present disclosure is greater than or equal to aV. If a is 6V, the third, fourth, fifth, and sixth switch circuits can also be configured using medium-voltage devices. This helps reduce the size of the third, fourth, fifth, and sixth switch circuits included in the voltage conversion circuit, thereby helping to reduce the size of the source driver circuit and facilitate the realization of a narrow-frame display.

[0135] In some embodiments, n = 1. It should be noted that for a liquid crystal display panel, if the voltage polarity of the data signals written to all data lines is the same in each frame, each driving unit only needs to be provided with one voltage conversion circuit, and accordingly, the switch group includes one third switch circuit, one fourth switch circuit, one fifth switch circuit, and one sixth switch circuit.

[0136] In a specific implementation, a voltage polarity conversion can be performed once every j frames, where j is an integer greater than or equal to 1. If j is equal to 1, the voltage polarity of the odd-numbered frames is opposite to the voltage polarity of the even-numbered frames. If j is greater than 1, a group of j consecutive frames is considered, and the voltage polarity of each frame in the odd group is opposite to the voltage polarity of each frame in the even group. For example, if j = 2, the voltage polarity of some frames may be "positive, positive, negative, negative, positive, positive."

[0137] Next, taking the voltage polarity of the i-th frame as positive and the voltage polarity of the i+th frame as negative as an example, the working process of the source driving circuit provided by the embodiment of the present disclosure is described.

[0138] It should be noted that the structure of the voltage conversion circuit is shown in Figure 6, and the structures of the third, fifth, fourth, and sixth switch circuits are shown in Figure 8. A timing diagram of the voltage conversion circuit and the switch group control signals is shown in Figure 9, where SW1, SW2, SW3, and SW4 are the control signals SW at the control terminals of the third, fourth, fifth, and sixth switch circuits, respectively.

[0139] In the i-th frame, in the data writing phase t1, the control signal SW1 is 6V, the control signal SW3 is 0V, and the control signals SW2 and SW4 are -6V; Vp1 is 6V, Vp2 is 0V, and the control signals at the control ends of the first switch circuit and the second switch circuit are the first control signal B1, and B1 is 6V; the first switch circuit and the third switch circuit are turned on, and the second switch circuit, the fourth switch circuit, the fifth switch circuit, and the sixth switch circuit are turned off, and the first voltage signal V1 is transmitted to the first switch circuit through the third switch circuit and output. In the i-th frame, charge sharing is completed before the first moment a1 of the blanking phase t2. During the blanking phase t2, control signal SW1 is 0V, control signal SW3 is 6V, and control signals SW2 and SW4 are -6V. Before the first moment a1 of the blanking phase t2, Vp1 is 6V and Vp2 is 0V. The first and fifth switch circuits are on, while the second, third, fourth, and sixth switch circuits are off. The first fixed voltage signal Vc1 is transmitted to the first switch circuit via the fifth switch circuit and output. In the i-th frame, during the blanking phase t2, at the first moment a1, Vp1 drops to 0V. At the second moment a2 after the first moment a1, Vp2 drops to -6V.

[0140] In the i+1 frame, in the data writing phase t1, the control signals SW1, SW2, and SW3 are 0V, and the control signal SW4 is -6V; Vp1 is 0V, Vp2 is -6V, and the control signals at the control ends of the first switch circuit and the second switch circuit are the second control signal B2, and B2 is -6V; the second switch circuit and the fourth switch circuit are turned on, and the first switch circuit, the third switch circuit, and the sixth switch circuit are turned off, and the second voltage signal V2 is transmitted to the second switch circuit through the fourth switch circuit and output. In the i+1 frame, charge sharing is completed before the third moment a3 of the blanking phase t2. In the blanking phase t2, the control signals SW1, SW3, and SW4 are 0V, and the control signal SW2 is -6V. In the blanking phase t2, before the third moment a3, Vp1 is 0V and Vp2 is -6V. The second switch circuit and the sixth switch circuit are turned on, and the first switch circuit, the third switch circuit, the fifth switch circuit, and the fourth switch circuit are turned off. The first fixed voltage signal Vc1 is transmitted to the first switch circuit through the sixth switch circuit and output. In the i-th frame, in the blanking phase t2, at the third moment a3, Vp2 rises to 0V, and at the fourth moment a1 after the third moment a3, Vp1 rises to 6V.

[0141] Alternatively, in some embodiments, n=2.

[0142] It should be noted that, for a liquid crystal display panel, if for each frame, half of the voltage polarity of the data signals written to all data lines is positive and the other half is negative. In some embodiments, as shown in FIG10 , each driving unit 1 is provided with two voltage conversion circuits 101, and the two voltage conversion circuits 101 are respectively a first voltage conversion circuit 101-1 and a second voltage conversion circuit 101-2. Correspondingly, the switch group includes two third switch circuits 1021, two fourth switch circuits 1022, two fifth switch circuits 1023, and two sixth switch circuits 1024. The third switch circuit 1021 marked in the figure 1021-1 and the fifth switch circuit 1023 marked in the figure 1023-1 are electrically connected to the first switch circuit 1011 in the first voltage conversion circuit 101-1, the fourth switch circuit 1022 marked in the figure 1022-1 and the sixth switch circuit 1024 marked in the figure 1024 are electrically connected to the first switch circuit 1011 in the first voltage conversion circuit 101-1. The first and second voltage conversion circuits 101-1 and 101-2 are electrically connected to the second switch circuit 1012. The third switch circuit 1021, referenced 1021-2, and the fifth switch circuit 1023, referenced 1023-2, are electrically connected to the first switch circuit 1011 in the second voltage conversion circuit 101-2. The fourth switch circuit 1022, referenced 1022-2, and the sixth switch circuit 1024, referenced 1024-2, are electrically connected to the second switch circuit 1012 in the second voltage conversion circuit 101-2. In a specific implementation, during the data writing phase, one of the first and second voltage conversion circuits 101-1 and 101-2 outputs a positive voltage, and the other outputs a negative voltage. The first switch circuit 1011 in the first voltage conversion circuit 101-1 and the first switch circuit 1011 in the second voltage conversion circuit 101-2 are not turned on at the same time. The second switch circuit 1012 in the first voltage conversion circuit 101-1 and the second switch circuit 1012 in the second voltage conversion circuit 101-2 are not turned on at the same time. The two third switch circuits 1021 are not turned on at the same time, the two fourth switch circuits 1022 are not turned on at the same time, the two fifth switch circuits 1023 are not turned on at the same time, and the two sixth switch circuits 1024 are not turned on at the same time. For ease of distinction, the first power supply signal and the second power supply signal in the first voltage conversion circuit 101-1 are represented by Vp1 and Vp2, respectively, and the first power supply signal and the second power supply signal in the second voltage conversion circuit 101-2 are represented by Vp1' and Vp2', respectively. Within the same drive unit, Vp1 is not equal to Vp1', and Vp2 is not equal to Vp2'.

[0143] In a specific implementation, voltage polarity conversion can be performed once every j frames, where j is an integer greater than or equal to 1. If j is equal to 1, for a data line, the voltage polarity of its data signal in odd-numbered frames is opposite to the voltage polarity in even-numbered frames. If j is greater than 1, a group of j consecutive frames is considered, and for a data line, the voltage polarity of its data signal in each frame of the odd group is opposite to the voltage polarity in each frame of the even group. For example, if j = 2, the voltage polarity of some frames may be "positive, positive, negative, negative, positive, positive."

[0144] Next, taking the example that the voltage polarity output by the first voltage conversion circuit of the i-th frame is positive and the voltage polarity output by the second voltage conversion circuit is negative, and the voltage polarity output by the first voltage conversion circuit of the i+ frame is negative and the voltage polarity output by the second voltage conversion circuit is positive, and taking the example that the voltage polarity of the odd frame is opposite to the voltage polarity of the even frame, the working process of the source driving circuit provided by the embodiment of the present disclosure is illustrated.

[0145] It should be noted that, taking FIG. 10 as an example, the specific structure of the voltage conversion circuit 101 is shown in FIG. 6 , and the specific structures of the third switch circuit 1021 , the fifth switch circuit 1023 , the fourth switch circuit 1022 and the sixth switch circuit 1024 are shown in FIG. 8 . A timing diagram of the voltage conversion circuit and the switch group control signals is shown in FIG11 , wherein SW1, SW2, SW3, and SW4 are control signals SW for the control terminals of the third switch circuit 1021 (reference numeral 1021-1), the fourth switch circuit 1022 (reference numeral 1022-1), the fifth switch circuit 1023 (reference numeral 1023-1), and the sixth switch circuit 1024 (reference numeral 1024-1), respectively. SW1′, SW2′, SW3′, and SW4′ are control signals SW for the control terminals of the third switch circuit 1021 (reference numeral 1021-2), the fourth switch circuit 1022 (reference numeral 1022-2), the fifth switch circuit 1023 (reference numeral 1023-2), and the sixth switch circuit 1024 (reference numeral 1024-2), respectively. In a specific implementation, to facilitate control, SW3 and SW3′ are inverse signals of each other, and SW4 and SW4′ are inverse signals of each other. It should be noted that the fact that SW3 and SW3' are mutually inverse signals means that when the fifth switch circuit whose control signal is SW3 at the control end is turned on in response to the SW3 signal, the fifth switch circuit whose control signal is SW3' at the control end is turned off in response to the SW3' signal; when the fifth switch circuit whose control signal is SW3 at the control end is turned off in response to the SW3 signal, the fifth switch circuit whose control signal is SW3' at the control end is turned on in response to the SW3' signal. The fact that SW4 and SW4' are mutually inverse signals means that when the sixth switch circuit whose control signal is SW4 at the control end is turned on in response to the SW4 signal, the sixth switch circuit whose control signal is SW4' at the control end is turned off in response to the SW4' signal; when the sixth switch circuit whose control signal is SW4 at the control end is turned off in response to the SW4 signal, the sixth switch circuit whose control signal is SW4' at the control end is turned on in response to the SW4' signal.

[0146] In the i-th frame, in the data writing phase t1, the control signals SW1 and SW3' are 6V, the control signals SW1', SW2', SW3, and SW4 are 0V, and the control signals SW2 and SW4' are -6V; Vp1 is 6V, Vp2 and Vp1' are 0V, and Vp2' is -6V; the control signals at the control ends of the first switch circuit 1011 and the second switch circuit 1012 in the first voltage conversion circuit 101-1 are the first control signal B1, and B1 is 6V; the control signals at the control ends of the first switch circuit 1011 and the second switch circuit 1012 in the second voltage conversion circuit 101-2 are the second control signal B2, and B2 is -6V; the first switch circuit 1011 in the first voltage conversion circuit 101-1, the second switch circuit 1012 in the second voltage conversion circuit 101-2, the third switch circuit 1021 with the reference numeral 1021-1, the fourth switch circuit 1022 with the reference numeral 1022-2, and the fourth switch circuit 1023 with the reference numeral 1024-3 are connected to the first switch circuit 1011 and the second switch circuit 1012. The fifth switch circuit 1023 marked as 1023-2 in the figure and the sixth switch circuit 1024 marked as 1024-1 in the figure are turned on, the second switch circuit 1012 in the first voltage conversion circuit 101-1, the first switch circuit 1011 in the second voltage conversion circuit 101-2, the third switch circuit 1021 in the figure, the fourth switch circuit 1022 in the figure, the fifth switch circuit 1023 in the figure, and the sixth switch circuit 1024 in the figure are turned off, the first voltage signal V1 is transmitted to the first switch circuit 1011 in the first voltage conversion circuit 101-1 through the third switch circuit 1021 in the figure and output, and the second voltage signal V2 is transmitted to the second switch circuit 1012 in the second voltage conversion circuit 101-2 through the fourth switch circuit 1023 in the figure and output.

[0147] In the i-th frame, charge sharing is completed before the first moment a1 of the blanking phase t2. In the blanking phase t2, the control signals SW1, SW1', SW3', and SW4' are 0V, the control signal SW3 is 6V, and the control signals SW2, SW2', and SW4 are -6V; Vp1 is 6V, Vp2 and Vp1' are 0V, and Vp2' is -6V; the control signals at the control ends of the first switch circuit 1011 and the second switch circuit 1012 in the first voltage conversion circuit 101-1 are the first control signal B1, and B1 is 6V; the control signals at the control ends of the first switch circuit 1011 and the second switch circuit 1012 in the second voltage conversion circuit 101-2 are the second control signal B2, and B2 is -6V; before the first moment a1 of the blanking phase t2, Vp1 is 6V, Vp2 and Vp1' are 0V, and Vp2' is -6V ; The first switch circuit 1011 in the first voltage conversion circuit 101-1, the second switch circuit 1012 in the second voltage conversion circuit 101-2, the fifth switch circuit 1023 with the reference numeral 1023-1, and the sixth switch circuit 1024 with the reference numeral 1024-2 are turned on, and the third switch circuit 1022, the fourth switch circuit 1023, the fifth switch circuit 1023 with the reference numeral 1023-2, and the sixth switch circuit 1024 with the reference numeral 1024-1 are turned off, and the first fixed voltage signal Vc1 is transmitted to the output of the first switch circuit 1011 in the first voltage conversion circuit 101-1 through the fifth switch circuit 1023 with the reference numeral 1023-1, and the first fixed voltage signal Vc1 is transmitted to the output of the second switch circuit 1012 in the second voltage conversion circuit 101-2 through the sixth switch circuit 1024 with the reference numeral 1024-2. In the i-th frame, in the blanking phase t2, at the first moment a1, Vp1 drops to 0V and Vp2' rises to 0V. At the second moment a2 after the first moment a1, Vp2 drops to -6V and Vp1' rises to 6V.

[0148] In the (i+1)th frame, in the data writing phase t1, the control signals SW1' and SW3 are 6 V, the control signals SW1, SW2, SW3', and SW4' are 0 V, and the control signals SW2' and SW4 are -6 V; Vp1 and Vp2' are 0 V, Vp2 is -6 V, and Vp1' is 6 V; the control signals at the control ends of the first switch circuit 1011 and the second switch circuit 1012 in the first voltage conversion circuit 101-1 are the second control signal B2, and B2 is -6 V; the control signals at the control ends of the first switch circuit 1011 and the second switch circuit 1012 in the second voltage conversion circuit 101-2 are the first control signal B1, and B1 is 6 V; the second switch circuit 1012 in the first voltage conversion circuit 101-1, the first switch circuit 1011 in the second voltage conversion circuit 101-2, the third switch circuit 1021 referenced 1021-2, the fourth switch circuit 1022 referenced 1022-1, The fifth switch circuit 1023 with a reference numeral 1023-1 and the sixth switch circuit 1024 with a reference numeral 1024-2 are turned on, and the first switch circuit 1011 in the first voltage conversion circuit 101-1, the second switch circuit 1012 in the second voltage conversion circuit 101-2, the third switch circuit 1021 with a reference numeral 1021-1, the fourth switch circuit 1022 with a reference numeral 1022-2, the fifth switch circuit 1023 with a reference numeral 1023-2, and the sixth switch circuit 1024-1 are turned off. The first voltage signal V1 is transmitted to the first switch circuit 1011 in the second voltage conversion circuit 101-1 through the third switch circuit 1021 with a reference numeral 1021-2 and outputted, and the second voltage signal V2 is transmitted to the second switch circuit 1012 in the first voltage conversion circuit 101-1 through the fourth switch circuit 1023 with a reference numeral 1022-1 and outputted.

[0149] In the i+1 frame, charge sharing is completed before the third moment a3 of the blanking phase t2. In the blanking phase t2, the control signals SW1, SW1', SW3, and SW4 are 0V, the control signal SW3' is 6V, and the control signals SW2, SW2', and SW4 are -6V; Vp1' is 6V, Vp2 is -6V, and Vp1, Vp2' is 0V; the control signals at the control ends of the first switch circuit 1011 and the second switch circuit 1012 in the first voltage conversion circuit 101-1 are the second control signal B2, and B2 is -6V; the control signals at the control ends of the first switch circuit 1011 and the second switch circuit 1012 in the second voltage conversion circuit 101-2 are the first control signal B1, and B1 is 6V; the second switch circuit 1012 in the first voltage conversion circuit 101-1, the first switch circuit 1011 in the second voltage conversion circuit 101-2, the fifth switch circuit 1023 with the reference numeral 1023-2, and the sixth switch circuit 1024 with the reference numeral 1024-1 are turned on, and the first switch circuit 1012 in the first voltage conversion circuit 101-1 is turned on. In the blanking phase t2, at a third time a3, Vp2 rises to 0V and Vp1' falls to 0V. At a fourth time a4 following the third time a3, Vp1 rises to 6V and Vp2' falls to -6V.

[0150] In some embodiments, as shown in FIG12 , the driving unit 1 further includes: n data selection circuits 103 ;

[0151] The data selection circuit includes m data selection switches, where m is an integer greater than 1;

[0152] Input terminals of the m data selection switches are electrically connected to the output terminal of the voltage conversion circuit 101 .

[0153] In some embodiments, as shown in FIG12 , the input of the data selection circuit 103 is electrically connected to the output of the voltage conversion circuit 101, and the output of the data selection circuit 103 is electrically connected to the data line dt. Specifically, the input of the data selection switch is electrically connected to the output of the voltage conversion circuit 101, and the output of the data selection switch is electrically connected to the data line dt. A control signal is input to the control terminal of the data selection switch. When the data selection switch is turned on in response to the control signal, it outputs a first voltage signal, a second voltage signal, or a first fixed voltage signal.

[0154] In some embodiments, as shown in FIG12 , the driving unit 1 includes two data selection circuits 103 , namely a first data selection circuit 103 - 1 and a second data selection circuit 103 - 2 . The first data selection circuit 103 - 1 is electrically connected to the first voltage conversion circuit 101 - 1 , and the second data selection circuit 103 - 2 is electrically connected to the second voltage conversion circuit 101 - 2 .

[0155] That is, in the source driving circuit provided by the embodiment of the present disclosure, a voltage conversion circuit in the driving unit can be electrically connected to multiple data lines through a data selection circuit. Compared with the case where one voltage conversion circuit is electrically connected to one data line, the number of driving units set can be reduced, thereby saving the area of ​​the source driving circuit.

[0156] In some embodiments, as shown in FIG12 , m=6.

[0157] In some embodiments, the data selection switch is a MOS tube transmission gate. For example, the data selection switch is an NMOS tube. The timing diagram of the two data selection circuits 103 shown in Figure 12 is shown in Figure 13, where SMUX <1> ~SMUX <12> dt1 to dt12. The timing diagram of the switch group and the voltage conversion circuit is shown in FIG11. In the case of a data write phase in the i-th frame, the data selection switches electrically connected to the data lines dt1 to dt6 output a first voltage signal, and the data selection switches electrically connected to the data lines dt7 to dt12 output a second voltage signal. In the data write phase in the (i+1) frame, the data selection switches electrically connected to the data lines dt1 to dt6 output a second voltage signal, and the data selection switches electrically connected to the data lines dt7 to dt12 output a first voltage signal.

[0158] In some embodiments, the voltage of the first constant voltage signal Vc1 is greater than or equal to −0.7V and less than or equal to 0.7V.

[0159] In a specific implementation, for example, the voltage of the first fixed voltage signal Vc1 is 0V.

[0160] Based on the same inventive concept, the embodiment of the present disclosure also provides another driving method of the source driver circuit provided by the embodiment of the present disclosure, as shown in FIG14 , including:

[0161] S101, determining an output voltage signal corresponding to each voltage conversion circuit in each driving unit in a current frame; the output voltage signal is a first voltage signal or a second voltage signal, and the polarity of the first voltage signal is opposite to the polarity of the second voltage signal;

[0162] S102. Load a control signal on the voltage conversion circuit according to the output voltage signal, so that the second switch circuit in the voltage conversion circuit is turned off in response to the first control signal and the first switch circuit is turned on in response to the first control signal, and the first voltage signal is output through the first switch circuit in the data writing phase of the current frame, and the first fixed voltage signal is output through the first switch circuit in the charge sharing phase after the data writing phase; or, so that the first opening circuit in the voltage conversion circuit is turned off in response to the second control signal and the second switch circuit is turned off and turned on in response to the second control signal, and the second voltage signal is output through the second switch circuit in the data writing phase of the current frame, and the first fixed voltage signal is output through the second switch circuit in the charge sharing phase after the data writing phase.

[0163] The driving method of the source driver circuit provided by the embodiment of the present disclosure, before the voltage signal of opposite polarity is converted, charge sharing is performed in the charge sharing stage to pull the output voltage to a first fixed voltage signal, which can reduce the voltage change of the voltage signal polarity conversion while realizing the voltage signal polarity conversion, avoid the voltage change exceeding the withstand voltage change of the voltage conversion circuit, and thus avoid damage to the voltage conversion circuit. It is beneficial to reduce the size of the first switching circuit and the second switching circuit included in the voltage conversion circuit. Compared with the prior art that uses high-voltage devices to realize voltage conversion, the size of the driving unit of the source driver circuit disclosed in the present disclosure is greatly reduced. When the source driver circuit is applied to high-resolution display products, even if the required number of driving units is large, narrow-frame display can still be achieved due to the greatly reduced size of the driving unit.

[0164] In some embodiments, the voltage conversion circuit further includes: a control circuit, the control circuit including a first inverter; and a control signal for the voltage conversion circuit, specifically including:

[0165] A second fixed voltage signal is loaded onto the input terminal of the first inverter, a first power signal is loaded onto the first power signal input terminal of the first inverter, and a second power signal is loaded onto the second power signal input terminal of the first inverter, so that the output terminal of the first inverter outputs a control signal to the control terminals of the first switching circuit and the second switching circuit.

[0166] In a specific implementation, the second fixed voltage signal applied to the input of the first inverter is 0V, the first power signal Vp1 applied to the first power signal input of the first inverter is bV, and the second power signal Vp2 applied to the second power signal input of the first inverter is 0V. The output of the first inverter outputs the first control signal B1 to the control terminals of the first and second switch circuits. B1 is bV. When b=a=6, B1 is 6V. The second fixed voltage signal applied to the input of the first inverter is 0V, the first power signal Vp1 applied to the first power signal input of the first inverter is 0V, and the second power signal Vp2 applied to the second power signal input of the first inverter is -bV. The output of the first inverter outputs the second control signal B2 to the control terminals of the first and second switch circuits. B2 is -bV. When b=a=6, B2 is -6V.

[0167] In some embodiments, n=1; applying a control signal to the voltage conversion circuit specifically includes:

[0168] The same first power signal and the same second power signal are applied to each first inverter, so that the output terminal of each first inverter outputs the first control signal or the second control signal.

[0169] In a specific implementation, the voltage polarity of the current frame is positive, and a control signal is applied to the voltage conversion circuit, specifically including:

[0170] The second fixed voltage signal loaded onto the input terminal of each first inverter is 0V, the first power signal Vp1 loaded onto the first power signal input terminal of each first inverter is bV, and the second power signal Vp2 loaded onto the second power signal input terminal of each first inverter is 0V, so that the output terminal of each first inverter outputs the first control signal to the control terminal of the first switching circuit and the second switching circuit.

[0171] In a specific implementation, the voltage polarity of the current frame is negative, and a control signal is applied to the voltage conversion circuit, specifically including:

[0172] The second fixed voltage signal applied to the input terminal of each first inverter is 0V, the first power signal Vp1 applied to the first power signal input terminal of each first inverter is 0V, and the second power signal Vp2 applied to the second power signal input terminal of each first inverter is -bV, so that the output terminal of each first inverter outputs the second control signal to the control terminal of the first switch circuit and the second switch circuit.

[0173] In some embodiments, the driving unit further includes: n third switching circuits, n fourth switching circuits, n fifth switching circuits, and n sixth switching circuits. After determining the voltage signal corresponding to each voltage conversion circuit in each driving unit in the current frame, the method further includes:

[0174] For each voltage conversion circuit, if it is determined that the voltage signal corresponding to the voltage conversion circuit is the first voltage signal, controlling a third switch circuit electrically connected to the voltage conversion circuit to be conductive during a data writing phase to input the first voltage signal, and controlling a fifth switch circuit electrically connected to the voltage conversion circuit to be conductive during a charge sharing phase to input the first fixed voltage signal;

[0175] For each voltage conversion circuit, if it is determined that the voltage signal corresponding to the voltage conversion circuit is the second voltage signal, the fourth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on during the data writing phase, and the second voltage signal is input; and the sixth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on during the charge sharing phase, and the first fixed voltage signal is input.

[0176] In some embodiments, n=1; for each driving unit, the following further comprises:

[0177] In the data writing phase, the third switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on and the fifth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned off; in the charge sharing phase, the fifth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on and the third switch circuit electrically connected to the voltage conversion circuit is controlled to be turned off;

[0178] Alternatively, in the data writing stage, the fourth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on and the sixth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned off; in the charge sharing stage, the sixth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on and the fourth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned off.

[0179] Specifically, the voltage polarity of the current frame is positive. During the data writing phase, the third switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on and the fifth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned off. During the charge sharing phase, the fifth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on and the third switch circuit electrically connected to the voltage conversion circuit is controlled to be turned off. During the data writing phase, the fourth and sixth switch circuits electrically connected to the voltage conversion circuit are controlled to be turned off. During the charge sharing phase, the fourth and sixth switch circuits electrically connected to the voltage conversion circuit are controlled to be turned off.

[0180] Specifically, the voltage polarity of the current frame is negative. During the data writing phase, the fourth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on and the sixth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned off. During the charge sharing phase, the sixth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on and the fourth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned off. During the data writing phase, the third and fifth switch circuits electrically connected to the voltage conversion circuit are controlled to be turned off. During the charge sharing phase, the third and fifth switch circuits electrically connected to the voltage conversion circuit are controlled to be turned off.

[0181] In a specific implementation, when n=1, a timing diagram of the driving method of the source driving circuit provided by the embodiment of the present disclosure is shown in FIG9 .

[0182] The current frame is the i-th frame. The driving method of the source driving circuit provided by the embodiment of the present disclosure includes:

[0183] In the data writing phase t1, the control signals loaded onto the control ends of the third switch circuit, the fourth switch circuit, the fifth switch circuit, and the sixth switch circuit are SW1, SW2, SW3, and SW4, respectively, and the voltages of SW1, SW2, SW3, and SW4 are 6V, -6V, 0V, and -6V, respectively, so that the third switch circuit is turned on and the fourth switch circuit, the fifth switch circuit, and the sixth switch circuit are turned off; and the second fixed voltage signal loaded onto the input end of each first inverter is 0V, the first power supply signal Vp1 loaded onto the first power supply signal input end of each first inverter is bV, and the second power supply signal Vp2 loaded onto the second power supply signal input end of each first inverter is 0V, so that the output end of each first inverter outputs the first control signal to the control ends of the first switch circuit and the second switch circuit, so that the first switch circuit is turned on and the second switch circuit is turned off; so that the first voltage signal V1 is transmitted to the first switch circuit through the third switch circuit and output.

[0184] During a charge sharing phase before the first moment a1 of a blanking phase t2, voltages of 0V, -6V, 6V, and -6V are applied to the control terminals of the third, fourth, fifth, and sixth switch circuits, respectively, to turn on the fifth switch circuit and turn off the third, fourth, and sixth switch circuits. Furthermore, a second fixed voltage signal of 0V is applied to the input terminal of each first inverter, a first power signal Vp1 of bV is applied to the first power signal input terminal of each first inverter, and a second power signal Vp2 of 0V is applied to the second power signal input terminal of each first inverter, so that the output terminal of each first inverter outputs a first control signal to the control terminals of the first and second switch circuits, turning on the first switch circuit and turning off the second switch circuit. Furthermore, the first fixed voltage signal Vc1 is transmitted to the first switch circuit via the fifth switch circuit and outputted.

[0185] In the blanking phase t2, at the first moment a1, the first power signal Vp1 applied to the first power signal input terminal of each first inverter is 0V. At the second moment a2 after the first moment a1, the second power signal Vp2 applied to the second power signal input terminal of each first inverter is -6V.

[0186] The current frame is the (i+1)th frame. The driving method of the source driving circuit provided by the embodiment of the present disclosure includes:

[0187] In the data writing phase t1, voltages of 0V, 0V, 0V, and -6V are respectively applied to the control terminals of the third switch circuit, the fourth switch circuit, the fifth switch circuit, and the sixth switch circuit to turn on the fourth switch circuit and turn off the third switch circuit, the fifth switch circuit, and the sixth switch circuit; and a second fixed voltage signal of 0V is applied to the input terminal of each first inverter, a first power signal Vp1 of 0V is applied to the first power signal input terminal of each first inverter, and a second power signal Vp2 of -bV is applied to the second power signal input terminal of each first inverter, so that the output terminal of each first inverter outputs a second control signal to the control terminals of the first switch circuit and the second switch circuit, so that the first switch circuit is turned off and the second switch circuit is turned on; so that the second voltage signal V2 is transmitted to the second switch circuit through the fourth switch circuit and output.

[0188] During a charge sharing phase before a third moment a3 of a blanking phase t2, voltages of 0V, -6V, 0V, and 0V are applied to the control terminals of the third, fourth, fifth, and sixth switch circuits, respectively, to turn on the sixth switch circuit and turn off the third, fourth, and fifth switch circuits. Furthermore, a second fixed voltage signal of 0V is applied to the input terminal of each first inverter, a first power signal Vp1 of 0V is applied to the first power signal input terminal of each first inverter, and a second power signal Vp2 of -bV is applied to the second power signal input terminal of each first inverter, so that the output terminal of each first inverter outputs a second control signal to the control terminals of the first and second switch circuits, turning off the first switch circuit and turning on the second switch circuit. Furthermore, the first fixed voltage signal Vc1 is transmitted to the second switch circuit via the sixth switch circuit and outputted.

[0189] In the blanking phase t2, at the third moment a3, the first power signal Vp1 loaded onto the first power signal input terminal of each first inverter is 6V. At the fourth moment a1 after the third moment a3, the second power signal Vp2 loaded onto the second power signal input terminal of each first inverter is 0V.

[0190] In some embodiments, n=2; applying the control signal to the voltage conversion circuit specifically includes:

[0191] For each driving circuit, a first power supply signal of b volts and a second power supply signal of 0 volts are loaded onto the first inverter included in one of the two voltage conversion circuits, so that the output end of the first inverter outputs a first control signal; and a first power supply signal of 0 volts and a second power supply signal of -b volts are loaded onto the first inverter included in the other of the two voltage conversion circuits, so that the output end of the first inverter outputs a second control signal.

[0192] In a specific implementation, for any driving circuit, in the data writing phase of the current frame, the polarity of the voltage signal output by the first voltage conversion circuit is positive, and the polarity of the voltage signal output by the second voltage conversion circuit is negative, and a control signal is applied to the voltage conversion circuit of the driving circuit, specifically including:

[0193] In the first voltage conversion circuit, the second fixed voltage signal applied to the input terminal of the first inverter is 0V, the first power signal Vp1 applied to the first power signal input terminal of the first inverter is bV, and the second power signal Vp2 applied to the second power signal input terminal of the first inverter is 0V, so that the output terminal of the first inverter outputs the first control signal to the control terminals of the first switch circuit and the second switch circuit;

[0194] In the second voltage conversion circuit, the second fixed voltage signal loaded to the input end of the first inverter is 0V, the first power signal Vp1 loaded to the first power signal input end of the first inverter is 0V, and the second power signal Vp2 loaded to the second power signal input end of the first inverter is -bV, so that the output end of the first inverter outputs the second control signal to the control end of the first switching circuit and the second switching circuit.

[0195] In a specific implementation, for any driving circuit, during the data writing phase of the current frame, the polarity of the voltage signal output by the second voltage conversion circuit is positive, and the polarity of the voltage signal output by the first voltage conversion circuit is negative, and a control signal is applied to the voltage conversion circuit of the driving circuit, specifically including:

[0196] In the first voltage conversion circuit, the second fixed voltage signal applied to the input terminal of the first inverter is 0V, the first power signal Vp1 applied to the first power signal input terminal of the first inverter is 0V, and the second power signal Vp2 applied to the second power signal input terminal of the first inverter is -bV, so that the output terminal of the first inverter outputs the second control signal to the control terminals of the first switch circuit and the second switch circuit;

[0197] In the second voltage conversion circuit, the second fixed voltage signal loaded to the input end of the first inverter is 0V, the first power signal Vp1 loaded to the first power signal input end of the first inverter is bV, and the second power signal Vp2 loaded to the second power signal input end of the first inverter is 0V, so that the output end of the first inverter outputs the first control signal to the control end of the first switching circuit and the second switching circuit.

[0198] In some embodiments, n=2; for each driving unit, the following further comprises:

[0199] During the data writing phase, the third switch circuit electrically connected to one of the two voltage conversion circuits is controlled to be turned on and the fourth switch circuit is turned off, and the third switch circuit electrically connected to the other of the two voltage conversion circuits is controlled to be turned off and the fourth switch circuit is controlled to be turned on;

[0200] In the charge sharing stage, the fifth switch circuit electrically connected to one of the two voltage conversion circuits is controlled to be turned on and the sixth switch circuit is controlled to be turned off, and the fifth switch electrically connected to the other of the two voltage conversion circuits is controlled to be turned off and the sixth switch circuit is controlled to be turned on.

[0201] In some embodiments, n=2; for each driving unit, the following further comprises:

[0202] One of the two fifth switch circuits electrically connected to the two voltage conversion circuits is controlled to be turned on and the other to be turned off.

[0203] In some embodiments, in the current frame, among the two fifth switching circuits included in each driving unit, one is turned on and the other is turned off in any stage. The fifth switching circuit turned on in the data writing stage is turned off in the charge sharing stage, and the fifth switching circuit turned off in the data writing stage is turned on in the charge sharing stage.

[0204] In some embodiments, n=2; for each driving unit, the following further comprises:

[0205] One of the two sixth switch circuits electrically connected to the two voltage conversion circuits is controlled to be turned on and the other to be turned off.

[0206] In some embodiments, in the current frame, of the two sixth switching circuits included in each driving unit, one is turned on and the other is turned off in any stage. The sixth switching circuit that is turned on in the data writing stage is turned off in the charge sharing stage, and the sixth switching circuit that is turned off in the data writing stage is turned on in the charge sharing stage.

[0207] In a specific implementation, for any driving circuit, in the data writing phase of the current frame, the polarity of the voltage signal output by the first voltage conversion circuit is positive, and the polarity of the voltage signal output by the second voltage conversion circuit is negative; in the data writing phase, controlling the third switch circuit electrically connected to one of the two voltage conversion circuits to be turned on and the fourth switch circuit to be turned off, and controlling the third switch electrically connected to the other of the two voltage conversion circuits to be turned off and the fourth switch circuit to be turned on, specifically includes:

[0208] During the data writing phase, the third switch circuit and the sixth switch circuit electrically connected to the first voltage conversion circuit are controlled to be turned on, and the fourth switch circuit and the fifth switch circuit are controlled to be turned off; and the third switch circuit and the sixth switch circuit electrically connected to the second voltage conversion circuit are controlled to be turned off, and the fourth switch circuit and the fifth switch circuit are controlled to be turned on;

[0209] In the charge sharing phase, controlling the fifth switch circuit electrically connected to one of the two voltage conversion circuits to be turned on and the sixth switch circuit to be turned off, and controlling the fifth switch electrically connected to the other of the two voltage conversion circuits to be turned off and the sixth switch circuit to be turned on, specifically includes:

[0210] In the charge sharing stage, the fifth switch circuit electrically connected to the first voltage conversion circuit is controlled to be turned on, and the third switch circuit, the fourth switch circuit, and the sixth switch circuit are controlled to be turned off; the sixth switch circuit electrically connected to the second voltage conversion circuit is controlled to be turned on, and the third switch circuit, the fourth switch circuit, and the fifth switch circuit are controlled to be turned off.

[0211] In a specific implementation, for any driving circuit, in the data writing phase of the current frame, the polarity of the voltage signal output by the first voltage conversion circuit is negative, and the polarity of the voltage signal output by the second voltage conversion circuit is positive; in the data writing phase, controlling the third switch circuit electrically connected to one of the two voltage conversion circuits to be turned on and the fourth switch circuit to be turned off, and controlling the third switch electrically connected to the other of the two voltage conversion circuits to be turned off and the fourth switch circuit to be turned on, specifically includes:

[0212] During the data writing phase, the third switch circuit and the sixth switch circuit electrically connected to the second voltage conversion circuit are controlled to be turned on, and the fourth switch circuit and the fifth switch circuit are controlled to be turned off, and the third switch circuit and the sixth switch circuit electrically connected to the first voltage conversion circuit are controlled to be turned off, and the fourth switch circuit and the fifth switch circuit are controlled to be turned on;

[0213] In the charge sharing phase, controlling the fifth switch circuit electrically connected to one of the two voltage conversion circuits to be turned on and the sixth switch circuit to be turned off, and controlling the fifth switch electrically connected to the other of the two voltage conversion circuits to be turned off and the sixth switch circuit to be turned on, specifically includes:

[0214] In the charge sharing stage, the fifth switch circuit electrically connected to the second voltage conversion circuit is controlled to be turned on, and the third switch circuit, the fourth switch circuit, and the sixth switch circuit are controlled to be turned off; the sixth switch circuit electrically connected to the first voltage conversion circuit is controlled to be turned on, and the third switch circuit, the fourth switch circuit, and the fifth switch circuit are controlled to be turned off.

[0215] In a specific implementation, when n=2, the timing diagram of the driving method of the source driving circuit provided by the embodiment of the present disclosure is shown in FIG11 . The structure of the source driving circuit is shown in FIG10 .

[0216] The current frame is the i-th frame. The driving method of the source driving circuit provided by the embodiment of the present disclosure includes:

[0217] In the data writing phase t1, the control signals loaded onto the control terminals of the third switch circuit 1021 with reference numeral 1021-1, the fourth switch circuit 1022 with reference numeral 1022-1, the fifth switch circuit 1023 with reference numeral 1023-1, and the sixth switch circuit 1024 with reference numeral 1024-1 are SW1, SW2, SW3, and SW4, respectively. The control signals loaded onto the control terminals of the third switch circuit 1021 with reference numeral 1021-2, the fourth switch circuit 1022 with reference numeral 1022-2, the fifth switch circuit 1023 with reference numeral 1023-2, and the sixth switch circuit 1024 with reference numeral 1024-2 are SW1, SW2, SW3, and SW4, respectively. 1', SW2', SW3', SW4', SW1 and SW3' are 6V, SW1', SW2', SW3 and SW4 are 0V, and SW2 and SW4' are -6V; so that the third switch circuit 1021 with the reference numeral 1021-1, the fourth switch circuit 1022 with the reference numeral 1022-2, the fifth switch circuit 1023 with the reference numeral 1023-2, and the sixth switch circuit 1024 with the reference numeral 1024-1 are turned on, and the third switch circuit 1021 with the reference numeral 1021-2, the fourth switch circuit 1022 with the reference numeral 1022-1, the fifth switch circuit 1023 with the reference numeral 1023-1, and the sixth switch circuit 1024 with the reference numeral 1024-1 are turned on. 2 is turned off; the second fixed voltage signal applied to the input terminal of the first inverter in the first voltage conversion circuit 101-1 is 0V, the first power signal Vp1 applied to the first power signal input terminal of the first inverter in the first voltage conversion circuit 101-1 is 6V, and the second power signal Vp2 applied to the second power signal input terminal of the first inverter in the first voltage conversion circuit 101-1 is 0V, so that the output terminal of the first inverter in the first voltage conversion circuit 101-1 outputs the first control signal B1 to the control terminals of the first switch circuit and the second switch circuit, and B1 is 6V, so that the first switch circuit in the first voltage conversion circuit 101-1 is turned on and the second switch circuit is turned on. The switch circuit is turned off; and the second fixed voltage signal applied to the input terminal of the first inverter in the second voltage conversion circuit 101-2 is 0V, the first power signal Vp1 applied to the first power signal input terminal of the first inverter in the second voltage conversion circuit 101-2 is 0V, and the second power signal Vp2 applied to the second power signal input terminal of the first inverter in the second voltage conversion circuit 101-2 is -6V, so that the output terminal of the first inverter in the second voltage conversion circuit 101-2 outputs the second control signal B2 to the control terminals of the first switch circuit and the second switch circuit, B2 is -6V, and the first switch circuit in the second voltage conversion circuit 101-2 is turned off and the second switch circuit is turned on;The first voltage signal V1 is transmitted to the first switch circuit 1011 in the first voltage conversion circuit 101-1 through the third switch circuit 1021 (reference numeral 1021-1) and outputted. The second voltage signal V2 is transmitted to the second switch circuit 1012 in the second voltage conversion circuit 101-2 through the fourth switch circuit 1023 (reference numeral 1022-2) and outputted.

[0218] In the charge sharing phase before the first moment a1 of the blanking phase t2, the control signals SW1, SW2, SW3, and SW4 are loaded onto the control ends of the third switch circuit 1021 with a reference numeral 1021-1, the fourth switch circuit 1022 with a reference numeral 1022-1, the fifth switch circuit 1023 with a reference numeral 1023-1, and the sixth switch circuit 1024 with a reference numeral 1024-1, respectively. The control signals loaded on the control terminals of the sixth switch circuit 1024 marked as 1024-2 are SW1', SW2', SW3', and SW4', respectively. SW1, SW1', SW3', and SW4' are 0V, SW3 is 6V, and SW2, SW2', and SW4 are -6V, so that the fifth switch circuit 1023 marked as 1023-1 and the sixth switch circuit 1024 marked as 1024-2 are turned on, and the third switch circuit 1022, the fourth switch circuit 1023, the fifth switch circuit 1023 marked as 1023-2, and the sixth switch circuit 1024 marked as 1024-1 are turned off. The second fixed voltage signal applied to the input terminal of the first inverter in the first voltage conversion circuit 101-1 is 0V, the first power signal Vp1 applied to the first power signal input terminal of the first inverter in the first voltage conversion circuit 101-1 is 6V, and the second power signal Vp2 applied to the second power signal input terminal of the first inverter in the first voltage conversion circuit 101-1 is 0V, so that the output terminal of the first inverter in the first voltage conversion circuit 101-1 outputs the first control signal B1 to the control terminals of the first switch circuit and the second switch circuit, and B1 is 6V, so that the first switch circuit in the first voltage conversion circuit 101-1 is turned on and the second switch circuit is turned off; and the second The second fixed voltage signal applied to the input terminal of the first inverter in the voltage conversion circuit 101-2 is 0V, the first power signal Vp1 applied to the first power signal input terminal of the first inverter in the second voltage conversion circuit 101-2 is 0V, and the second power signal Vp2 applied to the second power signal input terminal of the first inverter in the second voltage conversion circuit 101-2 is -6V, so that the output terminal of the first inverter in the second voltage conversion circuit 101-2 outputs the second control signal B2 to the control terminals of the first switch circuit and the second switch circuit. B2 is -6V, and the first switch circuit in the second voltage conversion circuit 101-2 is turned off and the second switch circuit is turned on.The first fixed voltage signal Vc1 is transmitted to the first switch circuit 1011 in the first voltage conversion circuit 101-1 through the fifth switch circuit 1023 (reference numeral 1023-1) and outputted. The first fixed voltage signal Vc1 is transmitted to the second switch circuit 1012 in the second voltage conversion circuit 101-2 through the sixth switch circuit 1024 (reference numeral 1024-2).

[0219] In the blanking phase t2, at the first moment a1, the first power signal Vp1 loaded onto the first power signal input terminal of the first inverter in the first voltage conversion circuit 101-1 is 0V, and the second power signal Vp2' loaded onto the second power signal input terminal of the first inverter in the second voltage conversion circuit 101-2 is 0V; at the second moment a2 after the first moment a1, the second power signal Vp2 loaded onto the second power signal input terminal of the first inverter in the first voltage conversion circuit 101-1 is -6V, and the first power signal Vp1' loaded onto the first inverter in the second voltage conversion circuit 101-2 is 6V.

[0220] The current frame is the (i+1)th frame. The driving method of the source driving circuit provided by the embodiment of the present disclosure includes:

[0221] In the data writing phase t1, the control signals loaded onto the control ends of the third switch circuit 1021 with reference numeral 1021-1, the fourth switch circuit 1022 with reference numeral 1022-1, the fifth switch circuit 1023 with reference numeral 1023-1, and the sixth switch circuit 1024 with reference numeral 1024-1 are SW1, SW2, SW3, and SW4, respectively. The control signals loaded onto the control ends of the third switch circuit 1021 with reference numeral 1021-2, the fourth switch circuit 1022 with reference numeral 1022-2, the fifth switch circuit 1023 with reference numeral 1023-2, and the sixth switch circuit 1024 with reference numeral 1024-2 are SW1, SW2, SW3, and SW4, respectively. ', SW2', SW3', SW4', SW1', SW3 are 6V, SW1, SW2, SW3', SW4' are 0V, SW2', SW4 are -6V, so that the third switch circuit 1021 with the reference numeral 1021-2, the fourth switch circuit 1022 with the reference numeral 1022-1, the fifth switch circuit 1023 with the reference numeral 1023-1, and the sixth switch circuit 1024 with the reference numeral 1024-2 are turned on, and the third switch circuit 1021 with the reference numeral 1021-1, the fourth switch circuit 1022 with the reference numeral 1022-2, the fifth switch circuit 1023 with the reference numeral 1023-2, and the sixth switch circuit 1024 with the reference numeral 1024-1 are turned on. The sixth switch circuit 1024 of the first voltage conversion circuit 101-1 is turned off; the second fixed voltage signal loaded on the input terminal of the first inverter in the first voltage conversion circuit 101-1 is 0V, the first power signal Vp1 loaded on the first power signal input terminal of the first inverter in the first voltage conversion circuit 101-1 is 0V, and the second power signal Vp2 loaded on the second power signal input terminal of the first inverter in the first voltage conversion circuit 101-1 is -6V, so that the output terminal of the first inverter in the first voltage conversion circuit 101-1 outputs the second control signal B2 to the control terminals of the first switch circuit and the second switch circuit, and B2 is -6V, so that the first switch circuit in the first voltage conversion circuit 101-1 is turned off and the second switch circuit is turned off. The second switch circuit is turned on; the second fixed voltage signal applied to the input terminal of the first inverter in the second voltage conversion circuit 101-2 is 0V, the first power signal Vp1 applied to the first power signal input terminal of the first inverter in the second voltage conversion circuit 101-2 is 0V, and the second power signal Vp2 applied to the second power signal input terminal of the first inverter in the second voltage conversion circuit 101-2 is -6V, so that the output terminal of the first inverter in the second voltage conversion circuit 101-2 outputs the first control signal B1 to the control terminals of the first switch circuit and the second switch circuit, B1 is 6V, and the first switch circuit in the second voltage conversion circuit 101-2 is turned on and the second switch circuit is turned off;The first voltage signal V1 is transmitted to the first switch circuit 1011 in the second voltage conversion circuit 101-1 through the third switch circuit 1021 (reference numeral 1021-2) and outputted. The second voltage signal V2 is transmitted to the second switch circuit 1012 in the first voltage conversion circuit 101-1 through the fourth switch circuit 1023 (reference numeral 1022-1) and outputted.

[0222] In the charge sharing phase before the third moment a3 of the blanking phase t2, the control signals SW1, SW2, SW3, and SW4 are loaded onto the control ends of the third switch circuit 1021 with a reference numeral 1021-1, the fourth switch circuit 1022 with a reference numeral 1022-1, the fifth switch circuit 1023 with a reference numeral 1023-1, and the sixth switch circuit 1024 with a reference numeral 1024-1, respectively. The control signals loaded on the control end of the sixth switch circuit 1024 marked as 1024-2 are SW1', SW2', SW3', and SW4' respectively, SW1, SW1', SW3, and SW4 are 0V, SW3' is 6V, and SW2, SW2', and SW4 are -6V, so that the fifth switch circuit 1023 marked as 1023-2 and the sixth switch circuit 1024 marked as 1024-1 are turned on, and the third switch circuit 1022, the fourth switch circuit 1023, the fifth switch circuit 1023 marked as 1023-1, and the sixth switch circuit 1024 marked as 1024-2 are turned off; the first voltage conversion circuit The second fixed voltage signal loaded onto the input terminal of the first inverter in the first voltage conversion circuit 101-1 is 0V, the first power signal Vp1 loaded onto the first power signal input terminal of the first inverter in the first voltage conversion circuit 101-1 is 0V, and the second power signal Vp2 loaded onto the second power signal input terminal of the first inverter in the first voltage conversion circuit 101-1 is -6V, so that the output terminal of the first inverter in the first voltage conversion circuit 101-1 outputs the second control signal B2 to the control terminals of the first switch circuit and the second switch circuit, and B2 is -6V, so that the first switch circuit in the first voltage conversion circuit 101-1 is turned off and the second switch circuit is turned on; and the second switch circuit is turned on. The second fixed voltage signal applied to the input terminal of the first inverter in the second voltage conversion circuit 101-2 is 0V, the first power signal Vp1 applied to the first power signal input terminal of the first inverter in the second voltage conversion circuit 101-2 is 0V, and the second power signal Vp2 applied to the second power signal input terminal of the first inverter in the second voltage conversion circuit 101-2 is -6V, so that the output terminal of the first inverter in the second voltage conversion circuit 101-2 outputs the first control signal B1 to the control terminals of the first switch circuit and the second switch circuit. B1 is 6V, and the first switch circuit in the second voltage conversion circuit 101-2 is turned on and the second switch circuit is turned off.The first fixed voltage signal Vc1 is transmitted to the first switch circuit 1011 in the second voltage conversion circuit 101-2 through the fifth switch circuit 1023 (reference numeral 1023-2) and outputted. The first fixed voltage signal Vc1 is also transmitted to the second switch circuit 1012 in the first voltage conversion circuit 101-1 through the sixth switch circuit 1024 (reference numeral 1024-1).

[0223] In the blanking phase t2, at the third moment a3, the second power signal Vp2 loaded onto the second power signal input terminal of the first inverter in the first voltage conversion circuit 101-1 is 0V, and the first power signal Vp1' loaded onto the first inverter in the second voltage conversion circuit 101-2 is 0V. At the fourth moment a4 after the third moment a3, the first power signal Vp1 loaded onto the first power signal input terminal of the first inverter in the first voltage conversion circuit 101-1 is 6V, and the second power signal Vp2' loaded onto the second power signal input terminal of the first inverter in the second voltage conversion circuit 101-2 is -6V.

[0224] In some embodiments, the driving unit further includes: n data selection circuits; and further includes:

[0225] The m data selection switches in each data selection circuit are controlled to be turned on in sequence, outputting a first voltage signal or a second voltage signal in a data writing phase, and outputting a first fixed voltage signal in a charge sharing phase.

[0226] In some embodiments, n=2, m=6. When the driving unit has two data selection circuits 103, the timing diagram of the driving method of the source driving circuit provided by the embodiment of the present disclosure is shown in FIG13 , wherein SMUX <1> ~SMUX <12> are control signals for the control terminals of the data selection switches electrically connected to the data lines dt1-dt12. During the data writing phase of the i-th frame, the data selection switches electrically connected to the data lines dt1-dt6 output a first voltage signal, and the data selection switches electrically connected to the data lines dt7-dt12 output a second voltage signal. During the data writing phase of the (i+1) frame, the data selection switches electrically connected to the data lines dt1-dt6 output a second voltage signal, and the data selection switches electrically connected to the data lines dt7-dt12 output a first voltage signal.

[0227] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes the source driving circuit provided by the embodiment of the present disclosure.

[0228] In some embodiments, as shown in FIG. 15 , the display panel specifically includes: an array substrate 5 and an opposite substrate 6 that are oppositely disposed, and a liquid crystal layer 7 located between the array substrate 5 and the opposite substrate 6 .

[0229] In some embodiments, the array substrate includes a plurality of data lines, and the plurality of data lines are electrically connected to the source driving circuit.

[0230] In a specific implementation, the array substrate also includes multiple scan lines, and multiple data lines and the multiple scan lines cross horizontally and vertically to divide the sub-pixel area. The sub-pixel also includes a thin film transistor and a pixel electrode. The gate of the thin film transistor is electrically connected to the scan line, the source of the thin film transistor is electrically connected to the data line, and the drain of the thin film transistor is electrically connected to the pixel electrode. The data signal provided to the data line by the source drive circuit controls the thin film transistor to turn on when the scan signal input by the scan line controls the sub-pixel to be charged.

[0231] In specific implementation, the source driving circuit can be manufactured independently of the film layers of the array substrate, that is, a chip including the source driving circuit provided by the embodiment of the present disclosure is pre-made, and then the chip is bound to the array substrate to realize the electrical connection between the source driving circuit and multiple data lines.

[0232] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device. As shown in FIG16 , the display device includes a display panel 8 provided by an embodiment of the present disclosure.

[0233] In some embodiments, as shown in FIG16 , the display device further includes a backlight module 9 , and the display panel 8 is located on the light-emitting side of the backlight module 9 .

[0234] The display device provided in the embodiments of the present disclosure is any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. Other essential components of the display device are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure. The implementation of the display device can be referenced to the above-described display panel embodiments, and any repetitive details will not be repeated.

[0235] In summary, the source driver circuit and its driving method, display panel, and display device provided by the embodiments of the present disclosure can realize the conversion of a first voltage signal and a second voltage signal of opposite polarity by using a driving unit including a voltage conversion circuit. Moreover, before the conversion of the voltage signals of opposite polarity, charge sharing is required to pull the output voltage to a first fixed voltage signal, which can reduce the voltage change of the voltage signal polarity conversion while realizing the voltage signal polarity conversion, avoid the voltage change exceeding the withstand voltage change of the voltage conversion circuit, and thus avoid damage to the voltage conversion circuit. It is conducive to reducing the size of the first switching circuit and the second switching circuit included in the voltage conversion circuit. Compared with the prior art that uses high-voltage devices to realize voltage conversion, the size of the driving unit of the source driver circuit disclosed in the present disclosure is greatly reduced. When the source driver circuit is applied to high-resolution display products, even if the required number of driving units is large, narrow-border display can still be achieved due to the greatly reduced size of the driving unit.

[0236] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0237] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A source driver circuit, wherein: The source driving circuit comprises: a plurality of driving units; The driving unit comprises: n voltage conversion circuits; wherein n is an integer greater than or equal to 1; Each of the voltage conversion circuits includes: a first switch circuit and a second switch circuit; the control end of the first switch circuit and the control end of the second switch circuit are used to input control signals, and the control signals include a first control signal and a second control signal; the second switch circuit is turned off in response to the first control signal, and the first switch circuit is turned on in response to the first control signal and sequentially outputs a first voltage signal and a first fixed voltage signal; the first switch circuit is turned off in response to the second control signal, and the second switch circuit is turned on in response to the second control signal and sequentially outputs a second voltage signal and the first fixed voltage signal; the polarity of the first voltage signal is opposite to the polarity of the second voltage signal.

2. The source driving circuit according to claim 1, wherein: The voltage conversion circuit further includes: a control circuit; The output end of the control circuit is electrically connected to the control end of the first switch circuit and the control end of the second switch circuit; The control circuit is used for outputting the control signal.

3. The source driving circuit according to claim 2, wherein: The control circuit includes a first inverter; The input terminal of the first inverter is used to input a second fixed voltage signal; The first power signal input terminal of the first inverter is used to input a first power signal, and the second power signal input terminal of the first inverter is used to input a second power signal; The output end of the first inverter is electrically connected to the control end of the first switch circuit and / or the control end of the second switch circuit, and is used to output the control signal.

4. The source driving circuit according to claim 3, wherein: The voltage of the second fixed voltage signal is 0V.

5. The source driving circuit according to claim 3 or 4, wherein: The voltage of the first voltage signal is greater than 0 volts and less than or equal to a volts, and the voltage of the second voltage signal is greater than 0 volts and less than or equal to -a volts; a is a positive number; The voltage of one of the first power supply signal and the second power supply signal is 0 volts, and the voltage of one of the first power supply signal and the second power supply signal is b volts; or, the voltage of one of the first power supply signal and the second power supply signal is 0 volts, and the voltage of one of the first power supply signal and the second power supply signal is -b volts; b is a positive number less than or equal to a.

6. The source driving circuit according to any one of claims 1 to 5, wherein: The first switch circuit and the second switch circuit include transmission gate switches.

7. The source driving circuit according to claim 6, wherein: The transmission gate switch includes a P-type transistor and / or an N-type transistor.

8. The source driving circuit according to claim 7, wherein: The transmission gate switch includes a P-type transistor and an N-type transistor; the input end of the P-type transistor is electrically connected to the input end of the N-type transistor, and the output end of the P-type transistor is electrically connected to the output end of the N-type transistor; The transmission gate switch further includes: a second inverter; In the first switch circuit, the input end of the second inverter is electrically connected to the control end of the N-type transistor, the output end of the second inverter is electrically connected to the control end of the P-type transistor, the input end of the P-type transistor and the input end of the N-type transistor are used to input the first voltage signal or the first fixed voltage signal, and the output end of the P-type transistor and the output end of the N-type transistor are used to output the first voltage signal or the first fixed voltage signal; In the second switching circuit, the output end of the second inverter is electrically connected to the control end of the N-type transistor, the input end of the second inverter is electrically connected to the control end of the P-type transistor, the input end of the P-type transistor and the input end of the N-type transistor are used to input the second voltage signal or the first fixed voltage signal, and the output end of the P-type transistor and the output end of the N-type transistor are used to output the second voltage signal or the first fixed voltage signal.

9. The source driving circuit according to any one of claims 1 to 8, wherein: The driving unit further includes: a switch group; the switch group includes n third switch circuits, n fourth switch circuits, n fifth switch circuits, and n sixth switch circuits; The output ends of the n third switch circuits are electrically connected to the input ends of the first switch circuits in the n voltage conversion circuits respectively; the input end of the third switch circuit is used to input the first voltage signal; The output ends of the n fourth switch circuits are electrically connected to the input ends of the second switch circuits in the n voltage conversion circuits respectively; the input end of the fourth switch circuit is used to input the second voltage signal; The output ends of the n fifth switch circuits are respectively electrically connected to the input ends of the first switch circuits in the n voltage conversion circuits, and the output ends of the n sixth switch circuits are respectively electrically connected to the input ends of the second switch circuits in the n voltage conversion circuits; the input ends of the fifth switch circuit and the input ends of the sixth switch circuit are used to input the first fixed voltage signal.

10. The source driving circuit according to claim 9, wherein: The third switch circuit, the fourth switch circuit, the fifth switch circuit, and the sixth switch circuit all include transmission gate switches.

11. The source driving circuit according to claim 10, wherein: The transmission gate switch included in the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit includes: a P-type transistor and an N-type transistor, the input end of the P-type transistor is electrically connected to the input end of the N-type transistor, and the output end of the P-type transistor is electrically connected to the output end of the N-type transistor; The transmission gate switch included in the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit further includes: a third inverter; the input end of the third inverter is electrically connected to the control end of the N-type transistor, and the output end of the third inverter is electrically connected to the control end of the P-type transistor; The input end of the P-type transistor and the input end of the N-type transistor included in the third switch circuit are used to input the first voltage signal, and the output end of the P-type transistor and the input end of the N-type transistor included in the third switch circuit are electrically connected to the input end of the first switch circuit; The fourth switch circuit includes an input end of the P-type transistor and an input end of the N-type transistor The input end of the P-type transistor and the input end of the N-type transistor included in the fourth switch circuit are electrically connected to the input end of the second switch circuit; The input end of the P-type transistor and the input end of the N-type transistor included in the fifth switch circuit are used to input the first fixed voltage signal, and the output end of the P-type transistor and the input end of the N-type transistor included in the fifth switch circuit are electrically connected to the input end of the first switch circuit; The input end of the P-type transistor and the input end of the N-type transistor included in the sixth switch circuit are used to input the first fixed voltage signal, and the output end of the P-type transistor and the input end of the N-type transistor included in the sixth switch circuit are electrically connected to the input end of the second switch circuit.

12. The source driving circuit according to claim 11, wherein: The substrate of the N-type transistor is electrically connected to the third power signal terminal, the substrate of the P-type transistor is electrically connected to the fourth power signal terminal, the signal of the third power signal terminal is a third power signal, and the signal of the fourth power signal terminal is a fourth power signal; the voltage of the third power signal is greater than the voltage of the fourth power signal; The voltage of the third power supply signal of the third switch circuit and the fifth switch circuit is a volt, and the voltage of the fourth power supply signal of the third switch circuit and the fifth switch circuit is 0 volt; the voltage of the third power supply signal of the fourth switch circuit and the sixth switch circuit is 0 volt, and the voltage of the fourth power supply signal of the fourth switch circuit and the sixth switch circuit is -a volt.

13. The source driving circuit according to any one of claims 1 to 12, wherein: The driving unit further includes: n data selection circuits; The data selection circuit includes m data selection switches, where m is an integer greater than 1; The input ends of the m data selection switches are electrically connected to the output end of the voltage conversion circuit.

14. The source driving circuit according to any one of claims 1 to 13, wherein: The voltage of the first fixed voltage signal is greater than or equal to -0.7 volts and less than or equal to 0.7 volts.

15. The source driving circuit according to any one of claims 1 to 14, wherein: n=1 or n=2.

16. A driving method of a source driving circuit according to any one of claims 1 to 15, wherein: The method comprises: Determine an output voltage signal corresponding to each voltage conversion circuit in each driving unit in a current frame; the output voltage signal is a first voltage signal or a second voltage signal, and the polarity of the first voltage signal is opposite to the polarity of the second voltage signal; A control signal is loaded on the voltage conversion circuit according to the output voltage signal, so that the second switch circuit in the voltage conversion circuit is turned off in response to the first control signal, the first switch circuit is turned on in response to the first control signal, the first voltage signal is output through the first switch circuit in the data writing phase of the current frame, and the first fixed voltage signal is output through the first switch circuit in the charge sharing phase after the data writing phase; or, the first opening circuit in the voltage conversion circuit is turned off in response to the second control signal, the second switch circuit is turned off and on in response to the second control signal, the second voltage signal is output through the second switch circuit in the data writing phase of the current frame, and the first fixed voltage signal is output through the second switch circuit in the charge sharing phase after the data writing phase.

17. The method according to claim 16, wherein: The voltage conversion circuit further includes: a control circuit, wherein the control circuit includes a first inverter; and a control signal for the voltage conversion circuit specifically includes: A second fixed voltage signal is loaded to the input end of the first inverter, a first power signal is loaded to the first power signal input end of the first inverter, and a second power signal is loaded to the second power signal input end of the first inverter, so that the output end of the first inverter outputs the control signal to the control ends of the first switching circuit and the second switching circuit.

18. The method according to claim 17, wherein: n=1; applying a control signal to the voltage conversion circuit, specifically including: The same first power signal and the same second power signal are applied to each of the first inverters, so that the output terminal of each of the first inverters outputs the first control signal or the second control signal.

19. The method according to claim 17, wherein: n=2; the voltage conversion circuit is loaded with a control signal specifically comprising: For each of the driving circuits, a first power signal of b volts and a second power signal of 0 volts are loaded on the first inverter included in one of the two voltage conversion circuits, so that the output end of the first inverter outputs a first control signal; and a first power signal of 0 volts and a second power signal of -b volts are loaded on the first inverter included in the other of the two voltage conversion circuits, so that the output end of the first inverter outputs a second control signal.

20. The method according to any one of claims 16 to 19, wherein: The driving unit further includes: n third switch circuits, n fourth switch circuits, n fifth switch circuits, and n sixth switch circuits. After determining the voltage signal corresponding to each voltage conversion circuit in each driving unit in the current frame, the method further includes: For each of the voltage conversion circuits, if it is determined that the voltage signal corresponding to the voltage conversion circuit is the first voltage signal, in the data writing phase, the third switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on to input the first voltage signal, and in the charge sharing phase, the fifth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on to input the first fixed voltage signal; For each of the voltage conversion circuits, if it is determined that the voltage signal corresponding to the voltage conversion circuit is the second voltage signal, the fourth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on during the data writing phase, and the second voltage signal is input; and the sixth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on during the charge sharing phase, and the first fixed voltage signal is input.

21. The method according to claim 20, wherein: n＝1； For each of the drive units, the method further comprises: In the data writing phase, the third switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on and the fifth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned off; In the charge sharing stage, the fifth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on and the third switch circuit electrically connected to the voltage conversion circuit is controlled to be turned off; Alternatively, in the data writing stage, the fourth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on and the sixth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned off; in the charge sharing stage, the sixth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned on and the sixth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned off. The fourth switch circuit electrically connected to the voltage conversion circuit is controlled to be turned off.

22. The method according to claim 20, wherein: n＝2； For each of the drive units, the method further comprises: In the data writing stage, the third switch circuit electrically connected to one of the two voltage conversion circuits is controlled to be turned on and the fourth switch circuit is turned off, and the third switch circuit electrically connected to the other of the two voltage conversion circuits is controlled to be turned off and the fourth switch circuit is turned on; In the charge sharing stage, the fifth switch circuit electrically connected to one of the two voltage conversion circuits is controlled to be turned on and the sixth switch circuit is controlled to be turned off, and the fifth switch circuit electrically connected to the other of the two voltage conversion circuits is controlled to be turned off and the sixth switch circuit is controlled to be turned on.

23. The method according to any one of claims 16 to 22, wherein: The driving unit further includes: n data selection circuits; the method further includes: The m data selection switches in each of the data selection circuits are controlled to be turned on in sequence, and the first voltage signal or the second voltage signal is output during the data writing phase, and the first fixed voltage signal is output during the charge sharing phase.

24. A display panel, wherein: The display panel comprises the source driving circuit according to any one of claims 1 to 15.

25. The display panel according to claim 24, wherein: The display panel specifically comprises: an array substrate and an opposite substrate arranged opposite to each other, and a liquid crystal layer located between the array substrate and the opposite substrate; The array substrate includes a plurality of data lines, and the plurality of data lines are electrically connected to the source driving circuit.

26. A display device, wherein: The display device comprises the display panel according to claim 24 or 25.

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