Semiconductor device

Abstract

Provided is a semiconductor device capable of improving insulation reliability around a bonding wire. A semiconductor device is provided with: a semiconductor chip (3) having a first main electrode (31) on the upper surface side of the semiconductor chip (3) and a second main electrode (33) on the lower surface side of the semiconductor chip (3); a bonding wire (4b) connected to the first main electrode (31); an insulating layer (9b) that covers the outer periphery of the bonding wire (4b); and a sealing member (7) that seals the semiconductor chip (3), the bonding wire (4b), and the insulating layer (4b), in which the ratio of the Young's modulus of the insulating layer (9b) to the Young's modulus of the sealing member (7) is 10 or more.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device (semiconductor module). Background Art

[0002] Patent document 1 discloses that the connection part of the bonding wire on the chip is coated with resin. Patent document 2 discloses that the aluminum wire bonded to the semiconductor element is covered with a primer layer, and the aluminum wire covered with the primer layer is covered with a first sealing layer. Patent document 3 discloses that a circuit substrate has a semiconductor element mounted via a bonding wire, and the semiconductor element and the bonding wire are covered with a resin coating material, and the surface of the resin coating material is covered with a silicone gel.

[0003] Patent document 4 discloses a power semiconductor device in which a semiconductor element and an aluminum wire are sealed with epoxy resin, and sealed with a silicone gel resin in a manner covering the epoxy resin. Patent document 5 discloses that a bonding wire connected to a semiconductor element is covered with a resin. Patent document 6 discloses that a bonding wire connected between a substrate and a housing and a connecting portion thereof are covered with a resin having a hardness higher than that of the gel.

[0004] Patent document 7 discloses a semiconductor device including wiring connected to a semiconductor element, a resin sealing member sealing the semiconductor element, and a semiconductive film covering at least a portion of the wiring and arranged between at least a portion of the wiring and the resin sealing member. Patent document 8 discloses a semiconductor device including a bonding wire bonded to a semiconductor element, a resin layer covering a bonding portion of the bonding wire at a surface of the semiconductor element, and a gel filling material sealing the semiconductor element, the bonding wire, and the resin layer.

[0005] Patent document 9 discloses a bonding wire for a semiconductor element having a bonding wire and a copper ion diffusion suppression layer covering the bonding wire surface. Patent document 10 discloses the following: the bonding wire is covered with a foamed polymer. Patent document 11 discloses a covered wire in which a core wire is covered with a covering resin. Patent document 12 discloses a semiconductor device in which a metal terminal of a semiconductor chip is connected to a lead by a covering wire, and the connection portion between the covering wires is covered with a resin.

[0006] Patent document 13 discloses a covered wire in which a core wire is covered with a covering resin. Patent documents 14 and 15 disclose the following contents respectively: a covered wire formed by covering the surface of a metal wire with an insulating covering film connects a metal terminal of a semiconductor chip to a lead. Patent document 16 discloses a semiconductor device having a bonding wire connecting a substrate to a semiconductor element, a first sealing layer sealing a space below the top of the bonding wire, and a second sealing layer provided on the upper part of the first sealing layer via the bonding wire.

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: Japanese Patent Application Publication No. 2007-012831

[0010] Patent Document 2: Japanese Patent Application Publication No. 2021-150466

[0011] Patent Document 3: Japanese Patent Application Publication No. 2000-228482

[0012] Patent Document 4: Japanese Patent Application Publication No. 2012-15222

[0013] Patent Document 5: Japanese Patent Application Publication No. 2019-9171

[0014] Patent Document 6: Japanese Patent Application Publication No. 2022-7343

[0015] Patent Document 7: Japanese Patent Application Publication No. 2017-224778

[0016] Patent Document 8: Japanese Patent Application Publication No. 2017-147327

[0017] Patent Document 9: Japanese Patent Application Publication No. 2012-231034

[0018] Patent Document 10: Japanese Patent Application Publication No. 2002-170842

[0019] Patent Document 11: Japanese Patent Application Laid-Open No. 9-260414

[0020] Patent Document 12: Japanese Patent Application Laid-Open No. 8-316264

[0021] Patent Document 13: Japanese Patent Application Laid-Open No. 2-304943

[0022] Patent Document 14: Japanese Patent Application Laid-Open No. 2-266541

[0023] Patent Document 15: Japanese Patent Application Laid-Open No. 63-318132

[0024] Patent Document 16: International Publication No. 2019 / 31513 Summary of the invention

[0025] Problem that the invention aims to solve

[0026] When voids such as bubbles inside the sealing member or peeling of the sealing member are generated around the bonding wire connected to the semiconductor chip or the like, the electric field intensity increases in the void portion, and the insulation reliability decreases.

[0027] In view of the above-mentioned problems, an object of the present disclosure is to provide a semiconductor device capable of improving insulation reliability around a bonding wire.

[0028] Solutions for solving problems

[0029] The main purpose of one embodiment of the present disclosure is a semiconductor device, which comprises: a semiconductor chip having a first main electrode on the upper surface side of the semiconductor chip and a second main electrode on the lower surface side of the semiconductor chip; a bonding wire connected to the first main electrode; an insulating layer covering the periphery of the bonding wire; and a sealing component that seals the semiconductor chip, the bonding wire and the insulating layer, wherein the ratio of the Young's modulus of the insulating layer to the Young's modulus of the sealing component is greater than 10.

[0030] Effects of the Invention

[0031] According to the present disclosure, it is possible to provide a semiconductor device capable of improving insulation reliability around a bonding wire. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a cross-sectional view of an example of a semiconductor device according to an embodiment.

[0033] Figure 2 It is a perspective view of another example of the semiconductor device according to the embodiment.

[0034] Figure 3 It is a schematic diagram of a bonding wire, an insulating layer, and a sealing member according to an embodiment.

[0035] Figure 4 : is a graph showing the relationship between the coating thickness of the bonding wire and the electric field strength according to the embodiment.

[0036] Figure 5 : is a graph showing the relationship between the wire diameter of the bonding wire and the electric field strength according to the embodiment. DETAILED DESCRIPTION

[0037] Below, the embodiments of the present disclosure are described with reference to the accompanying drawings. In the description of the accompanying drawings, the same or similar parts are marked with the same or similar symbols, and repeated descriptions are omitted. However, the drawings are schematic, and the relationship between thickness and plane dimensions, the thickness ratio of each layer, etc. are sometimes different from the actual situation. In addition, the drawings may also contain parts with different dimensional relationships and ratios. In addition, the embodiments shown below illustrate devices and methods for concretizing the technical ideas of the present disclosure. The technical ideas of the present disclosure do not specify the material, shape, structure, configuration, etc. of the structural components as the following materials, shapes, structures, configurations, etc.

[0038] In addition, the definitions of up and down, left and right, etc. in the following description are only for the convenience of explanation and do not limit the technical concept of the present disclosure. For example, if the object is rotated 90° to observe, up and down are changed to left and right, and if it is rotated 180° to observe, it is called upside down, which is self-evident.

[0039] In addition, in the following description, the "first main electrode" of the semiconductor chip refers to an electrode for the main current to flow into or out of the semiconductor chip. When the semiconductor chip is a field effect transistor (FET) or a static induction transistor (SIT), the "first main electrode" refers to either the source electrode or the drain electrode. When the semiconductor chip is an insulated gate bipolar transistor (IGBT), the "first main electrode" refers to either the emitter electrode or the collector electrode. When the semiconductor chip is a static induction (SI) thyristor or a gate turn-off (GTO) thyristor, the "first main electrode" refers to either the anode electrode or the cathode electrode. In addition, when the semiconductor chip is a FET or SIT, the "second main electrode" of the semiconductor chip refers to either the source electrode or the drain electrode that does not become the above-mentioned first main electrode. When the semiconductor chip is an IGBT, the "second main electrode" refers to either the emitter electrode or the collector electrode that does not become the above-mentioned first main electrode. When the semiconductor chip is an SI thyristor or a GTO thyristor, the "second main electrode" refers to either the anode electrode or the cathode electrode that does not become the above-mentioned first main electrode. That is, if the "first main electrode" of the semiconductor chip is the source electrode, the "second main electrode" refers to the drain electrode. If the "first main electrode" of the semiconductor chip is the emitter electrode, the "second main electrode" refers to the collector electrode. If the "first main electrode" of the semiconductor chip is the anode electrode, the "second main electrode" refers to the cathode electrode.

[0040] (Implementation Method)

[0041] <Structure of Semiconductor Device>

[0042] The semiconductor device (semiconductor module) according to the embodiment is as follows Figure 1 As shown, there is an insulating circuit substrate 1, and a power semiconductor chip (semiconductor chip) 3 arranged on the main surface (upper surface) side of one side of the insulating circuit substrate 1 via a bonding layer 2. A housing 5 is arranged in a manner surrounding the outer periphery of the insulating circuit substrate 1, the bonding layer 2 and the semiconductor chip 3. Terminals (external connection terminals) 6a and 6b are installed on the housing 5. The insulating circuit substrate 1, the semiconductor chip 3 and the external connection terminals 6a and 6b are electrically connected to each other via bonding wires 4a to 4c. A sealing member (sealing resin) 7 that seals the insulating circuit substrate 1, the bonding layer 2, the semiconductor chip 3, the bonding wires 4a to 4c, the insulating layers 9a to 9c, etc. is provided on the inner side of the housing 5.

[0043] The insulating circuit substrate 1 is composed of, for example, a direct copper bonding (DCB) substrate or an active brazing (AMB) substrate. The insulating circuit substrate 1 includes an insulating plate 10, conductive layers 11a and 11b provided on one main surface (upper surface) side of the insulating plate 10, and a conductive layer 12 provided on the other main surface (lower surface) side of the insulating plate 10. The insulating plate 10 is, for example, made of aluminum oxide (Al 2 O 3 ), aluminum nitride (AlN), silicon nitride (Si 3 N 4 ) or a resin insulating substrate made of a polymer material or the like. The conductive layers 11a, 11b, and 12 are made of, for example, conductive foil made of copper (Cu) or aluminum (Al).

[0044] The bonding layer 2 is composed of, for example, solder or sintered material. As the solder, for example, lead-free solders such as tin-antimony (Sn-Sb) series, tin-copper (Sn-Cu) series, tin-copper-silver (Sn-Cu-Ag) series, tin-silver (Sn-Ag) series, tin-silver-copper (Sn-Ag-Cu) series, tin-silver-bismuth-copper (Sn-Ag-Bi-Cu) series, tin-indium-silver-bismuth (Sn-In-Ag-Bi) series, tin-zinc (Sn-Zn) series, tin-zinc-bismuth (Sn-Zn-Bi) series, tin-bismuth (Sn-Bi) series, tin-indium (Sn-In) series, or lead solders such as tin-lead (Sn-Pb) series can be used. The sintered material is formed by heating and pressurizing a sheet-like sintered sheet or a paste-like conductive paste containing metal particles with a fine particle size of about several nm to several μm such as gold (Au), silver (Ag) or copper (Cu) and an organic component (binder) to sinter the material.

[0045] The semiconductor chip 3 is composed of, for example, an insulated gate bipolar transistor (IGBT), a field effect transistor (FET), an electrostatic induction (SI) thyristor, a gate turn-off (GTO) thyristor, a freewheeling diode (FWD), etc. Here, the case where the semiconductor chip 3 is a MOSFET is exemplified. The semiconductor chip 3 can be formed on a silicon (Si) substrate, or can be formed on a substrate using silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga 2 O 3 ), semiconductor substrates of wide-bandgap semiconductors such as diamond.

[0046] The maximum rated voltage of the semiconductor chip 3 is, for example, about 1.7 kV or more. The maximum rated voltage of the semiconductor chip 3 may be about 1.7 kV or less, or about 3.3 kV or more. The greater the maximum rated voltage of the semiconductor chip 3, the greater the insulation distance required between the components.

[0047] The semiconductor chip 3 has a first main electrode (source electrode) 31 and a gate electrode 32 on one main surface (upper surface) side, and a second main electrode (drain electrode) 33 on the other main surface (lower surface) side. The second main electrode 33 is bonded to the conductive layer 11a via the bonding layer 2. Figure 1 Although one semiconductor chip 3 is illustrated in the figure, the number of semiconductor chips can be appropriately set according to the current capacity of the semiconductor module and the like, and two or more semiconductor chips may be provided.

[0048] The housing 5 is made of, for example, a thermoplastic resin such as polyphenylene sulfide (PPS) or polybutylene terephthalate (PBT).

[0049] The external connection terminals 6a and 6b are made of metal materials such as copper (Cu) or aluminum (Al). The external connection terminals 6a and 6b can be connected to an external circuit. The shape, configuration position, and number of the external connection terminals 6a and 6b are not particularly limited. The external connection terminals 6a and 6b can also be bonded to the conductive layers 11a and 11b via a bonding layer such as solder or sintered material instead of the bonding wires 4a and 4c.

[0050] One end of the bonding wire 4a is connected to the conductive layer 11a, and the other end of the bonding wire 4a is connected to the external connection terminal 6a. The second main electrode 33 of the semiconductor chip 3 is electrically connected to the external connection terminal 6a via the conductive layer 11a and the bonding wire 4a.

[0051] One end of the bonding wire 4b is connected to the first main electrode 31 of the semiconductor chip 3, and the other end of the bonding wire 4b is connected to the conductive layer 11b. One end of the bonding wire 4c is connected to the conductive layer 11b, and the other end of the bonding wire 4c is connected to the external connection terminal 6b. The first main electrode 31 of the semiconductor chip 3 is electrically connected to the external connection terminal 6b via the bonding wire 4b, the conductive layer 11b, and the bonding wire 4c.

[0052] exist Figure 1 Although not shown in the figure, the gate electrode 32 of the semiconductor chip 3 is electrically connected to another external connection terminal (not shown) that can be connected to an external circuit via a bonding wire (not shown) or the like.

[0053] exist Figure 1 In the embodiment, the potential of the bonding wire 4a is the same as that of the external connection terminal 6a electrically connected to the second main electrode 33 of the semiconductor chip 3, and is different from the external connection terminal 6b electrically connected to the first main electrode 31 of the semiconductor chip 3. The potentials of the bonding wires 4b and 4c are the same as that of the external connection terminal 6b, and are different from the external connection terminal 6a.

[0054] For example, the bonding wire 4a may be disposed at a distance of about 5 mm or less from the external connection terminal 6b having a different potential from that of the bonding wire 4a, and the bonding wire 4a and the external connection terminal 6b are separated by a sealing member 7. The bonding wires 4b and 4c may be disposed at a distance of about 5 mm or less from the external connection terminal 6a having a different potential from that of the bonding wires 4b and 4c, and the bonding wires 4b and 4c and the external connection terminal 6a are separated by a sealing member 7.

[0055] The bonding wires 4a to 4c are made of metal materials such as copper (Cu), aluminum (Al) or gold (Au). The diameter of the bonding wires 4a to 4c is, for example, about 125 μm or more and about 500 μm or less. The diameter of the bonding wires 4a to 4c can also be about 400 μm or less, and can also be about 300 μm or less. The smaller the diameter of the bonding wires 4a to 4c, the smaller the pads connecting the bonding wires 4a to 4c can be, and thus the smaller the size of the component can be. On the other hand, the smaller the diameter of the bonding wires 4a to 4c, the higher the electric field strength around the bonding wires 4a to 4c, and therefore the greater the insulation distance required between the bonding wires 4a to 4c and each component.

[0056] The sealing member 7 is made of, for example, a resin material such as gel-like silicone (silicone gel) or fluorine gel. The longitudinal elastic coefficient (Young's modulus) of the sealing member 7 is, for example, about 1 kPa or more and 100 kPa or less. The relative dielectric constant of the sealing member 7 is, for example, about 3 or more and about 5 or less.

[0057] The sealing member 7 has the function of mechanically protecting the internal circuit from the influence of foreign matter, etc. For example, when a conductive foreign matter is attached to the exposed circuit, the circuit is short-circuited and a fault occurs. Even a foreign matter with low conductivity may cause a short-circuit fault due to electrical traces. By covering the internal circuit with the sealing member 7, such a fault can be prevented.

[0058] In addition, the sealing member 7 has the function of insulating the electrodes (circuits). The insulation reliability is ensured by covering and filling the circuit surface including the element surface, the bonding wire surface, and the terminal surface, and the electrodes (circuits). In the insulation between the electrodes performed by the sealing member 7, the insulation distance can be significantly shortened compared to the insulation performed by air, thereby enabling miniaturization of the module based on high-density mounting.

[0059] The gel such as silicone gel that constitutes the sealing member 7 is soft and has high followability, so it is not easy to peel off, but it has high moisture absorption (moisture permeability) and is easy to generate bubbles inside. Although the generation of bubbles can be suppressed by making the sealing member 7 hard, the followability to the bonding wires 4a~4c is reduced and it is easy to peel off. In addition, there are countless tiny gaps in the joints between the sealing member 7 and the components, and it is technically difficult to construct without any gaps. In addition, when the gaps are filled with resin, the stress in the thermal cycle becomes too large, which increases the risk of damage in the heating cycle and power cycle. In addition, it is difficult to completely fill the gaps in large modules.

[0060] Since the dielectric constant of gel such as silicone gel constituting the sealing member 7 is higher than that of air, when gaps such as bubbles inside the sealing member 7 or peeling of the sealing member 7 are generated between the electrodes, the electric field strength increases in the gap and the insulation reliability decreases. For example, when gaps are generated, the discharge start voltage even drops to about 1 / 3. In particular, the electric field is easily concentrated on the surface of the bonding wires 4a to 4c, so the discharge start voltage even drops to about 1 / 6 relative to other areas, and the thinner the bonding wires 4a to 4c, the lower the insulation performance.

[0061] If the maximum rated voltage of the semiconductor chip 3 is about 1.7 kV or less, even if a gap is formed between the electrodes, the required insulation distance for the bonding wires 4a to 4c is small, so the design (miniaturization) constraints are low. However, when the maximum rated voltage of the semiconductor chip 3 is a high withstand voltage of 3.3 kV or more, the required insulation distance for the bonding wires 4a to 4c with a diameter of about 300 μm is larger than the required insulation distance for the bonding wires 4a to 4c with a diameter of about 125 μm when the maximum rated voltage is about 1.7 kV or less, which becomes a burden for miniaturization.

[0062] For example, when the distance between different potentials of the bonding wires 4a to 4c is as short as about 5 mm or less, the electric field strength becomes high, and when bubbles are generated around the bonding wires 4a to 4c, the insulation performance is significantly reduced, resulting in an increased risk of discharge and short circuit failure. By lengthening the distance between different potentials of the bonding wires 4a to 4c, the risk of short circuit failure caused by the generation of bubbles can be reduced, but it is difficult to obtain a sufficient insulation distance as high voltage, miniaturization, and high-density mounting progress. Although the electric field can be effectively mitigated by thickening the bonding wires, the chip area and cost increase, and it is also necessary to avoid damage to the pads connecting the bonding wires.

[0063] Therefore, in the semiconductor device involved in the embodiment, the outer periphery of the bonding wires 4a to 4c is covered by the insulating layers (covering layers) 9a to 9c. The insulating layers 9a to 9c include, for example, at least one resin selected from polyamide resin, polyimide resin, polyamide-imide resin, polyester resin, epoxy resin, phenolic resin, fluororesin, acrylic resin, silicone resin, polyolefin resin, and polyetherimide resin. The insulating layers 9a to 9c may also include two or more resins selected from the above resins.

[0064] As a method of forming the insulating layers 9a to 9c on the peripheries of the bonding wires 4a to 4c, the insulating layers 9a to 9c may be formed by spray coating, dip coating, or dispense coating after the bonding wires 4a to 4c are respectively bonded to the first main electrode 31, the conductive layers 11a and 11b, the external connection terminals 6a and 6b, etc. of the semiconductor chip 3. Alternatively, the bonding wires 4a to 4c covered with the insulating layers 9a to 9c in advance such as enameled wires may be prepared, and the bonding wires 4a to 4c may be respectively bonded to the first main electrode 31, the conductive layers 11a and 11b, the external connection terminals 6a and 6b, etc. of the semiconductor chip 3.

[0065] exist Figure 1 In the example, all the bonding wires 4a to 4c are covered with the insulating layers 9a to 9c, but only a part of the bonding wires 4a to 4c may be covered with the insulating layer. For example, when the bonding wire 4b is close to a different potential portion such as an external connection terminal 6a having a different potential from that of the bonding wire 4b, only the bonding wire 4b close to the different potential portion may be covered with the insulating layer 9b. By selectively covering a part of the bonding wires 4a to 4c with the insulating layer, the material cost and the process cost can be reduced.

[0066] The insulating layers 9a to 9c are harder than the sealing member 7, and the Young's modulus of the insulating layers 9a to 9c is higher than that of the sealing member 7. The Young's modulus of the insulating layers 9a to 9c is, for example, about 100 kPa or more and about 10 GPa or less, and more preferably, about 100 kPa or more and about 1 GPa or less. By making the Young's modulus of the insulating layers 9a to 9c be more than 100 kPa, the generation of bubbles inside the insulating layers 9a to 9c can be well suppressed. By making the Young's modulus of the insulating layers 9a to 9c be less than 1 GPa, the followability of the insulating layers 9a to 9c to the bonding wires 4a to 4c can be well ensured.

[0067] The ratio of the Young's modulus of the insulating layers 9a to 9c to the Young's modulus of the sealing member 7 is, for example, about 10 or more. By setting the ratio of the Young's modulus of the insulating layers 9a to 9c to the Young's modulus of the sealing member 7 to 10 or more, the generation of bubbles inside the insulating layers 9a to 9c can be well suppressed.

[0068] The dielectric constant of the insulating layers 9a to 9c may be higher or lower than the relative dielectric constant of the sealing member 7. As the relative dielectric constant of the insulating layers 9a to 9c is low, the electric field strength can be relaxed even when bubbles are generated inside the sealing member 7 and an air layer with a dielectric constant of 1 is inserted. The relative dielectric constant of the insulating layers 9a to 9c is, for example, about 7 or less, and more preferably about 3 or less. By setting the relative dielectric constant of the insulating layers 9a to 9c to 7 or less, the electric field strength can be relaxed even when bubbles are generated inside the sealing member 7. By setting the relative dielectric constant of the insulating layers 9a to 9c to 3 or less, the electric field strength can be further reduced even when bubbles are generated inside the sealing member 7. Reducing the relative dielectric constant of the insulating layers 9a to 9c is a technical idea opposite to the segmented insulation technology, which is a technology that averages the electric field strength borne by each layer by stacking insulating layers with higher dielectric constants as they approach the center material.

[0069] The smaller the ratio of the dielectric constant of the insulating layers 9a to 9c to the dielectric constant of the sealing member 7 is, the more the electric field strength on the surface side (sealing member 7 side) of the insulating layers 9a to 9c can be relaxed. The ratio of the dielectric constant of the insulating layers 9a to 9c to the dielectric constant of the sealing member 7 is, for example, about 3 or less. By making the ratio of the dielectric constant of the insulating layers 9a to 9c to the dielectric constant of the sealing member 7 3 or less, the electric field strength on the surface side of the insulating layers 9a to 9c can be well relaxed. The ratio of the dielectric constant of the insulating layers 9a to 9c to the dielectric constant of the sealing member 7 can also be about 2 or less, or about 1 or less, or about 0.5 or less.

[0070] The thickness of the insulating layers 9a to 9c can be adjusted by adjusting the viscosity of the insulating layers 9a to 9c before curing, the pull-out speed in the case of dip coating, the number of coating times in the case of spray coating or dip coating, etc. The thickness of the insulating layers 9a to 9c may be approximately constant, or it may not be constant and have thick parts and thin parts. The thicker the thickness of the insulating layers 9a to 9c, the more the electric field strength on the surface side (sealing member 7 side) of the insulating layers 9a to 9c can be relaxed. The thickness of the insulating layers 9a to 9c is, for example, about 25 μm or more and about 500 μm or less. By setting the thickness of the insulating layers 9a to 9c to be more than 25 μm, the electric field strength on the surface side of the insulating layers 9a to 9c can be well relaxed.

[0071] On the other main surface (lower surface) side of the insulating circuit substrate 1, a heat dissipation base 8 is provided via a bonding layer 14. The bonding layer 14 is composed of, for example, a sintered material or solder. The bonding layer 14 may be composed of the same material as the bonding layer 2, or may be composed of a material different from the bonding layer 2. The heat dissipation base 8 is composed of, for example, a metal such as copper (Cu).

[0072] The heat dissipation fins 13 are provided on the lower surface side of the heat dissipation base 8 via the bonding layer 15. In addition, the heat dissipation base 8 may not be provided, but the heat dissipation fins 13 may be provided on the lower surface side of the insulating circuit substrate 1 via the bonding layer 15. The heat dissipation fins 13 may not be provided and the lower surface of the heat dissipation fins 13 may be exposed.

[0073] The heat sink 13 is made of, for example, a metal such as copper (Cu). The bonding layer 15 is made of, for example, a sintered material, solder, or a thermal interface material (TIM). As the TIM, a thermally conductive grease, an elastomer sheet, a room temperature curing (RTV) rubber, a gel, a phase change material, a silver solder, and other thermally conductive materials (thermal conductive compounds) can be used. The bonding layer 15 can be made of the same material as the bonding layers 2 and 14, or it can be made of a material different from the bonding layers 2 and 14.

[0074] Figure 2 : This is a three-dimensional view of another example of a semiconductor device involved in the embodiment. On the upper surface side of the conductive layer 11a, a plurality of semiconductor chips 3a to 3d are provided via bonding layers 2a to 2d. On the upper surface side of the conductive layer 11a, an external connection terminal 6a is provided via bonding layer 2e. On the upper surface side of the conductive layer 11b, an external connection terminal 6b is provided via bonding layer 2f. A housing 5 is provided in a manner surrounding the conductive layers 11a, 11b, bonding layers 2a to 2f, and semiconductor chips 3a to 3d. Figure 2 In the figure, the sealing member 7 which fills the inner side of the case 5 and seals the conductive layers 11a and 11b, the bonding layers 2a to 2f, and the semiconductor chips 3a to 3d is omitted from illustration.

[0075] The plurality of bonding wires 4a respectively covered by the insulating layer 9a electrically connect the first main electrode on the upper surface side of the semiconductor chip 3a, the first main electrode on the upper surface side of the semiconductor chip 3c, and the conductive layer 11b. The bonding wires 4b covered by the insulating layer 9b electrically connect the first main electrode on the upper surface side of the semiconductor chip 3b, the first main electrode on the upper surface side of the semiconductor chip 3d, and the conductive layer 11b.

[0076] exist Figure 2 In the embodiment, the potential of the bonding wires 4a and 4b is the same as that of the external connection terminal 6b electrically connected to the first main electrode on the upper surface side of the semiconductor chips 3a to 3d, and is different from that of the external connection terminal 6a electrically connected to the second main electrode on the lower surface side of the semiconductor chips 3a to 3d. The bonding wires 4a and 4b may be arranged at a distance of 5 mm or less from the external connection terminal 6a having a different potential from that of the bonding wires 4a and 4b, and the sealing member 7 is interposed between the bonding wires 4a and 4b and the external connection terminal 6a. For example, only one of the bonding wires 4a closest to the external connection terminal 6a is close to the external connection terminal 6a to a distance of about 5 mm or less and is covered by the insulating layer 9a, and the other bonding wires 4a and 4b are farther from the external connection terminal 6a than 5 mm and may not be covered by the insulating layer.

[0077] Figure 3 The bonding wire 4a, the insulating layer 9a and the sealing member 7 are shown in a cross section in the longitudinal direction of the bonding wire 4a, and the sealing member 7 is modeled as a cylinder coaxial with the bonding wire 4a. The outer peripheral surface of the sealing member 7 corresponds to the terminal surface of different potentials. The electric field concentration is the largest around the bonding wire 4a.

[0078] exist Figure 3 ε1 represents the relative dielectric constant of the insulating layer 9a, ε2 represents the relative dielectric constant of the sealing member 7, a represents the radius of the bonding wire 4a, b represents the distance between the center of the bonding wire 4a and the terminal surface, and c represents the outer peripheral radius of the insulating layer 9a.

[0079] Here, assuming that the radius of the uncovered bonding wire is a' and the distance between the center of the uncovered bonding wire and the terminal surface is b', the electric field intensity E(r) of the uncovered bonding wire can be expressed by the following equation (1).

[0080] [Number 1]

[0081]

[0082] On the other hand, Figure 3As shown, in the bonding wire 4a covered by the insulating layer 9a, the electric field intensity E1(r) inside the insulating layer 9a and the electric field intensity E2(r) outside the insulating layer 9a can be expressed by the following equations (2) and (3), respectively.

[0083] [Number 2]

[0084]

[0085] [Number 3]

[0086]

[0087] In the semiconductor device involved in the embodiment, the covering thickness (ca) of the insulating layer 9a is set so that E2(a, b, c, r=c)≤E(a', b', r=a'). In addition, it is particularly effective in the area where the distance (ba) and (b'-a') between different potentials are less than about 5 mm.

[0088] Figure 4 As an example of a semiconductor device according to an embodiment, the relationship between the thickness of the insulating layer and the electric field strength on the surface side (sealing member side) of the insulating layer is shown when the distance between the bonding wire and the terminal of different potentials is set to 5 mm and 3.3 kV is applied between the bonding wire and the terminal. The diameter of the bonding wire is 300 μm and 400 μm, and the ratio of the relative dielectric constant ε1 of the insulating layer to the relative dielectric constant ε2 of the sealing member (ε1 / ε2) is 0.5, 1, and 2.

[0089] Figure 5 As a comparative example of the semiconductor device involved in the embodiment, the relationship between the diameter of the bonding wire and the electric field strength on the surface side of the bonding wire is shown when the distance between the bonding wire and the terminal of different potential is set to 5 mm and 3.3 kV is applied between the bonding wire and the terminal. Figure 4 and Figure 5 For convenience, Figure 5 The positions of the electric field strengths corresponding to the uncovered bonding wires with diameters of 400 μm and 500 μm, respectively, are marked with dashed auxiliary lines.

[0090] like Figure 4 As shown, in any bonding wire covered by an insulating layer and having a diameter of 300 μm and 400 μm, the thicker the insulating layer, the more relaxed the electric field strength can be. In addition, in any bonding wire covered by an insulating layer and having a diameter of 300 μm and 400 μm, the smaller the ratio (ε1 / ε2) of the relative dielectric constant ε1 of the insulating layer to the relative dielectric constant ε2 of the sealing member, the more relaxed the electric field strength can be.

[0091] like Figure 4 and Figure 5 As shown, in the case of a bonding wire with a diameter of 300 μm and covered with an insulating layer, in which the ratio of the relative dielectric constant ε1 of the insulating layer to the relative dielectric constant ε2 of the sealing member (ε1 / ε2) is 0.5, if the thickness of the insulating layer is set to 25 μm or more, the electric field strength can be relaxed to the same extent as in the case of an uncovered bonding wire with a diameter of 400 μm.

[0092] In addition, if Figure 4 and Figure 5 As shown, in the case of a bonding wire covered with an insulating layer, with the ratio of the relative dielectric constant ε1 of the insulating layer to the relative dielectric constant ε2 of the sealing member (ε1 / ε2) being 0.5 and with a diameter of 300 μm, if the thickness of the insulating layer is set to be greater than 50 μm, the electric field strength can be mitigated to the same extent as in the case of an uncovered bonding wire with a diameter of 500 μm.

[0093] In addition, if Figure 4 and Figure 5 As shown, in the case of a bonding wire with a diameter of 400 μm and covered with an insulating layer, in which the ratio of the relative dielectric constant ε1 of the insulating layer to the relative dielectric constant ε2 of the sealing member (ε1 / ε2) is 0.5, if the thickness of the insulating layer is set to 25 μm or more, the electric field strength can be relaxed to the same extent as in the case of an uncovered bonding wire with a diameter of 500 μm.

[0094] According to a semiconductor device according to an embodiment of the present invention, Figure 1 and Figure 2 As shown, the outer periphery of the bonding wires 4a to 4c, where the electric field is easily concentrated, is covered with the insulating layers 9a to 9c, which are harder than the sealing member 7 such as silicone gel. As a result, the generation of bubbles inside the insulating layers 9a to 9c can be suppressed, and thus the generation of bubbles between the bonding wires 4a to 4c and the sealing member 7 can be suppressed. Therefore, even if the peeling of the sealing member 7 and bubbles cannot be completely suppressed, the insulation reliability can be improved by providing the insulating layers 9a to 9c between the sealing member 7 and the bonding wires 4a to 4c.

[0095] For example, in an uncovered bonding wire, bubbles generated at the sealing member near the bonding wire or at the interface between the sealing member and other materials are entangled with the bonding wire, forming a gap around the bonding wire similar to peeling. In contrast, according to the semiconductor device involved in the embodiment, the outer periphery of the bonding wires 4a to 4c is covered with insulating layers 9a to 9c, so bubbles generated at the interface between the sealing member and other materials do not reach the bonding wire. This can also suppress the generation of bubbles near the bonding wire, thereby suppressing the formation of gaps.

[0096] Therefore, according to the semiconductor device involved in the embodiment, even if the maximum rated voltage of the semiconductor chip 3 is a high withstand voltage of about 3.3 kV or more, it is possible to obtain an electric field relaxation effect equivalent to thickening without changing the wire diameter, so that a miniaturized design equivalent to the maximum rated voltage of the semiconductor chip 3 of about 1.7 kV can be performed. For example, even if the maximum rated voltage of the semiconductor chip 3 is about 3.3 kV, it is possible to use bonding wires 4a to 4c with a relatively thin diameter of about 300 μm, thereby reducing the size of the gate pad used only for signal input on the element surface. In particular, in SiC elements that are more expensive than Si elements, since the element size can be reduced, the cost can be reduced.

[0097] In addition, according to the semiconductor device involved in the embodiment, the insulating layers 9a~9c are only arranged on the periphery of the bonding wires 4a~4c. Therefore, even if the insulating layers 9a~9c are harder than the sealing member 7, the followability of the insulating layers 9a~9c to the bonding wires 4a~4c can be maintained, and the peeling between the bonding wires 4a~4c and the insulating layers 9a~9c can be suppressed.

[0098] (Other Embodiments)

[0099] As described above, the present disclosure is described through the embodiments, but it should not be understood that the discussion and drawings constituting a part of the present disclosure are used to limit the present disclosure. Based on the present disclosure, various alternative embodiments, examples, and application techniques will be clear to those skilled in the art.

[0100] For example, the case where the bonding wires 4a to 4c of the semiconductor device according to the embodiment are connected to the first main electrode 31 of the semiconductor chip 3, the conductive layers 11a and 11b, and the external connection terminals 6a and 6b is illustrated, but the connection destinations of the bonding wires 4a to 4c are not limited thereto and can be appropriately selected. In addition, the number of bonding wires 4a to 4c of the semiconductor device according to the embodiment is not limited and can be appropriately selected.

[0101] In addition, the structures disclosed in the embodiments can be appropriately combined within the scope that does not cause contradictions. As such, it is self-evident that the present disclosure includes various embodiments that are not described herein. Therefore, the technical scope of the present disclosure is determined only by the specific matters of the invention involved in the claims that are properly derived from the above description.

[0102] Description of Reference Numerals

[0103] 1: insulating circuit substrate; 2, 2a~2f: bonding layer; 3, 3a~3d: semiconductor chip; 4a~4c: bonding wire; 5: housing; 6a, 6b: external connection terminal; 7: sealing member; 8: heat dissipation base; 9a~9c: insulating layer; 10: insulating plate; 11a, 11b, 12: conductive layer; 13: heat dissipation fin; 14, 15: bonding layer; 31: first main electrode; 32: gate electrode; 33: second main electrode.

Claims

1. A semiconductor device comprising: a semiconductor chip having a first main electrode on an upper surface side of the semiconductor chip and a second main electrode on a lower surface side of the semiconductor chip; a bonding wire connected to the first main electrode; an insulating layer covering the outer periphery of the bonding wire; as well as a sealing member that seals the semiconductor chip, the bonding wire, and the insulating layer, Here, a ratio of a Young's modulus of the insulating layer to a Young's modulus of the sealing member is 10 or more.

2. The semiconductor device according to claim 1, wherein The Young's modulus of the insulating layer is greater than or equal to 100 kPa and less than or equal to 10 GPa.

3. The semiconductor device according to claim 1 or 2, wherein: A ratio of a dielectric constant of the insulating layer to a dielectric constant of the sealing member is 3 or less.

4. The semiconductor device according to claim 1 or 2, wherein: The relative dielectric constant of the insulating layer is 7 or less.

5. The semiconductor device according to claim 1 or 2, wherein: The bonding wire has a diameter of 300 μm or more.

6. The semiconductor device according to claim 1 or 2, wherein: The thickness of the insulating layer is greater than 25 μm.

7. The semiconductor device according to claim 1 or 2, wherein: The thickness of the insulating layer is less than 500 μm.

8. The semiconductor device according to claim 1 or 2, wherein: The maximum rated voltage of the semiconductor chip is above 1.7 kV.

9. The semiconductor device according to claim 1 or 2, wherein: The bonding wire is provided at a position that is 5 mm or less away from a terminal having a different potential from that of the bonding wire, and the sealing member is interposed between the bonding wire and the terminal.

10. The semiconductor device according to claim 9, wherein The second main electrode is electrically connected to the terminal.

11. The semiconductor device according to claim 1 or 2, wherein: The insulating layer includes at least one resin selected from polyamide resin, polyimide resin, polyamideimide resin, polyester resin, epoxy resin, phenolic resin, fluororesin, acrylic resin, silicone resin, polyolefin resin, and polyetherimide resin.

12. The semiconductor device according to claim 1 or 2, wherein: The sealing member includes silicone gel or fluorine-based gel.

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