Buck converter

Abstract

According to the invention, the problem of miniaturization while common-mode noise is reduced is solved. A buck converter (100) includes a positive electrode input terminal (T1) and a negative electrode input terminal (T2), a positive electrode output terminal (T3) and a negative electrode output terminal (T4), a first positive side wiring portion (W11), a first negative side wiring portion (W12), a second positive side wiring portion (W21), a second negative side wiring portion (W22), a first capacitor (1), a second capacitor (2), a first inductor (11), a second inductor (12), a first switching element (Q1), and a second switching element (Q2). A third inductor (13), a third capacitor (3), a fourth capacitor (4), a fourth inductor (14), a ground conductor member (9), a fifth capacitor (5), a sixth capacitor (6), and a seventh capacitor (7). A seventh capacitor (7) is connected between the fifth node (N5) and the first capacitor (1).

Description

Technical Field

[0001] The present disclosure relates generally to buck converters, and more particularly to buck converters including switching elements. Background Art

[0002] Recently, in order to reduce the size of passive components included in switching power supply circuits, the switching frequency of switching elements has been increased more and more significantly. However, the increase in switching frequency will lead to an increase in electromagnetic noise. In particular, in switching power supply circuits, common mode noise will dominate in the frequency band of 1 MHz to 300 MHz (hereinafter referred to as the "MHz band"). This is why it is important to reduce common mode noise to cope with this significant increase in switching frequency.

[0003] Patent Document 1 discloses a power supply circuit having the capability of reducing common mode noise.

[0004] The power supply circuit of Patent Document 1 includes a DC / DC converter and a choke coil. The DC / DC converter includes a switching element for switching a DC input voltage supplied from a DC power supply, and supplies a DC output voltage corresponding to a duty ratio of an on-time and an off-time of the switching element to a load. The DC / DC converter includes an input side capacitor, a transistor (used as a switching element), a diode, and an output side capacitor.

[0005] The choke coil includes a pair of winding wires wound in opposite directions to each other and connected between a DC power supply and a DC / DC converter. The power supply circuit of Patent Document 1 reduces noise generated between a DC power supply and a load by using a choke coil.

[0006] The power supply circuit of Patent Document 1 needs to increase the impedance of the choke coil used as a noise filter as the switching frequency increases, which may increase the size of the choke coil and hinder the miniaturization of the power supply circuit.

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: WO 2017 / 002550 A1 Summary of the invention

[0010] An object of the present disclosure is to provide a buck converter having a capability that facilitates miniaturization while reducing common mode noise.

[0011] A buck converter according to an aspect of the present disclosure includes: a positive electrode input terminal and a negative electrode input terminal, a positive electrode output terminal and a negative electrode output terminal, a first positive side wiring section, a first negative side wiring section, a second positive side wiring section, a second negative side wiring section, a first capacitor, a second capacitor, a first inductor, a second inductor, a first switching element, a second switching element, a third inductor, a third capacitor, a fourth capacitor, a fourth inductor, a grounding conductor member, a fifth capacitor, a sixth capacitor, and a seventh capacitor. A first positive side wiring section is connected to the positive electrode input terminal. A first negative side wiring section is connected to the negative electrode input terminal. A second positive side wiring section is connected to the positive electrode output terminal. A second negative side wiring section is connected to the negative electrode output terminal. A first capacitor is connected between a first node of the first positive side wiring section and a second node of the first negative side wiring section. A second capacitor is connected between a third node of the first positive side wiring section and a fourth node of the first negative side wiring section. A first inductor is provided between the first node and the third node. A second inductor is provided between the second node and the fourth node. A first switching element is connected to the first positive side wiring section. The second switching element is connected between the first switching element and the first negative side wiring section. The third inductor is connected between the second positive side wiring section and the fifth node where the first switching element and the second switching element are connected together. The third capacitor is connected in parallel to the third inductor. The fourth capacitor is connected between the sixth node of the second positive side wiring section and the seventh node of the second negative side wiring section. The fourth inductor is arranged between the first negative side wiring section and the seventh node. The fifth capacitor is connected between the eighth node of the second positive side wiring section and the grounding conductor member. The eighth node is located between the sixth node of the second positive side wiring section and the positive electrode output terminal. The sixth capacitor is connected between the ninth node of the second negative side wiring section and the grounding conductor member. The ninth node is located between the seventh node of the second negative side wiring section and the negative electrode output terminal. The seventh capacitor is connected between the fifth node and the first capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic circuit diagram of a buck converter according to a first embodiment;

[0013] Figure 2 is the circuit diagram of a buck converter;

[0014] Figure 3 is a circuit diagram showing an equivalent circuit of a buck converter in the MHz band;

[0015] Figure 4 is a circuit diagram for simulating the noise generated in a buck converter;

[0016] Figure 5 is a graph showing frequency characteristics of noise generated in a buck converter and noise generated in a buck converter according to a comparative example;

[0017] Figure 6 is a circuit diagram of a buck converter according to a first modification of the first embodiment;

[0018] Figure 7 is a schematic circuit diagram of a buck converter according to a second variation of the first embodiment;

[0019] Figure 8 is a schematic circuit diagram of a buck converter according to a second embodiment;

[0020] Fig. 9 is a circuit diagram showing an equivalent circuit of a buck converter in the MHz band; and

[0021] Fig.10 is a circuit diagram of a step-down converter circuit according to a third embodiment. DETAILED DESCRIPTION

[0022] (First embodiment)

[0023] Now refer to Figures 1 to 3 A step-down converter 100 according to a first embodiment is described.

[0024] (1) Overview

[0025] like Figure 1 and Figure 2 As shown, the buck converter 100 includes a positive electrode input terminal T1 and a negative electrode input terminal T2 and a positive electrode output terminal T3 and a negative electrode output terminal T4. The buck converter 100 converts a first voltage input between the positive electrode input terminal T1 and the negative electrode input terminal T2 into a second voltage less than the first voltage, and outputs the second voltage between the positive electrode output terminal T3 and the negative electrode output terminal T4. In the buck converter 100, a DC power source may be connected, for example, between the positive electrode input terminal T1 and the negative electrode input terminal T2, and a load may be connected, for example, between the positive electrode output terminal T3 and the negative electrode output terminal T4.

[0026] (2) Details

[0027] like Figure 1As shown, the buck converter 100 includes a positive electrode input terminal T1 and a negative electrode input terminal T2, a positive electrode output terminal T3 and a negative electrode output terminal T4, a first positive side wiring section W11, a first negative side wiring section W12, a second positive side wiring section W21, and a second negative side wiring section W22. The buck converter 100 also includes a first capacitor 1, a second capacitor 2, a first inductor 11, a second inductor 12, a first switching element Q1, a second switching element Q2, a third inductor 13, a third capacitor 3, a fourth capacitor 4, and a fourth inductor 14. The buck converter 100 also includes a grounding conductor member 9, a fifth capacitor 5, a sixth capacitor 6, and a seventh capacitor 7. The buck converter 100 also includes a controller 10.

[0028] The positive electrode input terminal T1 can be connected to a DC power source E1 (refer to Figure 4 ) has a high potential output terminal (i.e., a positive electrode). The DC power supply E1 may, for example, include a battery. However, this is merely an example and should not be construed as limiting. Alternatively, the DC power supply E1 may also include a DC / DC converter or an AC / DC converter.

[0029] The negative electrode input terminal T2 may be connected to a DC power source E1 (refer to Figure 4 )'s low potential output terminal (i.e., negative electrode).

[0030] Load R12 (reference Figure 4 ) can be connected between the positive electrode output terminal T3 and the negative electrode output terminal T4, for example. Alternatively, in the buck converter 100, for example, a DC / AC converter can be connected between the positive electrode output terminal T3 and the negative electrode output terminal T4 instead of the load R12.

[0031] The first positive side wiring section W11 is connected to the positive electrode input terminal T1. That is, the first positive side wiring section W11 is a wiring section connected to the positive electrode input terminal T1 in the buck converter 100. More specifically, the first positive side wiring section W11 is a wiring section between the positive electrode input terminal T1 and the first switching element Q1. In other words, the first positive side wiring section W11 is an input positive electrode bus bar.

[0032] The first negative side wiring section W12 is connected to the negative electrode input terminal T2. That is, the first negative side wiring section W12 is a wiring section connected to the negative electrode input terminal T2 in the buck converter 100. The first negative side wiring section W12 has a first end and a second end. The negative electrode input terminal T2 is connected to the first end of the first negative side wiring section W12. The second switching element Q2 is connected to the second end of the first negative side wiring section W12. Thus, a series circuit of the first switching element Q1 and the second switching element Q2 is connected between the first positive side wiring section W11 and the first negative side wiring section W12. The first negative side wiring section W12 is an input negative electrode bus.

[0033] The second positive side wiring section W21 is connected to the positive electrode output terminal T3. That is, the second positive side wiring section W21 is a wiring section connected to the positive electrode output terminal T3 in the buck converter 100. The second positive side wiring section W21 is a wiring section between the fifth node N5 and the positive electrode output terminal T3. The fifth node N5 is a node on the path between the first switching element Q1 and the second switching element Q2. The second positive side wiring section W21 is an output positive electrode bus.

[0034] The second negative side wiring section W22 is connected to the negative electrode output terminal T4. That is, the second negative side wiring section W22 is a wiring section in the buck converter 100 that is connected to the negative electrode output terminal T4. The second negative side wiring section W22 has a first end and a second end. The first end of the second negative side wiring section W22 is connected to the second switching element Q2 and the second end of the first negative side wiring section W12. The second end of the second negative side wiring section W22 is connected to the negative electrode output terminal T4. The second negative side wiring section W22 is an output negative electrode bus.

[0035] The first capacitor 1 is connected between the first node N1 of the first positive side wiring section W11 and the second node N2 of the first negative side wiring section W12. In other words, the first capacitor 1 is connected between the positive electrode input terminal T1 and the negative electrode input terminal T2. The first capacitor 1 has a first end and a second end. In the first capacitor 1, the first end of the first capacitor 1 is connected to the first node N1 of the first positive side wiring section W11, and the second end of the first capacitor 1 is connected to the second node N2 of the first negative side wiring section W12. The first capacitor 1 has a function of serving as a smoothing capacitor. The first capacitor 1 may be, for example, an electrolytic capacitor. The capacitance of the first capacitor 1 may be, for example, equal to or greater than 200nF and equal to or less than 500μF.

[0036] The second capacitor 2 is connected between the third node N3 of the first positive side wiring section W11 and the fourth node N4 of the first negative side wiring section W12. In other words, the first capacitor 1 is connected between the positive electrode input terminal T1 and the negative electrode input terminal T2. The second capacitor 2 has a function of serving as a smoothing capacitor. The second capacitor 2 may be, for example, an electrolytic capacitor. The capacitance of the second capacitor 2 may be, for example, equal to or greater than 200 nF and equal to or less than 500 μF.

[0037] The first inductor 11 is arranged between the first node N1 and the third node N3. The inductance of the first inductor 11 is smaller than the inductance of the third inductor 13. The inductance of the first inductor 11 may be, for example, equal to or greater than 2nH and equal to or less than 30μH. The first inductor 11 may be composed of, for example, a portion of the first positive side wiring portion W11. In other words, the first inductor 11 is composed of, for example, a parasitic inductance component in a portion of the first positive side wiring portion W11 located between the first node N1 and the third node N3. In this case, the inductance of the first inductor 11 may be calculated, for example, as a parasitic inductance component formed in a portion of the first positive side wiring portion W11 located between the first node N1 and the third node N3 on the circuit board by three-dimensional electromagnetic field analysis or impedance measurement.

[0038] The second inductor 12 is arranged between the second node N2 and the fourth node N4. The inductance of the second inductor 12 is smaller than the inductance of the third inductor 13. The inductance of the second inductor 12 may be, for example, equal to or greater than 2nH and equal to or less than 30nH. The second inductor 12 may be constituted by, for example, a portion of the first negative side wiring portion W12. In other words, the second inductor 12 is constituted by, for example, a parasitic inductance component in a portion of the first negative side wiring portion W12 located between the second node N2 and the fourth node N4. In this case, the inductance of the second inductor 12 may be calculated, for example, by three-dimensional electromagnetic field analysis or impedance measurement as a parasitic inductance component formed in a portion of the first negative side wiring portion W12 located between the second node N2 and the fourth node N4 on the circuit board.

[0039] The first switching element Q1 is connected to the first positive-side wiring portion W11. The second switching element Q2 is connected between the first switching element Q1 and the first negative-side wiring portion W12.

[0040] Each of the first switching element Q1 and the second switching element Q2 may be, for example, Figure 2 The normally-off n-channel metal oxide semiconductor field effect transistor (MOSFET) shown in FIG. Figure 2, the first diode D1 connected in anti-parallel to the first switching element Q1 is a parasitic diode of an n-channel MOSFET used as the first switching element Q1. However, this is merely an example and should not be construed as limiting. Alternatively, the first diode D1 may also be an external diode. In addition, the second diode D2 connected in anti-parallel to the second switching element Q2 is a parasitic diode of an n-channel MOSFET used as the second switching element Q2. However, this is merely an example and should not be construed as limiting. Alternatively, the second diode D2 may also be an external diode. In Figure 2 In the example shown, each of the first switching element Q1 and the second switching element Q2 includes a first main terminal (drain terminal), a second main terminal (source terminal), and a control terminal (gate terminal). Figure 2 In the example shown, the first main terminal of the first switching element Q1 is connected to the first positive side wiring section W11, the second main terminal of the first switching element Q1 is connected to the first main terminal of the second switching element Q2, and the second main terminal of the second switching element Q2 is connected to the first negative side wiring section W12. In the first diode D1, the anode of the first diode D1 is connected to the second main terminal (source terminal) of the first switching element Q1, and the cathode of the first diode D1 is connected to the first main terminal (drain terminal) of the first switching element Q1. In the second diode D2, the anode of the second diode D2 is connected to the second main terminal (source terminal) of the second switching element Q2, and the cathode of the second diode D2 is connected to the first main terminal (drain terminal) of the second switching element Q2.

[0041] In the buck converter 100, the first switching element Q1 and the second switching element Q2 are controlled by the controller 10. In the buck converter 100, the first switching element Q1 and the second switching element Q2 are alternately turned on and off. The switching frequency of the first switching element Q1 and the second switching element Q2 may be, for example, equal to or higher than 1 kHz and equal to or lower than 1 MHz.

[0042] The third inductor 13 is connected between the fifth node N5 that connects the first switching element Q1 and the second switching element Q2 and the second positive wiring portion W21. The fifth node N5 is provided for the wiring portion between the first switching element Q1 and the second switching element Q2. From the viewpoint of circuit configuration, the fifth node N5 is a connection node between the first switching element Q1 and the second switching element Q2. The third inductor 13 may be, for example, a choke coil. The inductance of the third inductor 13 may be, for example, equal to or greater than 200 nH and equal to or less than 30 μH.

[0043] The third capacitor 3 is connected in parallel to the third inductor 13. The capacitance of the third capacitor 3 is smaller than the capacitance of any one of the first capacitor 1, the second capacitor 2, and the fourth capacitor 4. The third capacitor 3 can be implemented as, for example, the inter-winding capacitance of the third inductor 13. In this case, the capacitance of the third capacitor 3 can be calculated as the inter-winding capacitance of the third inductor 13 used as a choke coil by, for example, three-dimensional electromagnetic field analysis or impedance measurement. Therefore, the capacitance of the third capacitor 3 can be uniquely determined by the winding wire structure of the third inductor 13 as a choke coil.

[0044] The fourth capacitor 4 is connected between the sixth node N6 of the second positive side wiring section W21 and the seventh node N7 of the second negative side wiring section W22. In other words, the fourth capacitor 4 is connected between the positive electrode output terminal T3 and the negative electrode output terminal T4. The fourth capacitor 4 has a first end and a second end. In the fourth capacitor 4, the first end of the fourth capacitor 4 is connected to the sixth node N6 of the second positive side wiring section W21, and the second end of the fourth capacitor 4 is connected to the seventh node N7 of the second negative side wiring section W22. The fourth capacitor 4 has a function of serving as a smoothing capacitor. The fourth capacitor 4 may be, for example, an electrolytic capacitor. The capacitance of the fourth capacitor 4 may be, for example, equal to or greater than 200nF and equal to or less than 500μF.

[0045] The fourth inductor 14 is arranged between the first negative side wiring portion W12 and the seventh node N7 of the second negative side wiring portion W22. The inductance of the fourth inductor 14 is smaller than the inductance of the third inductor 13. The inductance of the fourth inductor 14 may be, for example, equal to or greater than 2nH and equal to or less than 30nH. The fourth inductor 14 may be constituted by, for example, a portion of the second negative side wiring portion W22. In other words, the fourth inductor 14 is constituted by, for example, a parasitic inductance component in a portion of the second negative side wiring portion W22 located between the first negative side wiring portion W12 and the seventh node N7. In this case, the inductance of the fourth inductor 14 may be calculated, for example, by three-dimensional electromagnetic field analysis or impedance measurement as a parasitic inductance component formed in a portion of the second negative side wiring portion W22 located between the first negative side wiring portion W12 and the seventh node N7 on the circuit board.

[0046] The grounding conductor member 9 can be configured as, for example, a housing of the buck converter 100. The housing accommodates a circuit module of the buck converter 100. The circuit module includes a circuit board (e.g., a printed wiring board) and a plurality of circuit components mounted on the circuit board. The plurality of circuit components include a first capacitor 1, a second capacitor 2, a first switching element Q1, a second switching element Q2, a third inductor 13, and a fourth capacitor 4. The housing has conductivity. The material used for the housing can be, for example, a metal or an alloy. The housing has the function of shielding surrounding components from the leakage magnetic field generated by the buck converter 100. Alternatively, the grounding conductor member 9 can be a grounding conductor included in the circuit board.

[0047] The fifth capacitor 5 is connected between the eighth node N8 of the second positive side wiring section W21 and the grounding conductor member 9. The eighth node N8 is located between the sixth node N6 of the second positive side wiring section W21 and the positive electrode output terminal T3. The capacitance of the fifth capacitor 5 is smaller than the capacitance of any one of the first capacitor 1, the second capacitor 3, and the fourth capacitor 4. Alternatively, the fifth capacitor 5 may be a parasitic capacitance generated between the second positive side wiring section W21 and the grounding conductor member 9.

[0048] The sixth capacitor 6 is connected between the ninth node N9 of the second negative wiring portion W22 and the grounding conductor member 9. The ninth node N9 is located between the seventh node N7 of the second negative wiring portion W22 and the negative electrode output terminal T4. The capacitance of the sixth capacitor 6 is smaller than the capacitance of any one of the first capacitor 1, the second capacitor 2, and the fourth capacitor 4. Alternatively, the sixth capacitor 6 may be a parasitic capacitance generated between the second negative wiring portion W22 and the grounding conductor member 9.

[0049] The seventh capacitor 7 is connected between the fifth node N5 and the first capacitor 1 .

[0050] The controller 10 controls the first switching element Q1 and the second switching element Q2. The agent for performing the function of the controller 10 includes a computer system. The computer system includes a single or multiple computers. The computer system may include a processor and a memory as its main hardware components. The computer system is used as an agent for performing the function of the controller 10 according to the present disclosure by causing the processor to execute a program stored in the memory of the computer system. The program may be pre-stored in the memory of the computer system. Alternatively, the program may also be downloaded via a telecommunications line, or distributed after being recorded in a non-transitory storage medium such as a memory card, an optical disk, or a hard disk drive (disk) (any of which is readable by the computer system). The processor of the computer system may be composed of a single or multiple electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). These electronic circuits may be integrated together on a single chip or distributed on multiple chips, whichever is appropriate. These multiple chips may be aggregated together in a single device or distributed in multiple devices without limitation.

[0051] The controller 10 outputs a first control signal for controlling the on / off state of the first switching element Q1 and a second control signal for controlling the on / off state of the second switching element Q2. Each of the first control signal and the second control signal may be, for example, a pulse width modulation (PWM) signal having a potential level that alternates between a first potential level (hereinafter referred to as a "low level") and a second potential level (hereinafter referred to as a "high level") higher than the first potential level. The first switching element Q1 becomes conductive when the first control signal has a high level, and becomes off when the first control signal has a low level. The second switching element Q2 becomes conductive when the second control signal has a high level, and becomes off when the second control signal has a low level. In addition, in order to prevent the respective on periods of the first switching element Q1 and the second switching element Q2 from overlapping each other, the controller 10 sets a dead time period between the high level period of the first control signal and the high level period of the second control signal.

[0052] In the following description, circuit constants of respective constituent elements will be defined as follows.

[0053] In this specification, the capacitance of the first capacitor 1 will be designated by C1, the capacitance of the second capacitor 2 will be designated by C2, the capacitance of the third capacitor 3 will be designated by C3, the capacitance of the fourth capacitor 4 will be designated by C4, the capacitance of the fifth capacitor 5 will be designated by C5, the capacitance of the sixth capacitor 6 will be designated by C6, and the capacitance of the seventh capacitor 7 will be designated by C7.

[0054] Furthermore, in the following description, the inductance of the first inductor 11 will be designated by L1 , the inductance of the second inductor 12 will be designated by L2 , the inductance of the third inductor 13 will be designated by L3 , and the inductance of the fourth inductor 14 will be designated by L4 .

[0055] Figure 3 It is shown as Figure 1 The circuit diagram of the equivalent circuit of the buck converter 100 in the MHz band is shown. Figure 3 In the embodiment, the inductor 15 is an inductor having a parallel combined inductance of the first inductor 11 and the second inductor 12 (=(L1×L2) / (L1+L2)). Figure 3 , capacitor 56 is a capacitor having a parallel combined capacitance of fifth capacitor 5 and sixth capacitor 6 (= C5 + C6 ).

[0056] Each of the first capacitor 1, the second capacitor 2, and the fourth capacitor 4 is a smoothing capacitor and has a relatively large capacitance (e.g., equal to or greater than 200nF and equal to or less than 500μF). In the buck converter 100, the impedance of each of the first capacitor 1, the second capacitor 2, and the fourth capacitor 4 on the MHz band is small to a negligible degree compared with the impedance of each of the first inductor 11, the second inductor 12, and the third capacitor 3 on the MHz band. Thus, in the equivalent circuit of the buck converter 100 on the MHz band, the first node N1 and the second node N2 can be regarded as short-circuited to each other, and thus can be regarded as the same node. In addition, in the equivalent circuit of the buck converter 100 on the MHz band, the third node N3 and the fourth node N4 can be regarded as short-circuited to each other, and thus can be regarded as the same node. In addition, in the equivalent circuit of the buck converter 100 on the MHz band, the sixth node N6 and the seventh node N7 can be regarded as short-circuited to each other, and thus can be regarded as the same node.

[0057] In addition, the third inductor 13 is a choke coil and has an inductance of, for example, equal to or greater than 200 nH and equal to or less than 30 μH. In the buck converter 100, the impedance of the third inductor 13 on the MHz band is much greater than the impedance of each of the first inductor 11 and the second inductor 12 on the MHz band. Therefore, in the equivalent circuit of the buck converter 100 on the MHz band, the portion including the third inductor 13 can be regarded as open.

[0058] In the equivalent circuit diagram of the buck converter 100 on the MHz frequency band, a switching circuit portion including a first switching element Q1 and a second switching element Q2 is connected between the fifth node N5 and the third node N3 and the fourth node N4 as a noise source for generating a voltage Vsw between the fifth node N5 and the third node N3 (or the fourth node N4) due to the operation of the first switching element Q1 and the second switching element Q2.

[0059] If the mode conversion outside the circuit of the buck converter 100 is ignored, the common-mode noise of the buck converter 100 in the MHz band originates from the potential V1 (common-mode voltage V1) at the first node N1 (or the second node N2) relative to the grounded conductor member 9 or the current I1 flowing through the grounded conductor member 9 (hereinafter also referred to as "common-mode current I1").

[0060] Figure 3 The equivalent circuit shown has a Wheatstone bridge circuit configuration. Thus, if the condition that the ratio of the impedance of the seventh capacitor 7 to the parallel combined impedance of the first inductor 11 and the second inductor 12 is equal to the ratio of the impedance of the third capacitor 3 to the impedance of the fourth inductor 14 is satisfied, the voltage transfer coefficient (=V1 / Vsw) from the switching circuit portion to the positive electrode input terminal T1 and the negative electrode input terminal T2 will be zero. That is, if the condition represented by the following formula (1) is satisfied, the voltage transfer coefficient will ideally be equal to zero.

[0061] [Mathematical formula 1]

[0062]

[0063] where ω is the angular frequency.

[0064] In equation (1), the angular frequency ω can be offset on both sides. Therefore, equation (1) can be modified into the following equation (2):

[0065] [Mathematical formula 2]

[0066]

[0067] The buck converter 100 can reduce the generation of common-mode noise caused by the operation of the first switching element Q1 and the second switching element Q2 regardless of the frequency in the MHz band by designing the various circuit constants (L1, L2, L4, C3, C7) to satisfy the condition defined by equation (2) (hereinafter referred to as the "impedance balance condition").

[0068] In this case, equation (2) can be modified into the following equation (3):

[0069] [Mathematical formula 3]

[0070]

[0071] Therefore, the buck converter 100 can reduce the generation of common mode noise caused by the operation of the first switching element Q1 and the second switching element Q2 regardless of the frequency in the MHz band by designing the various circuit constants (L1, L2, L4, C3, C7) to satisfy the condition defined by equation (3).

[0072] In order to reduce the generation of common mode noise compared to the case where the seventh capacitor 7 is not provided, the capacitance C7 of the seventh capacitor 7 does not necessarily have to have a value that satisfies the impedance balance condition, but may also have a value that is 0.5 to twice as large as the value when the impedance balance condition is satisfied. That is, the capacitance C7 of the seventh capacitor 7 may have a value that satisfies the following formula (4):

[0073] [Formula 4]

[0074]

[0075] That is, even if the impedance balance condition is not satisfied, the buck converter 100 can reduce common mode noise compared to a configuration that does not include the seventh capacitor 7 as long as the capacitance C7 of the seventh capacitor 7 has a value that is 0.5 to twice as large as the value when the impedance balance condition is satisfied.

[0076] (3) Characteristics

[0077] exist Figure 5 , reference numeral A1 indicates a first example of allowing the buck converter 100 according to the first embodiment to be Figure 4 The common mode current I1 (reference Figure 3 The common mode current I1 includes a current flowing from the fifth node N5 to the ground conductor member 9 via the sixth node N6 and the fifth capacitor 5, and a current flowing from the fifth node N5 to the ground conductor member 9 via the seventh node N7 and the sixth capacitor 6.

[0078] exist Figure 4 In the circuit shown, a DC power source E1 is connected between the positive electrode input terminal T1 and the negative electrode input terminal T2 of the step-down converter 100 via a pseudo power supply circuit network 17. Figure 4 In the example shown, the pseudo power supply circuit network 17 is a circuit network for stabilizing the power supply impedance when the DC power supply E1 is viewed from the step-down converter 100. Figure 4 In the example shown, the pseudo power supply circuit network 17 includes two inductors 170, 175, four capacitors 171, 172, 176, 177 and four resistors 173, 174, 178, 179. Figure 4 In the example shown, load R12 is a load resistor.

[0079] like Figure 5 The frequency characteristic of the common mode current I1 indicated by the reference symbol A1 in FIG. 1 is obtained by using Figure 4 The simulation model of the circuit shown in FIG. 1 is obtained by performing transient analysis to calculate the common mode current I1 flowing through the ground conductor member 9 and performing fast Fourier transform on the common mode current I1. Figure 5 Reference symbol B1 shown indicates the frequency characteristic of the common mode current in the buck converter according to the comparative example. The buck converter according to the comparative example does not include the seventh capacitor 7 of the buck converter 100 according to the first embodiment.

[0080] For the first example described above, the circuit constants of the respective constituent elements are set to the values ​​shown in Table 1 below so that the impedance balance condition is satisfied. In addition, for each of the first capacitor 1, the second capacitor 2, the fourth capacitor 4, the fifth capacitor 5, and the sixth capacitor 6, its equivalent series resistance (ESR) and equivalent series inductance (ESL) are considered.

[0081] [Table 1]

[0082]

[0083]

[0084] In addition, if Figure 5 The frequency characteristics of the common mode current I1 according to the first example indicated by reference symbol A1 in FIG. 1 are obtained when the output voltage of the DC power supply E1 is set to 24 V, the switching frequency of each of the first switching element Q1 and the second switching element Q2 is set to 100 kHz, and the output power of the step-down converter 100 is set to 144 W. Figure 5 The frequency characteristics of the common mode current according to the comparative example indicated by reference symbol B1 are obtained under the same conditions as those of the first example.

[0085] As from Figure 5 It can be seen that, according to the first example, the common mode current can be reduced by several tens of dBμA at a frequency band equal to or higher than 20 MHz, as compared with the comparative example.

[0086] For the first example described above, these results are obtained by simulating using circuit constants designed to satisfy the impedance balance condition. However, in reality, the circuit constants will be different for each constituent element. Thus, simulations are performed in a case where all circuit constants except the capacitance C7 of the seventh capacitor 7 are set to the same values ​​as those shown in Table 1 and the capacitance C7 of the seventh capacitor 7 is changed. The results of these simulations are summarized in Table 2 below. According to the first example, the impedance balance condition is satisfied only when the capacitance C7 of the seventh capacitor 7 is 4nF. Note that the values ​​of the common mode current in Table 2 are the values ​​of the common mode current at 50MHz.

[0087] [Table 2]

[0088] Capacitor C7 Common mode current Comparison Examples – 44.3dBμA Example 2 2nF 43.4dBμA Example 3 3nF 40.3dBμA Example 1 4nF 34.1dBμA Example 4 5nF 34.3dBμA Example 5 6nF 37.7dBμA Example 6 7nF 39.7dBμA Example 7 8nF 41.1dBμA

[0089] As can be seen from Table 2, if the capacitance C7 of the seventh capacitor 7 satisfies the impedance balance condition (i.e., when C7=4nF), the common mode current becomes minimum. In addition, it can also be seen that even if the capacitance C7 of the seventh capacitor 7 does not satisfy the impedance balance condition, but has a value as large as 0.5 times to twice the value when the impedance balance condition is satisfied, the common mode current can be reduced compared to the comparative example.

[0090] (4) Advantages

[0091] The buck converter 100 according to the first embodiment includes a first capacitor 1, a second capacitor 2, a first inductor 11, a second inductor 12, a third capacitor 3, a fourth inductor 14, a fifth capacitor 5, a sixth capacitor 6 and a seventh capacitor 7. The seventh capacitor 7 is connected between the fifth node N5 and the first capacitor 1. This enables the buck converter 100 according to the first embodiment to contribute to miniaturization while reducing common mode noise. More specifically, the buck converter 100 according to the first embodiment includes a first inductor 11, a second inductor 12, a third capacitor 3, a fourth inductor 14 and a seventh capacitor 7, so that the equivalent circuit on the MHz band will be a circuit with a Wheatstone bridge circuit configuration. This enables the buck converter 100 according to the first embodiment to reduce common mode noise without using any common mode choke coils, thereby contributing to miniaturization while reducing common mode noise.

[0092] In addition, if the capacitance C7 of the seventh capacitor 7 has a value satisfying the equation (3), the buck converter 100 according to the first embodiment can further reduce the common mode noise.

[0093] In addition, if the capacitance C7 of the seventh capacitor 7 has a value that satisfies equation (4), the buck converter 100 according to the first embodiment can use a capacitor having a larger tolerance on the capacitance C7 as the seventh capacitor 7, thereby reducing the cost of the seventh capacitor 7 and ultimately reducing the total cost of the buck converter 100.

[0094] (5) Modification of the First Embodiment

[0095] (5.1) First Modification

[0096] Reference Figure 6 A buck converter 101 according to a first modification of the first embodiment is described. In the following description, the buck converter 101 according to the first modification has the same structure as the buck converter 100 according to the first embodiment described above (refer to FIG. 1 ). Figure 1 and Figure 2 ) will be designated by the same figure mark as the figure mark of the corresponding part, and its description will be omitted herein.

[0097] In the buck converter 101 according to the first modification, the second switching element Q2 is implemented as a diode, which is a difference from the buck converter 100 according to the first embodiment. In the diode used as the second switching element Q2, the anode of the diode is connected to the first negative side wiring portion W12, and the cathode of the diode is connected to the first switching element Q1. In the buck converter 101 according to the first modification, the controller 10 controls the on / off state of the first switching element Q1.

[0098] The step-down converter 101 according to the first modification includes the seventh capacitor 7 similarly to the step-down converter 100 according to the first embodiment, and thus can contribute to miniaturization while reducing common mode noise.

[0099] (5.2) Second Modification

[0100] Reference Figure 7 A buck converter 102 according to a second modification of the first embodiment will be described. In the following description, the buck converter 102 according to the second modification has the same features as the buck converter 100 according to the first embodiment described above (refer to FIG. 1 ). Figure 1 and Figure 2 ) will be designated by the same figure mark as the figure mark of the corresponding part, and its description will be omitted herein.

[0101] In the buck converter 102 according to the second modification, the seventh capacitor 7 is connected between the first node N1 and the fifth node N5 instead of the second node N2 and the fifth node N5, which is different from the buck converter 100 according to the first embodiment described above.

[0102] As in the buck converter 100 according to the first embodiment described above, in the buck converter 102 according to the second modification, the first node N1 and the second node N2 can be regarded as the same node in the MHz band. Therefore, the equivalent circuit of the buck converter 102 according to the second modification in the MHz band is the same as Figure 3 Therefore, like the buck converter 100 according to the first embodiment, the buck converter 102 according to the second modification includes the seventh capacitor 7, and thus can contribute to miniaturization while reducing common mode noise.

[0103] In addition, in the buck converter 100 according to the first embodiment, when viewed in a plan view in the thickness direction defined for the circuit board, the wiring portion between the fifth node N5 and the seventh capacitor 7 intersects with the first negative side wiring portion W12. Thus, sometimes a configuration is adopted in which a multilayer printed wiring board is adopted as the circuit board, and a part of the wiring portion between the fifth node N5 and the seventh capacitor 7 is extended to a layer different from the layer including the first negative side wiring portion W12 in the circuit board, for example, through a through-hole conductor. In contrast, in the buck converter 102 according to the second modification, the wiring portion between the fifth node N5 and the seventh capacitor 7 does not intersect with any other wiring portion (including the first positive side wiring portion W11 and the first negative side wiring portion W12), thereby reducing the possibility of generating an unnecessary parasitic inductance component in the wiring portion between the fifth node N5 and the seventh capacitor 7. In addition, the step-down converter 102 according to the second modification enables the wiring section between the fifth node N5 and the seventh capacitor 7, the first positive side wiring section W11 and the first negative side wiring section W12 to be arranged on the same layer, thereby increasing the degree of freedom of wiring design of the circuit board.

[0104] (5.3) Third Modification

[0105] The buck converter 100 according to the third modified example of the first embodiment has the same features as the buck converter 100 according to the first embodiment described above (see Figure 1 and Figure 2 ) has the same circuit configuration, so its illustration is omitted.

[0106] In the buck converter 100 according to the third modification, each of the first inductor 11, the second inductor 12, and the fourth inductor 14 is implemented as a chip inductor, and each of the third capacitor 3 and the seventh capacitor 7 is implemented as a chip capacitor, which is a difference from the buck converter 100 according to the first embodiment. Each of the inductance L1 of the first inductor 11, the inductance L2 of the second inductor 12, and the inductance L4 of the fourth inductor 14 may be, for example, equal to or greater than 2 nH and equal to or less than 30 nH. Each of the capacitance C3 of the third capacitor 3 and the capacitance C7 of the seventh capacitor 7 may be equal to or greater than 2 nF and equal to or less than 30 nF.

[0107] The buck converter 100 according to the third variant makes it easier to calculate the impedance between the first node N1 and the third node N3, the impedance between the second node N2 and the fourth node N4, the impedance between the fourth node N4 and the seventh node N7, the impedance between the fifth node N5 and the sixth node N6, and the impedance between the second node N2 and the fifth node N5, thereby making it easier to design the buck converter 100 that satisfies the impedance balance condition.

[0108] (Second embodiment)

[0109] Reference Figure 8 A buck converter 103 according to the second embodiment is described. In the following description, the buck converter 103 according to the second embodiment has the same structure as the buck converter 102 according to the second modification of the first embodiment described above (refer to FIG. 1 ). Figure 7 ) will be designated by the same figure mark as the figure mark of the corresponding part, and its description will be omitted herein.

[0110] (1) Configuration

[0111] The buck converter 103 according to the second embodiment further includes an eighth capacitor 8 connected between the fifth node N5 and the second node N2, which is different from the buck converter 102 according to the second modification of the first embodiment. Thus, the buck converter 103 according to the second embodiment includes the seventh capacitor 7 connected to the first end of the first capacitor 1 via the first node N1 and the eighth capacitor 8 connected to the second end of the first capacitor 1 via the second node N2.

[0112] Fig. 9 It is shown as Figure 8 The circuit diagram of the equivalent circuit of the buck converter 103 in the MHz band is shown. Fig. 9 In the embodiment, the inductor 15 is an inductor having a parallel combined inductance of the first inductor 11 and the second inductor 12 (=(L1×L2) / (L1+L2)). Fig. 9, capacitor 56 is a capacitor having a parallel combined capacitance of fifth capacitor 5 and sixth capacitor 6 (= C5 + C6 ).

[0113] As in the first embodiment described above, the equivalent circuit of the buck converter 103 according to the second embodiment in the MHz band has a Wheatstone bridge circuit configuration. The impedance balance condition according to the second embodiment is expressed by the following equation (5):

[0114] [Formula 5]

[0115]

[0116] Wherein, C8 is the capacitance of the eighth capacitor 8 .

[0117] The buck converter 103 can reduce the generation of common-mode noise caused by the operation of the first switching element Q1 and the second switching element Q2 regardless of the frequency in the MHz band by designing various circuit constants (L1, L2, L4, C3, C7, C8) to satisfy the impedance balance condition defined by equation (5).

[0118] In this case, equation (5) can be modified into the following equation (6):

[0119] [Mathematical formula 6]

[0120]

[0121] Therefore, the buck converter 103 can further reduce the generation of common-mode noise caused by the operation of the first switching element Q1 and the second switching element Q2 regardless of the frequency in the MHz band by designing the various circuit constants (L1, L2, L4, C3, C7, C8) to satisfy the condition defined by equation (6).

[0122] In order to reduce the generation of common mode noise compared to the case where neither the seventh capacitor 7 nor the eighth capacitor 8 is provided, the combined capacitance (C7+C8) of the seventh capacitor 7 and the eighth capacitor 8 does not necessarily have to have a value that satisfies the impedance balance condition, but may also have a value as large as 0.5 to twice the value when the impedance balance condition is satisfied. That is, (C7+C8) may have a value that satisfies the following formula (7):

[0123] [Mathematical formula 7]

[0124]

[0125] That is, even if the impedance balance condition is not satisfied, the buck converter 103 can reduce common mode noise compared to a configuration that does not include the seventh capacitor 7 or the eighth capacitor 8, as long as (C7+C8) has a value that is 0.5 to twice as large as the value when the impedance balance condition is satisfied.

[0126] (2) Advantages

[0127] The buck converter 103 according to the second embodiment includes a first capacitor 1, a second capacitor 2, a first inductor 11, a second inductor 12, a third capacitor 3, a fourth inductor 14, a fifth capacitor 5, a sixth capacitor 6, a seventh capacitor 7 and an eighth capacitor 8. The seventh capacitor 7 is connected between the fifth node N5 and the first node N1. The eighth capacitor 8 is connected between the fifth node N5 and the second node N2. This enables the buck converter 103 according to the second embodiment to contribute to miniaturization while reducing common mode noise. More specifically, the buck converter 103 according to the third embodiment includes a first inductor 11, a second inductor 12, a third capacitor, a fourth inductor 14, a seventh capacitor 7 and an eighth capacitor 8, so its equivalent circuit on the MHz band will be a circuit with a Wheatstone bridge circuit configuration. This enables the buck converter 103 according to the second embodiment to reduce common mode noise without using any common mode choke coil, thereby contributing to miniaturization while reducing common mode noise.

[0128] In addition, the buck converter 103 according to the second embodiment includes the eighth capacitor 8, so that each of the seventh capacitor 7 and the eighth capacitor 8 can have a capacitance smaller than that of the seventh capacitor 7 in the buck converter 100 according to the first embodiment. This enables the buck converter 103 according to the second embodiment to reduce the capacitance component in the first current loop when the first switching element Q1 is in the on state and the capacitance component in the second current loop when the second switching element Q2 is in the on state, thereby reducing the generation of ringing due to LC resonance. The first current loop is a current loop including the first switching element Q1, the seventh capacitor 7 and the first inductor 11. The second current loop is a current loop including the second switching element Q2, the eighth capacitor 8 and the second inductor 12.

[0129] In addition, if (C7+C8) has a value satisfying the above-mentioned equation (6), the buck converter 103 according to the second embodiment can further reduce the common mode noise.

[0130] In addition, if (C7+C8) has a value that satisfies equation (7), the buck converter 103 according to the second embodiment can use capacitors having a larger tolerance in capacitance as each of the seventh capacitor 7 and the eighth capacitor 8, thereby reducing the cost of the seventh capacitor 7 and the eighth capacitor 8 and ultimately reducing the total cost of the buck converter 103.

[0131] (Third Embodiment)

[0132] Reference Fig.10 A buck converter 104 according to a third embodiment will be described. In the following description, the buck converter 104 according to the third embodiment has the same structure as the buck converter 101 according to the first modification of the first embodiment described above (refer to FIG. 1 ). Figure 6 ) will be designated by the same figure mark as the figure mark of the corresponding part, and its description will be omitted herein.

[0133] (1) Configuration

[0134] The buck converter 104 according to the third embodiment further includes a resistor 31 connected in series to the seventh capacitor 7 between the fifth node N5 and the second node N2, which is different from the buck converter 101 according to the first modification of the first embodiment. In the buck converter 104, the resistor 31 is connected between the seventh capacitor 7 and the fifth node N5.

[0135] In the buck converter 104, the impedance of the resistor 31 on the MHz band is sufficiently small compared to the impedance of the seventh capacitor 7 on the MHz band. As used herein, the expression "the impedance of the resistor 31 on the MHz band is sufficiently small compared to the impedance of the seventh capacitor 7 on the MHz band" means that for the impedance on the MHz band, the impedance of the resistor 31 is preferably equal to or less than 1 / 10 of the impedance of the seventh capacitor 7, and more preferably equal to or less than 1 / 100 of the impedance of the seventh capacitor 7. In the buck converter 104, the circuit constant of the resistor 31 is set so that the impedance of the resistor 31 on the MHz band is sufficiently small compared to the impedance of the seventh capacitor 7 on the MHz band. The resistor 31 has a characteristic that its impedance is constant regardless of the frequency. The seventh capacitor 7 has a characteristic that its impedance decreases as the frequency increases.

[0136] In the buck converter 104 according to the third embodiment, the impedance of the resistor 31 on the MHz band is sufficiently small compared to the impedance of the seventh capacitor 7 on the MHz band. Therefore, in the equivalent circuit of the buck converter 104 on the MHz band, the resistor 31 can be ignored. Therefore, the equivalent circuit of the buck converter 104 on the MHz band is the same as the equivalent circuit of the buck converter 100 on the MHz band according to the first embodiment. Therefore, the impedance balance condition according to the third embodiment is the same as the impedance balance condition according to the first embodiment, and is the same as the impedance balance condition represented by equation (2). Note that in the buck converter 104, the second switching element Q2 is implemented as a diode. Alternatively, as in the buck converter 100 according to the first embodiment, the second switching element Q2 can also be implemented as an n-channel MOSFET.

[0137] (2) Advantages

[0138] Like the step-down converter 100 according to the first embodiment, the step-down converter 104 according to the third embodiment includes the seventh capacitor 7 , thereby contributing to miniaturization while reducing common mode noise.

[0139] In addition, the buck converter 104 according to the third embodiment further includes a resistor 31 connected in series to the seventh capacitor 7 between the fifth node N5 and the second node N2. Thus, the resistor 31 is also included in the current loop including the second switching element Q2, the seventh capacitor 7 and the second inductor 12.

[0140] This configuration can not only reduce the resonance in the current loop, but also reduce the ringing when the second switching element Q2 transitions from the off state to the on state, thereby enabling further reduction of common mode noise.

[0141] (Other Modifications)

[0142] Note that the above-mentioned first to third embodiments and their variants are merely exemplary embodiments and their variants among various embodiments of the present disclosure and should not be interpreted as limiting. On the contrary, the first to third embodiments and their variants can be easily modified in various ways according to design choices or any other factors without departing from the scope of the present disclosure.

[0143] The respective switching elements in the first switching element Q1 and the second switching element Q2 in the buck converter 100 according to the first embodiment do not necessarily have to be n-channel MOSFETs, but may also be p-channel MOSFETs. In addition, in the above-mentioned first embodiment, the respective switching elements in the first switching element Q1 and the second switching element Q2 are Si-based MOSFETs. However, this is merely an example and should not be construed as restrictive. Alternatively, the respective switching elements in the first switching element Q1 and the second switching element Q2 may also be, for example, SiC-based MOSFETs. Alternatively again, the respective switching elements in the first switching element Q1 and the second switching element Q2 may also be, for example, bipolar transistors, insulated gate bipolar transistors (IGBTs) or GaN-based gate injection transistors (GITs).

[0144] Alternatively, the resistor 31 described for the third embodiment may also be provided for each of the second variation of the first embodiment, the third variation of the first embodiment, and the second embodiment.

[0145] (All aspects)

[0146] The preceding description provides specific implementations of the following aspects of the present disclosure.

[0147] A step-down converter (100; 101; 102; 103; 104) according to a first aspect includes a positive electrode input terminal (T1) and a negative electrode input terminal (T2), a positive electrode output terminal (T3) and a negative electrode output terminal (T4), a first positive side wiring section (W11), a first negative side wiring section (W12), a second positive side wiring section (W21), a second negative side wiring section (W22), a first capacitor (1), a second capacitor (2), a first inductor (11), a second inductor (12), a first switching element (Q1), a second switching element (Q2), a third inductor (13), a third capacitor (3), a fourth capacitor (4), a fourth inductor (14), a grounding conductor member (9), a fifth capacitor (5), a sixth capacitor (6), and a seventh capacitor (7). The first positive side wiring section (W11) is connected to the positive electrode input terminal (T1). The first negative side wiring section (W12) is connected to the negative electrode input terminal (T2). The second positive wiring section (W21) is connected to the positive electrode output terminal (T3). The second negative wiring section (W22) is connected to the negative electrode output terminal (T4). The first capacitor (1) is connected between the first node (N1) of the first positive wiring section (W11) and the second node (N2) of the first negative wiring section (W12). The second capacitor (2) is connected between the third node (N3) of the first positive wiring section (W11) and the fourth node (N4) of the first negative wiring section (W12). The first inductor (11) is arranged between the first node (N1) and the third node (N3). The second inductor (12) is arranged between the second node (N2) and the fourth node (N4). The first switching element (Q1) is connected to the first positive wiring section (W11). The second switching element (Q2) is connected between the first switching element (Q1) and the first negative wiring section (W12). The third inductor (13) is connected between the fifth node (N5) where the first switching element (Q1) and the second switching element (Q2) are connected together and the second positive wiring section (W21). The third capacitor (3) is connected in parallel to the third inductor (13). The fourth capacitor (4) is connected between the sixth node (N6) of the second positive wiring section (W21) and the seventh node (N7) of the second negative wiring section (W22). The fourth inductor (14) is provided between the first negative wiring section (W12) and the seventh node (N7). The fifth capacitor (5) is connected between the eighth node (N8) of the second positive wiring section (W21) and the grounding conductor member (9). The eighth node (N8) is located between the sixth node (N6) of the second positive wiring section (W21) and the positive electrode output terminal (T3). The sixth capacitor (6) is connected between the ninth node (N9) of the second negative wiring section (W22) and the grounding conductor member (9). The ninth node (N9) is located between the seventh node (N7) of the second negative-side wiring portion (W22) and the negative electrode output terminal (T4).The seventh capacitor (7) is connected between the fifth node (N5) and the first capacitor (1).

[0148] This aspect can contribute to miniaturization while reducing common mode noise.

[0149] In the buck converter (100; 101; 102; 103) according to the second aspect which can be implemented in combination with the first aspect, the seventh capacitor (7) is connected between the fifth node (N5) and the first node (N1).

[0150] This aspect can reduce the possibility of generating unnecessary parasitic inductance components between the fifth node (N5) and the seventh capacitor (7).

[0151] In a buck converter (100; 101; 102; 104) according to the third aspect which can be implemented in combination with the first aspect or the second aspect, it is satisfied that:

[0152] [Mathematical formula 8]

[0153]

[0154] Wherein, C3 is the capacitance of the third capacitor (3), L1 is the inductance of the first inductor (11), L2 is the inductance of the second inductor (12), L4 is the inductance of the fourth inductor (14), and C7 is the capacitance of the seventh capacitor (7).

[0155] This aspect enables further reduction of common mode noise.

[0156] In a buck converter (100; 101; 102; 104) according to the fourth aspect which can be implemented in combination with the first aspect or the second aspect, it is satisfied that:

[0157] [Mathematical formula 9]

[0158]

[0159] Wherein, C3 is the capacitance of the third capacitor (3), L1 is the inductance of the first inductor (11), L2 is the inductance of the second inductor (12), L4 is the inductance of the fourth inductor (14), and C7 is the capacitance of the seventh capacitor (7).

[0160] This aspect enables a capacitor having a larger tolerance in capacitance to be used as the seventh capacitor (7), thereby reducing the cost of the seventh capacitor (7) and ultimately reducing the overall cost of the buck converter (100; 101; 102; 104).

[0161] The buck converter (103) according to the fifth aspect, which can be implemented in combination with the second aspect, further includes an eighth capacitor (8) connected between the fifth node (N5) and the second node (N2).

[0162] This aspect makes it possible to reduce the capacitance component generated in the first current loop when the first switching element (Q1) is turned on and the capacitance component generated in the second current loop when the second switching element (Q2) is turned on, thereby reducing the occurrence of ringing due to LC resonance.

[0163] The buck converter (103) according to the sixth aspect, which can be implemented in combination with the fifth aspect, satisfies:

[0164] [Formula 10]

[0165]

[0166] Wherein, C3 is the capacitance of the third capacitor (3), L1 is the inductance of the first inductor (11), L2 is the inductance of the second inductor (12), L4 is the inductance of the fourth inductor (14), C7 is the capacitance of the seventh capacitor (7), and C8 is the capacitance of the eighth capacitor (8).

[0167] This aspect enables further reduction of common mode noise.

[0168] The buck converter (103) according to the seventh aspect, which can be implemented in combination with the fifth aspect, satisfies:

[0169] [Mathematical formula 11]

[0170]

[0171] Wherein, C3 is the capacitance of the third capacitor (3), L1 is the inductance of the first inductor (11), L2 is the inductance of the second inductor (12), L4 is the inductance of the fourth inductor (14), C7 is the capacitance of the seventh capacitor (7), and C8 is the capacitance of the eighth capacitor (8).

[0172] This aspect enables capacitors having a larger tolerance in capacitance to be used as each of the seventh capacitor (7) and the eighth capacitor (8), thereby reducing the cost of the seventh capacitor (7) and the eighth capacitor (8), and ultimately reducing the overall cost of the buck converter (103).

[0173] In a buck converter (100; 101; 102; 103; 104) according to the eighth aspect which can be implemented in combination with any one of the first to seventh aspects, the first inductor (11) is composed of a portion of the first positive side wiring portion (W11), the second inductor (12) is composed of a portion of the first negative side wiring portion (W12), and the fourth inductor (14) is composed of a portion of the second negative side wiring portion (W22).

[0174] This aspect enables the number of required components to be reduced, thereby contributing to miniaturization and cost reduction.

[0175] In the buck converter (100; 101; 102; 103; 104) according to the ninth aspect which can be implemented in combination with any one of the first to eighth aspects, the third inductor (13) is a choke coil, and the third capacitor (3) is an inter-winding capacitance of the choke coil.

[0176] This aspect enables the number of required components to be reduced, thereby contributing to miniaturization and cost reduction.

[0177] The buck converter (100; 101; 102; 103; 104) according to the tenth aspect, which can be implemented in combination with any one of the first to ninth aspects, also includes a resistor (31) which is connected in series to the seventh capacitor (7) between the fifth node (N5) and the second node (N2).

[0178] This aspect enables further reduction of common mode noise.

[0179] Description of Reference Numerals

[0180] 1First capacitor

[0181] 2 Second capacitor

[0182] 3Third capacitor

[0183] 4Fourth capacitor

[0184] 5Fifth capacitor

[0185] 6 Sixth capacitor

[0186] 7Seventh capacitor

[0187] 8 Eighth capacitor

[0188] 9 Grounding conductor member

[0189] 10 Controller

[0190] 11First Inductor

[0191] 12 Second Inductor

[0192] 13Third Inductor

[0193] 14 Fourth Inductor

[0194] 31 Resistors

[0195] 100,101,102,103,104 Buck Converter

[0196] Q1 first switching element

[0197] Q2 Second switching element

[0198] T1 positive electrode input terminal

[0199] T2 negative electrode input terminal

[0200] T3 positive electrode output terminal

[0201] T4 negative electrode output terminal

[0202] W11 First positive wiring section

[0203] W12 First negative side wiring section

[0204] W21 Second positive wiring section

[0205] W22 Second negative side wiring section

Claims

1. A buck converter, comprising: a positive electrode input terminal and a negative electrode input terminal; A positive electrode output terminal and a negative electrode output terminal; a first positive-side wiring section connected to the positive electrode input terminal; a first negative-side wiring section connected to the negative electrode input terminal; a second positive-side wiring section connected to the positive electrode output terminal; a second negative-side wiring section connected to the negative electrode output terminal; a first capacitor connected between a first node of the first positive-side wiring section and a second node of the first negative-side wiring section; a second capacitor connected between a third node of the first positive wiring section and a fourth node of the first negative wiring section; a first inductor disposed between the first node and the third node; a second inductor disposed between the second node and the fourth node; a first switching element connected to the first positive-side wiring section; a second switching element connected between the first switching element and the first negative-side wiring section; a third inductor connected between a fifth node at which the first switching element and the second switching element are connected together and the second positive-side wiring portion; a third capacitor connected in parallel to the third inductor; a fourth capacitor connected between a sixth node of the second positive wiring section and a seventh node of the second negative wiring section; a fourth inductor provided between the first negative side wiring portion and the seventh node, Grounding conductor member; a fifth capacitor connected between an eighth node of the second positive-side wiring portion and the grounded conductor member, the eighth node being located between a sixth node of the second positive-side wiring portion and the positive electrode output terminal; a sixth capacitor connected between a ninth node of the second negative-side wiring portion and the grounding conductor member, the ninth node being located between a seventh node of the second negative-side wiring portion and the negative electrode output terminal; as well as A seventh capacitor is connected between the fifth node and the first capacitor.

2. The buck converter according to claim 1, wherein: The seventh capacitor is connected between the fifth node and the first node.

3. The buck converter according to claim 1 or 2, wherein: The buck converter satisfies: [Mathematical formula 1] Wherein, C3 is the capacitance of the third capacitor, L1 is the inductance of the first inductor, L2 is the inductance of the second inductor, L4 is the inductance of the fourth inductor, and C7 is the capacitance of the seventh capacitor.

4. The buck converter according to claim 1 or 2, wherein: The buck converter satisfies: [Mathematical formula 2] Wherein, C3 is the capacitance of the third capacitor, L1 is the inductance of the first inductor, L2 is the inductance of the second inductor, L4 is the inductance of the fourth inductor, and C7 is the capacitance of the seventh capacitor. 5 . The buck converter of claim 2 , further comprising an eighth capacitor connected between the fifth node and the second node.

6. The buck converter according to claim 5, wherein: The buck converter satisfies: [Mathematical formula 3] Wherein, C3 is the capacitance of the third capacitor, L1 is the inductance of the first inductor, L2 is the inductance of the second inductor, L4 is the inductance of the fourth inductor, C7 is the capacitance of the seventh capacitor, and C8 is the capacitance of the eighth capacitor.

7. The buck converter according to claim 5, wherein: The buck converter satisfies: [Formula 4] Wherein, C3 is the capacitance of the third capacitor, L1 is the inductance of the first inductor, L2 is the inductance of the second inductor, L4 is the inductance of the fourth inductor, C7 is the capacitance of the seventh capacitor, and C8 is the capacitance of the eighth capacitor.

8. The buck converter according to any one of claims 1 to 7, wherein: The first inductor is formed by a part of the first positive wiring portion. The second inductor is constituted by a part of the first negative side wiring portion, and The fourth inductor is formed by a part of the second negative-side wiring portion.

9. The buck converter according to any one of claims 1 to 8, wherein: The third inductor is a choke coil, and The third capacitor is an inter-winding capacitance of the choke coil.

10. The buck converter according to any one of claims 1 to 9, further comprising a resistor connected in series to the seventh capacitor between the fifth node and the second node.

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