Semiconductor device

Abstract

The purpose of the present invention is to suppress damage to an element due to the fact that carriers flow into an IGBT region from a diode region and are concentrated at a boundary portion during recovery of a diode. In a semiconductor device having an IGBT region (4), a diode region (5), and a wiring region (6) in the same chip, the wiring region (6) has a gate flow path (7) that supplies a gate potential to a trench gate electrode (20), a well layer (28) that has a deeper diffusion depth of impurities than a trench (19), and a plurality of first contact regions (33) that electrically connect the well layer (28) and an emitter electrode (21). The area of the first contact region (33) near a boundary portion (10) near a boundary portion (9) between the IGBT region (4) and the diode region (5) is larger than the area of the first contact region (33) at a position farther from the boundary portion (10).

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] RC-IGBT (RC: Reverse-Conducting, reverse-conducting IGBT) with IGBT (Insulated Gate Bipolar Transistor) and diode built in the same chip can share the terminal area of ​​the diode with the IGBT, so it has the advantage of reducing the chip size. In addition, since the timing of the operation of the IGBT and the diode is different, the heat caused by the loss in one of the IGBT area and the diode area is dispersed to the other, and the heat can be dissipated throughout the chip, which also has the advantage of reducing thermal resistance.

[0003] On the other hand, in RC-IGBT, when the IGBT is turned on and the diode changes from conduction to non-conduction, that is, when the diode recovers, carriers (holes) easily flow from the diode area to the IGBT area, so there is a problem that carriers (holes) are concentrated at the boundary between the diode area and the IGBT area, causing the device to be destroyed.

[0004] As a semiconductor device for reducing the destruction of such elements, for example, Patent Document 1 discloses the following technology: In order to prevent the destruction caused by the recovery current concentrated near the triple point where the IGBT, the diode, and the gate flow channel intersect, as disclosed in Patent Document 1, Figure 2 , Figure 5 , Figure 6 As in the case of providing a separation groove at the boundary portion, or as in Patent Document 1 Figure 7 In this way, the contact region for hole extraction in the region near the boundary with the diode region is eliminated.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2009-94158 Summary of the invention

[0008] Problems to be solved by the invention

[0009] However, in the method of providing the separation groove of Patent Document 1, when a well layer deeper than the groove is provided, there is a problem that holes may flow into the boundary portion through the well layer and may concentrate holes. In addition, in order to solve this problem, if the separation groove is formed deeper than the well layer, there is a problem that the groove of the IGBT region becomes too deep, or the depth of the groove of the IGBT region and the depth of the separation groove need to be changed.

[0010] In addition, it can be inferred that the method of eliminating the contact region for hole extraction at the boundary with the diode region in Patent Document 1 is based on the idea of ​​eliminating the contact region for hole extraction so that holes do not accumulate or are difficult to accumulate. However, there is a problem that even if the contact region for hole extraction is eliminated, the possibility of hole accumulation cannot be eliminated.

[0011] The problem to be solved by the present invention is to provide a semiconductor device, in which, even if the wiring region has a well layer deeper than the trench, carriers are prevented from flowing from the diode region to the IGBT region during the recovery of the diode and carriers are concentrated at the boundary portion, causing the element to be destroyed.

[0012] Solutions to Solve Problems

[0013] In order to solve the above-mentioned problems, the semiconductor device of the present invention is characterized in that, for example, in a semiconductor device having a GBT region, a diode region and a wiring region in the same chip, the IGBT in the IGBT region has an emitter electrode arranged on the surface side, a collector electrode arranged on the back side, and a trench gate electrode arranged inside the trench, the diode in the diode region has a surface electrode connected to the emitter electrode, and a back electrode connected to the collector electrode, the wiring region has a gate flow channel for supplying a gate potential to the trench gate electrode, a well layer having an impurity diffusion depth deeper than the trench, and a plurality of first contact regions electrically connecting the well layer to the emitter electrode, and the area of ​​the first contact region near the boundary portion close to the boundary portion between the IGBT region and the diode region is larger than the area of ​​the first contact region at a position away from the boundary portion.

[0014] Effects of the Invention

[0015] According to the present invention, since the area of ​​the contact region near the boundary portion is larger, the effect of extracting carriers becomes larger. Therefore, in a semiconductor device having an IGBT region, a diode region, and a wiring region in the same chip, even if the wiring region has a well layer deeper than the trench, it is possible to suppress the flow of carriers from the diode region to the IGBT region during the recovery of the diode and the concentration of carriers at the boundary portion, thereby preventing the element from being destroyed. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a top view of the semiconductor device of the embodiment.

[0017] Figure 2 is a top view of the semiconductor device of Example 1, Figure 1 Enlarged view of part E.

[0018] Figure 3 yes Figure 2 A-A' section view.

[0019] Figure 4 yes Figure 2 BB' section view.

[0020] Figure 5 yes Figure 2 C-C' section view.

[0021] Figure 6 yes Figure 2 D-D' section view.

[0022] Figure 7 is a top view of the semiconductor device of Example 2, Figure 1 Enlarged view of part E. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present invention will be described using the accompanying drawings. In each of the drawings and embodiments, the same or similar components are denoted by the same reference numerals and repeated descriptions are omitted.

[0024] Example 1

[0025] Figure 1 is a top view of the semiconductor device of the embodiment. Figure 1 This is a diagram common to both Embodiment 1 and Embodiment 2.

[0026] The semiconductor device 1 of the embodiment has an IGBT region 4 and a diode region 5 in the same chip. The semiconductor device 1 has an active region 2 in which the IGBT region 4 and the diode region 5 are alternately formed; a terminal region 3 surrounding the active region 2; a gate channel 7 as a gate wiring for supplying a gate potential; and a gate pad 8 connected to the outside and supplying a gate potential to the gate channel 7. In addition, the semiconductor device 1 has an emitter electrode 21 of the IGBT and a surface electrode 38 of the diode on the surface side in the active region 2, but Figure 1 Illustration omitted.

[0027] Figure 2 is a top view of the semiconductor device of Example 1, Figure 1 Enlarged view of part E. Figure 3 yes Figure 2 A-A' section view, Figure 4 yes Figure 2 The BB' section view, Figure 5 yes Figure 2 The C-C' section view, Figure 6 yes Figure 2 In addition, Figure 2The emitter electrode 21 and the surface electrode 38 are also omitted in the figure.

[0028] like Figure 2 as well as Figure 3 As shown, the IGBT of the IGBT region 4 has an emitter electrode 21 provided on the surface side, a collector electrode 22 provided on the back side, and a trench gate electrode 20 provided inside the trench 19. The emitter electrode 21 and the collector electrode 22 are formed of, for example, metal, and the trench gate electrode 20 is formed of, for example, polysilicon.

[0029] In addition, the IGBT of the IGBT region 4 has: Figure 3 The drift layer 11 is formed of a semiconductor of the second conductivity type (in the example of n-type) provided on the surface side of the drift layer 11; Figure 3 The main body layer 12 is formed of a semiconductor of the first conductivity type (in which the example of p-type is shown in FIG. 1 ); the emitter layer 13 is provided on the surface side of the main body layer 12 and is formed of a semiconductor of the first conductivity type; the interlayer insulating film 24 is provided between the emitter layer 13 and the trench gate electrode 20 and the emitter electrode 21; the buffer layer 15 is provided on the back side of the drift layer 11 and is formed of a semiconductor of the first conductivity type; and the collector layer 16 is provided between the buffer layer 15 and the collector electrode 22 and is formed of a semiconductor of the second conductivity type. The emitter electrode 21 is connected to the emitter layer 13 in the fourth contact region 36, and is connected to the main body layer 12 via the fourth contact region 36 and the contact layer 14 formed of a semiconductor of the second conductivity type.

[0030] The trench 19 has a depth that penetrates the body layer 12 and reaches the drift layer 11. Inside the trench 19, a gate insulating film 23 is provided so as to surround the trench gate electrode 20.

[0031] The diode in the diode region 5 has a front electrode 38 connected to the emitter electrode 21 and a back electrode 39 connected to the collector electrode 22 . The front electrode 38 is formed integrally with the emitter electrode 21 , and the back electrode 39 is formed integrally with the collector electrode 22 .

[0032] In addition, the diode of the diode region 5 includes: a drift layer 11; a surface-side semiconductor layer 17 provided on the surface side of the drift layer 11 and formed of a semiconductor of the second conductivity type; an interlayer insulating film 24; a buffer layer 15; and a back-side semiconductor layer 18 provided between the buffer layer 15 and the back electrode 39 and formed of a semiconductor of the first conductivity type. In addition, in the diode region 5, a structure without the buffer layer 15 may be adopted. The surface electrode 38 is connected to the surface-side semiconductor layer 17 via the fifth contact region 37 and the contact layer 14.

[0033] A trench electrode 25 formed of, for example, polysilicon and an in-trench insulating film 26 formed so as to surround the trench electrode 25 are provided inside the trench 19 of the diode region 5 .

[0034] like Figure 2 , Figure 4 , Figure 5 As shown, the wiring region 6 has: a gate flow channel 7 for supplying a gate potential to the trench gate electrode 20; a well layer 28 having a diffusion depth of impurities deeper than the trench 19; and a plurality of first contact regions 33 for electrically connecting the well layer 28 to the emitter electrode 21. The first contact regions 33 provided on the IGBT region 4 side of the wiring region 6 enable carriers (holes) to be derived. In addition, the well layer 28 is formed of a semiconductor of the second conductivity type, and becomes shallower midway and contacts the main layer 12 and the surface-side semiconductor layer 17 (see Figure 6 ) is connected. In addition, the first contact region 33 is connected to the well layer 28 via the contact layer 14. An insulating film 27 is formed on the surface of the well layer 28 and is connected to the gate insulating film 23 and the in-trench insulating film 26.

[0035] In addition, the wiring region 6 has a first lead wiring 29, which is connected to the gate runner 7 and the trench gate electrode 20 and leads the wiring from the trench gate electrode 20 to the outside of the trench 19. The first lead wiring 29 is formed of, for example, polysilicon. The first lead wiring 29 is also formed at a position overlapping with the gate runner 7, and is connected to the gate runner 7 via a contact hole (not shown) formed in the interlayer insulating film 24. The first lead wiring 29 has a first opening 31 larger than the first contact region 33 at a position corresponding to the first contact region 33. As a result, the emitter electrode 21 can avoid the first lead wiring 29 and be connected to the well layer 28 through the first contact region 33.

[0036] like Figure 2 as well as Figure 6 As shown, the wiring region 6 has a plurality of second contact regions 34, which electrically connect the well layer 28 to the surface electrode 38. Carriers (holes) can be extracted by the second contact region 34 provided on the diode region 5 side of the wiring region 6. In addition, the second contact region 34 is connected to the well layer 28 via the contact layer 14.

[0037] In addition, the wiring region 6 has a second lead-out wiring 30, which is connected to the trench electrode 25 and leads the wiring from the trench electrode 25 to the outside of the trench 19. The second lead-out wiring 30 is formed of, for example, polysilicon. The second lead-out wiring 30 has a second opening 32 larger than the second contact region 34 at a position corresponding to the second contact region 34. Thus, the surface electrode 38 can avoid the second lead-out wiring 30 and be connected to the well layer 28 through the second contact region 34.

[0038] The wiring region 6 has a third contact region 35, and the third contact region 35 electrically connects the second lead wiring 30 and the surface electrode 38 at a position different from the second contact region 34. Thus, the first contact region 33, the second contact region 34, and the third contact region 35 can be formed together, and the trench gate electrode 20 can be connected to the gate runner 7 via the first lead wiring 29, and the trench electrode 25 can be connected to the emitter electrode 21 via the second lead wiring 30 and the surface electrode 38.

[0039] like Figure 2 As shown, in the semiconductor device 1 of the first embodiment, the area of ​​the first contact region 33 near the boundary 10 near the boundary 9 between the IGBT region 4 and the diode region 5 is larger than the area of ​​the first contact region 33 at a position away from the boundary 10. As a result, the effect of extracting carriers (holes) becomes greater near the boundary 10 where carriers (holes) from the diode region 5 are likely to concentrate.

[0040] In addition, since the area of ​​the first contact region 33 near the boundary portion 10 is only increased instead of the entire area of ​​the first contact region 33, the first opening portion 31 of the first lead wiring 29 does not need to be enlarged at a position away from the boundary portion 10, thereby reducing the increase in gate resistance associated with the increase in the area of ​​the first contact region 33.

[0041] And, if Figure 2 As shown, in the semiconductor device 1 of the first embodiment, the area of ​​the second contact region 34 near the boundary portion 10 is also larger than the area of ​​the second contact region 34 at a position away from the boundary portion 10. As a result, the effect of extracting carriers (holes) near the boundary portion 10 is increased even on the diode region 5 side.

[0042] In addition, in Example 1, the case where the first conductivity type is n-type and the second conductivity type is p-type is described as an example. In this case, the surface electrode 38 is an anode electrode, the back electrode 39 is a cathode electrode, the surface side semiconductor layer 17 is an anode layer, and the back side semiconductor layer 18 is a cathode layer. In addition, the carrier is a hole. It is not limited to the first conductivity type being p-type and the second conductivity type being n-type. In this case, the anode is opposite to the cathode, and the carrier is an electron instead of a hole.

[0043] In addition, the impurity concentration is illustrated as an example with the drift layer 11 being a low-concentration n- type, the emitter layer 13 being a high-concentration n+ type, the contact layer 14 being a high-concentration p+ type, and the back side semiconductor layer 18 being a high-concentration n+ type, but it is not limited to this and can be appropriately changed within the range of operation.

[0044] As described above, according to the semiconductor device 1 of the first embodiment, since the area of ​​the contact region near the boundary portion is large, the effect of extracting carriers becomes larger. Therefore, in a semiconductor device having an IGBT region, a diode region, and a wiring region in the same chip, even when the wiring region has a well layer deeper than the trench, it is possible to suppress the flow of carriers from the diode region to the IGBT region during diode recovery and the concentration of carriers at the boundary portion to cause element destruction.

[0045] Example 2

[0046] Figure 7 is a top view of the semiconductor device of Example 2, Figure 1 Enlarged view of part E.

[0047] The second embodiment is a modified example of the first embodiment, and the areas of the first contact region 33 and the second contact region 34 are different from those of the first embodiment.

[0048] like Figure 7 As shown, in the semiconductor device 1 of the second embodiment, the area of ​​the first contact region 33 near the boundary 10 gradually increases toward the boundary 9. Similarly, the area of ​​the second contact region 34 near the boundary 10 gradually increases toward the boundary 9.

[0049] According to the second embodiment, the increase in gate resistance compared with the first embodiment is reduced, and the effect of extracting carriers can be increased. The other structures and effects are the same as those of the first embodiment.

[0050] Although the embodiments of the present invention have been described above, the present invention is not limited to the structures described in the embodiments, and various changes can be made within the scope of the technical concept of the present invention. In addition, part or all of the structures described in the embodiments can also be combined and applied.

[0051] Explanation of symbols

[0052] 1—semiconductor device, 2—active region, 3—terminal region, 4—IGBT region, 5—diode region, 6—wiring region, 7—gate flow channel, 8—gate pad, 9—boundary portion, 10—near boundary portion, 11—drift layer, 12—body layer, 13—emitter layer, 14—contact layer, 15—buffer layer, 16—collector layer, 17—surface semiconductor layer, 18—back semiconductor layer, 19—trench, 20—trench gate electrode, 21—emitter electrode Pole, 22—collector electrode, 23—gate insulating film, 24—interlayer insulating film, 25—trench electrode, 26—in-trench insulating film, 27—insulating film, 28—well layer, 29—first lead wiring, 30—second lead wiring, 31—first opening, 32—second opening, 33—first contact region, 34—second contact region, 35—third contact region, 36—fourth contact region, 37—fifth contact region, 38—surface electrode, 39—back electrode.

Claims

1. A semiconductor device comprising an IGBT region, a diode region and a wiring region in the same chip, It is characterized in that The IGBT in the IGBT region has an emitter electrode provided on the front side, a collector electrode provided on the back side, and a trench gate electrode provided inside the trench. The diode in the diode region has a surface electrode connected to the emitter electrode and a back electrode connected to the collector electrode. The wiring region includes a gate flow channel for supplying a gate potential to the trench gate electrode, a well layer having an impurity diffusion depth deeper than the trench, and a plurality of first contact regions for electrically connecting the well layer to the emitter electrode. An area of ​​the first contact region near a boundary portion between the IGBT region and the diode region is larger than an area of ​​the first contact region at a position far from the boundary portion.

2. The semiconductor device according to claim 1, It is characterized in that The area of ​​the first contact region near the boundary portion gradually increases toward the boundary portion.

3. The semiconductor device according to claim 1, It is characterized in that The wiring region has a first lead wiring connected to the gate channel and the trench gate electrode and leading the wiring from the trench gate electrode to the outside of the trench. The first lead wiring has a first opening that is larger than the first contact region at a position corresponding to the first contact region.

4. The semiconductor device according to claim 1, It is characterized in that The wiring region has a plurality of second contact regions, and the plurality of second contact regions electrically connect the well layer and the surface electrode. An area of ​​the second contact region near the boundary portion is larger than an area of ​​the second contact region at a position away from the boundary portion.

5. The semiconductor device according to claim 4, It is characterized in that The area of ​​the second contact region near the boundary portion gradually increases toward the boundary portion.

6. The semiconductor device according to claim 4, It is characterized in that The diode region has a trench electrode disposed inside the trench. The wiring region includes a second lead wiring connected to the trench electrode and leading the wiring from the trench electrode to the outside of the trench, and a third contact region electrically connecting the second lead wiring to the surface electrode at a position different from the second contact region. The second lead wiring has a second opening that is larger than the second contact region at a position corresponding to the second contact region.

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