Semiconductor device

Abstract

A semiconductor substrate (11) is provided with an FS layer (13) between a collector layer (12) and a drift layer (14). The total dose of the collector layer (12) is less than 1 * 1013 / cm2. The collector layer (12) has a plurality of carrier concentration peaks. At least a part of the collector layer (12) is configured such that the dose contained in + / -3 [sigma] p accounts for 13% or more of the total dose with respect to the deepest peak value, which is the peak value at the deepest position with respect to the back surface (11b) of the semiconductor substrate (11).

Description

[0001] Cross-reference to related applications

[0002] This application is based on patent application No. 2022-172331 filed in Japan on October 27, 2022, and the contents of the basic application are cited in their entirety by reference. Technical Field

[0003] The disclosure in this specification relates to a semiconductor device. Background Art

[0004] Patent Document 1 discloses a semiconductor device in which an IGBT is formed as a vertical element. The contents of the prior art document are incorporated by reference as explanations of technical elements in this specification.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2020-43301 Summary of the invention

[0008] In Patent Document 1, in order to improve the withstand voltage, an n+ type field stop layer is arranged between an n- type drift layer and a p+ type collector layer. Furthermore, in order to improve the short circuit withstand capacity, the distance between the field stop layer and the maximum peak value of the carrier concentration in the collector layer, and the ratio of the total dose amount of the collector layer to the total dose amount of the field stop layer are set to satisfy a prescribed relationship.

[0009] However, in applications requiring low turn-off losses, the total dose of the collector layer must be reduced, and sometimes the ratio of the distance to the total dose does not satisfy the prescribed relationship. In other words, short-circuit tolerance may not be ensured. In the above viewpoints or other viewpoints not mentioned, further improvements are required for semiconductor devices.

[0010] An object of the present invention is to provide a semiconductor device capable of improving short-circuit withstand capability and reducing turn-off loss.

[0011] The semiconductor device disclosed herein comprises: a drift layer of the first conductivity type; a base layer of the second conductivity type, arranged on the drift layer and provided on one side of a semiconductor substrate; an emitter region of the first conductivity type, formed on a surface layer on one side of the base layer; a gate electrode, disposed opposite to the base layer between the drift layer and the emitter region via a gate insulating film; a collector layer of the second conductivity type, arranged on the side opposite to the base layer with respect to the drift layer and provided on the back side of the semiconductor substrate; a field stop layer of the first conductivity type, arranged between the collector layer and the drift layer, and having a higher carrier concentration than the drift layer; an emitter electrode, arranged on one side and electrically connected to the base layer and the emitter region; and a collector electrode, arranged on the back side and electrically connected to the collector layer; the total dose of the collector layer is less than 1×10 13 / cm 2 The collector layer has multiple carrier concentration peaks, and at least a portion of the collector layer is constructed to satisfy the following conditions, namely: the dose contained in ±3σp relative to the deepest peak accounts for more than 13% of the total dose, and the deepest peak is the peak at the deepest position relative to the back side.

[0012] According to the disclosed semiconductor device, the total dose of the collector layer is less than 1×10 13 / cm 2 , so the turn-off loss can be reduced. In addition, at least a portion of the collector layer is set so that the dose included in ±3σp relative to the deepest peak among the multiple peaks accounts for more than 13% of the total dose. As a result, the short-circuit tolerance can be improved. As a result, a semiconductor device that can improve the short-circuit tolerance and reduce the turn-off loss can be provided.

[0013] The multiple embodiments disclosed in this specification adopt different technical means to achieve their respective purposes. The reference numerals in parentheses in the claims are illustrative of the correspondence with the parts of the embodiments described later, and are not intended to limit the technical scope. The purposes, features and effects disclosed in this specification will become clearer by referring to the subsequent detailed description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a diagram showing a semiconductor device according to the first embodiment.

[0015] Figure 2 It is along Figure 1 Cross-sectional view along line II-II.

[0016] Figure 3 This is a timing chart showing the operation of the semiconductor device.

[0017] Figure 4 It is a diagram showing the electric field strength of a semiconductor device.

[0018] Figure 5 This is a diagram for explaining the peak value of the electric field intensity during a short circuit.

[0019] Figure 6 It is a graph showing the peak value of the carrier concentration in the collector layer.

[0020] Figure 7 A graph showing the relationship between the dose of the deepest peak and the improvement rate of short-circuit withstand capability.

[0021] Figure 8 This is a graph showing the relationship between the on-state voltage and the turn-off loss.

[0022] Fig. 9 It is a diagram showing a semiconductor device according to a second embodiment.

[0023] Fig.10 It is a diagram showing the first element region.

[0024] Fig.11 It is a diagram showing the second element region.

[0025] Fig.12 It is a figure which shows a modification example.

[0026] Fig.13 It is a figure which shows a modification example.

[0027] Fig.14 It is a figure which shows a modification example. DETAILED DESCRIPTION

[0028] Hereinafter, a plurality of embodiments are described based on the accompanying drawings. In addition, in each embodiment, repeated descriptions are sometimes omitted by marking the corresponding constituent elements with the same reference numerals. In the case where only a part of the structure is described in each embodiment, the structure of other embodiments previously described can be applied to the other parts of the structure. In addition, not only the combination of structures explicitly stated in the description of each embodiment, but also the structures of multiple embodiments can be partially combined with each other even if not explicitly stated, as long as the combination does not particularly cause obstacles.

[0029] The semiconductor device of this embodiment is applied to, for example, a power conversion device of a mobile body using a rotating electric machine as a driving source. The mobile body is, for example, an electric vehicle such as a battery electric vehicle (BEV), a hybrid electric vehicle (HEV), a plug-in hybrid electric vehicle (PHEV), an electric vertical take-off and landing machine, an aerial vehicle such as an unmanned aerial vehicle, a ship, a construction machine, and an agricultural machine.

[0030] (First Embodiment)

[0031] First, based on Figure 1 and Figure 2 , the schematic structure of the semiconductor device is described. Figure 1is a top plan view of a semiconductor device. Figure 2 It is along Figure 1 As an example, the semiconductor device of this embodiment is applied to a DC-DC converter.

[0032] <Semiconductor Device>

[0033] Hereinafter, the plate thickness direction of the semiconductor substrate is referred to as the Z direction. A direction orthogonal to the Z direction is referred to as the X direction. A direction orthogonal to both the Z direction and the X direction is referred to as the Y direction. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X direction and the Y direction, is referred to as the planar shape. In addition, sometimes, the planar observation from the Z direction is simply referred to as the planar observation.

[0034] like Figure 1 and Figure 2 As shown, the semiconductor device 10 includes a semiconductor substrate 11. The semiconductor substrate 11 is made of silicon (Si) or a wide-bandgap semiconductor having a bandgap wider than that of silicon. Examples of wide-bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (Ga 2 O 3 ), diamond, etc.

[0035] A vertical element is formed on the semiconductor substrate 11. The vertical element is configured so that the main current flows in the thickness direction of the semiconductor substrate 11, that is, in the Z direction. The vertical element is an IGBT. IGBT is the abbreviation of Insulated Gate Bipolar Transistor. The semiconductor substrate 11 has a surface 11a and a back surface 11b as the plate surface for setting electrodes.

[0036] The semiconductor substrate 11 includes a collector layer 12, a field stop layer 13 (hereinafter, FS layer 13), a drift layer 14, a base layer 15, an emitter region 16, and a base contact region 17. The semiconductor substrate 11 is obtained by forming each semiconductor region by ion implantation of impurities, etc. The semiconductor region of the semiconductor substrate 11 is sometimes referred to as a semiconductor layer, a diffusion layer, etc.

[0037] The collector layer 12 is arranged on the side opposite to the base layer 15 with respect to the drift layer 14. The collector layer 12 is formed on the surface layer on the back surface 11b side of the semiconductor substrate 11. The collector layer 12 provides the back surface 11b of the semiconductor substrate 11. The collector layer 12 is a p-conductivity type (p+) semiconductor region having a higher impurity concentration than the base layer 15.

[0038] The FS layer 13 is arranged between the collector layer 12 and the drift layer 14. The FS layer 13 is formed on the surface of the collector layer 12 opposite to the back surface 11b. The FS layer 13 is an n-conductivity type (n+) semiconductor region having a higher carrier concentration (impurity concentration) than the drift layer 14. By providing the FS layer 13, the extension of the depletion layer to the collector layer 12 side can be suppressed. The FS layer 13 is sometimes also called a buffer layer.

[0039] The drift layer 14 is disposed between the FS layer 13 and the base layer 15. The drift layer 14 is formed on the surface of the FS layer 13 opposite to the surface on the collector layer 12 side. The drift layer 14 is an n-conductivity type (n-) semiconductor region having a lower impurity concentration than the FS layer 13.

[0040] The base layer 15 is arranged on the surface of the drift layer 14 opposite to the surface on the FS layer 13 side. The base layer 15 is formed on the surface layer on the side of the one surface 11a of the semiconductor substrate 11. The base layer 15 provides the one surface 11a of the semiconductor substrate 11. The base layer 15 is a p-conductivity type (p) semiconductor region having a lower impurity concentration than the collector layer 12. The base layer 15 is sometimes referred to as a channel region, a body region, etc.

[0041] The emitter region 16 is provided in the surface layer on the side of one surface 11a in the base layer 15. The emitter region 16 terminates in the base layer 15. The emitter region 16 is an n-conductivity type (n+) semiconductor region having a higher carrier concentration than the drift layer 14. The emitter region 16 is formed so as to be in contact with the side surface of the trench 18 described later. The emitter region 16 extends along the extending direction of the trench 18.

[0042] The base contact region 17 is provided in the surface layer on the side of the one surface 11a in the base layer 15, similarly to the emitter region 16. The base contact region 17 terminates in the base layer 15. The base contact region 17 is a p-conductivity type (p+) semiconductor region having a higher impurity concentration than the base layer 15. The base contact region 17 is provided adjacent to the emitter region 16. The base contact region 17 also extends along the extension direction of the trench 18. As an example, the base contact region 17 of the present embodiment is formed to a position deeper than the emitter region 16. The base contact region 17 is sometimes referred to as a body contact region, a contact region, etc.

[0043] A plurality of grooves 18 are formed in the semiconductor substrate 11 of the above structure. The grooves 18 are formed to have a predetermined depth from one side 11a. The grooves 18 penetrate the base layer 15. The front end of the grooves 18 reaches the drift layer 14. As an example, the plurality of grooves 18 of the present embodiment extend in the X direction respectively. The plurality of grooves 18 are arranged at approximately equal intervals in the Y direction and are strip-shaped when viewed in a plane. The grooves 18 define a cell. A cell is sometimes referred to as a main cell, a unit structural unit, a unit circuit, an element, etc. A plurality of cells are connected in parallel to each other to form an IGBT of a trench gate structure.

[0044] A gate insulating film 19 is formed on the wall surface of the trench 18. The gate insulating film 19 is composed of an oxide film or the like, and is formed so as to cover the wall surface of the trench 18. In addition, a gate electrode 20 is formed on the surface of the gate insulating film 19 so as to fill the trench 18. The gate electrode 20 is composed of doped polysilicon or the like. The trench 18 is filled with the gate insulating film 19 and the gate electrode 20.

[0045] The gate electrode 20 penetrates the base layer 15 and reaches the drift layer 14. A plurality of gate electrodes 20 are formed on the semiconductor substrate 11. The plurality of gate electrodes 20 extend in the X direction. The plurality of gate electrodes 20 are arranged at substantially equal intervals in the Y direction and have a stripe shape when viewed in a plan view.

[0046] An emitter electrode 21 is disposed on one surface 11a of the semiconductor substrate 11. The emitter electrode 21 is electrically connected to the emitter region 16. The emitter electrode 21 is electrically connected to the base layer 15 via the base contact region 17. The emitter electrode 21 is electrically separated from the gate electrode 20 by an interlayer insulating film 22 such as BPSG. BPSG is an abbreviation for boro phospho silicate glass.

[0047] On one side 11a of the semiconductor substrate 11, a pad 23 serving as a signal electrode is also provided. The pad 23 is formed at a position that does not overlap with the emitter electrode 21 when viewed in a plan view, specifically, is formed on a peripheral region surrounding the element formation region. The pad 23 includes at least a pad for the gate electrode 20. As an example, in this embodiment, five pads 23 are formed on the semiconductor substrate 11. The five pads 23 are concentrated on one end side in the Y direction in the semiconductor substrate 11 having a substantially rectangular shape in a plan view, and are arranged in the X direction.

[0048] A protective film 24 is disposed on one side 11a of the semiconductor substrate 11. The protective film 24 is an insulating film provided on the one side 11a of the semiconductor substrate 11 so as to cover the peripheral portion of the emitter electrode 21. The protective film 24 is composed of, for example, polyimide, silicon nitride film, etc. The protective film 24 has an opening 241 that defines a bonding region of the emitter electrode 21 and an opening 242 that defines a bonding region of the pad 23.

[0049] A collector electrode 25 is disposed on the back surface 11 b of the semiconductor substrate 11 . The collector electrode 25 is formed on substantially the entire area of ​​the back surface 11 b . The collector electrode 25 is electrically connected to the collector layer 12 .

[0050] In the semiconductor device 10 configured as described above, the n-conductivity type corresponds to the first conductivity type, and the p-conductivity type corresponds to the second conductivity type.

[0051] <Operation of Semiconductor Device>

[0052] Next, based on Figure 3 , the operation of the semiconductor device 10 (IGBT) is described. Figure 3 It is a diagram showing the operation of the semiconductor device 10 .

[0053] When a higher voltage than the emitter electrode 21 is applied to the collector electrode 25, the pn junction formed between the base layer 15 and the drift layer 14 becomes reverse conductive and forms a depletion layer. In order to turn on the IGBT, a voltage higher than the threshold voltage Vth of the insulating gate structure is applied to the gate electrode 20 while a higher voltage than the emitter electrode 21 is applied to the collector electrode 25. Figure 3 In the process, at time t1, a voltage equal to or higher than the threshold voltage Vth is applied to the gate electrode 20.

[0054] As a result, the gate-emitter voltage Vge rises, and an inversion layer, that is, a channel, is formed in the base layer 15 at a portion in contact with the trench 18. Then, electrons are supplied from the emitter region 16 to the drift layer 14 via the inversion layer, and electrons are supplied from the collector layer 12 to the drift layer 14, and the resistance value of the drift layer 14 decreases due to conductivity modulation, and the IGBT becomes conductive. That is, the collector-emitter voltage Vce decreases, and the current Ic flows.

[0055] Furthermore, if the voltage application to the gate electrode 20 is stopped at time t2, the gate-emitter voltage Vge decreases, the inversion layer disappears, and the IGBT becomes cut-off. That is, the current Ic decreases, and the IGBT becomes cut-off. However, if a short circuit occurs, Figure 3 As shown by the middle dotted line, the current Ic increases sharply and the collector-emitter voltage Vce decreases sharply.

[0056] <Electric field strength during short circuit>

[0057] Next, based on Figure 4 and Figure 5 , the electric field strength during short circuit is explained. Figure 4 The simulation results of the reference example are shown. Figure 5 is a diagram for explaining the peak value of the electric field intensity generated in the FS in the reference example. Figure 5 In the equation, + (positive) represents holes and - (negative) represents electrons.

[0058] In the reference example, the symbol of each element is a symbol obtained by appending r to the end of the symbol of the element related to the semiconductor device 10. In the reference example, the total dose of the collector layer 12r is 3.56×10 12 cm -2 In addition, the collector layer 12r is formed by a single ion implantation, and in order to improve the ohmic characteristics, Figure 5 As shown, the peak of the carrier concentration occurs at a shallow position, that is, at a position close to the back surface 11 b .

[0059] like Figure 4 As shown, the electric field intensity at the time of off in the reference example has a peak near the junction of the base layer 15r and the drift layer 14r and gradually decreases toward the collector layer 12r. On the other hand, the electric field intensity at the time of short circuit has a peak in the FS layer 13r.

[0060] Thus, the peak value of the electric field intensity is generated in the FS layer 13r during short circuit because, for example, Figure 5 As shown in FIG. 1 , the number of holes injected into the end portion of the electric field strength (E) which is the back side of the substrate is small, and the number of electrons in the end portion surrounded by the dotted line becomes excessive. If a peak of the electric field strength is generated on the back side of the substrate, avalanche breakdown may occur near the peak. That is, in a structure having the FS layer 13r, the short circuit withstand capability may be reduced.

[0061] By increasing the carrier concentration of the collector layer 12r, more holes are injected into the position of the FS layer 13r where the electric field intensity may peak, thereby alleviating the above-mentioned transition state of the electrons. That is, the peak of the electric field intensity generated in the FS layer 13r during a short circuit can be suppressed.

[0062] <Collector Layer>

[0063] Next, based on Figure 6 , the structure of the collector layer 12 in the semiconductor device 10 will be mainly described. Figure 6 It is a diagram showing the peak values ​​of the carrier concentrations of the collector layer 12 and the FS layer 13 . Figure 6The distance from the back surface 11b of the semiconductor substrate 11 to the peak position of the carrier concentration is shown. When the position of the peak is shown, the top of the peak is used as a reference.

[0064] The semiconductor device 10 of the present embodiment is applied to a DC-DC converter as described above. In order to satisfy the low turn-off loss required for the converter, the total dose of the collector layer 12 is less than 1×10 13 / cm 2 By reducing the total dose in this way, hole injection can be suppressed during turn-off, thereby reducing turn-off loss. Therefore, for applications requiring low turn-off loss characteristics, it is difficult to increase the carrier concentration of the collector layer and improve short-circuit tolerance as described above.

[0065] Therefore, in this embodiment, if Figure 6 As shown, the carrier concentration of the collector layer 12 has multiple peaks. A part of the multiple peaks may not be a complete peak but may be in the state of a gentle shoulder. As an example, the collector layer 12 has two peaks 12a and 12b. Peak 12a is the peak at the deepest position from the back surface 11b among the multiple peaks, that is, the deepest peak. Peak 12a is the peak at the position closest to the FS layer 13 among the multiple peaks. Peak 12b is the peak at the position closest to the back surface 11b, that is, the shallowest peak. Peak 12b is the peak at the position farthest from the FS layer 13.

[0066] Furthermore, at least a portion of the collector layer 12 is configured to satisfy the following condition: the dose included in ±3σp relative to the peak at the deepest position based on the back surface 11b, i.e., the deepest peak, accounts for more than 13% of the total dose. As an example, in the present embodiment, in the entire region of the collector layer 12 in the element formation region, the dose included in ±3σp of the deepest peak, i.e., the peak 12a, accounts for more than 13% of the total dose.

[0067] Furthermore, the lowest concentration from the back surface 11b to the deepest peak is 1×10 16 / cm 3 The collector layer 12 is formed in the above manner. As an example, in this embodiment, the carrier concentration is lowest between the peaks 12a and 12b. Also, the concentration at the lowest concentration position 12c where the carrier concentration is lowest from the back surface 11b to the deepest peak, i.e., the peak 12a, is 1×10 16 / cm 3 above.

[0068] In addition, the carrier concentration of the FS layer 13 also has at least one peak. Figure 6In the example shown, there is one peak. If the distance from the back surface 11b to the maximum peak where the carrier concentration in the FS layer 13 is the maximum is L1, the distance L1 is 0.8 μm or more. The distance L1 is the distance to the top position of the maximum peak.

[0069] <Summary of First Embodiment>

[0070] As described above, in this embodiment, the total dose of the collector layer 12 is less than 1×10 13 / cm 2 Thus, by reducing the total dose in this way, hole injection can be suppressed during turn-off, thereby reducing turn-off loss.

[0071] In addition, at least a portion of the collector layer 12 is configured so that, among the multiple peaks of the carrier concentration, the dose contained in ±3σp relative to the deepest peak (peak 12a) accounts for more than 13% of the total dose. In this way, by ensuring the dose around the deepest peak, the short-circuit tolerance can be improved while reducing the total dose. Based on the above, the semiconductor device 10 of the present embodiment can improve the short-circuit tolerance and reduce the turn-off loss. The semiconductor device 10 is suitable for applications such as converters that require low turn-off characteristics. In the present embodiment, the collector layer 12 takes into account the above conditions throughout the entire area of ​​the element formation area.

[0072] Figure 7 This is a graph showing the relationship between the dose of the deepest peak and the improvement rate of short-circuit withstand capability in a structure having a plurality of peaks. Figure 7 The simulation results are shown in Figure 2. The dose of the deepest peak is the ratio (%) of the dose included in ±3σp of the deepest peak to the total dose. σp is the projection variance (Japanese original: projection dispersion) derived from the implantation depth of boron. In this simulation, the total dose is set to 5.4×10 12 / cm 2 , three levels of distance from the back surface 11b to the deepest peak, i.e., depth, were confirmed. The solid line represents the result of 0.55μm depth, the dotted line represents the result of 0.44μm depth, and the single-point dash line represents the result of 0.32μm depth. The tolerance improvement rate represents the change rate of the short-circuit tolerance relative to the structure with a single peak at a depth of 0.05μm. In addition, the depth of the collector layer 12 is set to 1μm.

[0073] like Figure 7As shown, if the dose included in the ±3σp of the deepest peak is set to be 13% or more of the total dose, the short-circuit tolerance can be improved regardless of the depth (position) of the deepest peak, and specifically, it can be improved by 5% or more. In particular, if the dose included in the ±3σp of the deepest peak is set to be 22% or more of the total dose, the short-circuit tolerance can be further improved regardless of the depth (position) of the deepest peak, and specifically, it can be improved by 10% or more. In addition, the deeper the position of the deepest peak, that is, the closer to the FS layer 13, the more the short-circuit tolerance can be improved. For example, when the depth of the deepest peak is set to 0.55μm, that is, the peak position is set to be closer to the FS layer 13 side than the center of the depth direction of the collector layer 12, by setting it to be 13% or more of the total dose, the short-circuit tolerance can be improved by more than 10%.

[0074] In the collector layer 12, the lowest concentration in the region from the back surface 11b of the semiconductor substrate 11 to the deepest peak is not particularly limited. As an example, in this embodiment, the lowest concentration from the back surface 11b to the deepest peak is 1×10 16 / cm 3 As a result, the on-state voltage can be reduced, and the turn-off loss can be reduced as described above.

[0075] Figure 8 The relationship between the on-state voltage (Von) and the turn-off loss (Eoff) is shown. Figure 8 : shows the simulation results. In this simulation, the depth of the collector layer 12 was set to 1 μm, and two levels of minimum concentration were confirmed. The solid line indicates 1×10 16 / cm 3 The solid line represents the results of 1×10 15 / cm 3 result.

[0076] If the minimum concentration is set to 1×10 16 / cm 3 , then the minimum concentration is set to 1×10 15 / cm 3 Compared with the structure of Figure 8 As shown, it is possible to reduce the turn-off loss while reducing the on-state voltage.

[0077] The distance L1 from the back surface 11b to the maximum peak of the FS layer 13 is not particularly limited. As an example, in the present embodiment, the distance L1 is 0.8 μm or more. Thus, even if damage occurs on the back surface 11b side during the manufacturing process, the damage is unlikely to reach the FS layer 13. Thus, the variation in the withstand voltage, that is, the variation in the characteristics of the semiconductor device 10, can be suppressed.

[0078] (Second Embodiment)

[0079] This embodiment is a modification of the previous embodiment as a basic form, and the description of the previous embodiment can be cited. In the previous embodiment, the above-mentioned conditions are satisfied in the entire region of the collector layer. Alternatively, the conditions may be satisfied in a part of the collector layer.

[0080] Fig. 9 A semiconductor device 10 according to this embodiment is shown. Fig. 9 Corresponds to Figure 2 .exist Fig. 9 , the back surface 11 b side of the semiconductor device 10 is shown. Fig.10 It is a diagram showing the first element region.

[0081] Fig.11 is a diagram showing the second element region. Fig.10 and Fig.11 In FIG. 1 , the carrier concentration of the collector layer is also shown.

[0082] like Fig. 9 , Fig.10 and Fig.11 As shown, the semiconductor substrate 11 includes a first element region 31 and a second element region 32. A portion of the plurality of cells is the first element region 31, and another portion is the second element region 32. As in the previous embodiment, the total dose of the collector layer 12 is less than 1×10 13 / cm 2 .

[0083] The structures of the collector layers 12 of the first element region 31 and the second element region 32 are different from each other. The collector layer 121 of the first element region 31 satisfies the above conditions. That is, the collector layer 121 is set so that the dose included in ±3σp relative to the deepest peak accounts for more than 13% of the total dose. In addition, the maximum peak 12m where the carrier concentration becomes the maximum in the collector layer 121 is located at a position closer to the drift layer 14 than the center C1 in the depth direction of the collector layer 12. That is, the maximum peak 12m is set at a position closer to the FS layer 13 than the center C1.

[0084] The collector layer 122 of the second element region 32 does not satisfy the above conditions. That is, the dose included in ±3σp relative to the deepest peak of the collector layer 122 is less than 13% of the total dose. In addition, the maximum peak 12m of the collector layer 122 is located at a position closer to the collector electrode 25 than the center C1 of the collector layer 12. That is, the maximum peak 12m is set at a position closer to the back surface 11b than the center C1.

[0085] As an example, in this embodiment, the first element region 31 and the second element region 32 are alternately arranged. Specifically, the first element region 31 and the second element region 32 are alternately arranged in the Y direction, which is the direction in which the plurality of trenches 18 are arranged side by side. The first element region 31 and the second element region 32 are alternately arranged in a stripe shape.

[0086] <Summary of Second Embodiment>

[0087] According to the present embodiment, the semiconductor substrate 11 includes the first element region 31 and the second element region 32. The total dose of the collector layer 12 is less than 1×10 13 / cm 2 The collector layer 121 of the first element region 31 is set so that the dose contained in the deepest peak ±3σp accounts for more than 13% of the total dose. Therefore, similar to the structure shown in the previous embodiment, the short-circuit tolerance can be improved and the turn-off loss can be reduced. In particular, since the maximum peak 12m is located at a position deeper than the center C1, the short-circuit tolerance can be improved.

[0088] On the other hand, the collector layer 122 of the second element region 32 does not satisfy the condition for the deepest peak. However, the maximum peak 12m of the collector layer 122 is located at a position shallower than the center C1. This can improve the ohmic characteristics.

[0089] Thus, the semiconductor device 10 includes the first element region 31 capable of improving short-circuit tolerance and reducing turn-off loss and the second element region 32 capable of improving ohmic characteristics. The first element region 31 and the second element region 32 are mixed. Therefore, the short-circuit tolerance can be improved and the turn-off loss can be reduced, and the ohmic characteristics can be ensured.

[0090] As an example, in this embodiment, the first element regions 31 and the second element regions 32 are alternately arranged. This can suppress the deviation of characteristics within the plane. For example, the deviation of the ohmic contact portion can be suppressed.

[0091] <Modification>

[0092] The configuration of the first element region 31 and the second element region 32 is not limited to the above example. For example, the width of the second element region 32 can be set to a length greater than the thickness of the drift layer 14. Specifically, the width of the second element region 32 can be set to be greater than 50 μm. Thus, the operation of the second element region 32 can be further stabilized. In addition, the width is equivalent to the width of the collector layer. The width is the length of the corresponding collector layer, the length of the arrangement direction of the first element region 31 and the second element region 32.

[0093] The arrangement of the first element region 31 and the second element region 32 is not limited to an alternating arrangement. The semiconductor substrate 11 only needs to include at least one first element region 31 and at least one second element region 32. Fig.12 In the example shown, the semiconductor substrate 11 includes one first element region 31 and one second element region 32 .

[0094] The widths of the first element region 31 and the second element region 32 may be equal to each other or different from each other. Fig.13 As shown in FIG. 1 , the width of the first element region 31 may be wider than the width of the second element region 32. Thus, for example, the short circuit tolerance can be improved compared to a structure in which the widths are equal to each other. Fig.14 As shown, the width of the second element region 32 may be made wider than the width of the first element region 31. Thus, the ohmic characteristics can be improved compared with a structure in which the widths are equal to each other, for example.

[0095] The arrangement of the first element region 31 and the second element region 32 is not limited to a stripe shape, and may be arranged in a dot shape, for example.

[0096] (Other embodiments)

[0097] The disclosure in this specification and the drawings, etc. is not limited to the illustrated embodiments. The disclosure includes the illustrated embodiments and the variations based on these by those skilled in the art. For example, the disclosure is not limited to the combination of parts and / or elements shown in the embodiments. The disclosure can be implemented through a variety of combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure includes the content after the parts and / or elements of the embodiments are omitted. The disclosure includes the replacement or combination of parts and / or elements between one embodiment and other embodiments. The technical scope of the disclosure is not limited to the description of the embodiments. The disclosed technical scope is expressed by the description of the claims, and it should be understood that it also includes all changes within the meaning and scope equivalent to the description of the claims.

[0098] The disclosure in the specification and drawings is not limited by the claims. The disclosure in the specification and drawings includes the technical ideas described in the claims, and further involves various and wider technical ideas than the technical ideas described in the claims. Therefore, it is possible to extract a variety of technical ideas from the disclosure in the specification and drawings without being restricted by the claims.

[0099] When a certain element or layer is referred to as "on", "linked", "connected" or "coupled", it may be directly on, linked, connected or coupled with respect to other elements or other layers, or there may be an intermediate element or intermediate layer. Conversely, when "directly on", "directly linked", "directly connected" or "directly coupled" is referred to, there is no intermediate element or intermediate layer. Other words used to illustrate the relationship between elements should be interpreted in the same way (for example, "between" versus "directly between", "adjacent" versus "directly adjacent", etc.). When used in this specification, the term "and / or" includes any combination related to one or more of the associated listed items, as well as all combinations.

[0100] The spatially relative terms "inside", "outside", "back", "bottom", "low", "top", "high", etc. are used here to facilitate the description of the relationship between an element or feature such as the illustrated diagram and other elements or features. In addition to the orientation depicted in the accompanying drawings, spatially relative terms can also be intended to include different orientations of the device in use or operation. For example, if the device in the figure is turned over, the element described as "below" or "directly below" other elements or features is oriented "above" other elements or features. Therefore, the term "bottom" can include both upper and lower directions. The device can also be oriented in other directions (it can also be rotated 90 degrees or in other directions), and the spatially relative descriptors used in this specification are interpreted accordingly.

[0101] Although the IGBT 11 is shown as an example of a vertical element, the present invention is not limited thereto. An IGBT in which a diode for reflux is connected in anti-parallel may be used, that is, an RC-IGBT. RC is an abbreviation for Reverse Conducting.

[0102] Although the example of the gate electrode 20 having a trench structure is shown, the present invention is not limited thereto and the gate electrode 20 may be arranged on one surface 11 a of the semiconductor substrate 11 via the gate insulating film 19 .

[0103] The n-conductivity type is set as the first conductivity type and the p-conductivity type is set as the second conductivity type, but the present invention is not limited thereto. The p-conductivity type may be set as the first conductivity type and the n-conductivity type may be set as the second conductivity type.

[0104] (Disclosure of technical ideas)

[0105] This specification discloses multiple technical ideas recorded in the following multiple items. Some items are sometimes recorded by selectively citing a multiple dependent form of a preceding item in a subsequent item. Furthermore, some items are sometimes recorded by citing a multiple dependent form of an item in another multiple dependent form (a multiple dependent form referring to another multiple dependent form). These items recorded in multiple dependent forms define multiple technical ideas.

[0106] <Technical Thought 1>

[0107] A semiconductor device comprises: a drift layer (14) of a first conductivity type; a base layer (15) of a second conductivity type, arranged on the drift layer and provided on one side (11a) of a semiconductor substrate (11); an emitter region (16) of a first conductivity type, formed on the surface of the one side of the base layer; a gate electrode (20), disposed opposite to the base layer located between the drift layer and the emitter region via a gate insulating film (19); and a collector layer (12) of a second conductivity type, arranged at a position opposite to the drift layer. The back side (11b) of the semiconductor substrate is provided on the side opposite to the base layer; a field stop layer (13) of the first conductivity type is arranged between the collector layer and the drift layer, and has a higher carrier concentration than the drift layer; an emitter electrode (21) is arranged on the one side and is electrically connected to the base layer and the emitter region; and a collector electrode (25) is arranged on the back side and is electrically connected to the collector layer; the collector layer has a plurality of peak values ​​of carrier concentration, and the total dose of the collector layer is less than 1×10 13 / cm 2 , at least a portion of the collector layer is constructed to satisfy the following condition: the dose contained in ±3σp relative to the deepest peak accounts for more than 13% of the total dose, and the deepest peak is the peak at the deepest position relative to the back side.

[0108] <Technical Thoughts 2>

[0109] In the semiconductor device according to technical idea 1, a distance from the back surface to a maximum peak where the carrier concentration in the field stop layer reaches a maximum is 0.8 μm or more.

[0110] <Technical Thought 3>

[0111] In the semiconductor device according to the technical idea 1 or the technical idea 2, the lowest concentration from the back surface to the deepest peak is 1×10 16 / cm 3 above.

[0112] <Technical Thought 4>

[0113] A semiconductor device as described in any one of technical ideas 1 to 3, wherein the semiconductor substrate comprises: a first element region (31), wherein the collector layer of the first element region satisfies the condition, and a maximum peak at which the carrier concentration in the collector layer becomes maximum is located at a position closer to the drift layer than the center of the collector layer; and a second element region (32), wherein the collector layer of the second element region does not satisfy the condition, and the maximum peak is located at a position closer to the collector electrode than the center.

[0114] <Technical Thought 5>

[0115] In the semiconductor device according to technical idea 4, the first element regions and the second element regions are arranged alternately.

Claims

1. A semiconductor device, It is characterized in that have: A drift layer (14) of a first conductivity type; A second conductive type base layer (15) is disposed on the drift layer and provided on one side (11a) of the semiconductor substrate (11); An emitter region (16) of a first conductivity type is formed on a surface layer on the one side of the base layer; A gate electrode (20) disposed opposite to the base layer located between the drift layer and the emitter region via a gate insulating film (19); A collector layer (12) of a second conductivity type, arranged on a side opposite to the base layer relative to the drift layer, and provided on a back side (11b) of the semiconductor substrate; A first conductive type field stop layer (13), arranged between the collector layer and the drift layer, having a higher carrier concentration than the drift layer; An emitter electrode (21), arranged on the one side and electrically connected to the base layer and the emitter region; as well as A collector electrode (25) is disposed on the back surface and is electrically connected to the collector layer. The total dose of the collector layer is less than 1×10 13 / cm 2 , The collector layer has a plurality of carrier concentration peaks. At least a portion of the collector layer is configured to satisfy the following condition: a dose included in ±3σp with respect to a deepest peak accounts for 13% or more of the total dose, the deepest peak being the peak at the deepest position with respect to the back surface.

2. The semiconductor device according to claim 1, It is characterized in that A distance from the rear surface to a maximum peak at which carrier concentration in the field stop layer reaches a maximum is 0.8 μm or more.

3. The semiconductor device according to claim 1 or 2, It is characterized in that The lowest concentration from the back to the deepest peak is 1×10 16 / cm 3 above.

4. The semiconductor device according to claim 1, It is characterized in that The semiconductor substrate comprises: a first element region (31), wherein the collector layer of the first element region satisfies the condition, and a maximum peak at which the carrier concentration in the collector layer becomes maximum is located at a position closer to the drift layer than the center of the collector layer; as well as A second element region (32), wherein the collector layer of the second element region does not satisfy the condition, and the maximum peak is located at a position closer to the collector electrode than the center.

5. The semiconductor device according to claim 4, It is characterized in that The first element regions and the second element regions are arranged alternately.

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