Semiconductor device and method of manufacturing the same

Abstract

Provided is a semiconductor device that is easy to miniaturize. Provided is a semiconductor device in which parasitic capacitance is reduced. The semiconductor device includes a transistor, a first insulating layer and a second insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer. The first insulating layer is over the first conductive layer and has a first opening to the first conductive layer. The second conductive layer is over the first insulating layer. The semiconductor layer is in contact with the second conductive layer, a side surface of the first insulating layer in the first opening, and a top surface of the first conductive layer. The third insulating layer is in contact with a top surface of the first insulating layer and the semiconductor layer in the first opening. The second insulating layer is over the third insulating layer and has a second opening to the third insulating layer at a position overlapping the first opening. The third conductive layer is provided so as to fill the second opening and the first opening.

Description

Technical Field

[0001] One embodiment of the present invention relates to a transistor, a semiconductor device, a memory device, a display device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices, input-output devices, driving methods of these devices, or manufacturing methods of these devices. Semiconductor devices refer to all devices that can work by utilizing semiconductor characteristics. Background Art

[0003] In recent years, semiconductor devices have been developed, and CPUs, memories, or LSIs other than these are mainly used in semiconductor devices. The CPU is a collection of semiconductor elements including a semiconductor integrated circuit (including at least transistors and memories) formed by processing a semiconductor wafer to form a chip and having electrodes formed as connection terminals.

[0004] A semiconductor circuit (IC chip) of a CPU, a memory, or an LSI other than these is mounted on a circuit board, for example, a printed wiring board, and is used as one of the components of various electronic devices.

[0005] In addition, the technology of forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely used in electronic devices such as integrated circuits and image display devices (simply recorded as display devices). As semiconductor thin films that can be applied to transistors, silicon-based semiconductor materials are widely known, and as other materials, oxide semiconductors have attracted attention.

[0006] In addition, it is known that the leakage current of a transistor using an oxide semiconductor is extremely small in a non-conducting state. For example, Patent Document 1 discloses a low-power CPU that utilizes the characteristic of low leakage current. In addition, for example, Patent Document 2 discloses a storage device that realizes long-term retention of stored content.

[0007] In recent years, with the miniaturization and lightness of electronic devices, the demand for further high density of integrated circuits has increased. In addition, it is required to improve the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technology in which a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film are stacked to overlap and set a plurality of memory cells, thereby improving the density of the integrated circuit. In addition, Patent Document 4 discloses a vertical transistor in which a gate electrode covers the side of an oxide semiconductor via a gate insulator.

[0008] [Prior technical literature]

[0009] [Patent Document]

[0010] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187

[0011] [Patent Document 2] Japanese Patent Application Publication No. 2011-151383

[0012] [Patent Document 3] International Patent Application Publication No. 2021 / 053473

[0013] [Patent Document 4] Japanese Patent Application Publication No. 2013-211537

[0014] [Non-patent literature]

[0015] [Non-patent document 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig., 2019, pp. 50-53 Summary of the invention

[0016] Technical problem to be solved by the invention

[0017] One of the purposes of one embodiment of the present invention is to provide a semiconductor device that is easy to miniaturize. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device that can achieve high integration. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device that reduces parasitic capacitance. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device that reduces wiring load. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with high reliability. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with a fast operating speed.

[0018] One object of one embodiment of the present invention is to provide a semiconductor device, a memory device, a display device, or an electronic device having a novel structure. One object of one embodiment of the present invention is to at least alleviate at least one of the problems of the prior art.

[0019] Note that the description of these purposes does not prevent the existence of other purposes. Note that one embodiment of the present invention does not necessarily achieve all of the above purposes. In addition, purposes other than the above can be extracted from the description of the specification, drawings, claims, etc.

[0020] Solutions to technical problems

[0021] One embodiment of the present invention is a semiconductor device including a transistor, a first insulating layer and a second insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer and a third insulating layer. The first insulating layer is located above the first conductive layer and has a first opening that reaches the first conductive layer. The second conductive layer is located above the first insulating layer. The semiconductor layer contacts the second conductive layer, the side surface of the first insulating layer in the first opening and the top surface of the first conductive layer. The third insulating layer contacts the semiconductor layer in the first opening. The second insulating layer is located above the third insulating layer and has a second opening that reaches the third insulating layer at a position overlapping with the first opening. The third conductive layer is arranged in a manner that fills the second opening and the first opening.

[0022] Furthermore, in the above aspect, the second insulating layer preferably has a portion thicker than the third insulating layer.

[0023] In the above aspect, it is preferable to include a wiring that is in contact with the top surface of the third conductive layer and has a portion overlapping the semiconductor layer or the second conductive layer via the second insulating layer.

[0024] In the above embodiment, the second opening preferably has a portion extending in one direction. In this case, the portion of the third conductive layer located in the second opening is preferably used as a wiring.

[0025] Furthermore, in the above aspect, the opening diameter of the upper end of the first opening is preferably larger than the opening diameter of the lower end of the first opening.

[0026] In addition, another embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a first insulating layer having a first opening; forming a semiconductor layer in contact with the side surface in the first opening of the first insulating layer; forming a third insulating layer in covering the first insulating layer and the semiconductor layer; forming a dummy layer on the third insulating layer and at a position overlapping with the first opening; forming a second insulating layer covering the third insulating layer and the dummy layer; etching the upper portion of the second insulating layer to expose the top surface of the dummy layer; removing the dummy layer to form a second opening in the second insulating layer that overlaps with the first opening and reaches the third insulating layer; and forming a conductive layer in the second opening.

[0027] In the above, when removing the dummy layer, it is preferable to use a wet etching method.

[0028] Furthermore, in the above, it is preferable that a wiring in contact with the conductive layer is formed on the second insulating layer.

[0029] Effects of the Invention

[0030] According to one embodiment of the present invention, a semiconductor device that is easy to miniaturize can be provided. In addition, a semiconductor device that can achieve high integration can be provided. In addition, a semiconductor device that reduces parasitic capacitance can be provided. In addition, a semiconductor device that reduces wiring load can be provided. In addition, a semiconductor device with high reliability can be provided. In addition, a semiconductor device with good electrical characteristics can be provided. In addition, a semiconductor device with a high operating speed can be provided.

[0031] According to one embodiment of the present invention, a semiconductor device, a storage device, a display device, or an electronic device having a novel structure can be provided. According to one embodiment of the present invention, at least one of the problems of the prior art can be alleviated.

[0032] Note that the description of these effects does not prevent the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of the above effects. In addition, effects other than the above can be extracted from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1A and Figure 1B This is an example of the structure of a semiconductor device.

[0034] FIG. 2A to FIG. 2C This is an example of the structure of a semiconductor device.

[0035] Figure 3A and Figure 3B This is an example of the structure of a semiconductor device.

[0036] FIG. 4A to FIG. 4D This is an example of the structure of a semiconductor device.

[0037] FIG. 5A to FIG. 5D This is an example of the structure of a semiconductor device.

[0038] FIG. 6A to FIG. 6D This is an example of the structure of a semiconductor device.

[0039] FIG. 7A to FIG. 7C This is an example of the structure of a semiconductor device.

[0040] FIG. 8A to FIG. 8D This is an example of the structure of a semiconductor device.

[0041] 9A to 9D This is an example of the structure of a semiconductor device.

[0042] Fig. 10A and Fig. 10D The diagrams illustrate an example of a method for manufacturing a semiconductor device.

[0043] Fig.11A and Fig. 11CThe diagrams illustrate an example of a method for manufacturing a semiconductor device.

[0044] Fig. 12A and Fig. 12B The diagrams illustrate an example of a method for manufacturing a semiconductor device.

[0045] Fig.13A and Fig. 13B The diagrams illustrate an example of a method for manufacturing a semiconductor device.

[0046] FIG. 14A to FIG. 14C This is an example of the structure of a storage device.

[0047] Fig.15A and Fig. 15B This is an example of the structure of a storage device.

[0048] Fig.16A and Fig. 16B This is an example of the structure of a storage device.

[0049] Fig.17A and Fig. 17B This is an example of the structure of a storage device.

[0050] Fig.18 This is an example of the structure of a storage device.

[0051] Fig.19 This is an example of the structure of a storage device.

[0052] Fig. 20A and Fig. 20B This is an example of the structure of a storage device.

[0053] FIG. 21A to FIG. 21D This is an example of the structure of a storage device.

[0054] Fig. 22 This is an example of the structure of a storage device.

[0055] Fig.23A and Fig. 23B This is an example of the structure of a display device.

[0056] Fig.24 This is an example of the structure of a display device.

[0057] Fig.25 This is an example of the structure of a display device.

[0058] Fig.26 This is an example of the structure of a display device.

[0059] FIG. 27A to FIG. 27C This is an example of the structure of a display device.

[0060] Fig.28A and Fig.28B This is an example of the structure of a display device.

[0061] FIG. 29A to FIG. 29D It is an example of the structure of an electronic device.

[0062] FIG. 30A to FIG. 30F It is an example of the structure of an electronic device.

[0063] FIG. 31A to FIG. 31G It is an example of the structure of an electronic device.

[0064] Fig.32A and Fig.32B It is an example of the structure of an electronic component.

[0065] FIG. 33A to FIG. 33C It is an example of the structure of a large computer.

[0066] Fig.34A It is an example of the structure of space equipment. Fig.34B This is an example of the structure of a storage system. DETAILED DESCRIPTION

[0067] The following describes the embodiments with reference to the accompanying drawings. However, a person skilled in the art can easily understand that the embodiments can be implemented in a plurality of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0068] Note that in the structure of the invention described below, the same symbols are used in common between different drawings to represent the same parts or parts with the same function, and their repeated description is omitted. In addition, when representing parts with the same function, the same hatching is sometimes used without special additional symbols.

[0069] Note that in each of the drawings described in this specification, the size of each component, the thickness of a layer, or a region may be exaggerated for clarity, and therefore, the present invention is not limited to the sizes in the drawings.

[0070] Note that ordinal numbers such as “first” and “second” used in this specification and the like are provided to avoid confusion among constituent elements and are not intended to limit the number of constituent elements.

[0071] A transistor is a type of semiconductor element and can realize functions of amplifying current or voltage, controlling switching operations of conduction or non-conduction, etc. The transistor in this specification includes IGFET (Insulated Gate Field Effect Transistor) and thin film transistor (TFT: Thin Film Transistor).

[0072] In addition, the functions of "source" and "drain" may be interchanged when transistors with different polarities are used or when the current direction of the circuit operation changes. Therefore, in this specification, "source" and "drain" may be interchanged.

[0073] In addition, in this specification, "electrical connection" includes connection through "an element having some kind of electrical function". Here, "an element having some kind of electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected objects. For example, "an element having some kind of electrical function" includes switching elements such as transistors, resistors, coils, and other elements having various functions in addition to electrodes and wiring.

[0074] Note that in this specification, etc., the top surface shape of a component refers to the outline shape of the component when viewed from a plane. In addition, viewed from a plane refers to the situation when viewed from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0075] Note that in this specification, etc., "the top surface shapes are roughly consistent" refers to the case where at least a portion of the contours of each layer in the stack overlap. For example, this includes the case where the upper layer and the lower layer are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, there are cases where the contours do not overlap and the upper layer is located inside the lower layer or the upper layer is located outside the lower layer. In this case, it can sometimes be said that "the top surface shapes are roughly consistent."

[0076] Note that, in the following, the directions such as "upper" and "lower" are basically used in accordance with the directions in the drawings. However, for the sake of simplicity, the directions indicated by "upper" or "lower" in the specification are sometimes inconsistent with the drawings. For example, when describing the stacking order (or formation order) of a laminate, etc., even if the surface (formed surface, supporting surface, bonding surface, flat surface, etc.) on one side of the laminate is located on the upper side of the laminate in the drawings, the direction is sometimes described as "lower" and the opposite direction is described as "upper".

[0077] In addition, in this specification, "film" and "layer" may be interchanged. For example, "insulating layer" and "insulating film" may be interchanged.

[0078] (Implementation Method 1)

[0079] In this embodiment, a structure example and a manufacturing method example of a semiconductor device which is one embodiment of the present invention are described. A transistor is described below as an example of a semiconductor device.

[0080] The source electrode and drain electrode of the transistor of one embodiment of the present invention are located at different heights (for example, the height in the direction perpendicular to the substrate surface or insulating plane on which the transistor is set), so the current flowing through the semiconductor layer flows in the height direction. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction), so one embodiment of the present invention can be called a vertical transistor, a vertical channel transistor, etc.

[0081] More specifically, an insulating layer serving as a first spacer is provided between a lower electrode of one of the source electrode and the drain electrode of the transistor and an upper electrode of the other, and a semiconductor layer forming a channel is provided inside a first opening provided in the insulating layer in such a manner that the lower electrode is connected to the upper electrode. A gate insulating layer and a gate electrode are provided inside the first opening to overlap with the semiconductor layer. Since the source electrode, the semiconductor layer, and the drain electrode can be provided in an overlapping manner, the occupied area can be greatly reduced compared to a so-called planar transistor in which a semiconductor layer is arranged on a plane.

[0082] Furthermore, it is preferred to provide a gate wiring electrically connected to the gate electrode. In this case, an insulating layer serving as a second spacer is provided between the gate wiring and the upper electrode. For example, the second spacer is preferably thicker than the gate insulating layer. In addition, the second spacer is preferably made of a low dielectric constant material such as silicon oxide or silicon oxynitride. Thus, the parasitic capacitance between the gate wiring and the upper electrode can be effectively reduced.

[0083] The gate electrode is disposed inside each of the second opening and the first opening, and the second opening and the first opening are disposed in the second spacer and the first spacer, respectively. A top surface of the gate electrode may contact a gate wiring disposed on the second spacer.

[0084] Alternatively, the gate electrode itself can be used as the gate wiring. For example, the second opening provided in the second spacer is formed into the same shape as the wiring, and the gate electrode is formed in a manner embedded in the second opening. Thus, there is no need to provide a gate wiring separately, so the process can be simplified.

[0085] As a method for manufacturing a semiconductor device, a semiconductor layer and a gate insulating layer are first formed along the side surface within the first opening of a first spacer, and a second spacer is formed thereon, and then a second opening for embedding a gate electrode is formed. Note that in the above method, when forming the second opening, it is necessary to etch a portion of the second spacer until the gate insulating layer is reached. At this time, when the gate insulating layer is damaged, there is a concern that the reliability of the transistor will be reduced. Thus, before forming the second spacer, a dummy pattern (also called a dummy gate) is formed at the position where the gate electrode is set later, and the second spacer is formed in a manner covering the dummy gate. Next, after etching the upper part of the second spacer to expose the top surface of the dummy gate, the dummy gate is removed, and the gate electrode is formed in a manner to fill the recess generated after removing the dummy gate. Through the above method, a transistor with high reliability can be achieved.

[0086] Here, the channel length of the transistor can be precisely controlled according to the thickness of the insulating layer used as the first spacer, so the unevenness of the channel length can be significantly reduced compared with the planar transistor. Furthermore, by thinning the insulating layer, transistors with extremely short channel lengths can also be manufactured. For example, transistors with a channel length of less than 2 μm, less than 1 μm, less than 500 nm, less than 300 nm, less than 200 nm, less than 100 nm, less than 50 nm, less than 30 nm, or less than 20 nm and more than 5 nm, more than 7 nm, or more than 10 nm can be manufactured. Thus, transistors with extremely small channel lengths that cannot be achieved by mass production exposure devices can be realized. In addition, transistors with a channel length less than 10 nm can be realized without the very expensive exposure devices used in the most advanced LSI technology.

[0087] A transistor in one embodiment of the present invention can make the channel length extremely small, reduce the occupied area, allow large current to flow, reduce parasitic capacitance, and operate at high speed. A transistor in one embodiment of the present invention can be applied to various semiconductor devices. For example, it can be applied to storage devices, computing devices, display devices, camera devices, etc.

[0088] Next, more specific examples will be described with reference to the drawings.

[0089] [Structure example]

[0090] Figure 1A and Figure 1B Each of them is a three-dimensional schematic diagram of the transistor 10 . Figure 1B Yes Figure 1A In addition, in Figure 1A and Figure 1B In the figure, only the outlines of some components (interlayer insulating layer, etc.) are shown.

[0091] Figure 1A and Figure 1B Arrows are used to indicate the X, Y, and Z directions. Figure 1A and Figure 1B The same X, Y, and Z symbols are used to indicate directions, but the directions do not necessarily need to be consistent between the figures.

[0092] Figure 2A is a plan view of transistor 10, Figure 2B , Figure 2C Along the Figure 2A Schematic diagram of the cross section of the cut-off lines A1-A2 and B1-B2 in FIG. Figure 2A Some components (insulating layer, etc.) are omitted.

[0093] The transistor 10 is provided on an insulating layer 11 provided on a substrate (not shown). The transistor 10 includes a conductive layer 31 used as one of a source electrode and a drain electrode, a semiconductor layer 21, an insulating layer 22 used as a gate insulating layer, a conductive layer 23 used as a gate electrode, and a conductive layer 32 used as the other of a source electrode and a drain electrode. The conductive layer 31 and the conductive layer 32 are also used as wiring.

[0094] The conductive layer 31 is provided on the insulating layer 11, and the insulating layer 41 is provided on the conductive layer 31. The conductive layer 32 is provided on the insulating layer 41. The insulating layer 41 has an opening 20a that reaches the conductive layer 31. The semiconductor layer 21 is provided in a manner of contacting the inner wall (also referred to as the side surface, the side wall) of the opening 20a of the insulating layer 41, and in contact with the top surface of the conductive layer 31 and the top surface and the side surface of the conductive layer 32, respectively. The insulating layer 22 is provided in a manner of covering the insulating layer 45, the conductive layer 32, and the semiconductor layer 21. The portion of the insulating layer 22 located inside the opening 20a is provided along the top surface of the semiconductor layer 21.

[0095] The insulating layer 42 is provided on the insulating layer 22. The insulating layer 42 includes an opening 20b overlapping the opening 20a and reaching the insulating layer 22. The conductive layer 23 is provided so as to be embedded in the openings 20a and 20b and in contact with the surface of the insulating layer 22.

[0096] The top surfaces of the insulating layer 42 and the conductive layer 23 are flattened and have substantially the same height. The conductive layer 33 used as wiring is provided on the insulating layer 42. The conductive layer 33 is provided in contact with the top surface of the conductive layer 23. The conductive layer 33 is used as a gate wiring, for example.

[0097] Here, the conductive layer 31 is embedded in the insulating layer 44, the conductive layer 32 is embedded in the insulating layer 45, and the conductive layer 33 is embedded in the insulating layer 46. Furthermore, their top surfaces are flattened, and the heights of the top surfaces of the conductive layer and the insulating layer are roughly the same. By adopting this structure, it is not affected by the step, so it is preferred. The insulating layer 44, the insulating layer 45 and the insulating layer 46 are used as interlayer insulating layers. For example, it is preferable to use an inorganic insulating material with a low dielectric constant such as silicon oxide and silicon oxynitride.

[0098] The source electrode and drain electrode of the transistor 10 having the above structure are located at different heights, so the current flowing through the semiconductor flows in the height direction. In other words, the channel length direction can have a component in the height direction (vertical direction), so the transistor of one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, etc. In the transistor 10, the source electrode, the semiconductor, and the drain electrode can be overlapped, so compared with the so-called planar transistor (also called a lateral transistor, LFET (Lateral FET), etc.) in which the semiconductor is configured on a plane, the occupied area can be greatly reduced.

[0099] In addition, the channel length of the transistor 10 can be precisely controlled according to the thickness of the insulating layer 41 used as a spacer, so the unevenness of the channel length can be significantly reduced compared to a planar transistor. Furthermore, by thinning the insulating layer 41, a transistor with an extremely short channel length can also be manufactured. For example, a transistor with a channel length of less than 50nm, less than 30nm, or less than 20nm and more than 5nm, more than 7nm, or more than 10nm can be manufactured. Therefore, even if an existing mass production exposure device is used instead of a very expensive exposure device used in the most advanced LSI technology, a transistor with a channel length less than 10nm can be realized.

[0100] The semiconductor layer 21 can use various semiconductor materials, and it is particularly preferred to use an oxide semiconductor including a metal oxide. By using an oxide semiconductor formed under appropriate conditions, a transistor having both high on-state current and extremely low off-state current can be realized at low cost. Below, unless otherwise specified, a preferred structural example of the case where an oxide semiconductor is used as the semiconductor layer 21 is described.

[0101] Each top surface of the conductive layer 31 and the conductive layer 32 is in contact with the semiconductor layer 21. Therefore, when an oxide semiconductor is used as the semiconductor layer 21, due to the deposition process of the semiconductor film to be the semiconductor layer 21 or the influence of the subsequent heating, the exposed surface of the conductive layer 31 and the conductive layer 32 is oxidized near the semiconductor layer 21 to form an insulating oxide film between the conductive layer 31 and the semiconductor layer 21, so that the contact resistance is sometimes increased. Therefore, at least the uppermost part of the conductive layer 31 and the conductive layer 32 preferably uses an oxide conductor containing a conductive oxide. Thus, the increase in contact resistance caused by surface oxidation of the conductive layer 31 and the conductive layer 32 can be prevented. The conductive layer 31 and the conductive layer 32 may also be referred to as an oxide layer, a metal oxide layer, or an oxide conductor layer.

[0102] Conductive layer 31 can be used as one of source wiring and drain wiring. In addition, conductive layer 32 can be used as the other of source wiring and drain wiring. In this way, when one or both of conductive layer 31 and conductive layer 32 are used as wiring, it is preferred that the resistance is low. For this reason, it is preferred to use a material having a higher conductivity than an oxide conductor, such as a metal, an alloy or their nitride. In particular, one or both of conductive layer 31 and conductive layer 32 preferably has a stacked structure including a layer composed of the material having a high conductivity, wherein at least the uppermost portion uses the above-mentioned oxide conductor.

[0103] Here, the transistor 10 is provided at the intersection of the conductive layer 33 used as the gate wiring and the conductive layer 32 used as the source wiring or the drain wiring. Therefore, at the intersection of the conductive layer 33 and the conductive layer 32, a parasitic capacitance is generated in the overlapping portion thereof. However, in one embodiment of the present invention, an insulating layer 42 is provided between the conductive layer 33 and the conductive layer 32, thereby significantly reducing the parasitic capacitance compared to a case where there is no insulating layer 42 (for example, a case where the conductive layer 33 and the conductive layer 32 overlap with the insulating layer 22).

[0104] Furthermore, by increasing the thickness of the insulating layer 42, the parasitic capacitance between the conductive layer 33 and the conductive layer 32 can be reduced. For example, the insulating layer 42 can be thicker than the insulating layer 22. In addition, the insulating layer 42 is more preferably thicker than at least one of the insulating layer 44, the insulating layer 45, and the insulating layer 46. The thicker the insulating layer 42 is, the more the parasitic capacitance between the conductive layer 33 and the conductive layer 32 can be reduced, so it is preferred, but its thickness can be set in consideration of productivity. For example, the thickness of the insulating layer 42 can be less than 2 times or less than 3 times the thickness of the insulating layer 41.

[0105] exist Figure 2B and Figure 2C In FIG. 1 , a laminated film including an insulating layer 41a, an insulating layer 41b, and an insulating layer 41c is shown as Figure 1A and Figure 1B In the case of the insulating layer 41. In addition, Figure 3A yes Figure 2B Magnified image of .

[0106] The semiconductor layer 21 is arranged in a manner in contact with the inner wall in the opening 20a of the insulating layer 41b. The insulating layer 41b preferably uses an oxide insulating film. In particular, it is preferable to use an oxide insulating film that releases oxygen by heating. In addition, it is preferable to adopt a structure in which the insulating layer 41b is sandwiched by the insulating layer 41a and the insulating layer 41c that have a barrier property to oxygen. As a result, the oxygen contained in the insulating layer 41b can be enclosed in the area surrounded by the insulating layer 41a, the insulating layer 41c and the semiconductor layer 21, and the oxygen in the insulating layer 41b can be prevented from being separated and reduced during the process, so that oxygen can be supplied to the semiconductor layer 21 more efficiently.

[0107] The portion of the semiconductor layer 21 that contacts the insulating layer 41b is a region where oxygen vacancies are reduced, and can be said to be an i-type region. On the other hand, the portion that does not contact the insulating layer 41b is preferably an n-type region containing a plurality of carriers. That is, the portion of the semiconductor layer 21 that contacts the insulating layer 41b can be referred to as a channel formation region, and the outer region thereof can be referred to as a low resistance region (also referred to as a source region or a drain region). Figure 3A In FIG. 1 , the channel formation region 21 i and the low resistance region 21 n of the semiconductor layer 21 are given different hatchings.

[0108] At this time, if Figure 3A As shown, the channel length L of the transistor 10 can be said to be the length of the portion that contacts the insulating layer 41b and is located on the shortest path connecting the portion that contacts the conductive layer 31 and the portion that contacts the conductive layer 32 in the semiconductor layer 21. When the angle (θ) of the side wall of the opening 20a of the insulating layer 41b is 90 degrees, the channel length L is consistent with the thickness of the insulating layer 41b. By making θ less than (or greater than) 90 degrees, the channel length L can be made greater than the thickness of the insulating layer 41b.

[0109] On the other hand, the channel width W of the transistor 10 depends on the shape of the opening 20 a . Figure 3B From the Z direction, along Figure 3A A plan view of the truncated surface when the truncation line C1-C2 at the height where the insulating layer 41b is provided is truncated. Here, the case where the opening 20a has a cylindrical shape is shown. When the outline of the opening 20a is a circle with a diameter R, the channel width W can be regarded as the circumference of the opening 20a (i.e., =π×R). Here, when the angle θ of the side wall of the opening 20a of the insulating layer 41b is offset from 90 degrees, the circumference of the opening 20a is different according to the height. At this time, the circumference of the height where the diameter of the opening 20a is the smallest can be regarded as the channel width W, or the circumference of the height of the upper end of the opening 20a can be regarded as the channel width W.

[0110] Since the semiconductor layer 21 and the insulating layer 22 are formed along the inner wall of the opening 20a of the insulating layer 41b, the thickness of this part is sometimes thinned depending on the deposition method. For example, in deposition methods such as sputtering or plasma CVD, the thickness of the film deposited on a surface inclined or perpendicular to the substrate surface tends to be thinner than the thickness of the film deposited on a surface parallel to the substrate surface. On the other hand, when a deposition method such as atomic layer deposition (ALD) or thermal CVD is used, a film of uniform thickness can be deposited regardless of the angle of the formed surface. For example, when the angle θ of the side wall of the opening 20a of the insulating layer 41b is greater than 75 degrees, greater than 80 degrees, or greater than 85 degrees, it is preferred to form the semiconductor layer 21 and the insulating layer 22 using the ALD method.

[0111] The diameter of the opening 20b provided in the insulating layer 42 is preferably equal to or larger than the diameter of the opening 20a provided in the insulating layer 41b. By making the opening 20b larger than the opening 20a, it is possible to prevent the opening 20a from being filled up due to the positional misalignment when forming the opening 20b.

[0112] Here, the thickness of the insulating layer 42 may be equal to or greater than the channel length L. For example, by setting the thickness of the insulating layer 42 to be equal to or greater than the thickness of the insulating layer 41 b , the parasitic capacitance can be more effectively reduced.

[0113] [Components]

[0114] <Substrate>

[0115] As a substrate for forming a transistor, for example, an insulator substrate, a semiconductor substrate or a conductor substrate can be used. As an insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), a resin substrate, etc. can be cited. In addition, as a semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide or gallium oxide can be cited. In addition, a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, etc. can also be cited. As a conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. can be cited. Alternatively, a substrate containing a metal nitride, a substrate containing a metal oxide, etc. can also be used. In addition, an insulator substrate provided with a conductive layer or a semiconductor layer, a semiconductor substrate provided with a conductive layer or an insulating layer, a conductor substrate provided with a semiconductor layer or an insulating layer, etc. can also be cited. Alternatively, a substrate having elements provided on these substrates can also be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light emitting element, and a memory element.

[0116] <Semiconductor Layer>

[0117] The semiconductor layer 21 preferably includes a metal oxide (oxide semiconductor).

[0118] As metal oxides that can be used for the semiconductor layer 21, for example, In oxide, Ga oxide and Zn oxide can be cited. The metal oxide preferably contains at least In or Zn. In addition, the metal oxide preferably contains two or three selected from In, element M and Zn. Note that element M is a metal element or a semi-metal element with a high bond energy with oxygen, for example, a metal element or a semi-metal element with a higher bond energy with oxygen than In. As element M, specifically Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge and Sb can be cited. The element M contained in the metal oxide is preferably one or more of the above elements, and is particularly preferably one or more selected from Al, Ga, Y and Sn, among which Ga is more preferred. Note that the metal oxide containing In, M and Zn is sometimes referred to as In-M-Zn oxide below. Note that in this specification and the like, metal elements and semi-metal elements may be collectively referred to as “metal elements”, and the “metal elements” described in this specification and the like may include semi-metal elements.

[0119] When In-M-Zn oxide is used as the metal oxide, the atomic ratio of In in the In-M-Zn oxide is preferably greater than the atomic ratio of M. For example, as the atomic ratio of the metal elements of such In-M-Zn oxide, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn=6:1:6, In:M:Zn=5:2:5 or compositions in the vicinity thereof can be cited. Note that the composition in the vicinity includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of In in the metal oxide, the on-state current and field effect mobility of the transistor can be improved.

[0120] The atomic ratio of In in the In-M-Zn oxide may be smaller than the atomic ratio of M. For example, the atomic ratio of the metal elements in such an In-M-Zn oxide may be In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4 or compositions near these. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0121] The semiconductor layer 21 may be made of, for example, In-Zn oxide, In-Ga oxide, In-Sn oxide, In-Ti oxide, In-Ga-Al oxide, In-Ga-Sn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In-Al-Zn oxide, In-Ti-Zn oxide, In-Ga-Sn-Zn oxide, In-Ga-Al-Zn oxide, etc. In addition, Ga-Zn oxide may also be used.

[0122] Metal oxides may also replace In or contain one or more metal elements with a large period number in addition to In. There is a tendency that the greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, when a metal element with a large period number is included, the field effect mobility of the transistor can sometimes be improved. As metal elements with a large period number, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm and Eu can be cited. Note that La, Ce, Pr, Nd, Pm, Sm and Eu are called light rare earth elements.

[0123] In addition, the metal oxide may also contain one or more non-metallic elements. When the metal oxide contains non-metallic elements, the field effect mobility of the transistor may sometimes be improved. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0124] The metal oxide can be formed by sputtering or atomic layer deposition (ALD) as appropriate. Note that when the metal oxide is formed by sputtering, the composition of the deposited metal oxide is sometimes different from the composition of the target. In particular, the zinc content in the deposited metal oxide is sometimes reduced to about 50% of the zinc content in the target.

[0125] In this specification, etc., the content rate of a certain metal element in a metal oxide refers to the ratio of the number of atoms of the element to the total number of atoms of the metal element contained in the metal oxide. For example, a metal oxide contains a metal element X, a metal element Y, and a metal element Z, and the number of atoms of the metal element X, the metal element Y, and the metal element Z contained in the metal oxide is A, respectively. X , A Y , A Z When the content of metal element X is expressed as A X / (A X +A Y +A Z ). In addition, when the ratio of the number of atoms of metal element X, metal element Y, and metal element Z in the metal oxide (atomic ratio) is expressed as B X :B Y :B Z When the content of metal element X is expressed as B X / (B X +B Y +B Z ).

[0126] For example, when a metal oxide containing In is used, a transistor with a large on-state current can be realized by increasing the In content.

[0127] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, a transistor with high reliability for forward bias can be realized. In other words, a transistor with a small change in threshold voltage in a PBTS (Positive Bias Temperature Stress) test can be realized. In addition, when using a metal oxide containing Ga, the Ga content is preferably lower than the In content. Thus, a transistor with high mobility and high reliability can be realized.

[0128] On the other hand, by increasing the Ga content, a transistor with high reliability to light can be realized. In other words, a transistor with a small change in threshold voltage in the NBTIS (Negative Bias Temperature Illumination Stress) test can be realized. Specifically, the band gap of a metal oxide in which the atomic number of Ga is greater than the atomic number of In is larger, which can reduce the change in threshold voltage of the transistor in the NBTIS test.

[0129] Furthermore, by increasing the zinc content, a highly crystalline metal oxide is formed, and diffusion of impurities in the metal oxide can be suppressed. As a result, variations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.

[0130] The semiconductor layer 21 may also have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the semiconductor layer 21 may also be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form them, thereby reducing manufacturing costs. Note that a stacked structure of two or more oxide semiconductor layers with different stacked compositions may also be adopted. In addition, by utilizing the ALD method, a metal oxide layer whose composition changes continuously in the thickness direction may be formed. Thus, compared with the case of using a film with a predetermined composition, not only can the range of design options be expanded, but also the generation of interface states, etc., generated between two layers with different compositions can be prevented, thereby improving electrical properties and reliability.

[0131] In the case where the semiconductor layer 21 has a two-layer structure, it is preferred to use a material (a material with high conductivity) whose mobility is higher than that of the first layer in the second layer, that is, the layer close to the gate electrode. Thus, a transistor that is normally off and has a large on-state current can be formed. Therefore, low power consumption and high performance can be achieved. In addition, a material whose mobility is higher than that of the second layer can also be used in the first layer, that is, the layer on the side in contact with the source electrode and the drain electrode. Thus, the contact resistance between the semiconductor layer 21 and the source electrode or the drain electrode can be reduced, thereby reducing the parasitic resistance and forming a transistor with a large on-state current.

[0132] When the semiconductor layer 21 has a three-layer structure, it is preferable to use a material having a higher mobility in the second layer than in the first and third layers. This can realize a transistor with high on-state current and high reliability.

[0133] For example, the mobility or conductivity mentioned above can be replaced by the indium content. In addition, the following factors also affect mobility and conductivity: the presence or absence of elements other than indium that help improve conductivity or the content of the element. As an example of a high mobility material, for example, In:Ga:Zn=4:3:2 [atomic ratio] and materials near it, In:Zn=1:1 [atomic ratio] and materials near it, In:Zn=4:1 [atomic ratio] and materials near it, In:Sn:Zn=40:X:10 [atomic ratio] (X is greater than 0.1 and less than 5, typically X=1) and materials near it, etc. can be cited. On the other hand, as materials whose mobility or conductivity is lower than the above-mentioned materials, there can be listed materials such as In:Ga:Zn=1:3:2 [atomic ratio] and materials close to it, materials such as In:Ga:Zn=1:3:4 [atomic ratio] and materials close to it, materials such as In:Ga:Zn=2:2:1 [atomic ratio] and materials close to it, materials such as In:Ga:Zn=1:1:1 [atomic ratio] and materials close to it, and materials such as In:Ga:Zn=1:1:2 [atomic ratio] and materials close to it.

[0134] It is preferable to use a crystalline metal oxide layer as the semiconductor layer 21. For example, a metal oxide layer having a CAAC (c-axis aligned crystal: c-axis oriented crystal) structure, a polycrystalline structure, a microcrystalline (nc: nano-crystal) structure, etc. can be used. By using a crystalline metal oxide layer for the semiconductor layer 21, the defect state density in the semiconductor layer 21 can be reduced, thereby realizing a semiconductor device with high reliability.

[0135] The higher the crystallinity of the metal oxide layer used for the semiconductor layer 21, the lower the defect state density in the semiconductor layer 21. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0136] Compared with transistors using amorphous silicon, transistors using oxide semiconductors (hereinafter referred to as OS transistors) have very high field effect mobility. In addition, the leakage current between the source and drain of the OS transistor in the off state (hereinafter also referred to as off-state current) is extremely low, and the charge stored in the capacitor connected in series with the transistor can be maintained for a long period of time. In addition, by using OS transistors, the power consumption of semiconductor devices can be reduced.

[0137] A semiconductor device of one embodiment of the present invention can be applied to a display device, for example. When increasing the luminous brightness of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To this end, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Because the source-drain withstand voltage of an OS transistor is higher than that of a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Thus, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be increased to increase the luminous brightness of the light-emitting device.

[0138] When the transistor operates in the saturation region, the OS transistor can make the change in the source-drain current for the change in the gate-source voltage smaller than the Si transistor. Therefore, by using the OS transistor as the driving transistor included in the pixel circuit, the amount of current flowing through the light-emitting device can be tightly controlled. As a result, the number of grayscales of the pixel circuit can be increased. In addition, even if the electrical characteristics (such as resistance) of the light-emitting device change or the electrical characteristics are uneven, a stable current can flow.

[0139] As described above, by using an OS transistor as a driving transistor included in a pixel circuit, “suppression of black blur”, “increase in light emission brightness”, “multi-grayscale”, “suppression of the influence of manufacturing unevenness of light-emitting devices”, etc. can be achieved.

[0140] OS transistors have little change in electrical characteristics due to exposure to radiation, that is, they have high tolerance to radiation, so they can be appropriately used in environments where radiation may be incident. OS transistors can also be said to have high reliability with respect to radiation. For example, OS transistors can be appropriately used as pixel circuits of flat-panel detectors for X-rays. In addition, OS transistors can be appropriately used in semiconductor devices used in outer space. As radiation, electromagnetic radiation (for example, X-rays and gamma rays) and particle radiation (for example, alpha rays, beta rays, proton radiation, and neutron radiation) can be cited.

[0141] Note that the semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors. For example, a semiconductor composed of a single element or a compound semiconductor can be used. As a semiconductor composed of a single element, silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, amorphous silicon) or germanium can be cited. As a compound semiconductor, for example, gallium arsenide and silicon germanium can be cited. As a compound semiconductor, for example, an organic semiconductor, a nitride semiconductor or an oxide semiconductor can be cited. Note that these semiconductor materials can also contain impurities as dopants.

[0142] Alternatively, the semiconductor layer 21 may also have a layered material used as a semiconductor. A layered material is a general term for a group of materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds such as van der Waals bonds that are weaker than covalent bonds and ionic bonds. The layered material has high conductivity in a unit layer, that is, has high two-dimensional conductivity. By using a material used as a semiconductor and having high two-dimensional conductivity in a channel formation region, a transistor with a large on-state current can be provided.

[0143] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing oxygen group elements (elements belonging to Group 16). In addition, examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specifically, examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS 2 ), Molybdenum selenide (typically MoSe 2 ), molybdenum telluride (typically MoTe 2 ), tungsten sulfide (typically WS 2 ), tungsten selenide (typically WSe 2 ), tungsten telluride (typically WTe 2 ), hafnium sulfide (typically HfS 2 ), hafnium selenide (typically HfSe 2 ), zirconium sulfide (typically ZrS 2 ), zirconium selenide (typically ZrSe 2 )wait.

[0144] There is no particular limitation on the crystallinity of the semiconductor material used for the semiconductor layer 21, and an amorphous semiconductor, a single crystal semiconductor, or a semiconductor having crystallinity other than a single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part thereof) can be used. When a semiconductor having crystallinity is used, it is preferred because it can suppress the degradation of the characteristics of the transistor.

[0145] <Gate Insulation Layer>

[0146] The insulating layer 22 is used as a gate insulating layer of a transistor and is also used as a dielectric layer of a capacitor. When an oxide semiconductor is used for the semiconductor layer 21, an oxide insulating film is preferably used as a film in the insulating layer 22 that is at least in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride and Ga-Zn oxide can be used. In addition, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, etc. can also be used as the insulating layer 22. In addition, the insulating layer 22 can also have a stacked structure, for example, it can also have a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0147] Note that in this specification and the like, an oxynitride refers to a material containing more oxygen than nitrogen, and an oxynitride refers to a material containing more nitrogen than oxygen.

[0148] In addition, the insulating layer 22 is preferably used by stacking an insulating material composed of a high-k material, and preferably uses a stacked structure of a high relative dielectric constant (high-k) material and a material having a dielectric strength greater than the high-k material. For example, as the insulating layer 22, an insulating film (also referred to as ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in sequence can be used. In addition, for example, an insulating film (also referred to as ZAZA) in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in sequence can be used. In addition, for example, an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are stacked in sequence can be used. By stacking an insulator with a larger dielectric strength such as aluminum oxide, the dielectric strength can be increased and the electrostatic destruction of the capacitor can be suppressed.

[0149] In addition, a material exhibiting ferroelectricity may be used as the insulating layer 22. Examples of the material exhibiting ferroelectricity include hafnium oxide, zirconium oxide, HfZrO X (X is a real number greater than 0) and other metal oxides.

[0150] <Conductive layer>

[0151] Each top surface of the conductive layer 31 and the conductive layer 32 is in contact with the semiconductor layer 21. Here, when an oxide semiconductor is used as the semiconductor layer 21, when a metal that is easily oxidized, such as aluminum, is used for the upper part of the conductive layer 31 or the conductive layer 32, an insulating oxide (such as aluminum oxide) may be formed between the conductive layer 31 or the conductive layer 32 and the semiconductor layer 21 to hinder conduction therebetween. Therefore, at least the uppermost part of the conductive layer 31 and the conductive layer 32 is preferably made of a conductive material that is not easily oxidized, a conductive material that maintains low resistance even if oxidized, or an oxide conductive material.

[0152] As the conductive layer 31 and the conductive layer 32, for example, titanium, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. are preferably used. These are conductive materials that are not easily oxidized or materials that maintain conductivity even if oxidized, so they are preferred.

[0153] Alternatively, conductive oxides such as indium oxide, zinc oxide, In-Sn oxide, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide, and Ga-Zn oxide may be used. In particular, conductive oxides containing indium are preferably used because they have high conductivity. In addition, oxide materials such as In-Ga-Zn oxide that can be applied to the semiconductor layer 21 may also be used for a conductive layer by increasing carrier concentration.

[0154] The conductive layer 23 is used as a gate electrode, and various conductive materials can be used. As the conductive layer 23, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy with the metal element as a component is preferably used. In addition, nitrides of the above metals or alloys or oxides of the above metals or alloys can also be used. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. are preferably used. In addition, semiconductors with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used.

[0155] In addition, the conductive layer 23 may also use the nitride and oxide that can be used for the conductive layer 31 and the conductive layer 32 .

[0156] Since the conductive layer 31 and the conductive layer 32 are also used as wiring, a low-resistance conductive material can also be stacked. In addition, the lower the resistance of the conductive layer 33, the more preferably. As the conductive layer 31, the conductive layer 32 and the conductive layer 33, the same conductive material as the conductive layer 23 can be used.

[0157] <Insulation layer>

[0158] The insulating layer 41 (or the insulating layer 41b) has a portion in contact with the semiconductor layer 21. When an oxide semiconductor is used for the semiconductor layer 21, in order to improve the interface characteristics between the semiconductor layer 21 and the insulating layer 41, it is preferred that an oxide is used for at least the portion of the insulating layer 41 in contact with the semiconductor layer 21. For example, silicon oxide or silicon oxynitride can be appropriately used.

[0159] In addition, the insulating layer 41 preferably uses a film that releases oxygen by heating. Thus, oxygen can be supplied to the semiconductor layer 21 by heat applied in the manufacturing process of the transistor 10, oxygen vacancies in the semiconductor layer 21 can be reduced, and reliability can be improved. As a method for supplying oxygen to the insulating layer 41, heat treatment in an oxygen atmosphere, plasma treatment in an oxygen atmosphere, etc. can be cited. In addition, oxygen can also be supplied to the insulating layer 41 by depositing an oxide film on the top surface of the insulating layer 41 in an oxygen atmosphere by sputtering. Then, the oxide film can also be removed.

[0160] The insulating layer 41 is preferably formed by a deposition method such as a sputtering method or a plasma CVD method. In particular, by depositing by a sputtering method using a deposition method that does not use hydrogen gas as a deposition gas, a film containing very little hydrogen can be formed. As a result, the supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 10 can be stabilized.

[0161] As the insulating layer 41a and the insulating layer 41c, it is preferable to use a film that does not diffuse oxygen easily. Thus, it is possible to prevent oxygen in the insulating layer 41b from penetrating to the insulating layer 11 side through the insulating layer 41a and penetrating to the insulating layer 22 side through the insulating layer 41c due to heating. In other words, by sandwiching the upper and lower parts of the insulating layer 41b with the insulating layer 41a and the insulating layer 41c that do not diffuse oxygen easily, the oxygen in the insulating layer 41b can be confined. Thus, oxygen can be effectively supplied to the semiconductor layer 21.

[0162] As the insulating layer 41a and the insulating layer 41c, for example, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. In particular, silicon nitride and silicon nitride oxide have the characteristics of rarely releasing impurities (such as water and hydrogen) and not easily allowing oxygen and hydrogen to pass through, so they can be appropriately used as the insulating layer 41a and the insulating layer 41c.

[0163] [Deformation example]

[0164] An example in which a part of the configuration is different from the above example is described below. Note that the description of the part overlapping with the above content may be omitted.

[0165] <Deformation Example 1>

[0166] Figure 4A and Figure 4B is a schematic cross-sectional view of the transistor 10a. Figure 4A is with Figure 2B Similarly, in the cross-sectional view parallel to the extension direction of the conductive layer 32, Figure 4B is with Figure 2C The cross-sectional view is also parallel to the extension direction of the conductive layer 33. The transistor 10a is different from the above-mentioned transistor 10 mainly in the shape of the opening 20b.

[0167] In the transistor 10a, the end of the semiconductor layer 21 is located inside the opening 20b. Figure 4A As shown, the diameter of the opening 20 b is greater than the width of the conductive layer 33 .

[0168] In this way, by increasing the diameter of the opening 20 b , the contact area between the conductive layer 23 and the conductive layer 33 can be increased, thereby reducing the contact resistance between the conductive layer 23 and the conductive layer 33 .

[0169] <Deformation Example 2>

[0170] Figure 4C and Figure 4D The transistor 10b shown is an example in which the side wall of the opening 20a has a tapered shape. In the transistor 10b, the diameter of the upper end (opening diameter) of the opening 20a is larger than the diameter of the lower end (opening diameter).

[0171] The side wall of the opening 20a has a tapered shape, so that the coverage of the semiconductor layer 21, the insulating layer 22, etc. is improved, and even if a deposition method such as a sputtering method is used, the generation of defects such as a low-density region in the film can be suppressed. For example, the angle θ can be greater than 45 degrees and less than 90 degrees, greater than 60 degrees and less than 90 degrees, or greater than 70 degrees and less than 90 degrees. In addition, when a deposition method with extremely high coverage such as an ALD method is used, the angle θ can also be greater than 90 degrees.

[0172] When the side wall of the opening 20a has a tapered shape, the diameter of the opening 20a corresponding to the channel width of the transistor 10c increases from the conductive layer 31 side to the conductive layer 32 side. At this time, the magnitude of the current flowing through the transistor 10c is limited by the portion with the smallest diameter. Therefore, the channel width of the transistor 10c can be regarded as the circumference of the portion with the smallest diameter. Therefore, by having the side wall of the opening 20a have a tapered shape, a transistor having a channel width smaller than the diameter of the upper end of the opening 20a can be manufactured.

[0173] in addition, Figure 5A and Figure 5B The transistor 10c and Figure 5C and Figure 5D The transistor 10d shown is an example of a case where the angle of the side wall of the opening 20b is not 90 degrees in addition to the opening 20a. Figure 5C and Figure 5D As shown, the diameter of the upper end of the opening 20 b is preferably greater than the diameter of the lower end of the opening 20 b , thereby increasing the contact area between the conductive layer 23 and the conductive layer 33 .

[0174] <Deformation Example 3>

[0175] Fig. 6A and Figure 6BThe transistor 10 e shown is different from the above-mentioned transistor 10 mainly in that the transistor 10 e includes a conductive layer 26 and an insulating layer 27 .

[0176] The conductive layer 26 is used as a second gate electrode (or back gate electrode). In addition, the insulating layer 27 is located between the conductive layer 26 and the semiconductor layer 21 and is used as a second gate insulating layer (or back gate insulating layer). The conductive layer 26 can be supplied with a fixed potential or an arbitrary signal. By providing the conductive layer 26 and supplying an appropriate potential to the conductive layer 26, the potential on the back channel side of the semiconductor layer 21 can be fixed, thereby reducing the unevenness of the electrical characteristics. In addition, the conductive layer 26 can also be electrically connected to any one of the conductive layer 31, the conductive layer 32 and the conductive layer 23 to be supplied with the same potential.

[0177] The conductive layer 26 is embedded in the insulating layer 41b. Therefore, the conductive layer 26 is provided between the insulating layer 41a and the insulating layer 41c. The insulating layer 27 is provided along the side surfaces of the conductive layer 32, the insulating layer 41c, the conductive layer 26, and the insulating layer 41a. For example, an opening is formed in the conductive layer 32, the insulating layer 41c, the conductive layer 26, and the insulating layer 41a, an insulating film covering the opening is formed by a deposition method with high coverage, and then anisotropic etching is performed, thereby forming the insulating layer 27.

[0178] <Deformation Example 4>

[0179] Figure 6C and Fig.6D The transistor 10 f shown is different from the transistor 10 and the transistor 10 a mainly in the shape of the conductive layer 31 .

[0180] The conductive layer 31 has a recessed portion, and the semiconductor layer 21, the insulating layer 22, and the conductive layer 23 are provided along the recessed portion. At this time, the height of the lower end of the conductive layer 23 is preferably lower than the height of the top surface of the conductive layer 31.

[0181] In the transistor 10f, the portion of the semiconductor layer 21 in contact with the conductive layer 31 is a region where the resistance is lower than that of the channel formation region. Therefore, by making the height of the lower end of the conductive layer 23 lower than the top surface of the conductive layer 31, the gate electric field can be uniformly applied to the entire channel formation region of the semiconductor layer 21, thereby preventing the formation of a high resistance region (bias region) due to the difficulty in applying the gate electric field in the semiconductor layer 21. Therefore, a transistor with improved on-state current can be realized. In order to realize such a structure, for example, the thickness of the conductive layer 31 is preferably at least thicker than the sum of the thickness of the semiconductor layer 21 and the thickness of the insulating layer 22.

[0182] <Deformation Example 5>

[0183] The above description describes a structure that can reduce the parasitic capacitance between the conductive layer 33 and the conductive layer 32, but in the case where there is no strict requirement for wiring capacitance, such as a circuit that does not require high-speed operation, the conductive layer 23 can be used as a gate electrode and gate wiring without providing the conductive layer 33. This can significantly reduce the number of manufacturing steps.

[0184] Fig. 7A , Figure 7B and Figure 7C The transistor 10 g shown mainly differs from the transistor 10 in that the former does not include the conductive layer 33 ; and in the partial shape of the conductive layer 23 .

[0185] In transistor 10g, the shape of opening 20b provided in insulating layer 42 (ie, the shape of conductive layer 23) is not cylindrical but extends in one direction. Transistor 10g shows an example in which opening 20b and conductive layer 23 have shapes extending in the Y direction.

[0186] At this time, the diameter in the direction perpendicular to the extending direction of the opening 20b ( Figure 7B The smaller the diameter of the opening 20b in the semiconductor layer 21 is, the smaller the width of the conductive layer 23 is, the smaller the area where the conductive layer 23 and the conductive layer 32 intersect can be, thereby reducing the parasitic capacitance between them, which is preferred. For example, it is preferred to set the diameter to be less than the width of the semiconductor layer 21 or equal to or less than the diameter of the opening 20a.

[0187] Fig. 8A and Figure 8B The transistor 10h shown in the figure shows an example in which the diameter in the direction perpendicular to the extending direction of the opening 20b is larger than the width of the semiconductor layer 21. By increasing the width of the conductive layer 23 in this way, the wiring resistance of the conductive layer 23 can be reduced.

[0188] Figure 8C and Fig.8D The transistor 10i shown is a modified example of the transistor 10b described above, in which the conductive layer 23 also has a wiring function. Fig.9A and Fig. 9B The transistor 10j shown is a modified example of the transistor 10e described above. Fig. 9C and Fig.9D The transistor 10k shown is a modified example of the above-mentioned transistor 10f.

[0189] The above is the description of the modified examples.

[0190] [Manufacturing method example]

[0191] Next, a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described. Here, an example of a method for manufacturing the transistor 10 will be described.

[0192] FIG. 10A to FIG. 13B 1 is a schematic cross-sectional view of each step of the method for manufacturing a semiconductor device shown below. Figure 2B and Figure 2C cross section.

[0193] Hereinafter, an insulating material for forming an insulating layer, a conductive material for forming a conductive layer, or a semiconductor material for forming a semiconductor layer can be appropriately deposited by sputtering, CVD, MBE, PLD, ALD, or the like.

[0194] In addition, as a sputtering method, there can be cited an RF sputtering method using a high frequency power supply for a sputtering power supply, a DC sputtering method using a direct current power supply, and a pulsed DC sputtering method in which the voltage applied to an electrode is changed in a pulsed manner. The RF sputtering method is mainly used when depositing an insulating film, and the DC sputtering method is mainly used when depositing a metal conductive film. In addition, the pulsed DC sputtering method is mainly used when depositing compounds such as oxides, nitrides, and carbides using a reactive sputtering method.

[0195] Note that the CVD method can be divided into a plasma CVD (PECVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, etc. Furthermore, it can be divided into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method according to the source gas used.

[0196] By using the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since the thermal CVD method does not use plasma, the plasma damage to the object to be processed can be reduced. In addition, in the thermal CVD method, no plasma damage is generated during deposition, so a film with fewer defects can be obtained.

[0197] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method using a reactant excited by plasma, or the like is used.

[0198] The CVD method and the ALD method are different from the sputtering method. The CVD method and the ALD method are deposition methods that have good step coverage and are not easily affected by the shape of the object to be processed. In particular, the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of an opening with a high aspect ratio. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferably used in combination with other deposition methods such as the CVD method with a fast deposition rate.

[0199] In addition, when the CVD method is used, a film of any composition can be deposited according to the flow ratio of the source gas. For example, when the CVD method is used, a film whose composition continuously changes can be deposited by changing the flow ratio of the source gas while performing deposition. When deposition is performed while changing the flow ratio of the source gas, since the time required for conveying or adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of the semiconductor device can sometimes be improved.

[0200] When using the ALD method, a film of any composition can be deposited by introducing multiple different precursors at the same time. Alternatively, when introducing multiple different precursors, a film of any composition can be deposited by controlling the number of cycles of each precursor. In addition, as with the CVD method, a film with a continuously changing composition can be deposited.

[0201] First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate. As the insulating layer 11, an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used. The insulating layer 11 can be deposited by sputtering, CVD, MBE, PLD, ALD, etc. When the surface on which the insulating layer 11 is formed is not flat, it is preferred to perform a flattening treatment after depositing the insulating layer 11 so that the top surface of the insulating layer 11 becomes flat.

[0202] Next, a conductive film to be the conductive layer 31 is formed on the insulating layer 11. Next, a resist mask is formed on the conductive film by photolithography or the like, and portions of the conductive film not covered by the resist mask are removed by etching, and then the resist mask is removed. Thus, the conductive layer 31 can be formed. Next, by depositing an insulating film to be the insulating layer 44 and removing portions overlapping with the conductive layer 31, the insulating layer 44 and the conductive layer 31 embedded in the insulating layer 44 ( Fig. 10A The insulating film to be the insulating layer 44 is preferably processed by a CMP (Chemical Mechanical Polishing) method. For example, the insulating film is processed until the top surface of the conductive layer 31 is exposed. Fig. 10A Insulation layer 44 is shown.

[0203] Alternatively, an insulating film that will become the insulating layer 44 may be first formed, an opening may be formed in the insulating film, a conductive film may be formed to fill the opening, and a polishing process (flattening process) may be performed using a CMP method until the top surface of the insulating film is exposed, thereby forming the insulating layer 44 and the conductive layer 31.

[0204] By performing a planarization process in such a manner that the height of the top surface of the insulating layer 44 is consistent with that of the conductive layer 31, the top surface of the insulating layer 41 to be formed later can be made flat. Note that the insulating layer 41 may be provided to cover the conductive layer 31 without providing the insulating layer 44, in which case it is preferred to perform a planarization process using a CMP method to planarize the top surface of the insulating layer 41.

[0205] Next, insulating layers 41a, 41b, and 41c (hereinafter sometimes collectively referred to as insulating layers 41) are formed on the conductive layer 31 and the insulating layer 44. Fig. 10B ). The insulating layer 41a, the insulating layer 41b, and the insulating layer 41c may be formed by sputtering, CVD, MBE, PLD, ALD, or the like as appropriate.

[0206] Here, since the thickness of the insulating layer 41 affects the channel length of the transistor, it is important that the thickness of the insulating layer 41 does not vary.

[0207] By depositing the insulating layer 41b by sputtering in an oxygen-containing atmosphere, the insulating layer 41b containing a large amount of oxygen can be formed. In addition, by using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulating layer 41b can be reduced. In this way, by depositing the insulating layer 41b, oxygen is supplied from the insulating layer 41b to the channel formation region of the semiconductor layer 21, thereby reducing oxygen vacancies.

[0208] Next, a conductive layer 32 and an insulating layer 45 are formed on the insulating layer 41 ( Fig. 10C ). The conductive layer 32 and the insulating layer 45 can be formed by the same method as the conductive layer 31 and the insulating layer 44 described above.

[0209] Next, an opening 20a ( 20b ) reaching the conductive layer 31 is formed in the conductive layer 32 and the insulating layer 41. Fig. 10D ).

[0210] The side wall of the opening 20a is preferably perpendicular to the top surface of the conductive layer 31. By adopting this structure, a transistor with a small footprint can be manufactured. Alternatively, the side wall of the opening 20a may also have a tapered shape. By having a tapered shape, the coverage of the film formed inside the opening 20a can be improved.

[0211] The maximum width of the opening 20a (the maximum diameter of the opening 20a when the opening 20a is circular when viewed from a plane) is preferably as fine as possible. For example, the maximum width of the opening 20a is preferably less than 1 μm, less than 500 nm, less than 300 nm, less than 150 nm, less than 100 nm, less than 60 nm, less than 50 nm, less than 40 nm, less than 30 nm, or less than 20 nm, and is greater than 5 nm. In particular, in order to perform microfabrication on the opening 20a, it is preferred to use a lithography technique using short-wavelength light such as EUV light or an electron beam.

[0212] Since the aspect ratio of the opening 20a is large, it is preferably formed by anisotropic etching. Since processing using a dry etching method is suitable for micro-processing, it is particularly preferred. In addition, the etching conditions of the processing may be different in each of the conductive layer 32, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a. In addition, the angle of the side wall of the opening 20a may be different in each of the conductive layer 32, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a.

[0213] When etching the insulating layer 41, a portion of the upper portion of the conductive layer 31 may be etched, and the thickness of the conductive layer 31 at the bottom of the opening 20a may be reduced. Alternatively, after forming the opening 20a, a portion of the upper portion of the conductive layer 31 may be etched to reduce the thickness of the conductive layer 31.

[0214] Next, heat treatment may also be performed. The heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. In addition, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas or in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of the oxygen gas may be set to about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in order to compensate for the oxygen that has been released, the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. By performing the above-mentioned heat treatment, impurities such as water and hydrogen contained in the insulating layer 41 or the like may be reduced before depositing the oxide semiconductor film that will become the semiconductor layer.

[0215] In addition, the gas used in the above-mentioned heat treatment is preferably highly purified. For example, the amount of water contained in the gas used in the above-mentioned heat treatment may be 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas for heat treatment, it is possible to prevent moisture and the like from being absorbed by the insulating layer 41 and the like as much as possible.

[0216] Next, a semiconductor film to be the semiconductor layer 21 is formed so as to cover the insulating layer 41, the conductive layer 31, the conductive layer 32, the opening 20a, the insulating layer 45, etc., and unnecessary portions are removed by etching to form the semiconductor layer 21 ( Fig.11A ).

[0217] An oxide semiconductor film can be used as the semiconductor film. The oxide semiconductor film can be appropriately deposited by sputtering, CVD, MBE, PLD, ALD, etc. Here, the oxide semiconductor film is preferably formed in a manner that contacts the bottom and side walls of the opening 20a with a high aspect ratio. Therefore, when depositing the oxide semiconductor film, it is preferred to use a deposition method with good coverage, and more preferably a CVD method or an ALD method. For example, In-Ga-Zn oxide can be deposited as the oxide semiconductor film by the ALD method. In addition, when the opening 20a has a conical shape, the oxide semiconductor film can be deposited by sputtering.

[0218] In addition, it is preferred that microwave treatment is performed in an oxygen-containing atmosphere during or after the oxide semiconductor film is deposited to reduce the concentration of impurities in the oxide semiconductor film. As impurities, hydrogen and carbon can be cited in particular. In addition, by performing microwave treatment, the crystallinity of the oxide semiconductor film can sometimes be improved. Here, microwave treatment refers to, for example, treatment using a device including a power supply that generates high-density plasma using microwaves.

[0219] By performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be plasmatized using microwaves or high frequencies such as RF to allow the oxygen plasma to act. In addition, as oxygen acting on the oxide semiconductor, there are various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen free radicals (also known as atoms, molecules, or ions with unpaired electrons, also known as O free radicals). In addition, the oxygen acting on the oxide semiconductor can be one or more of the above forms, and oxygen free radicals are particularly preferred.

[0220] In addition, heating the substrate during the microwave treatment in the oxygen-containing atmosphere is preferred because the impurity concentration in the oxide semiconductor film can be further reduced. The substrate may be heated at a temperature of 100° C. to 650° C., preferably 200° C. to 600° C., and more preferably 300° C. to 450° C.

[0221] By heating the substrate during the microwave treatment in the oxygen-containing atmosphere as described above, the carbon concentration in the oxide semiconductor film measured by SIMS can be reduced to less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3, and more preferably less than 1×10 18 atoms / cm 3 .

[0222] Note that the above shows a structure in which the oxide semiconductor film is subjected to microwave treatment in an oxygen-containing atmosphere, but the present invention is not limited to this. For example, the microwave treatment may be performed on an insulating film located near the oxide semiconductor film in an oxygen-containing atmosphere, and more specifically, the microwave treatment may be performed on a silicon oxide film. In this way, the hydrogen contained in the silicon oxide film can be used as H 2 O is released to the outside. By releasing hydrogen from the silicon oxide film located near the oxide semiconductor film, a highly reliable semiconductor device can be provided.

[0223] In addition, when the semiconductor layer 21 has a stacked structure, the deposition methods of each layer may be the same or different. For example, when the semiconductor layer 21 has a two-layer stacked structure, the lower oxide semiconductor film may be deposited by sputtering and the upper oxide semiconductor film may be deposited by ALD. The oxide semiconductor film deposited by sputtering may easily have crystallinity. Thus, by providing a crystalline oxide semiconductor film as the lower oxide semiconductor film, the crystallinity of the upper oxide semiconductor film may be improved. In addition, even if pinholes or breaks are formed in the lower oxide semiconductor film deposited by sputtering, the portion overlapping with the pinholes or breaks may be blocked by the upper oxide semiconductor film deposited by ALD with good coverage.

[0224] Here, the oxide semiconductor film is preferably formed in contact with the top surface of the conductive layer 31 in the opening 20 a , the side surfaces of the insulating layer 41 in the opening 20 a , and the side surfaces and top surface of the conductive layer 32 on the insulating layer 41 .

[0225] After the oxide semiconductor film is formed, heat treatment is preferably performed. The heat treatment can be performed within a temperature range in which the oxide semiconductor film does not undergo polycrystallization, and can be performed at a temperature above 250°C and below 650°C, preferably above 400°C and below 600°C. In addition, the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas or in an atmosphere containing an oxidizing gas of more than 10 ppm, more than 1%, or more than 10%. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of the oxygen gas can be set to about 20%. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen gas or an inert gas atmosphere, and then in order to compensate for the detached oxygen, the heat treatment is performed in an atmosphere containing an oxidizing gas of more than 10 ppm, more than 1%, or more than 10%.

[0226] In addition, the gas used in the above-mentioned heat treatment is preferably highly purified. For example, the amount of water contained in the gas used in the above-mentioned heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas for heat treatment, it is possible to prevent moisture and the like from being absorbed by the above-mentioned oxide semiconductor film and the like as much as possible.

[0227] Here, the heat treatment is preferably performed while the semiconductor film is in contact with the insulating layer 41b containing a large amount of oxygen. This allows oxygen to be supplied from the insulating layer 41b to the channel formation region of the semiconductor film, thereby reducing oxygen vacancies.

[0228] Note that although the heat treatment is performed after the oxide semiconductor film is deposited, the present invention is not limited to this and the heat treatment may be performed in a later step.

[0229] Next, the insulating layer 22 ( Fig. 11B The insulating layer 22 can be appropriately deposited by sputtering, CVD, MBE, PLD, ALD, or the like.

[0230] It is preferable to provide the insulating layer 22 with a thickness as uniform as possible on the side of the semiconductor layer 21 in the opening 20a. Therefore, it is particularly preferable to form the insulating layer 22 using the ALD method, which is a deposition method with extremely excellent coverage. When the side wall of the opening 20a has a tapered shape, the insulating layer 22 can be formed using a deposition method such as a sputtering method.

[0231] Next, a dummy layer 35 is formed on the insulating layer 22 at a position overlapping the opening 20a. Fig. 11C ).

[0232] The dummy layer 35 is formed at a position where the conductive layer 23 is to be set later. Therefore, a portion of the dummy layer 35 is provided in a manner embedded in the opening 20a. In addition, the upper portion of the dummy layer 35 protrudes upward compared to the top surface of the portion of the insulating layer 22 that overlaps the conductive layer 32 and the semiconductor layer 21. The higher the height of the protruding portion, the greater the thickness of the insulating layer 42 to be formed later can be, so it is preferred.

[0233] The dummy layer 35 is removed in a later process, so it is preferable to use a material with a high etching selectivity ratio with respect to the film (insulating layer 22, insulating layer 42, etc.) in contact with the dummy layer 35. For example, a film having a composition different from that of the insulating layer 22 and the insulating layer 42 can be used for the dummy layer 35. More specifically, a film containing constituent elements different from those of the insulating layer 22 and the insulating layer 42, a film containing constituent elements the same as those of the insulating layer 22 and the insulating layer 42 and having a composition different from them, a film having a density different from that of the insulating layer 22 and the insulating layer 42, etc. can be used for the dummy layer 35. In addition, a film containing constituent elements different from those of the dummy layer 35 can be used for one or both of the insulating layer 22 and the insulating layer 42.

[0234] In particular, the dummy layer 35 is preferably deposited using a deposition method or condition that causes as little deposition damage to the insulating layer 22 as possible. When depositing using a sputtering method or a CVD method, it is preferably deposited under conditions that cause as little damage to the formed surface as possible by reducing the power supply voltage. In addition, deposition methods such as vacuum evaporation, ALD, or a wet method cause very little damage to the formed surface, and are therefore suitable for the formation of the dummy layer 35. Examples of wet methods that can be used to form the dummy layer 35 include spin coating, dipping, spraying, inkjet, dispenser, screen printing, offset printing, blade, slit coating, roller coating, curtain coating, and blade coating.

[0235] In addition, it is preferable to use a material that can be removed by wet etching for the dummy layer 35. This can significantly reduce damage to the insulating layer 22 when etching the dummy layer 35, compared with the case of using dry etching.

[0236] As the dummy layer 35, various materials can be used as long as they are films having a composition different from that of the insulating layer 22 and the insulating layer 47. For example, semiconductor films such as silicon and germanium, inorganic insulating films such as silicon nitride, silicon oxynitride, aluminum oxide, and aluminum nitride, metal films such as aluminum, copper, molybdenum, and tungsten, and oxide conductor films such as indium oxide and zinc oxide can be cited.

[0237] In addition, an organic film of acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimide amide resin, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors of these resins may be used as the dummy layer 35. The above-mentioned organic insulating film can be formed by a deposition method (such as a wet method or a vacuum evaporation method) that causes little deposition damage to the formed surface, and has a high degree of freedom in selecting a chemical solution (etchant) that can be used in wet etching, so it is preferred.

[0238] The dummy layer 35 can also be reduced in size (also referred to as shrinking) by performing isotropic etching after forming the dummy layer 35. Thus, the dummy layer 35 can be miniaturized even with a material that is difficult to form a fine pattern with photolithography.

[0239] Next, an insulating layer 42 is formed so as to cover the insulating layer 22 and the dummy layer 35 ( Fig. 12A The insulating layer 42 can be formed by the same method as the insulating layer 41 b and the like. At this time, the top surface of the insulating layer 42 is formed with depressions and projections reflecting the shape of the dummy layer 35 .

[0240] Next, the insulating layer 42 is polished (planarized) by CMP to expose the top surface of the dummy layer 35 ( Fig. 12B ). At the same time, the top surface of the insulating layer 42 can be planarized.

[0241] Next, the dummy layer 35 is removed by etching ( Fig.13A As described above, the dummy layer 35 is preferably etched by a method having a high etching selectivity with respect to the insulating layer 22 and the insulating layer 42. In particular, it is preferable to remove the dummy layer 35 by wet etching. At this time, it is important to perform etching by using an etchant and etching conditions having a high etching selectivity with respect to the insulating layer 22 and the insulating layer 42.

[0242] For example, when an organic film is used as the dummy layer 35 , etching damage to the insulating layer 22 can be reduced as much as possible by utilizing a wet etching method using an organic solvent as an etchant.

[0243] Alternatively, when an organic substance is used as the dummy layer 35 , the dummy layer 35 may be etched by plasma treatment (also referred to as ashing) in an oxygen-containing atmosphere.

[0244] By removing the dummy layer 35 , an opening 20 b may be formed in the insulating layer 42 .

[0245] After removing the dummy layer 35, a heat treatment may be performed. In particular, when wet etching is used to etch the dummy layer 35, heat treatment is preferred because it can remove water adsorbed on the surfaces of the insulating layer 42 and the insulating layer 22. The heat treatment method can refer to the above description.

[0246] Next, a conductive film that will later become the conductive layer 23 is formed on the insulating layer 42. A portion of the conductive film is embedded in the opening 20a and the opening 20b. The conductive film is preferably deposited by a deposition method with high coverage or embedding properties, for example, more preferably by a CVD method or an ALD method. In addition, when the side walls of the openings 20a and the openings 20b have a tapered shape, the conductive film can be deposited by a sputtering method.

[0247] Next, the upper portion of the conductive film is etched by a CMP method or a dry etching method until the top surface of the insulating layer 42 is exposed, thereby forming a conductive layer 23 ( Fig. 13B ).

[0248] Finally, the conductive layer 33 and the insulating layer 46 are formed on the insulating layer 42 and the conductive layer 23. The conductive layer 33 and the insulating layer 46 can be formed by the same method as that of the conductive layer 31 and the insulating layer 44.

[0249] Through the above steps, the transistor 10 can be manufactured.

[0250] By using a manufacturing method in one embodiment of the present invention, damage to the gate insulating layer can be reduced, thereby realizing a semiconductor device with high reliability. In addition, a thicker interlayer insulating layer can be formed between the gate wiring and one of the source wiring and the drain wiring, thereby reducing parasitic capacitance and realizing a transistor suitable for a circuit that requires high-speed operation.

[0251] The above is the description of the example of the production method.

[0252] [Application Examples]

[0253] The structure of a memory device using transistors and capacitors will be described below.

[0254] Fig.14A 1 is a circuit diagram of a memory cell 30. The memory cell 30 is composed of a transistor Tr1 and a capacitor C, which can also be referred to as 1Tr1C. The gate of the transistor Tr1 is connected to the wiring WL, one of the source and the drain is connected to the wiring BL, and the other is connected to one electrode of the capacitor C. The other electrode of the capacitor C is connected to the wiring PL.

[0255] The memory cell 30 can store data by holding the data potential input from the wiring BL through the transistor Tr1 in the capacitor C. In addition, the data can be held by making the transistor Tr1 non-conductive. In addition, the data can be read by outputting the potential corresponding to the held data to the wiring BL by making the transistor Tr1 conductive. The wiring WL is supplied with a signal for controlling the conduction and non-conduction of the transistor Tr1. In addition, the wiring PL is supplied with a predetermined potential (e.g., a fixed potential).

[0256] Fig. 14B and Fig. 14C is a cross-sectional view of the memory cell 30 . Fig. 14B is a cross-sectional view along the extension direction of the conductive layer 32, Fig. 14C It is a cross-sectional view along the extending direction of the conductive layer 31 and the conductive layer 33. The memory cell 30 has a structure in which the transistor 10 is stacked on the capacitor 50. The transistor 10 and the capacitor 50 correspond to the transistor Tr1 and the capacitor C, respectively.

[0257] The structure of the transistor 10 can refer to the above description, and the description thereof will be omitted. Here, an example of using the transistor 10 is shown, but the present invention is not limited to the transistor 10 and can be replaced with various transistors described above.

[0258] The capacitor 50 includes a conductive layer 51, a conductive layer 52, and an insulating layer 53 interposed therebetween. The capacitor 50 constitutes a so-called MIM (Metal-Insulator-Metal) capacitor.

[0259] The capacitor 50 is provided on the insulating layer 11. The conductive layer 34 and the insulating layer 47 on the conductive layer 34 are provided on the insulating layer 11. The insulating layer 47 is provided with an opening 20c that reaches the conductive layer 34. The conductive layer 51 is provided inside the opening 20c in a manner in contact with the side surface of the insulating layer 47 and the top surface of the conductive layer 34. In addition, the insulating layer 53 is provided in a manner covering the insulating layer 47 and the conductive layer 51. The insulating layer 48 is provided on the insulating layer 53, and the insulating layer 48 is provided with an opening 20d that overlaps with the opening 20c. The conductive layer 52 is provided in a manner embedded in the opening 20d and the opening 20c.

[0260] The top surfaces of the conductive layer 52 and the insulating layer 48 are flattened and have substantially the same height. The insulating layer 44 and the conductive layer 31 are provided on the conductive layer 52 and the insulating layer 48. The conductive layer 31 is provided in contact with the top surface of the conductive layer 52.

[0261] exist Fig. 14B and Fig. 14C , the conductive layer 32 corresponds to the wiring BL, the conductive layer 33 corresponds to the wiring WL, and the conductive layer 34 corresponds to the above-mentioned wiring PL.

[0262] A low-resistance conductive material can be used as the conductive layer 34, the conductive layer 51, and the conductive layer 52. For example, the material that can be used for the conductive layer 23 described above can be used.

[0263] The insulating layer 53 is used as a dielectric layer of the capacitor 50. The thinner the thickness of the insulating layer 53 is and the higher the relative dielectric constant is, the greater the capacitance of the capacitor 50 can be. For example, the high-k material that can be used for the insulating layer 22 described above is preferably used.

[0264] Fig.15A and Fig. 15B An example of a memory device in which two memory cells 30 are connected to the same wiring is shown. Fig.15A is a schematic top view of a storage device, Fig. 15B is along Fig.15A Schematic cross-sectional view of the cutoff line A3-A4 in FIG.

[0265] The conductive layer 33 serving as the wiring WL is provided in each of the two memory cells 30. The conductive layer 32 serving as the wiring BL is provided in a manner shared by the two memory cells 30.

[0266] In addition, the conductive layer 32 used as the wiring BL is embedded in each interlayer insulating layer and is electrically connected to the conductive layer 61 used as a plug (also called a connection electrode) and the conductive layer 62. The conductive layer 61 can also be electrically connected to a sense amplifier (not shown) provided below the insulating layer 11. In addition, the conductive layer 61 can also be electrically connected to the conductive layer 32 of the memory cell stacked above the insulating layer 65.

[0267] The insulating layer 65 is used as a barrier layer, and has a function of preventing impurities such as water and hydrogen from diffusing into the storage device from the outside.

[0268] In addition, by arranging the memory cells 30 in a three-dimensional matrix, a memory cell array can be formed. As an example of a memory cell array, Fig.16A and Fig. 16B An example of a storage device is shown in which 4×2×4 storage cells 30 are arranged in the X direction, the Y direction, and the Z direction. Fig.16A is a plan view of the storage device, Fig. 16B It is along Fig.16A A cross-sectional view along the cut-off line A3-A4 in FIG.

[0269] A group of four memory cells 30 may be referred to as a memory unit 60 . Fig.16A and Fig. 16B Eight storage units (storage unit 60 [1, 1] to storage unit 60 [2, 4]) are shown. In storage unit 60 [a, b] (a, b are each a positive integer), a represents an address in the Y direction, and b represents an address in the Z direction.

[0270] The storage unit 60 is centered on the conductive layer 61 or the conductive layer 62, and each two storage units 30 are arranged at symmetrical positions. The conductive layers 32 of each storage unit 60 stacked in the Z direction are electrically connected to each other through the conductive layer 62. In this way, by stacking a plurality of storage units 60, the storage capacity per unit area can be increased, and a storage device that can be miniaturized or highly integrated can be provided.

[0271] Fig.17A and Fig. 17B An example is shown in which the connection portion is arranged at the end of the storage unit. Fig.17A is a plan view of the storage device, Fig. 17B2 is a cross-sectional view. Here, as an example of a memory cell array, an example of a memory device configured with 3×3×m (m is an integer greater than or equal to 2) memory cells 30 is shown. Among the layers including the memory cells 30, the first layer is represented as layer 70[1], and the mth layer (uppermost layer) is represented as layer 70[m].

[0272] Conductive layer 63 is provided outside the memory cell. Conductive layer 63 may also be connected to wiring in a layer above layer 70 including conductive layer 63. For example, conductive layer 63 provided in layer 70[1] is electrically connected to wiring provided in layer 70[2]. In addition, without limitation thereto, conductive layer 63 may also be electrically connected to wiring in layer 70 below layer 70 including conductive layer 63.

[0273] Fig.18 An example of a cross-sectional structure of a memory device is shown in which a layer including the memory cell 30 is stacked on a layer provided with a driver circuit including a sense amplifier.

[0274] Fig.18 An example is shown in which a capacitor 50 is stacked above a transistor 90 and a transistor 10 thereon. The transistor 90 is one of the transistors in the sense amplifier.

[0275] By providing the sense amplifier so as to overlap with the memory cell 30, the bit line can be shortened. Thus, the load on the bit line can be reduced, and the read sensitivity of the sense amplifier can be improved. Therefore, the storage capacitance of the memory cell can be reduced.

[0276] The transistor 90 is provided on a substrate 91 and includes a conductive layer 94 used as a gate, an insulating layer 93 used as a gate insulating layer, a semiconductor region 92 formed by a portion of the substrate 91, and a low resistance region 95a and a low resistance region 95b used as a source region or a drain region. The transistor 90 may be a p-channel type or an n-channel type.

[0277] Here, in Fig.18 In the transistor 90 shown, a semiconductor region 92 (a part of a substrate 91) forming a channel has a convex shape. In addition, a conductive layer 94 is provided so as to cover the side and top surfaces of the semiconductor region 92 via an insulating layer 93. Since the convex portion of the semiconductor substrate is used, this transistor 90 is also called a FIN type transistor.

[0278] It is preferable that a structure in which interlayer insulating layers and wiring layers are alternately stacked (also referred to as a multilayer wiring layer) is provided between a layer in which the transistor 90 is provided and a layer in which the memory cell 30 is provided. Fig.18 An example is shown in which the low resistance region 95 b of the transistor 90 is electrically connected to the conductive layer 32 serving as the bit line of the memory cell 30 through a wiring and a plug.

[0279] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0280] (Implementation Method 2)

[0281] In this embodiment, refer to Figures 19 to 22 A memory device according to one embodiment of the present invention will be described. In this embodiment, a memory device configuration example in which a layer including memory cells is stacked on a layer including a driver circuit including a sense amplifier will be described.

[0282] <Configuration Example of Storage Device>

[0283] Fig.19 4 is a block diagram showing a configuration example of a storage device 480 according to one embodiment of the present invention. Fig.19 The illustrated memory device 480 includes a layer 420 and a stacked layer 470 .

[0284] Layer 420 is a layer including Si transistors. In layer 470, element layers 430[1] to 430[m] (m is an integer greater than or equal to 2) are stacked. Element layers 430[1] to 430[m] are layers including OS transistors. Layer 470 in which layers including OS transistors are stacked can be stacked on layer 420.

[0285] Elements such as OS transistors and capacitors included in the element layers 430 [ 1 ] to 430 [ m ] constitute memory cells. Fig.19 An example is shown in which the element layers 430 [ 1 ] to 430 [ m ] include a plurality of memory cells 432 arranged in a matrix of m rows and n columns (n ​​is an integer greater than or equal to 2).

[0286] exist Fig.19 , the 1st row and 1st column storage unit 432 is represented as storage unit 432[1, 1], and the mth row and nth column storage unit 432 is represented as storage unit 432[m, n]. In addition, in the present embodiment, etc., sometimes "row i" is used to represent an arbitrary row. In addition, sometimes "column j" is used to represent an arbitrary column. Therefore, i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n. In addition, in the present embodiment, etc., the i-th row and j-th column storage unit 432 is represented as storage unit 432[i, j]. Note that in the present embodiment, etc., when represented as "i+α" (α is a positive integer or a negative integer), "i+α" is not less than 1 and not greater than m. Similarly, when represented as "j+α", "j+α" is not less than 1 and not greater than n.

[0287] Furthermore, as an example, Fig.19m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction are shown. In the present embodiment and the like, the first (1st row) wiring WL is represented as wiring WL[1], and the mth (mth row) wiring WL is represented as wiring WL[m]. Similarly, the first (1st row) wiring PL is represented as wiring PL[1], and the mth (mth row) wiring PL is represented as wiring PL[m]. Similarly, the first (1st column) wiring BL is represented as wiring BL[1], and the nth (nth column) wiring BL is represented as wiring BL[n]. Note that the number of layers of the element layers 430[1] to 430[m] and the number of wirings WL (and wirings PL) may be different.

[0288] The plurality of memory cells 432 arranged in the i-th row are electrically connected to the i-th row wiring WL (wiring WL[i]) and the i-th row wiring PL (wiring PL[i]). The plurality of memory cells 432 arranged in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).

[0289] Wiring BL is used as a bit line for writing and reading data. Wiring WL is used as a word line for controlling the on or off (conductive state or non-conductive state) of an access transistor used as a switch. Wiring PL is used as a constant potential line connected to a capacitor. In addition, wiring for transmitting a back gate potential may be provided separately.

[0290] The memory cells 432 included in the element layers 430[1] to 430[m] are connected to the sense amplifier 446 (sense amplifier) ​​through the wiring BL. The wiring BL can be arranged in a direction parallel to or perpendicular to the substrate surface on which the layer 420 is provided. By forming the wiring BL extending from the memory cells 432 included in the element layers 430[1] to 430[m] by wiring arranged in a direction parallel to the substrate surface and wiring arranged in a direction perpendicular to the substrate surface, the wiring length between the element layer 430 and the sense amplifier 446 can be shortened. Since the signal transmission distance between the memory cell and the sense amplifier can be shortened and the resistance and parasitic capacitance of the bit line can be greatly reduced, the power consumption and signal delay can be reduced. Thus, the power consumption and signal delay of the memory device 480 can be reduced. In addition, the memory device 480 can work even if the capacitance of the capacitor included in the memory cell 432 is reduced. Thus, the memory device 480 can be miniaturized.

[0291] The layer 420 includes a PSW 471 (power switch), a PSW 472, and a peripheral circuit 422. The peripheral circuit 422 includes a drive circuit 440, a control circuit 473 (Control Circuit), and a voltage generation circuit 474. Note that each circuit included in the layer 420 is a circuit including Si transistors.

[0292] In the storage device 480, each circuit, each signal and each voltage can be appropriately selected as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1 and PON2 are signals input from the outside, and signal RDA is a signal output to the outside. Signal CLK is a clock signal.

[0293] In addition, the signal BW, the signal CE, and the signal GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signal PON1 and the signal PON2 are power gating control signals. In addition, the signal PON1 and the signal PON2 can also be generated in the control circuit 473.

[0294] The control circuit 473 is a logic circuit that has the function of controlling the overall operation of the storage device 480. For example, the control circuit performs a logic operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (for example, writing operation, reading operation) of the storage device 480. Alternatively, the control circuit 473 generates a control signal for the driving circuit 440 to execute the above operation mode.

[0295] The voltage generating circuit 474 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 474. For example, when the signal WAKE is applied with an H level signal, the signal CLK is input to the voltage generating circuit 474, and the voltage generating circuit 474 generates a negative voltage.

[0296] The driving circuit 440 is a circuit for writing and reading data to the memory cell 432. The driving circuit 440 includes the above-mentioned sense amplifier 446 in addition to the row decoder 442, the column decoder 444, the row driver 443, the column driver 445, the input circuit 447, and the output circuit 448.

[0297] The row decoder 442 and the column decoder 444 have the function of decoding the signal ADDR. The row decoder 442 is a circuit for specifying a row to be accessed, and the column decoder 444 is a circuit for specifying a column to be accessed. The row driver 443 has the function of selecting the wiring WL specified by the row decoder 442. The column driver 445 has the following functions: a function of writing data to the memory cell 432; a function of reading data from the memory cell 432; a function of holding the read data, etc.

[0298] The input circuit 447 has a function of holding a signal WDA. The data held in the input circuit 447 is output to the column driver 445. The output data of the input circuit 447 is the data (Din) written to the memory cell 432. The data (Dout) read out from the memory cell 432 by the column driver 445 is output to the output circuit 448. The output circuit 448 has a function of holding Dout. In addition, the output circuit 448 has a function of outputting Dout to the outside of the memory device 480. The data output from the output circuit 448 is a signal RDA.

[0299] PSW471 has a function of controlling the supply of VDD to the peripheral circuit 422. PSW472 has a function of controlling the supply of VHM to the row driver 443. Here, the high power supply voltage of the storage device 480 is VDD, and the low power supply voltage is GND (ground potential). In addition, VHM is a high power supply voltage for making the word line high, which is higher than VDD. The PSW471 is turned on and off by the signal PON1, and the PSW472 is turned on and off by the signal PON2. Fig.19 In the embodiment, the number of power domains to which VDD is supplied in the peripheral circuit 422 is one, but it may be more than one. In this case, a power switch may be provided for each power domain.

[0300] Element layers 430 [ 1 ] to 430 [ m ] may be disposed in an overlapping manner on layer 420 . Fig. 20A 4 is a perspective view of a memory device 480 showing a state in which five (m=5) element layers 430 [ 1 ] to 430 [ 5 ] are stacked on a layer 420 .

[0301] exist Fig. 20A In the embodiment, the element layer 430 disposed in the first layer is referred to as element layer 430[1], the element layer 430 disposed in the second layer is referred to as element layer 430[2], and the element layer 430 disposed in the fifth layer is referred to as element layer 430[5]. Fig. 20AThe wiring WL and the wiring PL extending in the X direction and the wiring BL and the wiring BLB extending in the Y direction and the Z direction (directions perpendicular to the substrate surface on which the driver circuit is provided) are shown. The wiring BLB is an inversion bit line. Note that in order to make the drawings easier to understand, a part of the wiring WL and the wiring PL included in each of the element layers 430 is omitted.

[0302] Fig. 20B Yes Description Fig. 20A The schematic diagram of the structural example of the memory cell 432 included in the sense amplifier 446 connected to the wiring BL and the wiring BLB and the element layers 430[1] to 430[5] connected to the wiring BL and the wiring BLB is shown. In addition, the structure in which multiple memory cells (memory cells 432) are electrically connected to one wiring BL and the wiring BLB is also called a "memory string".

[0303] Fig. 20B An example of a circuit structure of a memory cell 432 connected to a wiring BLB is shown. The memory cell 432 includes a transistor 437 and a capacitor 438. With respect to the transistor 437, the capacitor 438, and each wiring (BL, WL, etc.), for example, the wiring BL[1] and the wiring WL[1] are sometimes referred to as the wiring BL and the wiring WL, etc. As the memory cell 432, for example, the memory cell 30 shown in the above embodiment can be used. That is, the transistor 10 can be used as the transistor 437, and the capacitor 50 can be used as the capacitor 438. In addition, as the transistor included in the sense amplifier 446, a transistor 90 (see Fig.18 ).

[0304] In the memory cell 432, one of the source and the drain of the transistor 437 is connected to the wiring BL. The other of the source and the drain of the transistor 437 is connected to one electrode of the capacitor 438. The other electrode of the capacitor 438 is connected to the wiring PL. The gate of the transistor 437 is connected to the wiring WL.

[0305] The wiring PL is a wiring that supplies a constant potential for maintaining the potential of the capacitor 438. By connecting a plurality of wirings PL to use as one wiring, the number of wirings can be reduced.

[0306] In one embodiment of the present invention, while stacking OS transistors, wiring used as bit lines is arranged in a direction perpendicular to the surface of the substrate on which the layer 420 is provided. Furthermore, the transistor 437 and the capacitor 438 included in the memory cell 432 are arranged in a direction perpendicular to the surface of the substrate on which the layer 420 is provided. By arranging each element and each wiring in a direction perpendicular to the surface of the substrate, the wiring length between element layers can be shortened, and the density of elements arranged per unit area can be increased. Thus, a memory device excellent in reducing storage capacity and power consumption can be realized.

[0307] [Configuration Example of Memory Cell 432 and Sense Amplifier 446]

[0308] Fig.21A and Fig.21B 4 is a circuit diagram corresponding to the above-mentioned storage unit 432 and a circuit block diagram corresponding to the circuit diagram. Fig.21A and Fig.21B As shown, sometimes the storage unit 432 is represented as a block in the drawings and the like. Fig.21A and Fig.21B The same expression can be applied even when the wiring BL shown is replaced with the wiring BLB.

[0309] also, Fig. 21C and Fig.21D 1 is a circuit diagram corresponding to the sense amplifier 446 and a circuit block diagram corresponding to the circuit diagram. The sense amplifier 446 shows a switch circuit 482, a precharge circuit 483, a precharge circuit 484, and an amplifier circuit 485. In addition to the wiring BL and the wiring BLB, the wiring SA_OUT and the wiring SA_OUTB for outputting the read signal are also shown.

[0310] like Fig. 21C As shown, the switch circuit 482 includes, for example, n-channel transistors 482_1 and 482_2. The transistors 482_1 and 482_2 switch the conduction state of the wiring pair of wiring SA_OUT and wiring SA_OUTB and the wiring pair of wiring BL and wiring BLB according to the signal CSEL.

[0311] like Fig. 21C As shown, the precharge circuit 483 is composed of n-channel transistors 483_1 to 483_3. The precharge circuit 483 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to the potential VDD / 2 in accordance with the signal EQ.

[0312] like Fig. 21CAs shown, the precharge circuit 484 is composed of p-channel transistors 484_1 to 484_3. The precharge circuit 484 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to the potential VDD / 2 in accordance with the signal EQB.

[0313] like Fig. 21C As shown, the amplifier circuit 485 is composed of p-channel transistors 485_1 and 485_2 and n-channel transistors 485_3 and 485_4 connected to wiring SAP or wiring SAN. Wiring SAP or wiring SAN is a wiring having a function of supplying VDD or VSS. Transistors 485_1 to 485_4 are transistors constituting an inverter loop.

[0314] also, Fig.21D is corresponding to Fig. 21C The circuit block diagram of the sense amplifier 446 described in FIG. Fig.21D As shown, the sense amplifier 446 is sometimes represented as a block in drawings, etc.

[0315] Fig. 22 yes Fig.19 A circuit diagram of the storage device 480 is shown. Fig. 22 Use in FIG. 21A to FIG. 21D The circuit blocks described in .

[0316] like Fig. 22 As shown, layer 470 having element layer 430[m] includes memory cell 432. As an example, Fig. 22 The memory cell 432 shown is connected to a pair of wiring BL[1] and wiring BLB[1] or wiring BL[2] and wiring BLB[2]. The memory cell 432 connected to the wiring BL is a memory cell that performs data writing or reading.

[0317] The wiring BL[1] and the wiring BLB[1] are connected to the sense amplifier 446[1], and the wiring BL[2] and the wiring BLB[2] are connected to the sense amplifier 446[2]. The sense amplifier 446[1] and the sense amplifier 446[2] can be connected according to Fig. 21C The data is read out by using the various signals described in .

[0318] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0319] (Implementation method 3)

[0320] In this embodiment, a structural example of a display device to which a transistor of one embodiment of the present invention can be applied is described.

[0321] The transistor of one embodiment of the present invention can be formed into an extremely micronized form, so a display device using the transistor of one embodiment of the present invention can be an extremely high-definition display device. For example, the display device of one embodiment of the present invention can be used for the display portion of information terminal devices (wearable devices) such as watch-type and bracelet-type devices, and the display portion of VR devices such as head-mounted displays and glasses-type AR devices that can be worn on the head (HMD: Head Mounted Display).

[0322] [Display module]

[0323] Fig.23A 2 is a perspective view of a display module 280. The display module 280 includes a display device 200A and an FPC 290. Note that the display device included in the display module 280 is not limited to the display device 200A, and may be a display device 200B or a display device 200C which will be described later.

[0324] The display module 280 includes a substrate 291 and a substrate 292. The display module 280 includes a display portion 281. The display portion 281 is a region that displays an image.

[0325] Fig. 23B Schematic perspective view showing the structure of one side of the substrate 291. A circuit portion 282, a pixel circuit portion 283 on the circuit portion 282, and a pixel portion 284 on the pixel circuit portion 283 are stacked on the substrate 291. In addition, a terminal portion 285 for connecting to the FPC 290 is provided on a portion of the substrate 291 that does not overlap with the pixel portion 284. The terminal portion 285 and the circuit portion 282 are electrically connected via a wiring portion 286 composed of a plurality of wirings.

[0326] The pixel portion 284 includes a plurality of pixels 284 a arranged periodically. Fig. 23B An enlarged view of one pixel 284a is shown on the right side of FIG. The pixel 284a includes a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.

[0327] The pixel circuit unit 283 includes a plurality of pixel circuits 283a arranged periodically. One pixel circuit 283a controls the light emission of three light emitting devices included in one pixel 284a. One pixel circuit 283a may also include three circuits for controlling the light emission of one light emitting device. For example, the pixel circuit 283a may adopt a structure having at least one selection transistor, one current control transistor (driving transistor) and a capacitor for one light emitting device. At this time, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. Thus, an active matrix display panel can be realized.

[0328] The circuit section 282 includes a circuit for driving each pixel circuit 283a of the pixel circuit section 283. For example, it is preferable to include one or both of a gate line driving circuit and a source line driving circuit. In addition, it may also include at least one of an operation circuit, a storage circuit, and a power supply circuit. In addition, the transistor provided in the circuit section 282 may also constitute a part of the pixel circuit 283a. That is, the pixel circuit 283a may also be constituted by the transistor included in the pixel circuit section 283 and the transistor included in the circuit section 282.

[0329] The FPC 290 is used as wiring for supplying video signals, power supply potential, and the like from the outside to the circuit portion 282. Alternatively, an IC may be mounted on the FPC 290.

[0330] The display module 280 can adopt a structure in which one or both of the pixel circuit unit 283 and the circuit unit 282 are overlapped on the lower side of the pixel unit 284, so that the display unit 281 can have an extremely high aperture ratio (effective display area ratio). For example, the aperture ratio of the display unit 281 can be 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. In addition, the pixels 284a can be arranged at an extremely high density, thereby making the display unit 281 have an extremely high definition. For example, the display unit 281 preferably arranges the pixels 284a with a definition of 2000ppi or more, more preferably 3000ppi or more, more preferably 5000ppi or more, and more preferably 6000ppi or more and 20000ppi or less or 30000ppi or less.

[0331] This display module 280 is very clear, so it is suitable for use in VR devices such as head-mounted displays or glasses-type AR devices. For example, because the display module 280 has a display unit 281 with extremely high clarity, in the structure of the display unit of the display module 280 viewed through a lens, even if the user uses a lens to magnify the display unit, the pixels cannot be seen, thereby achieving a highly immersive display. In addition, the display module 280 is not limited to this, and can also be applied to electronic devices with a smaller display unit. For example, it is suitable for the display unit of wearable electronic devices such as watch-type devices.

[0332] [Display device 200A]

[0333] Fig.24 The display device 200A shown includes a substrate 331 , a light emitting element 110R, a light emitting element 110G, a light emitting element 110B, a capacitor 240 , and a transistor 320 .

[0334] Substrate 331 is equivalent to Fig.23A The substrate 291 in.

[0335] The transistor 320 is a vertical channel transistor in which an oxide semiconductor is used as a semiconductor layer forming a channel. The transistor 320 includes a semiconductor layer 321, an insulating layer 323, a conductive layer 324, a conductive layer 325, a conductive layer 326, and the like.

[0336] As the transistor 320 , any of the transistors described in Embodiment 1 can be used.

[0337] An insulating layer 332 is provided over the substrate 331. The insulating layer 332 functions as a barrier layer that prevents impurities such as water and hydrogen from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from escaping from the semiconductor layer 321 to the insulating layer 332 side. As the insulating layer 332, for example, a film into which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.

[0338] Conductive layer 327 is provided on insulating layer 332, and conductive layer 325 is provided on conductive layer 327. Insulating layer 334 is provided on conductive layer 325, and conductive layer 326 is provided on insulating layer 334. Openings are provided in insulating layer 334 and conductive layer 326, and semiconductor layer 321 is provided in the openings. Insulating layer 323 is provided to cover semiconductor layer 321 and conductive layer 326, insulating layer 264 is provided on insulating layer 323, and conductive layer 324 is provided in the openings provided in insulating layer 264. In addition, insulating layer 265 and conductive layer 328 are provided on insulating layer 264 and conductive layer 324. In addition, insulating layer 266 is provided on insulating layer 265 and conductive layer 328.

[0339] The insulating layer 264, the insulating layer 265, and the insulating layer 266 are used as interlayer insulating layers. A barrier layer for preventing impurities such as water or hydrogen in the insulating layer 266 and the like from diffusing into the transistor 320 may be provided between the insulating layer 266 and the insulating layer 265. As the barrier layer, an insulating film similar to the insulating layer 332 can be used.

[0340] The plug 274 electrically connected to one of the conductive layers 326 is embedded in the insulating layer 266, the insulating layer 265, and the insulating layer 264. Here, the plug 274 preferably includes a conductive layer 274a covering the side surfaces of the openings of the insulating layer 266, the insulating layer 265, and the insulating layer 264 and a portion of the top surface of the conductive layer 326, and a conductive layer 274b in contact with the top surface of the conductive layer 274a. At this time, as the conductive layer 274a, it is preferable to use a conductive material in which hydrogen and oxygen are not easily diffused.

[0341] In addition, a capacitor 240 is provided on the insulating layer 266. The capacitor 240 includes a conductive layer 241, a conductive layer 245, and an insulating layer 243 located therebetween. The conductive layer 241 is used as one electrode of the capacitor 240, the conductive layer 245 is used as the other electrode of the capacitor 240, and the insulating layer 243 is used as a dielectric of the capacitor 240.

[0342] Conductive layer 241 is provided on insulating layer 266 and embedded in insulating layer 254. Conductive layer 241 is electrically connected to conductive layer 326 of transistor 320 through plug 274. Insulating layer 243 is provided to cover conductive layer 241. Conductive layer 245 is provided in a region overlapping conductive layer 241 with insulating layer 243 interposed therebetween.

[0343] The cover capacitor 240 is provided with an insulating layer 255 a , an insulating layer 255 b is provided on the insulating layer 255 a , and an insulating layer 255 c is provided on the insulating layer 255 b .

[0344] Insulating layer 255a, insulating layer 255b, and insulating layer 255c may use an inorganic insulating film as appropriate. For example, it is preferable to use a silicon oxide film as insulating layer 255a and insulating layer 255c, and to use a silicon nitride film as insulating layer 255b. Thus, insulating layer 255b can be used as an etching protection film. Although an example in which a portion of insulating layer 255c is etched to form a recess is shown in this embodiment, the recess may not be provided in insulating layer 255c.

[0345] The light emitting element 110R, the light emitting element 110G, and the light emitting element 110B are provided on the insulating layer 255c. The light emitting element 110R, the light emitting element 110G, and the light emitting element 110B will be described in detail in Embodiment 4.

[0346] The light emitting element 110R includes a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light emitting element 110G includes a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light emitting element 110B includes a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are provided in the light emitting element 110R, the light emitting element 110G, and the light emitting element 110B.

[0347] The organic layer 112R included in the light-emitting element 110R includes a light-emitting organic compound that emits at least red light. The organic layer 112G included in the light-emitting element 110G includes a light-emitting organic compound that emits at least green light. The organic layer 112B included in the light-emitting element 110B includes a light-emitting organic compound that emits at least blue light. The organic layer 112R, the organic layer 112G, and the organic layer 112B may each be referred to as an EL layer, and include at least a layer (light-emitting layer) including a light-emitting organic compound.

[0348] The display device 200A forms a light-emitting device for each light-emitting color, so the chromaticity change between low-brightness light and high-brightness light is small. In addition, the organic layers 112R, 112G, and 112B are separated from each other, so even if a high-definition display panel is used, crosstalk between adjacent sub-pixels can be suppressed. Therefore, a high-definition and high-quality display device can be realized.

[0349] An insulating layer 125 , a resin layer 126 , and a layer 128 are provided in a region between adjacent light emitting elements.

[0350] The pixel electrodes 111R, 111G, and 111B of the light-emitting elements are electrically connected to the conductive layer 326 of the transistor 320 via the plugs 256 embedded in the insulating layers 255a, 255b, and 255c, the conductive layer 241 embedded in the insulating layer 254, and the plugs 274. The height of the top surface of the insulating layer 255c is the same or substantially the same as the height of the top surface of the plug 256. Various conductive materials can be used as the plugs.

[0351] Furthermore, a protective layer 121 is provided on the light emitting elements 110R, 110G, and 110B. A substrate 170 is bonded to the protective layer 121 via an adhesive layer 171 .

[0352] No insulating layer covering the top end of the pixel electrode 111 is provided between two adjacent pixel electrodes 111. Therefore, the interval between adjacent light emitting elements can be made very small. Therefore, a high-definition or high-resolution display device can be realized.

[0353] [Display device 200B]

[0354] Hereinafter, a display device having a partially different structure from the above example will be described. Note that the same parts as above refer to the above description, and the description may be omitted.

[0355] Fig.25 The display device 200B shown in the figure shows an example in which a planar transistor 320A and a vertical channel transistor 320B are stacked on each other in which semiconductor layers are formed on a plane. The transistor 320B has the same structure as the transistor 320 in the display device 200A described above.

[0356] The transistor 320A includes a semiconductor layer 351 , an insulating layer 353 , a conductive layer 354 , a pair of conductive layers 355 , an insulating layer 356 , and a conductive layer 357 .

[0357] An insulating layer 352 is provided over the substrate 331. The insulating layer 352 functions as a barrier layer that prevents impurities such as water and hydrogen from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from escaping from the semiconductor layer 351 to the insulating layer 352 side. As the insulating layer 352, for example, a film into which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.

[0358] A conductive layer 357 is provided on the insulating layer 352, and an insulating layer 356 is provided so as to cover the conductive layer 357. The conductive layer 357 is used as a first gate electrode of the transistor 320A, and a part of the insulating layer 356 is used as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 356 that contacts the semiconductor layer 351. The top surface of the insulating layer 356 is preferably planarized.

[0359] The semiconductor layer 351 is provided on the insulating layer 356. The semiconductor layer 351 preferably includes a metal oxide (also referred to as an oxide semiconductor) film having semiconductor characteristics. A pair of conductive layers 355 are in contact with the semiconductor layer 351 and function as a source electrode and a drain electrode.

[0360] An insulating layer 358 and an insulating layer 350 are provided to cover the top surface and side surfaces of the pair of conductive layers 355 and the side surfaces of the semiconductor layer 351. The insulating layer 358 is used as a barrier layer that prevents impurities such as water and hydrogen from diffusing into the semiconductor layer 351 and oxygen from escaping from the semiconductor layer 351. As the insulating layer 358, an insulating film similar to the insulating layer 352 described above can be used.

[0361] The insulating layer 358 and the insulating layer 350 are provided with openings reaching the semiconductor layer 351. The insulating layer 353 and the conductive layer 354 are embedded in the openings and are in contact with the top surface of the semiconductor layer 351. The conductive layer 354 functions as a second gate electrode, and the insulating layer 353 functions as a second gate insulating layer.

[0362] The top surfaces of the conductive layer 354, the insulating layer 353, and the insulating layer 350 are planarized so that their heights are uniform or substantially uniform, and an insulating layer 359 is provided to cover them. The insulating layer 359 functions as a barrier layer for preventing impurities such as water and hydrogen from diffusing into the transistor 320. The insulating layer 359 can use the same insulating film as the insulating layer 352 described above.

[0363] As the transistor 320, a structure in which two gates sandwich a semiconductor layer forming a channel is adopted. Alternatively, the two gates may be connected and the transistor may be driven by supplying the same signal to the two gates. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential for controlling the threshold voltage to one of the two gates and applying a potential for driving to the other.

[0364] [Display device 200C]

[0365] Fig.26 The display device 200C shown has a stacked structure of a transistor 310 having a channel formed in a semiconductor substrate and a transistor 320 which is a vertical channel transistor.

[0366] The transistor 310 is a transistor having a channel formation region in the substrate 301. As the substrate 301, for example, a semiconductor substrate such as a single crystal silicon substrate can be used. The transistor 310 includes a portion of the substrate 301, a conductive layer 311, a low resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 is used as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311, and is used as a gate insulating layer. The low resistance region 312 is a region doped with impurities in the substrate 301, and is used as one of a source and a drain. The insulating layer 314 covers the side of the conductive layer 311.

[0367] Furthermore, an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301 .

[0368] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0369] (Implementation 4)

[0370] In this embodiment, a structural example of a display device that can be used for a display device manufactured using a transistor of one embodiment of the present invention is described. The display device described below can be used for the pixel portion 284 in Embodiment 3 above, etc.

[0371] One embodiment of the present invention is a display device including a light-emitting element (also referred to as a light-emitting device). The display device includes two or more pixels with different luminescent colors. Each pixel includes a light-emitting element. Each light-emitting element includes a pair of electrodes and an EL layer therebetween. The light-emitting element is preferably an organic EL element (organic electroluminescent element). The two or more light-emitting elements with different luminescent colors each include an EL layer containing different luminescent materials. For example, a full-color display device can be realized by including three light-emitting elements that emit red (R), green (G) or blue (B) light, respectively.

[0372] When manufacturing a display device including a plurality of light-emitting elements with different luminescent colors, it is necessary to form at least a layer containing a light-emitting material (light-emitting layer) into an island shape. Here, when forming a part or all of the EL layer separately, there is a known method of forming an island-shaped organic film by a vapor deposition method using a shadow mask such as a metal mask. However, this method has various effects such as the accuracy of the metal mask, the misalignment between the metal mask and the substrate, the deflection of the metal mask, and the enlargement of the outline of the deposited film due to vapor scattering, etc., and the shape and position of the island-shaped organic film deviate from the shape and position at the time of design, making it difficult to achieve high definition and high aperture ratio of the display device. In addition, during vapor deposition, the thickness of the end portion becomes smaller due to the blurred outline of the layer. That is, the thickness of the island-shaped light-emitting layer sometimes varies depending on the position. In addition, when manufacturing a large-scale, high-resolution or high-definition display device, there is a concern that the manufacturing yield rate will decrease due to the low dimensional accuracy of the metal mask and deformation caused by heat, etc. Therefore, the following measures have been taken: the definition (also called pixel density) is simulated by adopting a special pixel arrangement such as a Pentile arrangement.

[0373] Note that in this specification, etc., "island-shaped" means a state in which two or more layers formed of the same material in the same process are physically separated. For example, an island-shaped light-emitting layer means a state in which the light-emitting layer is physically separated from an adjacent light-emitting layer.

[0374] In one embodiment of the present invention, the EL layer is processed into a fine pattern by photolithography without using a shadow mask such as a high-definition metal mask (FMM). Therefore, a display device with high definition and high aperture ratio, which is difficult to achieve at present, can be realized. In addition, since the EL layer can be manufactured separately, a display device with very clear and high contrast display quality can be realized. In addition, for example, the EL layer can also be processed into a fine pattern using both a metal mask and photolithography.

[0375] In addition, part or all of the EL layer can be physically separated. Thus, leakage current between light-emitting elements through a layer (also referred to as a common layer) commonly used by adjacent light-emitting elements can be suppressed. Therefore, unintentional light emission due to crosstalk can be suppressed, thereby realizing a display device with very high contrast. In particular, a display device with high current efficiency at low brightness can be realized.

[0376] One embodiment of the present invention can also realize a display device that combines a white light-emitting light-emitting element and a color filter. In this case, the light-emitting element of the same structure can be used for each light-emitting element in a pixel (sub-pixel) that emits light of different colors, and all layers in each light-emitting element can be used as a common layer. Furthermore, it is also possible to cut off part or all of each EL layer by using photolithography. Thus, the leakage current through the common layer can be suppressed and a display device with high contrast can be realized. In particular, in an element having a series structure in which a plurality of light-emitting layers are stacked with an intermediate layer having high conductivity, the leakage current through the intermediate layer can be effectively prevented, so a display device with high brightness, high definition and high contrast can be realized.

[0377] When the EL layer is processed by photolithography, degradation may occur due to the exposure of part of the light-emitting layer. Therefore, it is preferable to provide an insulating layer that covers at least the side of the island-shaped light-emitting layer. The insulating layer may also cover a part of the top surface of the island-shaped EL layer. The insulating layer is preferably made of a material that has a barrier property against water and oxygen. For example, an inorganic insulating film that does not easily diffuse water or oxygen may be used. Thus, degradation of the EL layer can be suppressed and a display device with high reliability can be realized.

[0378] In addition, there is an area (recess) between two adjacent light-emitting elements where the EL layer of each light-emitting element is not provided. When a common electrode or a common electrode and a common layer are formed in a manner covering the recess, a phenomenon sometimes occurs in which the common electrode is separated due to a step at the end of the EL layer (also called disconnection), resulting in the insulation of the common electrode on the EL layer. Therefore, it is preferable to adopt a structure in which a resin layer used as a planarization film is used to fill the local step located between two adjacent light-emitting elements (also called LFP: Local Filling Planarization). The resin layer is used as a planarization film. As a result, the disconnection of the common layer or the common electrode can be suppressed, and a display device with high reliability can be realized.

[0379] Hereinafter, a more specific configuration example of a display device according to one embodiment of the present invention will be described with reference to the drawings.

[0380] [Structural example 1]

[0381] Fig.27A FIG. 1 is a schematic top view of a display device 100 according to one embodiment of the present invention. The display device 100 includes a plurality of red light emitting elements 110R, a plurality of green light emitting elements 110G, and a plurality of blue light emitting elements 110B on a substrate 101. Fig.27A In order to distinguish the light-emitting elements, symbols R, G, and B are attached to the light-emitting area of ​​each light-emitting element.

[0382] The light-emitting elements 110R, 110G, and 110B are all arranged in a matrix. Fig.27A A so-called stripe arrangement in which light-emitting elements of the same color are arranged in one direction is shown. Note that the arrangement method of the light-emitting elements is not limited to this, and other arrangement methods such as S stripe arrangement, Delta arrangement, Bayer arrangement, zigzag arrangement, etc. can also be used, and Pentile arrangement, Diamond arrangement, etc. can also be used.

[0383] As the light-emitting elements 110R, 110G, and 110B, OLED (Organic Light Emitting Diode) or QLED (Quantum-dot Light Emitting Diode) is preferably used. As the light-emitting substance contained in the EL element, for example, substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), and substances that exhibit thermally activated delayed fluorescence (Thermally activated delayed fluorescence: TADF materials) can be cited. As the light-emitting substance contained in the EL element, inorganic compounds (such as quantum dot materials) can also be used in addition to organic compounds.

[0384] In addition, Fig.27A A connection electrode 111C electrically connected to the common electrode 113 is shown. The connection electrode 111C is supplied with the potential (for example, anode potential or cathode potential) supplied to the common electrode 113. The connection electrode 111C is provided outside the display area where the light-emitting elements 110R, etc. are arranged.

[0385] The connection electrode 111C can be provided along the outer periphery of the display area. For example, it can be provided along one side of the outer periphery of the display area, or it can span two or more sides of the outer periphery of the display area. That is, when the top surface shape of the display area is rectangular, the top surface shape of the connection electrode 111C can be strip-shaped (rectangular), L-shaped, "冂"-shaped (bracket-shaped), or quadrilateral, etc.

[0386] Fig.27B , Fig.27C are respectively cross-sectional schematic views corresponding to Fig.27A the dotted lines A1 - A2 and A3 - A4 in Fig.27B A cross-sectional schematic view of the light-emitting elements 110R, 110G, and 110B is shown, Fig.27C A cross-sectional schematic view of the connection portion 140 where the connection electrode 111C is connected to the common electrode 113 is shown.

[0387] The light emitting element 110R includes a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light emitting element 110G includes a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light emitting element 110B includes a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The light emitting element 110R, the light emitting element 110G, and the light emitting element 110B share the common layer 114 and the common electrode 113.

[0388] The organic layer 112R included in the light-emitting element 110R includes a light-emitting organic compound that emits at least red light. The organic layer 112G included in the light-emitting element 110G includes a light-emitting organic compound that emits at least green light. The organic layer 112B included in the light-emitting element 110B includes a light-emitting organic compound that emits at least blue light. The organic layer 112R, the organic layer 112G, and the organic layer 112B may each be referred to as an EL layer, and include at least a layer (light-emitting layer) including a light-emitting organic compound.

[0389] Hereinafter, when describing the common contents among the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B, they are sometimes referred to as the light-emitting element 110. Similarly, when describing the common contents among the constituent elements distinguished by letters, such as the organic layer 112R, the organic layer 112G, and the organic layer 112B, the symbols without letters are sometimes used for description.

[0390] The organic layer 112 and the common layer 114 may independently include one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. For example, the organic layer 112 has a stacked structure in which a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer are stacked from one side of the pixel electrode 111, and the common layer 114 includes an electron injection layer.

[0391] The pixel electrode 111R, the pixel electrode 111G and the pixel electrode 111B are all arranged in each light-emitting element. In addition, the common electrode 113 and the common layer 114 are arranged as a layer commonly used by each light-emitting element. A conductive film that is translucent to visible light is used as one of the pixel electrodes and the common electrode 113, and a conductive film that is reflective is used as the other. By making each pixel electrode translucent and the common electrode 113 reflective, a bottom-emission type (bottom-emission structure) display device can be realized. On the contrary, by making each pixel electrode reflective and the common electrode 113 translucent, a top-emission type (top-emission structure) display device can be realized. In addition, by making both the pixel electrode and the common electrode 113 translucent, a double-sided emission type (double-sided emission structure) display device can also be realized.

[0392] A protective layer 121 is provided on the common electrode 113 so as to cover the light emitting elements 110R, 110G, and 110B. The protective layer 121 has a function of preventing impurities such as water from diffusing from above to each light emitting element.

[0393] The end of the pixel electrode 111 preferably has a tapered shape. When the end of the pixel electrode 111 has a tapered shape, the organic layer 112 provided along the end of the pixel electrode 111 may also have a tapered shape. By making the side of the pixel electrode 111 have a tapered shape, the coverage of the organic layer 112 provided across the end of the pixel electrode 111 can be improved. In addition, by making the side of the pixel electrode 111 have a tapered shape, foreign matter (for example, dust or particles, etc.) in the manufacturing process can be easily removed by washing treatment, etc., so it is preferred.

[0394] Note that in this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a component is inclined relative to the substrate surface. For example, it is preferable to have a region in which the angle formed by the inclined side surface and the substrate surface (also referred to as a taper angle) is less than 90°.

[0395] The organic layer 112 is processed into an island shape by photolithography. Therefore, the organic layer 112 has a shape at its end where the angle formed by the top surface and the side surface is close to 90 degrees. On the other hand, the thickness of the organic film formed using FMM (Fine Metal Mask) or the like tends to become thinner as it approaches the end. For example, the top surface is formed in a slope shape within a range of 1 μm to 10 μm from the end, so it is difficult to distinguish the top surface from the side surface.

[0396] An insulating layer 125 , a resin layer 126 , and a layer 128 are provided between two adjacent light emitting elements.

[0397] Between two adjacent light-emitting elements, the side surfaces of each organic layer 112 face each other via the resin layer 126. The resin layer 126 is located between two adjacent light-emitting elements and is provided in a manner to fill the end of each organic layer 112 and the area between the two organic layers 112. The top surface of the resin layer 126 has a smooth convex shape, and the common layer 114 and the common electrode 113 are provided in a manner to cover the top surface of the resin layer 126.

[0398] The resin layer 126 is used as a planarization film that fills the step between two adjacent light-emitting elements. By providing the resin layer 126, it is possible to prevent the common electrode 113 from being separated (also called disconnected) due to the step at the end of the organic layer 112, thereby preventing the common electrode on the organic layer 112 from being insulated. The resin layer 126 may also be referred to as an LFP (Local Filling Planning) layer.

[0399] As the resin layer 126, an insulating layer containing an organic material can be suitably used. For example, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors of the above resins can be used as the resin layer 126. In addition, as the resin layer 126, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinyl pyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can also be used.

[0400] In addition, a photosensitive resin may be used as the resin layer 126. A photoresist may be used as the photosensitive resin. A positive type material or a negative type material may be used as the photosensitive resin.

[0401] The resin layer 126 may also contain a material that absorbs visible light. For example, the resin layer 126 itself may be composed of a material that absorbs visible light, or the resin layer 126 may contain a pigment that absorbs visible light. As the resin layer 126, for example, the following resins may be used: a resin that can be used as a color filter that transmits red, blue, or green light and absorbs other light; or a resin that contains carbon black as a pigment and is used as a black matrix; etc.

[0402] The insulating layer 125 is in contact with the side surface of the organic layer 112. In addition, the insulating layer 125 covers the upper end portion of the organic layer 112. In addition, a portion of the insulating layer 125 is in contact with the top surface of the substrate 101.

[0403] The insulating layer 125 is located between the resin layer 126 and the organic layer 112 and is used as a protective film to prevent the resin layer 126 from contacting the organic layer 112. When the organic layer 112 and the resin layer 126 are in contact, the organic layer 112 may be dissolved by an organic solvent or the like used when forming the resin layer 126. Therefore, by providing the insulating layer 125 between the organic layer 112 and the resin layer 126, the side surface of the organic layer 112 can be protected.

[0404] The insulating layer 125 may be an insulating layer containing an inorganic material. As the insulating layer 125, for example, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film may be used. The insulating layer 125 may be a single-layer structure or a stacked-layer structure. As the oxide insulating film, a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film may be cited. As the nitride insulating film, a silicon nitride film and an aluminum nitride film may be cited. As the oxynitride insulating film, an oxynitride silicon film and an oxynitride aluminum film may be cited. As the nitride oxide insulating film, a nitride oxide silicon film and an nitride oxide aluminum film may be cited. In particular, by using a metal oxide film such as an aluminum oxide film or a hafnium oxide film or an inorganic insulating film such as a silicon oxide film formed by an ALD method for the insulating layer 125, the insulating layer 125 having fewer pinholes and having an excellent function of protecting the EL layer can be formed.

[0405] Note that in this specification, etc., oxynitride refers to a material containing more oxygen than nitrogen in its composition, and nitride oxide refers to a material containing more nitrogen than oxygen in its composition. For example, silicon oxynitride refers to a material containing more oxygen than nitrogen in its composition, and silicon nitride oxide refers to a material containing more nitrogen than oxygen in its composition.

[0406] The insulating layer 125 can be formed by a sputtering method, a CVD method, a PLD method, an ALD method, or the like. The insulating layer 125 is preferably formed by an ALD method having good coverage.

[0407] In addition, a reflective film (for example, a metal film including one or more selected from silver, palladium, copper, titanium, and aluminum) may be provided between the insulating layer 125 and the resin layer 126 so that the reflective film reflects the light emitted by the light-emitting layer. In this way, the light extraction efficiency can be further improved.

[0408] The layer 128 is a portion of a protective layer (also referred to as a mask layer or a sacrificial layer) that is used to protect the organic layer 112 when etching the organic layer 112. The layer 128 can use a material that can be used for the insulating layer 125. In particular, the layer 128 and the insulating layer 125 are preferably made of the same material, so that the same equipment for processing can be used.

[0409] In particular, metal oxide films such as aluminum oxide films and hafnium oxide films and inorganic insulating films such as silicon oxide films formed by the ALD method have fewer pinholes and are therefore excellent in the function of protecting the EL layer and can be suitably used for the insulating layers 125 and 128 .

[0410] The protective layer 121 may have, for example, a single-layer structure or a stacked-layer structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as silicon oxide films, silicon oxynitride films, silicon nitride oxide films, silicon nitride films, aluminum oxide films, aluminum oxynitride films, and hafnium oxide films. Alternatively, a semiconductor material or conductive material such as indium gallium oxide, indium zinc oxide, indium tin oxide, and indium gallium zinc oxide may be used as the protective layer 121.

[0411] As the protective layer 121, a laminated film of an inorganic insulating film and an organic insulating film can also be used. For example, it is preferred to sandwich an organic insulating film between a pair of inorganic insulating films. In addition, the organic insulating film is preferably used as a planarizing film. Therefore, the top surface of the organic insulating film can be made flat, so the coverage of the inorganic insulating film thereon is improved, thereby improving the barrier properties. In addition, the top surface of the protective layer 121 becomes flat, so when a structure (for example, a color filter, an electrode or a lens array of a touch sensor, etc.) is set above the protective layer 121, the influence of the concave-convex shape caused by the lower structure can be reduced, so it is preferred.

[0412] Fig.27C The connecting portion 140 that electrically connects the connecting electrode 111C and the common electrode 113 is shown. In the connecting portion 140, an opening is provided in the insulating layer 125 and the resin layer 126 above the connecting electrode 111C. The connecting electrode 111C and the common electrode 113 are electrically connected in the opening.

[0413] Notice, Fig.27C The connection portion 140 electrically connecting the connection electrode 111C and the common electrode 113 is shown, but the common electrode 113 may be provided on the connection electrode 111C via the common layer 114. In particular, when a carrier injection layer is used as the common layer 114, the resistivity of the material used for the common layer 114 is sufficiently low and the thickness is also thin, so in many cases there is no problem in positioning the common layer 114 at the connection portion 140. Thus, the common electrode 113 and the common layer 114 can be formed using the same shadow mask, so that the manufacturing cost can be reduced.

[0414] [Structural example 2]

[0415] Hereinafter, a display device having a partially different structure from that of the above-described structural example 1 will be described. Note that regarding the same parts as those of the above-described structural example 1, the above-described structural example 1 may be referred to and the description thereof may be omitted.

[0416] Fig.28A 1 is a schematic cross-sectional view of the display device 100a. The main differences between the display device 100a and the display device 100 are: the structure of the light emitting element; and the former includes a coloring layer.

[0417] The display device 100a includes a light-emitting element 110W that emits white light. The light-emitting element 110W includes a pixel electrode 111, an organic layer 112W, a common layer 114, and a common electrode 113. The organic layer 112W emits white light. For example, the organic layer 112W may include two or more light-emitting materials whose luminescent colors are in a complementary color relationship. For example, the organic layer 112W may include a light-emitting organic compound that emits red light, a light-emitting organic compound that emits green light, and a light-emitting organic compound that emits blue light. In addition, it may also include a light-emitting organic compound that emits blue light and a light-emitting organic compound that emits yellow light.

[0418] Each organic layer 112W is separated between two adjacent light emitting elements 110W. This can suppress leakage current flowing between adjacent light emitting elements 110W through the organic layer 112W, and can suppress crosstalk caused by the leakage current. Therefore, a display device with high contrast and color reproducibility can be realized.

[0419] An insulating layer 122 serving as a planarization film is provided over the protective layer 121 , and the colored layers 116R, 116G, and 116B are provided over the insulating layer 122 .

[0420] As the insulating layer 122, an organic resin film or an inorganic insulating film whose top surface is flattened can be used. Since the insulating layer 122 is the surface on which the colored layer 116R, the colored layer 116G, and the colored layer 116B are formed, the thickness of the colored layer 116R and the like can be made uniform when the top surface of the insulating layer 122 is flat, thereby improving the color purity. Note that when the thickness of the colored layer 116R and the like is not uniform, the amount of light absorption varies depending on the region in the colored layer 116R, thereby possibly causing a decrease in color purity.

[0421] [Structural example 3]

[0422] Fig.28B is a schematic cross-sectional view of the display device 100 b.

[0423] The light emitting element 110R includes a pixel electrode 111, a conductive layer 115R, an organic layer 112W, and a common electrode 113. The light emitting element 110G includes a pixel electrode 111, a conductive layer 115G, an organic layer 112W, and a common electrode 113. The light emitting element 110B includes a pixel electrode 111, a conductive layer 115B, an organic layer 112W, and a common electrode 113. The conductive layer 115R, the conductive layer 115G, and the conductive layer 115B are all light-transmissive and are used as optical adjustment layers.

[0424] A microcavity resonator (microcavity) structure can be realized by using a film that reflects visible light as the pixel electrode 111 and using a film that is both reflective and transmissive to visible light as the common electrode 113. At this time, by adjusting the thickness of the conductive layer 115R, the conductive layer 115G, and the conductive layer 115B so as to realize the most appropriate optical path length, even when using the organic layer 112 that emits white light, it is possible to extract light of different wavelengths from each of the light-emitting elements 110R, the light-emitting element 110G, and the light-emitting element 110B, thereby enhancing light.

[0425] Furthermore, by providing the colored layer 116R, the colored layer 116G, and the colored layer 116B on the optical paths of the light emitting element 110R, the light emitting element 110G, and the light emitting element 110B, respectively, light with high color purity can be extracted.

[0426] In addition, an insulating layer 123 is provided to cover the ends of the pixel electrode 111 and the conductive layer 115. The ends of the insulating layer 123 preferably have a tapered shape. By providing the insulating layer 123, the coverage of the organic layer 112W, the common electrode 113, the protective layer 121, etc. formed thereon can be improved.

[0427] The organic layer 112W and the common electrode 113 are respectively provided as a continuous film in each light emitting element. By adopting this structure, the manufacturing process of the display device can be greatly simplified, so it is preferred.

[0428] Here, the end of the pixel electrode 111 preferably has a substantially vertical shape. Thus, a steeply inclined portion can be formed on the surface of the insulating layer 123, and a thin portion can be formed in a portion of the organic layer 112W covering the portion, or a portion of the organic layer 112W can be separated. Thus, the leakage current generated between adjacent light-emitting elements through the organic layer 112W can be suppressed without processing the organic layer 112W using photolithography or the like.

[0429] The above is the description of the configuration example of the display device.

[0430] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0431] (Implementation method 5)

[0432] In this embodiment, an electronic device which is one embodiment of the present invention is described using FIGS. 29 to 31 .

[0433] The electronic device of this embodiment includes a display panel (display device) using a transistor of one embodiment of the present invention in a display portion. The display device of one embodiment of the present invention can easily achieve high definition and high resolution, and can also achieve high display quality. Therefore, it can be used in the display portion of various electronic devices.

[0434] Electronic devices include, for example, television sets, desktop or notebook personal computers, displays for computers, etc., digital signage, large-scale game consoles such as pinball machines, and other electronic devices with larger screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, sound reproduction devices, and the like.

[0435] In particular, since the display panel of one embodiment of the present invention can improve the clarity, it can be appropriately used in electronic devices including a smaller display unit. Examples of such electronic devices include watch-type and bracelet-type information terminal devices (wearable devices), wearable devices that can be worn on the head, VR devices such as head-mounted displays, glasses-type AR devices, and MR devices.

[0436] The display panel of one embodiment of the present invention preferably has an extremely high resolution such as HD (pixel number is 1280×720), FHD (pixel number is 1920×1080), WQHD (pixel number is 2560×1440), WQXGA (pixel number is 2560×1600), 4K (pixel number is 3840×2160), 8K (pixel number is 7680×4320), etc. In particular, it is preferably set to a resolution of 4K, 8K or above. In addition, the pixel density (definition) in the display panel of one embodiment of the present invention is preferably 100ppi or more, preferably 300ppi or more, more preferably 500ppi or more, more preferably 1000ppi or more, more preferably 2000ppi or more, more preferably 3000ppi or more, more preferably 5000ppi or more, and further preferably 7000ppi or more. By using a display panel having one or both of the above-mentioned high resolution and high definition, the sense of reality and depth can be further improved. In addition, there is no particular limitation on the screen ratio (aspect ratio) of the display panel of one embodiment of the present invention. For example, the display panel can be adapted to various screen ratios such as 1:1 (square), 4:3, 16:9, 16:10, etc.

[0437] The electronic device of this embodiment may also include a sensor (the sensor has the function of sensing, detecting, and measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, smell or infrared).

[0438] The electronic device of this embodiment may have various functions. For example, it may have the following functions: a function of displaying various information (static images, dynamic images, text images, etc.) on a display unit; a function of a touch panel; a function of displaying a calendar, date, or time, etc.; a function of executing various software (programs); a function of wireless communication; a function of reading programs or data stored in a storage medium; etc.

[0439] use FIG. 29A to FIG. 29D An example of a wearable device that can be worn on the head is described. These wearable devices have one or both of the function of displaying AR content and the function of displaying VR content. In addition, these wearable devices may also have the function of displaying SR or MR content in addition to AR and VR. When an electronic device has the function of displaying at least one of AR, VR, SR, and MR content, the user's sense of immersion can be improved.

[0440] Fig.29A The electronic device 700A shown and Fig.29B The electronic devices 700B shown include a pair of display panels 751, a pair of frames 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical components 753, a frame 757 and a pair of nose pads 758.

[0441] The display panel of one embodiment of the present invention can be applied to the display panel 751. Therefore, an electronic device capable of performing extremely high-definition display can be realized.

[0442] Both the electronic device 700A and the electronic device 700B can project the image displayed by the display panel 751 onto the display area 756 in the optical member 753. Since the optical member 753 is light-transmissive, the user can see the image displayed in the display area overlapping the transmitted image seen through the optical member 753. Therefore, both the electronic device 700A and the electronic device 700B are electronic devices capable of AR display.

[0443] The electronic device 700A and the electronic device 700B may also be provided with a camera capable of photographing the front as an imaging unit. In addition, by providing an acceleration sensor such as a gyro sensor on the electronic device 700A and the electronic device 700B, the user's head orientation can be detected and an image corresponding to the direction can be displayed on the display area 756.

[0444] The communication unit includes a wireless communication device, through which a video signal etc. can be supplied. In addition to or in place of the wireless communication device, a connector to which a cable for supplying a video signal and a power supply potential can be connected may be included.

[0445] Furthermore, electronic device 700A and electronic device 700B are provided with batteries, and can be charged wirelessly or by wire, or both.

[0446] The frame 721 may also be provided with a touch sensor module. The touch sensor module has a function of detecting whether the outer surface of the frame 721 is touched. Through the touch sensor module, various processes can be performed by detecting a user's tapping operation or sliding operation. For example, a process such as temporarily stopping or replaying a dynamic image can be performed through a tapping operation, and a process such as fast forwarding or rewinding can be performed through a sliding operation. In addition, by providing a touch sensor module in each of the two frames 721, the operating range can be expanded.

[0447] As the touch sensor module, various touch sensors can be used. For example, various methods such as electrostatic capacitance, resistance film, infrared, electromagnetic induction, surface acoustic wave, and optical can be used. In particular, it is preferred to use electrostatic capacitance or optical sensors in the touch sensor module.

[0448] When an optical touch sensor is used, a photoelectric conversion device (also called a photoelectric conversion element) can be used as a light receiving device (also called a light receiving element). In the active layer of the photoelectric conversion device, one or both of an inorganic semiconductor and an organic semiconductor can be used.

[0449] Fig.29C The electronic device 800A shown and Fig.29D The electronic device 800B shown includes a pair of display portions 820 , a housing 821 , a communication portion 822 , a pair of mounting portions 823 , a control portion 824 , a pair of imaging portions 825 , and a pair of lenses 832 .

[0450] The display unit 820 may be a display panel according to one embodiment of the present invention. Therefore, an electronic device capable of displaying with extremely high definition may be realized, so that the user may experience a high sense of immersion.

[0451] The display unit 820 is provided at a position visible through the lens 832 inside the housing 821. In addition, by displaying different images on each of the pair of display units 820, three-dimensional display using parallax can be performed.

[0452] The electronic device 800A and the electronic device 800B can both be referred to as VR-oriented electronic devices. A user who wears the electronic device 800A or the electronic device 800B can see the image displayed on the display unit 820 through the lens 832 .

[0453] The electronic device 800A and the electronic device 800B preferably have a mechanism in which the left and right positions of the lens 832 and the display unit 820 can be adjusted so that the lens 832 and the display unit 820 are located at the most suitable position according to the position of the user's eyes. In addition, it is preferable to have a mechanism in which the focus is adjusted by changing the distance between the lens 832 and the display unit 820.

[0454] The user can use the mounting portion 823 to mount the electronic device 800A or the electronic device 800B on the head. Fig.29C The example that the mounting portion 823 has a shape like the temples of glasses (also called temples, etc.) is shown in the figure, but it is not limited to this. As long as the user can put it on, the mounting portion 823 can have a helmet-type or belt-type shape, for example.

[0455] The imaging unit 825 has a function of acquiring external information. The data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used in the imaging unit 825. In addition, a plurality of cameras can be provided to correspond to various viewing angles such as telephoto and wide angle.

[0456] Note that the example including the imaging unit 825 is shown here, and a distance measuring sensor (hereinafter, also referred to as a detection unit) capable of measuring the distance to the object may be provided. In other words, the imaging unit 825 is a form of a detection unit. As the detection unit, for example, an image sensor or a distance image sensor such as a laser radar (LIDAR: Light Detection and Ranging) may be used. By using the image obtained by the camera and the image obtained by the distance image sensor, more information can be obtained, and a more accurate gesture operation can be achieved.

[0457] The electronic device 800A may also include a vibration mechanism used as a bone conduction headset. For example, any one or more of the display unit 820, the frame 821, and the mounting unit 823 may adopt a structure including the vibration mechanism. Thus, there is no need to separately provide audio equipment such as headphones, earphones, or speakers, and the image and sound can be enjoyed by only installing the electronic device 800A.

[0458] Electronic device 800A and electronic device 800B may both include input terminals. Cables for supplying video signals from a video output device or the like, power for charging a battery provided in the electronic device, and the like may be connected to the input terminals.

[0459] An electronic device according to one embodiment of the present invention may also have a function of wirelessly communicating with earphone 750. Earphone 750 includes a communication unit (not shown) and has a wireless communication function. Earphone 750 can receive information (such as sound data) from the electronic device through the wireless communication function. For example, Fig.29A The electronic device 700A shown has a function of transmitting information to the headset 750 through a wireless communication function. In addition, for example Fig.29C The electronic device 800A shown has a function of transmitting information to the headset 750 through a wireless communication function.

[0460] Furthermore, the electronic device may include an earphone unit. Fig.29B The electronic device 700B shown includes an earphone unit 727. For example, a structure in which the earphone unit 727 and the control unit are connected in a wired manner may be adopted. A part of the wiring connecting the earphone unit 727 and the control unit may also be arranged inside the frame 721 or the mounting portion 723.

[0461] same, Fig.29D The electronic device 800B shown includes an earphone unit 827. For example, a structure in which the earphone unit 827 and the control unit 824 are connected in a wired manner may be adopted. A part of the wiring connecting the earphone unit 827 and the control unit 824 may also be arranged inside the frame 821 or the mounting portion 823. In addition, the earphone unit 827 and the mounting portion 823 may also include magnets. Thus, the earphone unit 827 can be fixed to the mounting portion 823 by magnetic force, and storage becomes easy, which is preferred.

[0462] In addition, the electronic device may also include a sound output terminal that can be connected to an earphone or a headset. In addition, the electronic device may also include one or both of a sound input terminal and a sound input mechanism. As the sound input mechanism, for example, a sound receiving device such as a microphone can be used. By providing the sound input mechanism to the electronic device, the electronic device can have the so-called earphone function.

[0463] As described above, as electronic devices according to one embodiment of the present invention, both glasses-type (electronic devices 700A and 700B, etc.) and goggles-type (electronic devices 800A and 800B, etc.) are preferable.

[0464] Fig. 30A The electronic device 6500 shown is a portable information terminal device that can be used as a smartphone.

[0465] The electronic device 6500 includes a frame 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The display unit 6502 has a touch panel function. In addition, the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device. A semiconductor device of one embodiment of the present invention can be used for the display unit 6502, the control device 6509, etc. By using a semiconductor device of one embodiment of the present invention for the control device 6509, power consumption can be reduced, so it is preferred.

[0466] The display portion 6502 can use a display panel which is one embodiment of the present invention.

[0467] Fig. 30B 6506 is a schematic cross-sectional view of an end portion of a housing 6501 on the microphone 6506 side.

[0468] A light-transmitting protective component 6510 is provided on one side of the display surface of the frame 6501, and a display panel 6511, an optical component 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are provided in the space surrounded by the frame 6501 and the protective component 6510.

[0469] The display panel 6511 , the optical member 6512 , and the touch sensor panel 6513 are fixed to the protective member 6510 using an adhesive layer (not shown).

[0470] In a region outside the display portion 6502, a portion of the display panel 6511 is folded, and an FPC 6515 is connected to the folded portion. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0471] The display panel 6511 may use a flexible display of one embodiment of the present invention. Thus, an extremely lightweight electronic device may be realized. In addition, since the display panel 6511 is extremely thin, a large-capacity battery 6518 may be installed while suppressing the thickness of the electronic device. In addition, by folding a portion of the display panel 6511 to provide a connection portion with the FPC 6515 on the back of the pixel portion, an electronic device with a narrow frame may be realized.

[0472] Fig. 30C 100 shows an example of a television set. In a television set 7100, a display portion 7000 is incorporated in a housing 7101. Here, a structure in which the housing 7101 is supported by a stand 7103 is shown.

[0473] The operation can be performed by using the operation switch provided in the frame 7101 and the remote control operation machine 7111 provided separately. Fig. 30C Alternatively, the display unit 7000 may be provided with a touch sensor, and the television unit 7100 may be operated by touching the display unit 7000 with a finger or the like. Furthermore, the remote control unit 7111 may be provided with a display unit that displays information output from the remote control unit 7111. By using the operation keys or the touch panel provided in the remote control unit 7111, the channel and volume can be operated, and the image displayed on the display unit 7000 can be operated.

[0474] In addition, the television device 7100 includes a receiver and a modem. The receiver can receive general television broadcasts. Furthermore, the modem can be connected to a wired or wireless communication network to perform one-way (from a sender to a receiver) or two-way (between a sender and a receiver or between receivers, etc.) information communication.

[0475] Fig.30D An example of a notebook personal computer is shown. The notebook personal computer 7200 includes a frame 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7216, etc. A display unit 7000 is assembled in the frame 7211. The control device 7216 includes, for example, one or more selected from a CPU, a GPU, and a storage device. A semiconductor device of one embodiment of the present invention can be used for the display unit 7000, the control device 7216, etc. By using a semiconductor device of one embodiment of the present invention for the control device 7216, power consumption can be reduced, so it is preferred.

[0476] Fig.30E and Fig.30F An example of digital signage is shown.

[0477] Fig.30E The digital signage 7300 shown includes a housing 7301, a display portion 7000, a speaker 7303, etc. In addition, an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, etc. may be included.

[0478] Fig.30F The digital signage 7400 is shown to be disposed on a cylindrical pillar 7401. The digital signage 7400 includes a display unit 7000 disposed along a curved surface of the pillar 7401.

[0479] The larger the display unit 7000 is, the more information can be provided at one time. The larger the display unit 7000 is, the easier it is to attract people's attention, for example, the advertising effect can be improved.

[0480] By using a touch panel for the display unit 7000, not only can a static image or a dynamic image be displayed on the display unit 7000, but the user can also intuitively operate it, so it is preferred. In addition, when used for providing information such as route information or traffic information, the ease of use can be improved through intuitive operation.

[0481] like Fig.30E and Fig.30F As shown, the digital signage 7300 or the digital signage 7400 can preferably be linked with the information terminal device 7311 or the information terminal device 7411 such as a smartphone carried by the user through wireless communication. For example, the advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal device 7311 or the information terminal device 7411. In addition, by operating the information terminal device 7311 or the information terminal device 7411, the display of the display unit 7000 can be switched.

[0482] Furthermore, the game can be executed on the digital signage 7300 or the digital signage 7400 using the screen of the information terminal device 7311 or the information terminal device 7411 as an operation unit (controller). Thus, an unspecified number of users can participate in the game at the same time and enjoy the game.

[0483] exist FIG. 30C to FIG. 30F In the embodiment of the present invention, the display panel can be used for the display portion 7000 .

[0484] FIG. 31A to FIG. 31G The electronic device shown includes a frame 9000, a display portion 9001, a speaker 9003, an operation key 9005 (including a power switch or an operation switch), a connecting terminal 9006, a sensor 9007 (the sensor has the function of sensing, detecting, and measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, smell or infrared), a microphone 9008, etc.

[0485] FIG. 31A to FIG. 31GThe electronic device shown has various functions. For example, it may have the following functions: a function of displaying various information (static images, dynamic images, text images, etc.) on a display unit; a function of a touch panel; a function of displaying a calendar, date, or time, etc.; a function of controlling processing by using various software (programs); a function of wireless communication; a function of reading out programs or data stored in a storage medium and processing them; etc. Note that the functions of the electronic device are not limited to the above functions, but may have various functions. The electronic device may include multiple display units. In addition, a camera or the like may be provided in the electronic device so that it has the following functions: a function of taking a static image or a dynamic image, and storing the taken image in a storage medium (an external storage medium or a storage medium built into the camera); a function of displaying the taken image on a display unit; etc.

[0486] Below, we explain in detail FIG. 31A to FIG. 31G Electronic equipment shown.

[0487] Fig.31A 9101 is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 can be used as a smart phone, for example. Note that a speaker 9003, a connection terminal 9006, a sensor 9007, and the like can also be provided in the portable information terminal 9101. In addition, as the portable information terminal 9101, text or image information can be displayed on multiple surfaces thereof. Fig.31A 9050. In addition, information 9051 indicated by a dotted rectangle may be displayed on another surface of the display unit 9001. Examples of information 9051 include information indicating that an email, SNS, or phone call has been received; a title of the email or SNS; a sender's name of the email or SNS; a date; a time; a remaining battery level; and radio wave strength. Alternatively, icon 9050 may be displayed at a location where information 9051 is displayed.

[0488] Fig.31B 9102 is a three-dimensional diagram showing a portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, when the portable information terminal 9102 is placed in a jacket pocket, the user can confirm the information 9053 displayed at a position viewed from above the portable information terminal 9102. For example, the user can confirm the display without taking the portable information terminal 9102 out of the pocket, thereby determining whether to answer a call.

[0489] Fig.31C9103 is a perspective view showing a tablet terminal 9103. The tablet terminal 9103 can execute various application software such as mobile phone, reading and editing of e-mails and articles, playing music, network communication, computer games, etc. The tablet terminal 9103 includes a display portion 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front of the frame 9000, an operation key 9005 used as an operation button on the left side of the frame 9000, and a connection terminal 9006 on the bottom.

[0490] Fig.31D 9001 is a stereoscopic diagram showing a watch-type portable information terminal 9200. The portable information terminal 9200 can be used, for example, as a smart watch (registered trademark). In addition, the display surface of the display unit 9001 is curved, and a display can be performed along its curved display surface. In addition, the portable information terminal 9200 can perform hands-free calls, for example, by communicating with a headset capable of wireless communication. In addition, by utilizing the connection terminal 9006, the portable information terminal 9200 can perform data transmission or charging with other information terminals. In addition, charging can also be performed by wireless power supply.

[0491] FIG. 31E to FIG. 31G 9201 is a perspective view showing a foldable portable information terminal. Fig.31E is a perspective view of the portable information terminal 9201 in an unfolded state. Figure 31G This is a three-dimensional diagram of the folded state. Fig.31F is from Fig.31E Status and Figure 31G The portable information terminal 9201 is easy to carry in the folded state, and has a large display area that is seamlessly spliced ​​in the unfolded state, so the display is easy to browse. The display unit 9001 included in the portable information terminal 9201 is supported by three frames 9000 connected by hinges 9055. The display unit 9001 can be bent within a range of a curvature radius of 0.1 mm or more and 150 mm or less, for example.

[0492] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0493] (Implementation 6)

[0494] In this embodiment, an application example of a semiconductor device of one embodiment of the present invention is described. For example, a semiconductor device of one embodiment of the present invention can be used in electronic components, electronic devices, large computers, space equipment, and data centers (also referred to as DC). Electronic components, electronic devices, large computers, space equipment, and data centers using a semiconductor device of one embodiment of the present invention are effective in achieving high performance such as low power consumption.

[0495] An electronic component or the like using the semiconductor device of one embodiment of the present invention can be applied to the electronic device described in Embodiment 5.

[0496] [Electronic components]

[0497] Fig.32A A perspective view of a substrate (circuit board 704 ) on which an electronic component 700 is mounted is shown. Fig.32A The electronic component 700 shown includes a semiconductor device 710 within a mold 711. Fig.32A 700 is partially omitted to show the inside thereof. The electronic component 700 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 710 through the lead 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. By combining a plurality of these electronic components and electrically connecting them on the printed circuit board 702, a circuit board 704 is completed.

[0498] In addition, the semiconductor device 710 includes a driving circuit layer 715 and a storage layer 716. The storage layer 716 has a structure in which a plurality of memory cell arrays are stacked. The stacked structure of the driving circuit layer 715 and the storage layer 716 can be a monolithic stacked structure. In a monolithic stacked structure, each layer can be connected without using through-electrode technology such as TSV (Through Silicon Via) and bonding technology such as Cu-Cu direct bonding. When the driving circuit layer 715 and the storage layer 716 are stacked in a monolithic manner, for example, a so-called on-chip memory structure in which a memory is directly formed on a processor can be realized. By adopting the on-chip memory structure, high-speed operation of the interface part between the processor and the memory can be achieved.

[0499] In addition, by adopting an on-chip memory structure, the size of the connection wiring can be reduced compared to the technology using through-electrodes such as TSV, so the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, thereby increasing the bandwidth of the memory (also called memory bandwidth).

[0500] In addition, it is preferred that multiple memory cell arrays in the storage layer 716 are formed using OS transistors, and the multiple memory cell arrays are stacked in a monolithic manner. When multiple memory cell arrays are stacked in a monolithic manner, one or both of the bandwidth of the memory and the access delay of the memory can be improved. Bandwidth refers to the amount of data transmitted per unit time, and access delay refers to the time between access and the start of data exchange. In addition, when Si transistors are used in the storage layer 716, it is difficult to have a monolithic stacked structure compared to the case of using OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0501] In addition, the semiconductor device 710 may be referred to as a bare chip. In this specification, etc., a bare chip refers to a chip obtained by forming a circuit pattern on a disc-shaped substrate (also referred to as a wafer) or the like in the manufacturing process of a semiconductor chip, and cutting it into rectangular small pieces. As semiconductor materials that can be used for bare chips, for example, silicon (Si), silicon carbide (SiC) or gallium nitride (GaN) can be cited. For example, a bare chip obtained from a silicon substrate (also referred to as a silicon wafer) is sometimes referred to as a silicon chip.

[0502] then, Fig.32B The electronic component 730 is a perspective view. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0503] The electronic component 730 shows an example of using the semiconductor device 710 as a high bandwidth memory (HBM). In addition, the semiconductor device 735 can be used in an integrated circuit such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).

[0504] The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0505] The plug board 731 has a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits having different terminal spacings. The plurality of wirings are composed of a single layer or a plurality of layers. In addition, the plug board 731 has the function of electrically connecting the integrated circuit disposed on the plug board 731 to the electrode disposed on the package substrate 732. Therefore, the plug board is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". In addition, sometimes a through electrode is provided in the plug board 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, in the case of using a silicon plug board, TSV can also be used as a through electrode.

[0506] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

[0507] In addition, in SiP and MCM using silicon interposers, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not easy to occur. In addition, since the surface flatness of the silicon interposer is high, the connection between the integrated circuit arranged on the silicon interposer and the silicon interposer is not easy to occur. It is particularly preferred to use the silicon interposer for 2.5D packaging (2.5D mounting) in which a plurality of integrated circuits are arranged horizontally and configured on the interposer.

[0508] On the other hand, when a plurality of integrated circuits with different terminal spacings are electrically connected using silicon interposers and TSV, etc., a space such as the width of the terminal spacing is required. Therefore, when the size of the electronic component 730 is to be reduced, the width of the terminal spacing becomes a problem, and it is sometimes difficult to set up a plurality of wirings required to achieve a wide memory bandwidth. Therefore, as described above, it is preferred to adopt a monolithic stacked structure using OS transistors. In addition, a composite structure combining a memory cell array stacked using TSV and a memory cell array of a monolithic stacked structure may also be adopted.

[0509] In addition, a heat sink (heat sink plate) may be provided so as to overlap with the electronic component 730. When a heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the interposer 731 consistent. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the heights of the semiconductor device 710 and the semiconductor device 735 consistent.

[0510] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Fig.32BAn example of forming the electrode 733 using solder balls is shown. By arranging solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode 733 can be formed using conductive pins. By arranging conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0511] The electronic component 730 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0512] [Mainframe computer]

[0513] Fig.33A 1 is a perspective view of a mainframe computer 5600. In the mainframe computer 5600, a plurality of rack-mounted computers 5620 are housed in a rack 5610. The mainframe computer 5600 may also be referred to as a supercomputer.

[0514] Fig.33B A perspective view showing an example of a computer 5620. The computer 5620 includes a motherboard 5630. The motherboard 5630 is provided with a plurality of slots 5631 and a plurality of connection terminals. A personal computer card 5621 is inserted into the slot 5631. The personal computer card 5621 includes a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, which are connected to the motherboard 5630.

[0515] Fig.33C An example of a personal computer card 5621 is shown. The personal computer card 5621 is, for example, a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 includes a board 5622, and connection terminals 5623, 5624, 5625, an electronic component 5626, an electronic component 5627, an electronic component 5628, a connection terminal 5629, etc. mounted on the board 5622. Fig.33C Components other than the electronic component 5626, the electronic component 5627, and the electronic component 5628 are also shown.

[0516] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe and the like.

[0517] The connection terminals 5623, 5624, and 5625 can be used as interfaces for supplying power to the personal computer card 5621 or inputting signals, for example. In addition, for example, they can be used as interfaces for outputting signals calculated by the personal computer card 5621, for example. Examples of the specifications of the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when video signals are output from the connection terminals 5623, 5624, and 5625, HDMI (registered trademark) and the like can be cited as the specifications.

[0518] The electronic component 5626 includes a terminal (not shown) for inputting and outputting a signal, and the electronic component 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) included in the board 5622 .

[0519] The electronic components 5627 and 5628 include a plurality of terminals, and the electronic components 5627 and 5628 can be mounted by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. As the electronic component 5627, for example, an FPGA, a GPU, a CPU, etc. can be cited. As the electronic component 5627, for example, the electronic component 730 can be used. As the electronic component 5628, for example, a storage device can be cited. As the electronic component 5628, for example, the electronic component 700 can be used.

[0520] The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for learning and inference of artificial intelligence can be performed.

[0521] [Space Equipment]

[0522] The semiconductor device according to one embodiment of the present invention can be applied to space equipment.

[0523] A semiconductor device of one embodiment of the present invention includes an OS transistor. The electrical characteristics of the OS transistor change little due to exposure to radiation. In other words, it has high resistance to radiation, so it can be appropriately used in an environment where radiation may be incident. For example, an OS transistor can be appropriately used when used in outer space. Specifically, an OS transistor can be used as a transistor that constitutes a semiconductor device provided in a space shuttle, an artificial satellite, or a space probe. Examples of radiation include X-rays and neutron rays. Note that outer space refers to, for example, an altitude of 100 km or more, but the outer space shown in this specification may also include one or more of the thermosphere, mesosphere, and stratosphere.

[0524] exist Fig.34A In FIG. 6 , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig.34A An example of a planet 6804 in outer space is shown.

[0525] In addition, although Fig.34A Although not shown in the figure, a battery management system (also called BMS) or a battery control circuit may be provided in the secondary battery 6805. When an OS transistor is used for the battery management system or the battery control circuit, power consumption can be reduced and high reliability can be achieved even in outer space, so it is preferred.

[0526] In addition, outer space is an environment where the radiation dose is more than 100 times that of the ground. Examples of radiation include: electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays; and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, muon rays, etc.

[0527] When sunlight shines on the solar cell panel 6802, the power required for the artificial satellite 6800 to operate is generated. However, for example, when sunlight does not shine on the solar cell panel or when the amount of sunlight shining on the solar cell panel is small, the amount of power generated is reduced. Therefore, there is a possibility that the power required for the artificial satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even when the generated power is small, it is preferable to provide a secondary battery 6805 in the artificial satellite 6800. In addition, the solar cell panel is sometimes referred to as a solar cell module.

[0528] The artificial satellite 6800 can generate a signal. The signal is transmitted through the antenna 6803, and a receiver on the ground or other artificial satellites can receive the signal. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver receiving the signal can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0529] In addition, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is composed of, for example, one or more selected from a CPU, a GPU, and a storage device. In addition, as the control device 6807, a semiconductor device including an OS transistor of one embodiment of the present invention is preferably used. Compared with Si transistors, the electrical characteristics of OS transistors due to irradiation with radiation are less changed. In other words, OS transistors have high reliability and can be used appropriately even in an environment where radiation may be incident.

[0530] In addition, the artificial satellite 6800 may include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 may have a function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 may have a function of detecting thermal infrared rays released from the ground. Thus, the artificial satellite 6800 may be used as an earth observation satellite, for example.

[0531] Note that although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited to this. For example, a semiconductor device according to one embodiment of the present invention can be suitably applied to space equipment such as a spacecraft, a space capsule, and a space probe.

[0532] As described above, OS transistors have superior effects compared to Si transistors, such as being able to achieve a wide memory bandwidth and high resistance to radiation.

[0533] [Data Center]

[0534] For example, a semiconductor device according to one embodiment of the present invention can be applied to a storage system used in a data center or the like. A data center is required to manage data over a long period of time by ensuring data invariance. When managing data over a long period of time, it is necessary to enlarge facilities, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply to maintain data, or ensuring cooling equipment required for maintaining data.

[0535] By using a semiconductor device of one embodiment of the present invention in a storage system used in a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device for retaining data. Therefore, it is possible to miniaturize the storage system, miniaturize the power supply for retaining data, and reduce the scale of cooling equipment. As a result, it is possible to save space in the data center.

[0536] In addition, the power consumption of the semiconductor device of one embodiment of the present invention is low, so the heat generation of the circuit can be reduced. As a result, the negative impact of the heat generation on the circuit itself, the peripheral circuits and the modules can be reduced. In addition, by using the semiconductor device of one embodiment of the present invention, a data center that can operate stably even in a high temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0537] Fig.34B A storage system that may be used in a data center is shown. Fig.34B The storage system 7000 shown includes a plurality of servers 7001sb as a host 7001 (shown as a host computer). In addition, it includes a plurality of storage devices 7003md as storage 7003 (shown as storage). The host 7001 and the storage 7003 are shown to be connected via a storage area network 7004 (shown as SAN: Storage Area Network) and a storage control circuit 7002 (shown as a storage controller).

[0538] The host 7001 is equivalent to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0539] In the storage 7003, the access speed of data is shortened by using a flash memory, that is, the time required for data storage and output is shortened, but this time is much longer than the time required for a DRAM that can be used as a high-speed cache memory in the storage. In order to solve the problem of the high access speed of the storage 7003 in the storage system, a high-speed cache memory is generally provided in the storage to shorten the time for data storage and output.

[0540] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003 and then output to the host 7001 or the storage 7003.

[0541] When an OS transistor is used as a transistor for storing data in the cache memory to hold a potential corresponding to the data, the refresh frequency can be reduced to reduce power consumption. In addition, miniaturization can be achieved by stacking memory cell arrays.

[0542] Note that by using a semiconductor device of one embodiment of the present invention for one or more selected from electronic components, electronic devices, large computers, space equipment, and data centers, it is expected that the power consumption can be reduced. Therefore, it is currently believed that as the performance or integration of semiconductor devices increases, the energy demand increases, and by using a semiconductor device of one embodiment of the present invention, the carbon dioxide (CO2 ) is a representative greenhouse gas emission. In addition, a semiconductor device according to one embodiment of the present invention has low power consumption and is therefore also effective as a measure against global warming.

[0543] At least a part of this embodiment mode can be implemented in combination with other embodiment modes described in this specification as appropriate.

[0544] [Explanation of symbols]

[0545] 10a: transistor, 10b: transistor, 10c: transistor, 10d: transistor, 10e: transistor, 10f: transistor, 10g: transistor, 10h: transistor, 10i: transistor, 10j: transistor, 10k: transistor, 10: transistor, 11: insulating layer, 20a: opening, 20b: opening, 20c: opening, 20d: opening, 21i: channel formation region, 21n: low resistance region, 21: semiconductor layer, 22: insulating layer, 23: conductive layer, 26: conductive layer, 27: insulating layer, 30: memory cell, 31: conductive layer, 32: conductive layer, 33: conductive layer, 34: conductive layer, 35: dummy layer, 41a: insulating layer, 41b: insulating layer, 41c: insulating layer, 41: insulating layer, 42: insulating layer, 44: insulating layer, 45: insulating layer, 46: insulating layer, 47: insulating layer, 48: insulating layer, 50: capacitor, 51: conductive layer, 52: conductive layer, 53: insulating layer, 60[1,1]: storage unit, 60[2,4]: storage unit, 60[a,b]: storage unit, 60: storage unit, 61: conductive layer, 62: conductive layer, 63: conductive layer, 65: insulating layer, 70[1]: layer, 70[2]: layer, 70[m]: layer, 70: layer, 90: transistor, 91: substrate, 92: semiconductor region, 93: insulating layer, 94: conductive layer, 95a: low resistance region, 95b: low resistance region.

Claims

1. A semiconductor device, include: transistor; a first insulating layer; as well as The second insulating layer, The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer and a third insulating layer. The first insulating layer is located above the first conductive layer and has a first opening reaching the first conductive layer. The second conductive layer is located above the first insulating layer, The semiconductor layer is in contact with the second conductive layer, the side surface of the first insulating layer in the first opening, and the top surface of the first conductive layer. The third insulating layer contacts the semiconductor layer in the first opening, The second insulating layer is located above the third insulating layer and has a second opening reaching the third insulating layer at a position overlapping with the first opening. Furthermore, the third conductive layer is provided in a manner of filling the second opening and the first opening.

2. The semiconductor device according to claim 1, The second insulating layer has a portion that is thicker than the third insulating layer.

3. The semiconductor device according to claim 1, further comprising: include: wiring, The wiring is in contact with the top surface of the third conductive layer and has a portion overlapping the semiconductor layer or the second conductive layer via the second insulating layer.

4. The semiconductor device according to claim 1, wherein the second opening has a portion extending in one direction, And a portion of the third conductive layer located in the second opening is used as a wiring.

5. The semiconductor device according to claim 1, The opening diameter of the upper end of the first opening is larger than the opening diameter of the lower end.

6. A method for manufacturing a semiconductor device, comprising the following steps: forming a first insulating layer having a first opening; forming a semiconductor layer in contact with a side surface of the first opening of the first insulating layer; forming a third insulating layer in a manner of covering the first insulating layer and the semiconductor layer; forming a dummy layer on the third insulating layer and at a position overlapping the first opening; forming a second insulating layer covering the third insulating layer and the dummy layer; Etching an upper portion of the second insulating layer to expose a top surface of the dummy layer; removing the dummy layer, and forming a second opening in the second insulating layer that overlaps with the first opening and reaches the third insulating layer; as well as A conductive layer is formed in the second opening.

7. The method for manufacturing a semiconductor device according to claim 6, The dummy layer is removed by wet etching.

8. The method for manufacturing a semiconductor device according to claim 6 or 7, further comprising the following steps: A wiring in contact with the conductive layer is formed on the second insulating layer.

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