Semiconductor device

Abstract

This semiconductor device is provided with a transistor section and a diode section, and is provided with: a plurality of trench sections that are provided on the front surface of a semiconductor substrate and that include a gate trench section; a drift region of a first conductivity type provided on the semiconductor substrate; a base region of a second conductivity type provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; a first accumulation region of a first conductivity type provided above the base region and having a doping concentration higher than that of the drift region; and a contact region of a second conductivity type provided above the base region and having a higher doping concentration than that of the base region, the transistor portion having a boundary region including a boundary mesa portion sandwiched by the plurality of trench portions and provided adjacent to the diode portion, the boundary region including: the emitter region; the first part is arranged on the boundary mesa part; a second accumulation region of the first conductivity type, which is provided in the boundary mesa portion, and which has a higher doping concentration than the first accumulation region; and a gate trench portion provided so as to be in contact with the boundary mesa portion.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] Patent Document 1 states that “the peak value of the doping concentration of the accumulation region 16 in the narrow-width mesa portion 61 may be higher than the peak value of the doping concentration of the accumulation region 16 in the mesa portion 60 ”.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2019-220940

[0006] Patent Document 2: Japanese Patent Application Publication No. 2020-177973

[0007] Patent Document 3: International Publication No. 2018-030440 Summary of the invention

[0008] Technical issues

[0009] It is desirable to reduce reverse recovery losses while maintaining the active region of a semiconductor device.

[0010] Technical Solution

[0011] In a first aspect of the present invention, a semiconductor device is provided, which includes a transistor portion and a diode portion, the semiconductor device including: a plurality of groove portions provided on the front surface of a semiconductor substrate and including a gate groove portion; a drift region of a first conductivity type provided on the semiconductor substrate; a base region of a second conductivity type provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a higher doping concentration than the drift region; a first accumulation region of a first conductivity type provided above the base region and having a higher doping concentration than the drift region; and a contact region of a second conductivity type provided above the base region and having a higher doping concentration than the base region. The transistor portion may have a boundary region including a boundary mesa portion sandwiched by the plurality of groove portions and provided adjacent to the diode portion. The boundary region may include: the emitter region, which is arranged in the boundary mesa portion; a second accumulation region of the first conductivity type, which is arranged in the boundary mesa portion and has a higher doping concentration than the first accumulation region; and the gate groove portion, which is arranged in contact with the boundary mesa portion.

[0012] In the above semiconductor device, the doping concentration of the second accumulation region may be lower than the doping concentration of the emitter region.

[0013] In any of the above semiconductor devices, the doping concentration of the second accumulation region may be 1E16 cm -3 Above and 1E19cm -3 the following.

[0014] In any of the above-mentioned semiconductor devices, the second accumulation region may have a plurality of doping concentration peaks in a depth direction of the semiconductor substrate.

[0015] In any of the above semiconductor devices, the second accumulation region may have one peak of doping concentration in a depth direction of the semiconductor substrate.

[0016] In any of the above-mentioned semiconductor devices, the thickness of the second accumulation region in the depth direction of the semiconductor substrate may be greater than or equal to 0.5 μm and less than or equal to 4.0 μm.

[0017] In any of the above-mentioned semiconductor devices, the diode portion may not include any of the first accumulation region and the second accumulation region.

[0018] In any of the above-mentioned semiconductor devices, in the trench arrangement direction of the plurality of trench portions, a mesa width of the boundary mesa portion may be larger than a mesa width of a mesa portion other than the boundary mesa portion.

[0019] In any of the semiconductor devices described above, a width of the boundary region in a trench arrangement direction of the plurality of trench portions may be greater than or equal to 30 μm and less than or equal to 150 μm.

[0020] Any of the above-mentioned semiconductor devices may include a trench contact portion provided on the front surface of the semiconductor substrate.

[0021] In any of the above-described semiconductor devices, in the transistor portion, a position of a lower end of the trench contact portion may be shallower than a position of a lower end of the emitter region in a depth direction of the semiconductor substrate.

[0022] Any of the above semiconductor devices may include a plug region of the second conductivity type, the plug region of the second conductivity type being provided in contact with a bottom surface of the trench contact portion and having a doping concentration higher than that of the base region.

[0023] In any of the above-mentioned semiconductor devices, in the transistor portion, the plug region may be provided so as to extend in a trench extending direction of the plurality of trench portions.

[0024] In any of the above-mentioned semiconductor devices, in the diode portion, the plug regions may be discretely provided in a trench extending direction of the plurality of trench portions.

[0025] In any of the above-mentioned semiconductor devices, the diode portion has a cathode region of the first conductivity type on the back side of the semiconductor substrate, the doping concentration of the cathode region of the first conductivity type is higher than the doping concentration of the drift region, and the cathode region may include a first cathode portion of the first conductivity type and a second cathode portion of the second conductivity type.

[0026] In any of the above-mentioned semiconductor devices, the semiconductor device may include an anode region of the second conductivity type in the diode portion, the anode region of the second conductivity type being provided closer to the front surface side of the semiconductor substrate than the drift region.

[0027] In any of the above semiconductor devices, the doping concentration of the anode region may be lower than the doping concentration of the base region.

[0028] In any of the above-mentioned semiconductor devices, the semiconductor substrate may not have a lifetime control body region inside.

[0029] It should be noted that the above invention summary does not list all the features of the present invention. In addition, sub-combinations of these feature groups can also constitute other inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 An example of a top view of the semiconductor device 100 is shown.

[0031] Figure 2A An example of a cross section of the semiconductor device 100 is shown.

[0032] Figure 2B An example of a cross section of the semiconductor device 100 is shown.

[0033] Figure 2C An example of a cross section of the semiconductor device 100 is shown.

[0034] Figure 3 An example of a cross section of the semiconductor device 200 is shown.

[0035] Figure 4A An example of a top view of a semiconductor device 500 according to a comparative example is shown.

[0036] Figure 4B An example of a cross section of a semiconductor device 500 according to a comparative example is shown.

[0037] Figure 4C An example of a cross section of a semiconductor device 600 according to a comparative example is shown.

[0038] Figure 5 Represents the relationship between steady-state loss and reverse recovery loss.

[0039] Explanation of symbols

[0040] 10···semiconductor substrate, 12···emitter region, 14···base region, 15···contact region, 16···first accumulation region, 17···well region, 18···drift region, 19···anode region, 20···trench contact portion, 21···front surface, 22···collector region, 23···back surface, 24···collector electrode, 25···connecting portion, 26···second accumulation region, 30···dummy trench portion, 31···extension portion, 32···dummy insulating film, 33···connecting portion, 34···dummy conductive portion, 38···interlayer insulating film, 40···gate Groove portion, 41···Extension portion, 42···Gate insulating film, 43···Connection portion, 44···Gate conductive portion, 50···Gate metal layer, 52···Emitter electrode, 55…Contact hole, 56…Contact hole, 70…Transistor portion, 71…Mesa portion, 73…Plug region, 75…Main region, 80…Diode portion, 81…Mesa portion, 82…Cathode region, 181…First cathode portion, 182…Second cathode portion, 83…Plug region, 90…Boundary region, 91…Mesa portion, 100…Semiconductor device, 200…Semiconductor device, 500…Semiconductor device, 600…Semiconductor device DETAILED DESCRIPTION

[0041] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention involved in the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the technical means of the invention.

[0042] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of a substrate, layer, or other component is referred to as an upper surface, and the other surface is referred to as a lower surface. The directions of "upper", "lower", "front", and "back" are not limited to the direction of gravity or the mounting direction toward the substrate when the semiconductor device is actually mounted.

[0043] In this specification, orthogonal coordinate axes such as the X-axis, Y-axis, and Z-axis are sometimes used to explain technical matters. Orthogonal coordinate axes only determine the relative positions of components and do not limit specific directions. For example, the Z-axis is not limited to indicating the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions to each other. When the Z-axis direction is recorded without recording the positive or negative, it refers to the direction parallel to the +Z-axis and the -Z-axis.

[0044] In this specification, the plane parallel to the upper surface of the semiconductor substrate is referred to as the XY plane, and the orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are referred to as the X axis and the Y axis. In addition, the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z axis. The depth direction of the semiconductor substrate is sometimes referred to as the Z axis. It should be noted that in this specification, the situation of observing the semiconductor substrate along the Z axis direction is referred to as a top view. In addition, in this specification, the direction including the X axis and the Y axis and parallel to the upper and lower surfaces of the semiconductor substrate is sometimes referred to as a horizontal direction.

[0045] In each embodiment, an example is shown in which the first conductivity type is set to N type and the second conductivity type is set to P type, but the first conductivity type may be set to P type and the second conductivity type may be set to N type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment become opposite polarities.

[0046] In this specification, when it is said that they are "same" or "equal", it may include the case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0047] In this specification, the conductivity type of the doped region doped with impurities is set to P type or N type for description. In this specification, impurities sometimes specifically refer to either N-type donors or P-type acceptors, and are sometimes described as dopants. In this specification, doping refers to the process of introducing donors or acceptors into a semiconductor substrate to form a semiconductor showing N-type conductivity or a semiconductor showing P-type conductivity.

[0048] In this specification, the doping concentration refers to the concentration of donors or the concentration of acceptors in a thermal equilibrium state.

[0049] In the present specification, when it is described as P+ type or N+ type, it means that the doping concentration is higher than the doping concentration of P type or N type, and when it is described as P- type or N- type, it means that the doping concentration is lower than the doping concentration of P type or N type. In addition, when it is described as P++ type or N++ type in the present specification, it means that the doping concentration is higher than the doping concentration of P+ type or N+ type.

[0050] Figure 1 An example of a top view of a semiconductor device 100 is shown. The semiconductor device 100 of this example is a semiconductor chip including a transistor unit 70 and a diode unit 80. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT). The transistor unit 70 of this example includes a boundary region 90 at a portion adjacent to the diode unit 80.

[0051] The transistor section 70 is a region obtained by projecting the collector region 22 provided on the back side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10 . The collector region 22 will be described later. The transistor section 70 includes a transistor such as an IGBT. The transistor section 70 of this example includes a main region 75 .

[0052] The main region 75 is a region excluding the boundary region 90 in the transistor portion 70. The first accumulation region 16 described below is provided in the main region 75, but the second accumulation region 26 is not provided. The main region 75 forms a channel region when the semiconductor device 100 operates and functions as an active region.

[0053] The diode section 80 is a region obtained by projecting a cathode region 82 provided on the back surface of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The cathode region 82 has a first conductivity type. As an example, the cathode region 82 in this example is an N-type. The diode section 80 includes a diode such as a freewheeling diode (FWD) provided adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10.

[0054] exist Figure 1 , the edge side of the semiconductor device 100, that is, the area around the chip end, is shown, while other areas are omitted. For example, an edge terminal structure portion may be provided in the area on the negative side in the Y-axis direction of the semiconductor device 100 in this example. The edge terminal structure portion alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge terminal structure portion includes, for example, a guard ring, a field plate, a surface electric field reduction portion, and a structure formed by combining them. It should be noted that in this example, for convenience, the edge on the negative side in the Y-axis direction is described, but the same is true for other edges of the semiconductor device 100. The edge terminal structure portion may be provided to surround an active portion having a transistor portion 70 and a diode portion 80.

[0055] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride, etc. The semiconductor substrate 10 in this example is a silicon substrate.

[0056] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, a well region 17, an anode region 19, and a trench contact portion 20 on the front surface 21 of the semiconductor substrate 10. The front surface 21 will be described later. In addition, the semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.

[0057] The emitter electrode 52 is disposed above the gate trench 40, the dummy trench 30, the emitter region 12, the base region 14, the contact region 15, the well region 17, the anode region 19, and the trench contact 20. In addition, the gate metal layer 50 is disposed above the gate trench 40 and the well region 17.

[0058] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing a metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al), or an alloy containing aluminum, such as an aluminum-silicon alloy (AlSi), an aluminum-silicon-copper alloy (AlSiCu), or other metal alloys. At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al), or an alloy containing aluminum, such as an aluminum-silicon alloy (AlSi), an aluminum-silicon-copper alloy (AlSiCu), or other metal alloys. The emitter electrode 52 and the gate metal layer 50 may have a barrier metal formed of titanium, a titanium compound, or the like in the lower layer of the region formed of aluminum or an alloy containing aluminum. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0059] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 via the interlayer insulating film 38. Figure 1 The interlayer insulating film 38 is omitted in FIG. The trench contact portion 20 , the contact hole 55 , and the contact hole 56 are provided through the interlayer insulating film 38 .

[0060] The trench contact portion 20 is provided to extend from the upper surface of the interlayer insulating film 38 in the depth direction of the semiconductor substrate 10. The trench contact portion 20 has a bottom and a side portion. The trench contact portion 20 electrically connects the emitter electrode 52 to the semiconductor substrate 10. The trench contact portion 20 is provided to extend in the trench extension direction. The trench contact portion 20 of this example is arranged in a stripe shape along the gate trench portion 40 and the dummy trench portion 30.

[0061] The trench contact portion 20 is formed on the upper surface of each region of the emitter region 12 and the contact region 15 in the transistor portion 70. The trench contact portion 20 is not provided above the well region 17 provided at both ends in the Y-axis direction. In this way, one or more trench contacts 20 are formed in the interlayer insulating film. One or more trench contacts 20 may be provided to extend along the extension direction.

[0062] The trench contact 20 is provided above the anode region 19 in the diode portion 80. The trench contact 20 is provided on the upper surfaces of the contact region 15 and the anode region 19 in the boundary region 90. None of the trench contacts 20 is provided above the well regions 17 provided at both ends in the Y-axis direction.

[0063] In the transistor portion 70, a plug region 73 is provided below the trench contact portion 20. In addition, in the diode portion 80, a plug region 83 is provided below the trench contact portion 20. The plug region 73 and the plug region 83 will be described in detail later.

[0064] The contact hole 55 connects the gate metal layer 50 and the gate conductive portion in the transistor portion 70. A plug made of tungsten or the like may be formed inside the contact hole 55 via a barrier metal.

[0065] The contact hole 56 connects the emitter electrode 52 to the dummy conductive portion in the dummy trench portion 30. A plug made of tungsten or the like may be formed inside the contact hole 56 via a barrier metal.

[0066] The connection portion 25 electrically connects the front side electrode such as the emitter electrode 52 or the gate metal layer 50 to the semiconductor substrate 10. In one example, the connection portion 25 is provided between the gate metal layer 50 and the gate conductive portion. The connection portion 25 is also provided between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is a conductive material such as polysilicon doped with impurities. The connection portion 25 of this example is polysilicon doped with N-type impurities (N+). The connection portion 25 is provided above the front side 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0067] The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (in this example, the X-axis direction). The gate trench portions 40 of this example may include two extension portions 41 extending along an extension direction (in this example, the Y-axis direction) parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connection portion 43 connecting the two extension portions 41.

[0068] At least a portion of the connection portion 43 may be formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate groove portion 40, the electric field concentration at the ends of the extension portion 41 can be alleviated. At the connection portion 43 of the gate groove portion 40, the gate metal layer 50 may be connected to the gate conductive portion.

[0069] The dummy groove portion 30 is a groove portion electrically connected to the emitter electrode 52. The dummy groove portion 30 is arranged at a predetermined interval along a predetermined arrangement direction (in this example, the X-axis direction) similarly to the gate groove portion 40. The dummy groove portion 30 of this example may have a U-shape on the front surface 21 of the semiconductor substrate 10 similarly to the gate groove portion 40. That is, the dummy groove portion 30 may have two extension portions 31 extending along the extension direction, and a connection portion 33 connecting the two extension portions 31.

[0070] The main region 75 in the transistor section 70 of this example has a structure in which a pattern in which two dummy trench sections 30 are arranged between two gate trench sections 40 is repeatedly arranged. That is, the transistor section 70 of this example has the gate trench section 40 and the dummy trench section 30 at a ratio of 1:1. For example, the transistor section 70 has two extension sections 31 between two extension sections 41. In addition, the transistor section 70 has a portion where the two extension sections 41 are adjacent to each other.

[0071] However, the ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio of the gate trench portion 40 to the dummy trench portion 30 may be 2:3 or 2:4. In addition, the transistor portion 70 may have all trench portions as gate trench portions 40 without having dummy trench portions 30.

[0072] The gate trench 40 and the dummy trench 30 are provided in the boundary region 90 of the transistor portion 70 of this example. By providing the gate trench 40, the area of ​​the active region of the transistor portion 70 can be increased, and the operation efficiency of the semiconductor device 100 can be improved.

[0073] The well region 17 is a region of the second conductivity type provided on the front surface 21 side of the semiconductor substrate 10 more closely than the drift region 18 described later. The well region 17 is an example of a well region provided on the edge side of the semiconductor device 100. As an example, the well region 17 is of P+ type. The well region 17 is formed within a predetermined range from the end of the active portion on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depth of the gate groove portion 40 and the dummy groove portion 30. A portion of the gate metal layer 50 side of the gate groove portion 40 and the dummy groove portion 30 is formed in the well region 17. The bottom of the ends of the gate groove portion 40 and the dummy groove portion 30 in the extension direction may be covered by the well region 17.

[0074] The mesa portion 71 is a mesa portion provided adjacent to the groove portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion refers to a portion of the semiconductor substrate 10 sandwiched between two adjacent groove portions, and may be a portion from the front surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of each groove portion. The extension portion of each groove portion may be regarded as one groove portion. That is, the area sandwiched between two extension portions may be regarded as a mesa portion.

[0075] In the transistor portion 70, the mesa portion 71 is provided adjacent to at least one of the dummy trench portion 30 and the gate trench portion 40. The mesa portion 71 has the well region 17, the emitter region 12, the base region 14, and the contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter region 12 and the contact region 15 are alternately provided in the extension direction.

[0076] The base region 14 is a second conductivity type region provided on the front surface 21 side of the semiconductor substrate 10. As an example, the base region 14 is a P-type. The base region 14 can be provided at both ends of the mesa portion 71 in the Y-axis direction on the front surface 21 of the semiconductor substrate 10. Figure 1 Only one end portion of the base region 14 in the Y-axis direction is shown.

[0077] The emitter region 12 is a region of the first conductivity type disposed on the front surface 21 of the semiconductor substrate 10 and having a doping concentration higher than that of the drift region 18. As an example, the emitter region 12 of this example is of N++ type. An example of a dopant of the emitter region 12 is arsenic (As). The emitter region 12 is disposed in contact with the gate groove portion 40 on the front surface 21 of the mesa portion 71. The emitter region 12 can be disposed so as to extend along the X-axis direction from one of the two groove portions sandwiching the mesa portion 71 to the other.

[0078] In addition, the emitter region 12 may or may not be in contact with the dummy groove portion 30. In this example, the emitter region 12 is in contact with the dummy groove portion 30.

[0079] The contact region 15 is a region of the second conductivity type having a higher doping concentration than the base region 14. As an example, the contact region 15 of this example is of P+ type. The contact region 15 of this example is provided on the front surface 21 of the mesa portion 71. The contact region 15 may be provided extending along the X-axis direction from one of the two groove portions sandwiching the mesa portion 71 to the other. The contact region 15 may be in contact with the gate groove portion 40 or the dummy groove portion 30, or may not be in contact with the gate groove portion 40 or the dummy groove portion 30. The contact region 15 of this example is in contact with the dummy groove portion 30 and the gate groove portion 40.

[0080] The boundary region 90 is a region provided in the transistor portion 70 and adjacent to the diode portion 80. The boundary region 90 has the emitter region 12 and the contact region 15. The boundary region 90 of this example is arranged so that both ends in the X-axis direction become the gate trench portions 40.

[0081] The structure of the front surface 21 of the boundary region 90 may correspond to the structure of the front surface 21 of the main region 75. That is, the boundary region 90 may also be a region in which a channel is formed when the semiconductor device 100 operates and functions as an active region. The boundary region 90 may have the same structure as the main region 75 except that the second accumulation region 26 described later is provided instead of the first accumulation region 16.

[0082] The mesa portion 91 is provided in the boundary region 90. The mesa portion 91 has an emitter region 12 and a contact region 15 at the front surface 21 of the semiconductor substrate 10. The mesa portion 91 of this example has a base region 14 and a well region 17 on the negative side in the Y-axis direction. The mesa portion 91 may also have a base region 14 and a well region 17 on the positive side in the Y-axis direction.

[0083] In this example, a plurality of mesa portions 91 are provided in the boundary region 90. One mesa portion 91 may be provided in the boundary region 90. The width of the boundary region 90 in the groove arrangement direction (X-axis direction) of the plurality of groove portions may be 30 μm or more and 150 μm or less.

[0084] The mesa portion 81 is provided in a region sandwiched between adjacent dummy trench portions 30 in the diode portion 80. The mesa portion 81 has the anode region 19 on the front surface 21 of the semiconductor substrate 10. The mesa portion 81 of this example has the anode region 19 and the well region 17 on the negative side in the Y-axis direction.

[0085] The anode region 19 is a region of the second conductivity type. The doping concentration of the anode region 19 may be lower than the doping concentration of the base region 14. As an example, the anode region 19 of this example is of P-- type. The anode region 19 of this example is disposed on the front side 21 of the mesa portion 81. The anode region 19 may be disposed extending along the X-axis direction from one of the two dummy groove portions 30 sandwiching the mesa portion 81 to the other. The anode region 19 may be connected to the gate groove portion 40 at the boundary between the transistor portion 70 and the diode portion 80, or may not be connected to the gate groove portion 40 at the boundary between the transistor portion 70 and the diode portion 80. The anode region 19 of this example is connected to the gate groove portion 40 at the boundary between the transistor portion 70 and the diode portion 80.

[0086] The doping concentration of the anode region 19 in this example can be 1E16 cm -3 Above and 1E17cm -3 It should be noted that E refers to a power of 10, for example 1E16cm -3 It means 1×10 16 cm -3 The anode region 19 may have a peak of doping concentration in the depth direction of the semiconductor substrate 10. In addition, in the depth direction of the semiconductor substrate 10, the lower end of the anode region 19 may be at the same depth as the lower end of the base region 14, or may be located deeper than the lower end of the base region 14.

[0087] Figure 2A yes Figure 1 1 is an example of the a-a' cross section in FIG. The a-a' cross section is an XZ plane that does not pass through the plug region 83 described later in the transistor portion 70 and the diode portion 80. The semiconductor device 100 of this example includes a semiconductor substrate 10, a drift region 18, a first storage region 16, a second storage region 26, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the a-a' cross section. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0088] The drift region 18 is a region of the first conductivity type provided in the semiconductor substrate 10. As an example, the drift region 18 of this example is of N-type. The drift region 18 may be a region remaining without forming other doping regions in the semiconductor substrate 10. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0089] The collector region 22 is provided on the back surface 23 of the semiconductor substrate 10 in the transistor portion 70. The collector region 22 is a second conductivity type region having a doping concentration higher than that of the base region 14. As an example, the collector region 22 in this example is a P type.

[0090] The cathode region 82 is provided on the back surface 23 of the semiconductor substrate 10 in the diode portion 80. The cathode region 82 is a region of the first conductivity type having a doping concentration higher than that of the drift region 18. As an example, the cathode region 82 in this example is of N type.

[0091] The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor portion 70 and the diode portion 80. That is, the collector region 22 is provided below the boundary region 90 in this example. In addition, the cathode region 82 may include a first cathode portion 181 and a second cathode portion 182, as will be described in detail later.

[0092] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as metal.

[0093] The base region 14 is a region of the second conductivity type disposed above the drift region 18. The doping concentration of the base region 14 may be higher than the doping concentration of the anode region 19. The doping concentration of the base region 14 may be 3E16 cm -3 Above and 1E18cm -3 The base region 14 may be provided below the emitter region 12 . The base region 14 may be provided in contact with the gate trench portion 40 . The base region 14 may be provided in contact with the dummy trench portion 30 .

[0094] The first accumulation region 16 is a region of the first conductivity type provided at a position lower than the base region 14 in the depth direction of the semiconductor substrate 10. As an example, the first accumulation region 16 of this example is N-type. The first accumulation region 16 is provided in the main region 75 of the transistor portion 70, but not in the diode portion 80 and the boundary region 90. By providing the first accumulation region 16, it is possible to increase the carrier injection enhancement effect (IE effect) and reduce the on-voltage of the transistor portion 70.

[0095] A plurality of first accumulation regions 16 may be provided in the depth direction of the semiconductor substrate 10. In one example, the first accumulation region 16 is provided in two sections, namely, first accumulation regions 16a and 16b. The thicknesses of the first accumulation regions 16a and 16b in the depth direction of the semiconductor substrate 10 may be the same or different. A drift region 18 may be provided between the first accumulation regions 16a and 16b.

[0096] The first accumulation region 16 may be provided in three or more stages. In this case, the lower end of the first accumulation region 16 provided on the side closest to the back surface 23 among the first accumulation regions 16 may be located above the bottom of the adjacent groove portion. By providing the first accumulation region 16 in multiple stages, the clamping tolerance can be improved.

[0097] The second accumulation region 26 is a region of the first conductivity type provided below the base region 14 in the depth direction of the semiconductor substrate 10. As an example, the second accumulation region 26 of this example is of N+ type. The second accumulation region 26 is provided in the boundary region 90, but not in the diode portion 80 and the main region 75. By providing the second accumulation region 26, it is possible to suppress the injection of holes into the diode portion 80, and to reduce the reverse recovery loss Err. In addition, by not providing any of the first accumulation region 16 and the second accumulation region 26 in the diode portion 80, it is possible to suppress the increase in the steady-state loss Vf of the diode portion.

[0098] The doping concentration of the second accumulation region 26 may be higher than that of the first accumulation region 16. By making the doping concentration of the second accumulation region 26 higher than that of the first accumulation region 16, the reverse recovery loss Err can be reduced. The doping concentration of the first accumulation region 16 may be 1E16cm -3 Above and 1E18cm -3 Below, the doping concentration of the second accumulation region 26 can be 1E16cm -3 Above and 1E20cm -3 The doping concentration of the second accumulation region 26 may be lower than the doping concentration of the emitter region 12 .

[0099] A plurality of second accumulation regions 26 may be provided in the depth direction of the semiconductor substrate 10. In one example, the second accumulation region 26 is divided into two sections, namely, second accumulation regions 26a and 26b. The thicknesses of the second accumulation regions 26a and 26b in the depth direction of the semiconductor substrate 10 may be the same or different. A drift region 18 may be provided between the second accumulation regions 26a and 26b.

[0100] The second accumulation region 26 may have one peak of doping concentration in the depth direction of the semiconductor substrate 10, or may have multiple peaks of doping concentration in the depth direction of the semiconductor substrate 10. In this example, the second accumulation region 26 is divided into two sections, namely, the second accumulation region 26a and 26b, and has two peaks of doping concentration. The second accumulation region 26 may be divided into three or more sections. The number of sections of the second accumulation region 26 may be the same as or different from the number of sections of the first accumulation region 16. By making the second accumulation region 26 have multiple peaks of doping concentration, it is possible to increase the dose while reducing the concentration of each peak, thereby suppressing the reduction of clamping tolerance.

[0101] The thickness of the second accumulation region 26 in the depth direction of the semiconductor substrate 10 may be thinner than the thickness of the base region 14. In the present specification, the thickness of the second accumulation region 26 may refer to the length from the upper end of the second accumulation region 26 closest to the front surface 21 to the lower end of the second accumulation region 26 closest to the back surface 23 in the depth direction of the semiconductor substrate 10. In one example, the thickness of the second accumulation region 26 is greater than or equal to 0.5 μm and less than or equal to 4.0 μm.

[0102] One or more gate groove portions 40 and one or more dummy groove portions 30 are provided on the front side 21. Each groove portion is provided from the front side 21 to the drift region 18. In the region where at least any one of the emitter region 12, the base region 14, the contact region 15, the first accumulation region 16, the anode region 19, and the second accumulation region 26 is provided, each groove portion also penetrates these regions to reach the drift region 18. The groove portion penetrating the doped region is not limited to being manufactured in the order of forming the groove portion after forming the doped region. The case where the doped region is formed between the groove portions after the groove portion is formed is also included in the case where the groove portion penetrates the doped region.

[0103] The gate groove portion 40 has a gate groove formed on the front side 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate groove. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate groove. The gate conductive portion 44 is formed inside the gate groove at a position closer to the inside than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate groove portion 40 is covered by an interlayer insulating film 38 at the front side 21.

[0104] The gate conductive portion 44 includes a region facing the base region 14 adjacent to the mesa portion 71 via the gate insulating film 42 in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an inversion layer of electrons is formed in the surface layer of the interface in the base region 14 that is in contact with the gate trench.

[0105] The dummy groove portion 30 may have the same structure as the gate groove portion 40. The dummy groove portion 30 includes a dummy groove formed on the front side 21, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is formed to cover the inner wall of the dummy groove. The dummy conductive portion 34 is formed inside the dummy groove and is formed at a position further inside than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy groove portion 30 is covered by an interlayer insulating film 38 at the front side 21.

[0106] The interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or more trench contacts 20 for electrically connecting the emitter electrode 52 to the semiconductor substrate 10. The contact holes 55 and 56 may also be provided to penetrate the interlayer insulating film 38 in the same manner as the trench contacts 20.

[0107] The trench contact portion 20 penetrates the interlayer insulating film 38 and reaches the emitter region 12 or the anode region 19. The trench contact portion 20 electrically connects the emitter electrode 52 to the semiconductor substrate 10. In this example, the depth of the lower end of the trench contact portion 20 is shallower than the depth of the lower end of the emitter region 12. Thus, the threshold Vth of the semiconductor device 100 can be suppressed from rising, and the variation in the characteristics of the semiconductor device 100 can be suppressed.

[0108] The depth of the lower end of the trench contact portion 20 may be deeper than the depth of the lower end of the emitter region 12. By making the depth of the lower end of the trench contact portion 20 deeper than the depth of the lower end of the emitter region 12, the latch-up resistance can be improved. The depth of the lower end of the trench contact portion 20 may be greater than or equal to 0.3 μm and less than or equal to 0.5 μm from the front surface 21 of the semiconductor substrate 10.

[0109] The plug region 73 is a region of the second conductivity type provided below the bottom of the trench contact portion 20 in the transistor portion 70 and having a doping concentration higher than that of the base region 14. The doping concentration of the plug region 73 may be 1E19 cm -3 Above and 1E22cm -3 As an example, the plug region 73 of this example is of P++ type. The plug region 73 may be provided so as to cover the bottom and a part of the side wall of the trench contact portion 20 .

[0110] In one example, the plug region 73 is formed by implanting dopants through the trench contact portion 20. Alternatively, the trench contact portion 20 may be provided after the plug region 73 is formed.

[0111] The doping concentration of the plug region 73 may be higher than the doping concentration of the contact region 15 . In addition, the doping concentration of the plug region 73 may be the same as the doping concentration of the contact region 15 .

[0112] The plug region 73 is continuously provided in the trench extending direction in the mesa portion 71 and the mesa portion 91. That is, the plug region 73 is provided in a stripe shape in the mesa portion 71 and the mesa portion 91. By providing the plug region 73, the resistance of the bottom of the trench contact portion 20 in the transistor portion 70 can be reduced, and latch-up breakdown can be suppressed.

[0113] Figure 2B yes Figure 1 The bb' cross section is an example of the bb' cross section in FIG. The bb' cross section is an XZ plane passing through the plug region 83 in the transistor portion 70 and the diode portion 80. The structure included in the bb' cross section may be the same as the aa' cross section except for the plug region 83.

[0114] The plug region 83 is a region of the second conductivity type provided below the bottom of the trench contact portion 20 in the diode portion 80 and having a doping concentration higher than that of the anode region 19. The doping concentration of the plug region 83 may be 1E19 cm -3 Above and 1E22cm -3 The doping concentration of the plug region 83 may be the same as that of the plug region 73 in the transistor portion. As an example, the plug region 83 of this example is of P++ type. The plug region 83 may be provided to cover the bottom and part of the sidewall of the trench contact portion 20 .

[0115] The plug regions 83 are selectively provided along the trench extending direction in the land portion 81. That is, the plug regions 83 are provided in a dot shape in the land portion 81. The plug regions 83 may be selectively provided at equal intervals in the trench extending direction.

[0116] In one example, the plug region 83 is formed by implanting dopants through the trench contact 20. Alternatively, the trench contact 20 may be provided after the plug region 83 is formed.

[0117] By providing the plug region 83, the resistance at the bottom of the trench contact portion 20 in the diode portion 80 is reduced, and the steady-state loss Vf can be reduced. Although the steady-state loss Vf increases when the cathode region 82 described later is provided with the first cathode portion 181 and the second cathode portion 182, the value of the steady-state loss Vf increased by the second cathode portion 182 is reduced by adding the plug region 83, thereby reducing the switching loss.

[0118] Figure 2C yes Figure 1 The c-c' cross section is a YZ plane passing through the center of the width of the trench contact portion 20 in the X-axis direction in the diode portion 80. The semiconductor device 100 of this example has a semiconductor substrate 10, an emitter electrode 52, and a collector electrode 24 in the c-c' cross section.

[0119] The first cathode portion 181 is a region of the first conductivity type having a higher doping concentration than the drift region 18. In one example, the first cathode portion 181 is N-type. The width of the first cathode portion 181 in the trench extension direction (Y-axis direction) may be greater than the width of the second cathode portion 182 in the trench extension direction.

[0120] The second cathode portion 182 is a region of the second conductivity type provided adjacent to the first cathode portion 181 on the back surface 23 of the semiconductor substrate 10. That is, the second cathode portion 182 may be directly in contact with the first cathode portion 181. In one example, the second cathode portion 182 is of P type.

[0121] The first cathode portion 181 may be formed by ion implanting a P-type dopant and then flipping it with an N-type dopant in the ion implantation process for forming the second cathode portion 182. Conversely, the second cathode portion 182 may be formed by ion implanting an N-type dopant and then flipping it with a P-type dopant in the ion implantation process for forming the first cathode portion 181.

[0122] The first cathode portion 181 and the second cathode portion 182 are configured in a manner to form a boundary in contact with each other. The first cathode portion 181 and the second cathode portion 182 can be alternately configured in any direction. The first cathode portion 181 and the second cathode portion 182 of this example are alternately arranged in the groove extension direction (for example, the Y-axis direction), but can also be alternately arranged in the groove arrangement direction (for example, the X-axis direction). The first cathode portion 181 and the second cathode portion 182 can be configured in a stripe shape when viewed from above. One of the first cathode portion 181 and the second cathode portion 182 can be formed in a dot shape.

[0123] The cathode region 82 in the diode portion 80 of this example has a first cathode portion 181 and a second cathode portion 182 arranged to form a boundary in contact with each other. By providing the first cathode portion 181 and the second cathode portion 182 in the cathode region 82, the surge voltage can be reduced and the reverse recovery time of the diode portion can be shortened, thereby reducing the reverse recovery loss Err.

[0124] In addition, the semiconductor device 100 of this example is provided with a second accumulation region 26 in the boundary region 90. By providing the second accumulation region 26, the trade-off curve between the reverse recovery loss Err and the steady-state loss Vf can be adjusted in the direction of reducing the reverse recovery loss Err. By using the second accumulation region 26 in combination with the first cathode portion 181 and the second cathode portion 182, the reverse recovery loss Err and the steady-state loss Vf can be finely adjusted according to the required performance.

[0125] The semiconductor device 100 of this example does not have a lifetime control body region inside the semiconductor substrate 10. Generally, by providing the lifetime control body region in both the transistor portion 70 and the diode portion 80, hole injection from the transistor portion 70 can be suppressed, thereby reducing the reverse recovery loss Err. In this example, the reverse recovery loss Err is reduced by providing the trench contact portion 20 instead of providing the lifetime control body region.

[0126] Figure 3 yes Figure 1 A deformation example of the a-a' section in FIG. Figure 3 In the a-a' section, the second accumulation area 26 is set as one section. Figure 3 In the modified example, the thickness of the second accumulation region 26 in the depth direction of the semiconductor substrate 10 is thinner than the thickness of the first accumulation region 16 in the depth direction of the semiconductor substrate 10. The second accumulation region 26 may be provided so that the lower end thereof is located above the bottom of the adjacent gate trench portion 40.

[0127] Figure 3 The second accumulation region 26 in the modified example can be provided in a manner that does not have a peak in doping concentration but has a wider distribution of doping concentration. The wide distribution of doping concentration means that the amount of change in doping concentration can be less than 5% in the range of 1.0 μm to 3.5 μm by changing the acceleration voltage for injecting dopants and performing it in multiple steps, or can be less than 5% in the range of 90% of the thickness of the second accumulation region 26. By providing the second accumulation region 26 in a manner that has a wider distribution of doping concentration, the clamping tolerance can be further improved compared to the case where it is provided in multiple stages.

[0128] In this example, the pitch width W91 of the boundary mesa portion 91 of the boundary region 90 is the same as the pitch width W71 of the mesa portion 71 of the transistor portion and the pitch width W81 of the mesa portion 81 of the diode portion. The pitch width W91 of the boundary mesa portion 91 may be wider than the pitch width W71 of the transistor portion and the pitch width W81 of the diode portion. By making the pitch width W91 of the boundary mesa portion 91 wider than the pitch width W71 of the transistor portion and the pitch width W81 of the diode portion, the injection of holes into the diode portion 80 can be suppressed, and the reverse recovery loss Err can be reduced.

[0129] In this example, the boundary region 90 is provided over the plurality of mesa portions. The width of the boundary region 90 in the groove arrangement direction (X-axis direction) of the plurality of groove portions may be 30 μm or more and 150 μm or less.

[0130] The semiconductor device 200 of this example does not have a lifetime control body region inside the semiconductor substrate 10, similarly to the semiconductor device 100. Generally, by providing the lifetime control body region in both the transistor portion 70 and the diode portion 80, hole injection from the transistor portion 70 can be suppressed, thereby reducing the reverse recovery loss Err. In this example, the reverse recovery loss Err is reduced by providing the trench contact portion 20 instead of providing the lifetime control body region.

[0131] Although not shown in the figure, in the transistor portion 70, a second conductive type trench bottom region formed in a manner covering the bottom and a portion of the side of the trench portion may be provided at the lower end of the gate trench portion 40 and the dummy trench portion 30. The trench bottom region is provided in a manner not connected to the first accumulation region 16 and the second accumulation region 26. As an example, the trench bottom region is of P+ type. The doping concentration of the trench bottom region may be higher than the doping concentration of the base region 14, and may be lower than the doping concentration of the contact region 15. By providing the trench bottom region, the electric field concentration at the bottom of the trench portion can be alleviated.

[0132] Figure 4A An example of a top view of a semiconductor device 500 according to Comparative Example 1 is shown. Figure 4A In the embodiment, the boundary region 90 does not have the emitter region 12 but has the dummy groove portion 30, which is different from Figure 1 The embodiments are different.

[0133] In the semiconductor device 500 of Comparative Example 1, the boundary region 90 does not have the emitter region 12 and therefore cannot function as an active region. In the semiconductor devices 100 and 200 of this example, since the emitter region 12 is also provided in the boundary region 90, the area of ​​the active region of the transistor portion 70 can be increased compared to the semiconductor device 500 of Comparative Example 1.

[0134] Figure 4B yes Figure 4A An example of a d-d' section in FIG. The d-d' line corresponds to Figure 1 The b-b' line in Figure 4B In the semiconductor device 500 of Comparative Example 1 shown in FIG, the second accumulation region 26 is not provided in the boundary region 90. In the semiconductor devices 100 and 200 of this example, by providing the second accumulation region 26 in the boundary region 90, the injection of holes from the transistor portion 70 can be suppressed, and the reverse recovery loss Err can be reduced.

[0135] Figure 4C yes Figure 4A Deformation example of the d-d' section in. Figure 4C In the semiconductor device 600 of the comparative example 2 shown in FIG. 1 , the first accumulation region 16 is provided in the boundary region 90. Figure 4BThe semiconductor device 600 of the comparative example 2 is different from the semiconductor device 500 of the comparative example 1 shown in FIG. 1 . The semiconductor device 600 of the comparative example 2 has the first accumulation region 16 in the boundary region 90 . Therefore, the injection of holes from the transistor portion 70 can be suppressed, and the reverse recovery loss Err can be reduced compared to the semiconductor device 500 of the comparative example 1.

[0136] Figure 4C The semiconductor device 600 of the comparative example 2 shown does not have an emitter region 12 in the boundary region 90, so the boundary region 90 cannot operate as an active region. Since the semiconductor devices 100 and 200 of this example have an emitter region 12 in the boundary region 90, the area of ​​the active region of the transistor portion 70 can be increased compared to the semiconductor device 600 of the comparative example 2.

[0137] Figure 5 is a graph showing the relationship between the steady-state loss Vf and the reverse recovery loss Err. In the figure, the comparative example 1 indicated by the circle corresponds to Figure 4B The semiconductor device 500 of the comparative example 1 shown in FIG. 1 corresponds to the semiconductor device 500 of the comparative example 2 indicated by the triangle mark. Figure 4C The semiconductor device 600 of the comparative example 2 is shown in FIG. Figure 4C In the semiconductor device 600 shown, the doping concentration of the first accumulation region 16 is increased compared with the comparative example 2.

[0138] If you will Figure 5 By comparing Comparative Example 1 with Comparative Example 2, it can be seen that by setting the first accumulation region 16 in the boundary region 90, the steady-state loss Vf is slightly increased and the reverse recovery loss Err is reduced. In addition, by comparing Comparative Example 2 with Comparative Example 3, it can be seen that by increasing the doping concentration of the first accumulation region 16, the reverse recovery loss Err can be further reduced.

[0139] like Figure 5 As indicated by the cross mark, the semiconductor device 100 of this example can suppress hole injection from the transistor portion 70 to the diode portion 80 compared to Comparative Example 1, and can further reduce the steady-state loss Vf compared to Comparative Examples 1, 2, and 3 while maintaining the reverse recovery loss Err. In addition, since the boundary region 90 in the semiconductor device 100 of this example can function as an active region, the operation efficiency is improved compared to Comparative Examples 1, 2, and 3.

[0140] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. According to the description of the claims, the method to which such changes or improvements are made can also be included in the technical scope of the present invention.

[0141] It should be noted that the execution order of each process such as actions, processes, steps and stages in the device, system, program and method shown in the claims, specifications and drawings can be implemented in any order as long as "earlier than" or "in advance" is not specifically stated, and the previous processing results are not used in the subsequent processing. Even if the action flow in the claims, specifications and drawings is explained using "first" or "next" for convenience, it does not mean that it must be implemented in this order.

Claims

1. A semiconductor device, characterized in that: A transistor portion and a diode portion are provided, The semiconductor device comprises: A plurality of groove portions, which are disposed on the front surface of the semiconductor substrate and include a gate groove portion; A drift region of a first conductivity type, which is disposed on the semiconductor substrate; A base region of a second conductivity type, which is disposed above the drift region; An emitter region of the first conductivity type, which is disposed above the base region and has a doping concentration higher than that of the drift region; A first accumulation region of a first conductivity type, which is disposed above the base region and has a doping concentration higher than that of the drift region; as well as a contact region of the second conductivity type, which is disposed above the base region and has a doping concentration higher than that of the base region, The transistor portion has a boundary region including a boundary mesa portion sandwiched by the plurality of trench portions and is disposed adjacent to the diode portion. The boundary area includes: The emission area is arranged on the boundary table portion; A second accumulation region of the first conductivity type, which is disposed in the boundary mesa portion and has a doping concentration higher than that of the first accumulation region; and The gate trench portion is disposed in contact with the boundary mesa portion.

2. The semiconductor device according to claim 1, wherein: The doping concentration of the second accumulation region is lower than the doping concentration of the emission region.

3. The semiconductor device according to claim 1, wherein: The doping concentration of the second accumulation region is 1E16 cm -3 Above and 1E20cm -3 the following.

4. The semiconductor device according to claim 1, wherein: The second accumulation region has a plurality of doping concentration peaks in a depth direction of the semiconductor substrate.

5. The semiconductor device according to claim 1, wherein: The second accumulation region has a peak of doping concentration in a depth direction of the semiconductor substrate.

6. The semiconductor device according to claim 5, wherein: The second accumulation region has a thickness of 0.5 μm or more and 4.0 μm or less in a depth direction of the semiconductor substrate.

7. The semiconductor device according to claim 1, wherein: The diode unit does not have any of the first accumulation region and the second accumulation region.

8. The semiconductor device according to claim 1, wherein: In the groove arrangement direction of the plurality of groove portions, a mesa width of the boundary mesa portion is larger than a mesa width of a mesa portion other than the boundary mesa portion.

9. The semiconductor device according to claim 1, wherein: The width of the boundary region in the groove arrangement direction of the plurality of groove portions is greater than or equal to 30 μm and less than or equal to 150 μm.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that The semiconductor device includes a trench contact portion provided on the front surface of the semiconductor substrate.

11. The semiconductor device according to claim 10, wherein: In the transistor portion, a position of a lower end of the trench contact portion is shallower than a position of a lower end of the emitter region in a depth direction of the semiconductor substrate.

12. The semiconductor device according to claim 10, wherein: The semiconductor device includes a plug region of the second conductivity type, which is provided in contact with a bottom surface of the trench contact portion and has a doping concentration higher than that of the base region.

13. The semiconductor device according to claim 12, wherein: In the transistor portion, the plug region is provided extending in a trench extending direction of the plurality of trench portions.

14. The semiconductor device according to claim 12, wherein: In the diode portion, the plug regions are discretely provided in a trench extending direction of the plurality of trench portions.

15. The semiconductor device according to any one of claims 1 to 9, characterized in that The diode portion includes a cathode region of the first conductivity type on the back surface of the semiconductor substrate, and the doping concentration of the cathode region of the first conductivity type is higher than the doping concentration of the drift region. The cathode region includes a first cathode portion of a first conductivity type and a second cathode portion of a second conductivity type.

16. The semiconductor device according to any one of claims 1 to 9, characterized in that The semiconductor device includes an anode region of a second conductivity type in the diode portion, and the anode region of the second conductivity type is provided closer to the front surface side of the semiconductor substrate than the drift region.

17. The semiconductor device according to claim 16, wherein: The doping concentration of the anode region is lower than the doping concentration of the base region.

18. The semiconductor device according to any one of claims 1 to 9, characterized in that There is no lifetime control volume region inside the semiconductor substrate.

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