Substrate isolated strained gate all-around field effect transistor

Abstract

A gate all-around transistor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate. The substrate includes a plurality of isolation regions formed in the substrate, the plurality of isolation regions including an isolation material. The substrate further comprises buffer areas formed in the substrate, and the buffer areas separate the adjacent isolation areas. The semiconductor device further includes a plurality of fins, each fin formed on a corresponding isolation region of the plurality of isolation regions. Each fin includes a buffer layer in contact with an isolation material and a plurality of silicon layers and a plurality of silicon germanium layers, the plurality of silicon layers and the plurality of silicon germanium layers being alternately arranged in a plurality of stack pairs on the buffer layer.

Description

Technical Field

[0001] The present disclosure relates to transistor devices and methods for manufacturing transistor devices. More specifically, the present disclosure relates to gate-all-around (GAA) transistor devices and methods for manufacturing the same. Background Art

[0002] The electronics industry is experiencing an increasing demand for smaller and faster electronic devices that are simultaneously capable of supporting a greater number of increasingly complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby increasing production efficiency and reducing associated costs. However, this miniaturization has introduced greater complexity to the semiconductor manufacturing process. Therefore, achieving continued advancements in semiconductor ICs and devices requires similar advances in semiconductor manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced in an attempt to improve gate control by increasing gate-channel coupling, reduce off-state current, and reduce short-channel effect (SCE). One such multi-gate device that has been introduced is the gate-all-around transistor (GAA). In a GAA device, all side surfaces of the channel region are surrounded by the gate electrode, which results in more complete depletion in the channel region and less short-channel effect due to steeper subthreshold current swing and less drain induced barrier lowering (DIBL).

[0004] As transistor dimensions scale to smaller technology nodes, further improvements are needed in GAA design and manufacturing. Summary of the invention

[0005] The present disclosure relates to transistor devices and methods for manufacturing transistor devices. More particularly, the present disclosure relates to GAA transistor devices and methods for manufacturing the same.

[0006] In at least one aspect, a semiconductor device is provided. The semiconductor device includes a substrate. The substrate includes a plurality of isolation regions formed in the substrate, the plurality of isolation regions including isolation material. The substrate further includes a buffer region formed in the substrate, the buffer region separating adjacent isolation regions. The semiconductor device further includes a plurality of fins, each fin being formed on a corresponding isolation region in the plurality of isolation regions. Each fin includes a buffer layer contacting the isolation material and a plurality of silicon layers and a plurality of silicon germanium layers, the plurality of silicon layers and the plurality of silicon germanium layers being alternately arranged in a plurality of stacked pairs on the buffer layer.

[0007] Embodiments may include one or more of the following. The buffer region includes a relaxed Si(1-x)Ge(x) material, where x represents the concentration of germanium. The buffer layer includes a crystalline material selected from silicon, silicon germanium, or a combination of silicon and silicon germanium. The germanium concentration "x" in the relaxed Si(1-x)Ge(x) material forms a germanium concentration gradient in the buffer region. The crystalline material includes silicon germanium, and the silicon germanium has a substantially uniform germanium concentration that is equal to or substantially equal to the germanium concentration "x" in the relaxed Si(1-x)Ge(x) material at the top surface of the buffer region. The semiconductor device further includes a source / drain region formed in a source / drain recess defined by adjacent fins. The semiconductor device further includes a dielectric isolation layer that separates the source / drain region from the top surface of the buffer region. The thickness of the isolation region is greater than the thickness of the buffer region.

[0008] In another aspect, a method for forming a semiconductor device is provided. The method includes forming a plurality of isolation regions in a silicon substrate. The isolation regions include isolation materials. The method further includes removing a portion of the silicon substrate to form a recess between adjacent isolation regions. The method further includes filling the recess with a buffer material to form a buffer region. The method further includes growing a buffer layer over the silicon substrate, the isolation material, and the buffer material. The method further includes forming a superlattice structure on the buffer layer. The superlattice structure includes a plurality of silicon layers and a plurality of silicon germanium layers alternately arranged in a plurality of stacked pairs. The method further includes patterning and etching the superlattice structure and the buffer layer to form a fin from the superlattice structure and the buffer layer. The fin is aligned with the isolation region, and the fin defines a source / drain recess. The method further includes filling the source / drain recess with an epitaxial material to form a source / drain region.

[0009] Embodiments may include one or more of the following. The method further includes forming a dielectric isolation layer in the source / drain recess before filling the source / drain recess with an epitaxial material. Filling the recess with a buffer material to form a buffer region includes epitaxially growing a Si(1-x)Ge(x) material, where x represents a germanium concentration. Growing a buffer layer above a silicon substrate, an isolation material, and a buffer material includes epitaxially growing a crystalline material selected from silicon, silicon germanium, or a combination of silicon and silicon germanium. The germanium concentration "x" in the relaxed Si(1-x)Ge(x) material forms a germanium concentration gradient in the buffer region. The crystalline material includes silicon germanium, and the silicon germanium has a substantially uniform germanium concentration that is equal to or substantially equal to the germanium concentration "x" in the relaxed Si(1-x)Ge(x) material at the top surface of the buffer region. The crystalline material selectively grows in a vertical direction from the buffer region and then grows laterally above the isolation region.

[0010] In another aspect, a method for forming a semiconductor device is provided. The method includes forming a plurality of isolation regions in a silicon substrate. The isolation regions contain isolation material. The method further includes removing a portion of the silicon substrate to form a recess between adjacent isolation regions. The method further includes epitaxially growing a buffer material in the recess to form a buffer region. The method further includes epitaxially growing a buffer layer over the buffer region and the isolation region, wherein the buffer layer is epitaxially grown from the buffer region. The method further includes forming a superlattice structure on the buffer layer. The superlattice structure includes a plurality of silicon layers and a plurality of silicon germanium layers alternately arranged in a plurality of stacked pairs. The method further includes patterning and etching the superlattice structure and the buffer layer to form a fin from the superlattice structure and the buffer layer. The fin is aligned with the isolation region, and the fin defines a source / drain recess. The method further includes forming a spacer on an outer surface of the silicon germanium layer. The method further includes filling the source / drain recess with an epitaxial material to form a source / drain region.

[0011] Embodiments may include one or more of the following. Epitaxially growing a buffer material in the recess includes epitaxially growing a Si(1-x)Ge(x) material, where x represents a germanium concentration. Epitaxially growing a buffer layer over the buffer region and the isolation region includes epitaxially growing a crystalline material selected from silicon, silicon germanium, or a combination of silicon and silicon germanium. The germanium concentration "x" in the relaxed Si(1-x)Ge(x) material forms a germanium concentration gradient in the buffer region. The crystalline material includes silicon germanium, and the silicon germanium has a substantially uniform germanium concentration that is equal to or substantially equal to the germanium concentration "x" in the relaxed Si(1-x)Ge(x) material at the top surface of the buffer region.

[0012] In another aspect, a non-transitory computer readable medium has stored thereon instructions that, when executed by a processor, cause a process to perform the operations of the apparatus and / or method described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to understand in detail the manner in which the above-mentioned features of the present disclosure are achieved, the aspects briefly summarized above may be more particularly described with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments of the present disclosure and are therefore not to be considered as limiting the scope of the present disclosure, as the present disclosure may admit to other equally effective embodiments.

[0014] Figure 1 A schematic cross-sectional view of a GAA structure is illustrated according to one or more embodiments of the present disclosure.

[0015] Figure 2 A schematic cross-sectional view of another GAA structure according to one or more embodiments of the present disclosure is illustrated.

[0016] Figure 3 An exemplary flow chart illustrating a method of forming a GAA structure according to one or more embodiments of the present disclosure.

[0017] FIG. 4A to FIG. 4M Cross-sectional views illustrating various stages of forming a GAA structure according to one or more embodiments of the present disclosure.

[0018] Figure 5 A plan view of a cluster tool is illustrated in accordance with one or more embodiments of the present disclosure.

[0019] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially included in other embodiments without further recitation. DETAILED DESCRIPTION

[0020] Scaling down metal oxide semiconductor (MOS) devices has become a major challenge in the semiconductor industry. One problem with scaling down conventional planar devices is short channel effects, which begin to affect device performance. One solution to this problem is to introduce multi-gate devices with three-dimensional architectures, such as fin-based semiconductor devices or FINFETs and GAA devices. Since in their three-dimensional architectures, the gate is wrapped around the thin semiconductor fins of FINFETs or the gate electrode surrounds all side surfaces of the channel region of GAAs, improved gate control of the channel (and thus reduced short channel effects) can be achieved by using multiple gates. The most advanced GAAs today are formed on bulk silicon substrates where the drive current is proportional to the bulk silicon mobility. Therefore, the drive current is limited by the bulk silicon mobility.

[0021] Superlattice structures can be used in the fabrication of devices with three-dimensional architectures. These superlattice structures incorporate films, such as stacks of alternating silicon (Si) and silicon germanium (SiGe) layers, that have varying properties depending on the specific application for which the films are deposited.

[0022] The various aspects described utilize a relaxed SiGe buffer and epitaxial lateral overgrowth technique to form a local template of a strained GAA channel superlattice structure, thereby enhancing the mobility of n-FETs and p-FETs in the same biaxial strained silicon channel. In at least one embodiment, the structure further incorporates a bottom dielectric isolation under the channel to reduce substrate leakage current. The application of the GAA structure in multiple technology nodes is expanded due to the ability to adjust the degree of strain and thereby enhance the mobility in the channel. The technology for local substrate isolation is implemented without using a fully isolated silicon-on-insulator (SOI) substrate. Compared with SOI, the cost is reduced, and substrate isolation is performed only where it is needed, rather than substrate isolation on the entire wafer as in SOI. Forming a GAA channel region above a dielectric region (e.g., an STI region) implements substrate isolation (forming a pseudo-SOI structure), thereby reducing substrate leakage current. In addition, forming a single crystalline material above the dielectric region enables the formation of a strained Si / Si(1-x)Ge(x) superlattice for the GAA channel.

[0023] Figure 1 A schematic cross-sectional view of a gate all around (GAA) structure 100 according to one or more embodiments of the present disclosure is shown. The GAA structure 100 includes a multi-material layer 130 disposed above a substrate 110. The substrate 110 has a front side 110f (also referred to as a front surface) and a back side 110b opposite to the front side 110f. The substrate 110 may be a material such as crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, strained silicon, silicon germanium, germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned wafers on insulators (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire. The substrate 110 may have various sizes (e.g., 200 mm, 300 mm, 450 mm, or other diameters) and may be a rectangular or square panel. Unless otherwise noted, the described examples may be performed on substrates having a 200 mm diameter, a 300 mm diameter, or a 450 mm diameter.

[0024] The GAA structure 100 further includes isolation regions 112a to 112c formed in the substrate 110. The isolation regions 112a to 112c are formed in corresponding trenches 114a to 114c. In at least one embodiment, the isolation regions 112a to 112c are shallow trench isolations (STI). The trenches 114a to 114c extend from the front side 110f of the substrate 110 into the substrate 110. Thus, the top surface 113t of the isolation regions 112a to 112c is coplanar or substantially coplanar with the front side 110f of the substrate 110. The isolation regions 112a to 112c include a bottom surface 113b, a top surface 113t, and at least one sidewall 113s. The isolation regions 112a to 112c are formed by filling the trenches 114a to 114c with an isolation material. In at least one embodiment, the isolation material is a dielectric material. In one example, the isolation material comprises, consists of, or consists essentially of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-k dielectric such as a carbon-doped oxide, an ultra-low-k dielectric such as a porous carbon-doped silicon dioxide, a polymer such as a polyimide, combinations thereof, or the like. In a specific embodiment, the isolation material comprises, consists of, or consists essentially of silicon oxide.

[0025] The GAA structure 100 further includes buffer regions 118a-118b formed in the substrate 110. The buffer regions 118a-118b are formed in corresponding recesses 120a-120b. In at least one embodiment, the buffer regions 118a-118b are relaxed Si(1-x)Ge(x) buffer regions. Growing the relaxed SiGe buffer material in the buffer regions 118a-118b between the isolation regions 112a-112c enables dislocation termination on the sidewalls of the isolation regions 112a-112c, thereby reducing the dislocation density at the front side 110f of the substrate 110. In addition, the buffer regions enable epitaxial lateral overgrowth, such that a single crystalline epitaxial layer is formed on the front side 110f of the substrate 110. The recesses 120a-120b extend from the front side 110f of the substrate 110 into the substrate 110. Thus, the top surface 119t of the buffer regions 118a-118b is coplanar or substantially coplanar with the front side 110f of the substrate 110. The buffer regions 118a-118b include a bottom surface 119b, a top surface 119t, and at least one sidewall 119s. In at least one embodiment, the buffer regions 118a-118b extend from the sidewall of the isolation region to the sidewall of the adjacent isolation region. For example, Figure 1As shown, the buffer region 118a extends from the sidewall 113s of the isolation region 112a to the sidewall 113s of the isolation region 112b. In at least one embodiment, the bottom surface 119b of the buffer regions 118a to 118b is offset relative to the bottom surface 113b of the isolation regions 112a to 112b. In one example, Figure 1 As shown, the bottom surface 119b of the buffer regions 118a to 118b defines a plane located above the plane defined by the bottom surface 113b of the isolation regions 112a to 112b. In another example, the bottom surface 119b of the buffer regions 118a to 118b extends below the bottom surface 113b of the isolation regions 112a to 112b. In another example, the bottom surface 119b of the buffer regions 118a to 118b is coplanar or substantially coplanar with the bottom surface 113b of the isolation regions 112a to 112b. The buffer regions 118a to 118b are formed by filling the trenches 120a to 120b with SRB. In at least one embodiment, the strain relaxation buffer material has at least one component (e.g., a gradient concentration of germanium). In at least one embodiment, the SRB material includes a Group IV material, such as silicon and germanium. In one example, the SRB material includes Si 1-x Ge x , where x is the germanium concentration. The concentration (atomic percentage) of germanium in the buffer regions 118a to 118b may be gradient.

[0026] The GAA structure 100 further includes a multi-material layer 130. The multi-material layer 130 includes a buffer layer 134, a superlattice structure 141 disposed on the buffer layer 134, and optionally includes oxide layers 150a to 150c disposed on the superlattice structure 141. The oxide layers 150a to 150c may be gate oxide layers or dummy gate oxide layers. In at least one embodiment, the buffer layer 134 is a single crystalline epitaxial layer. In at least one embodiment, the buffer layer 134 includes, consists of, or consists essentially of a crystalline material selected from silicon, silicon germanium, or a combination of silicon and silicon germanium. In one example, the buffer layer 134 is a single crystalline silicon layer. In another example, the buffer layer 134 is a relaxed epitaxial Si(1-x)Ge(x) buffer material, wherein the germanium concentration "x" is gradient, uniform, or substantially uniform throughout the buffer layer 134. In at least one embodiment, the thickness of the buffer layer 134 is in a range from about 20Å to about 200Å, such as about 50Å.

[0027] The superlattice structure 141 includes at least one pair of layers, each pair including a first material layer 142 and a second material layer 144. Figure 1The illustrated example shows three pairs, each pair including a first material layer 142 and a second material layer 144 (alternating pairs, each pair including a first material layer 142 and a second material layer 144). The number of pairs may vary based on different process requirements having or not requiring additional first material layers 142 or second material layers 144. In one embodiment, the thickness of each single first material layer 142 may be between about 20Å and about 200Å, such as about 50Å, and the thickness of each single second material layer 144 may be between about 20Å and about 200Å, such as about 50Å. The superlattice structure 141 may have a total thickness between about 10Å and about 5000Å, such as between about 40Å and about 4000Å.

[0028] The first material layer 142 is a non-crystalline material layer. In at least one embodiment, the first material layer 142 is a Ge-containing layer, such as a SiGe layer, a Ge layer, or other suitable layers. Alternatively, the first material layer 142 is a doped silicon layer, including a p-type doped silicon layer or an n-type doped layer. In another embodiment, the first material layer 142 is a III-V material, such as a GaAs layer. In another embodiment, the second material layer 144 is a silicon layer, and the first material layer 142 is a metal material having a high dielectric constant material coating on the outer surface of the metal material. Suitable examples of high dielectric constant materials include hafnium dioxide (HfO2), zirconium dioxide (ZrO2), hafnium silicon oxide (HfSiO4), hafnium aluminum oxide (HfAlO), zirconium silicon oxide (ZrSiO4), tantalum dioxide (TaO2), aluminum oxide, aluminum dioxide doped hafnium, bismuth strontium titanium (bismuth strontium titanium, BST) or platinum zirconium titanium (platinumzirconium titanium, PZT). In one specific embodiment, the coating is a hafnium dioxide (HfO2) layer.

[0029] The spacer 146 is formed adjacent to the end of the first material layer 142 and can be considered as a part of the first material layer 142. The spacer 146 is a dielectric spacer, an air gap, or a combination of a dielectric spacer and an air gap. The spacer 146 can be formed by etching away a portion of each of the first material layers 142 using an etching precursor so as to form a recess at the end of each of the first material layers 142. The spacer 146 is formed in the recess adjacent to each of the first material layers 142. Prior to the deposition of the spacer 146, a liner layer (not shown) may be additionally formed in the recess. The spacer 146 is formed of a dielectric material and separates each of the nanowires or nanosheets formed as the second material layer 144. In at least one embodiment, the spacer 146 is selected to be a silicon-containing material, such as a low dielectric constant material, that can reduce the parasitic capacitance between the gate and the source / drain structure in the GAA nanowire structure. The silicon-containing material or low dielectric constant material may be silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, a doped silicon layer, or other suitable material, such as Black Diamond® material available from Applied Materials. In one example, the spacer 146 is a low dielectric constant material (e.g., a dielectric constant of less than 4) or a material containing silicon oxide / silicon nitride / silicon carbide. In another example, the spacer 146 is an air gap.

[0030] Each of the second material layers 144 is a crystalline layer, such as a single crystal, polycrystalline or monocrystalline silicon layer. The second material layer 144 is formed using an epitaxial deposition process. Alternatively, the second material layer 144 is a doped silicon layer, including a p-type doped silicon layer or an n-type doped layer. Suitable p-type dopants include B dopants, Al dopants, Ga dopants, In dopants, or the like. Suitable n-type dopants include N dopants, P dopants, As dopants, Sb dopants, or the like. In another alternative, the second material layer 144 is a III-V material, such as a GaAs layer.

[0031] The multi-material layer 130 further includes oxide layers 150 a to 150 c disposed on the superlattice structure 141 .

[0032] like Figure 1As shown, the multi-material layer 130 is patterned to form fins, such as a first fin 140a, a second fin 140b, and a third fin 140c. The fins 140a to 140c are each disposed on and aligned with the corresponding isolation regions 112a to 112c. For example, the first fin 140a is disposed on the isolation region 112a, the second fin 140b is disposed on the isolation region 112b, and the third fin 140c is disposed on the isolation region 112c. The formation and alignment of the fins 140a to 140c above the isolation regions 112a to 112c, respectively, isolates the substrate 110 from the fins 140a to 140c by establishing a pseudo SOI structure to reduce substrate leakage current. As shown in FIG. Figure 1 As shown, the fin includes a portion of the buffer layer 134, a portion of the first material layer 142, a portion of the second material layer 144, and a portion of the oxide layer 150. Figure 1 Three fins 140a - 140c are shown, but it will be appreciated that any suitable number and type of fins may be used.

[0033] The GAA structure 100 further includes source / drain regions 160a to 160b. The source / drain regions 160a to 160b are formed in recesses defined by adjacent fins 140a to 140c. Figure 1 As shown, the source / drain region 160a is formed in a recess defined between the first fin 140a and the second fin 140b, and the source / drain region 160b is formed in a recess defined between the second fin 140b and the third fin 140c. In at least one embodiment, the source / drain regions 160a to 160b are formed of doped silicon including p-type doped silicon and n-type doped silicon. In an embodiment where the GAA structure 100 is an n-channel metal oxide semiconductor (NMOS), the source / drain regions 160a to 160b are formed of silicon doped with an n-type dopant. Suitable n-type dopants include N dopants, P dopants, As dopants, Sb dopants, the like, or a combination thereof. In an embodiment where the GAA structure 100 is a p-channel metal oxide semiconductor (PMOS), the source / drain regions 160a to 160b are formed of silicon doped with a p-type dopant. Suitable p-type dopants include B dopants, Al dopants, Ga dopants, In dopants, the like, or combinations thereof.

[0034] like Figure 1 As shown, the source / drain regions 160a to 160b include a bottom surface 161b, a top surface 161t, and at least one sidewall 161s. Figure 1In at least one embodiment shown, the source / drain regions 160a to 160b extend from the sidewall of a fin (e.g., the first fin 140a) to the sidewall of an adjacent fin (e.g., the second fin 140b). The bottom surface 161b is defined by the top surface 119t of the buffer regions 118a to 118b. The at least one sidewall 161s is defined by the buffer layer 134 and the superlattice structure 141, such as the spacer 146 and the second material layer 144.

[0035] In at least one embodiment, the top surfaces 161 of the source / drain regions 160a-160b are offset relative to the top surfaces of the fins 140a-140c. Figure 1 As shown, top surfaces 161t of source / drain regions 160a-160b define a plane that is above a plane defined by top surfaces of fins 140a-140c.

[0036] Figure 2 FIG. 2 is a schematic cross-sectional view of another GAA structure 200 according to one or more embodiments of the present disclosure. The GAA structure 200 is similar to Figure 1 The GAA structure 100 is shown. However, Figure 2 The illustrated GAA structure 200 further includes bottom dielectric isolation layers 210a to 210b. The bottom dielectric isolation layers 210a to 210b are formed at the bottom of the recess defined by adjacent fins. For example, the bottom dielectric isolation layer 210a is formed at the bottom of the recess defined by the sidewalls of the first fin 140a and the sidewalls of the second fin 140b. The bottom dielectric isolation layers 210a to 210b isolate the buffer regions 118a to 118b from the source / drain regions 160a to 160b and the buffer layer 134. The bottom dielectric isolation layers 210a to 210b contact the top surfaces 119t of the buffer regions 118a to 118b, the sidewalls of the buffer layer 134, and the bottom surfaces 161b of the source / drain regions 160a to 160b.

[0037] Figure 3 An exemplary flow chart of a method 300 of forming a GAA structure according to one or more embodiments of the present disclosure is illustrated. FIG. 4A to FIG. 4M Cross-sectional views illustrating various stages of forming a GAA structure according to one or more embodiments of the present disclosure. FIG. 4A to FIG. 4M , provides cross-sectional views of some embodiments of GAA structures at various stages of manufacture to illustrate Figure 3 Although the method 300 is described in conjunction with FIG. 4A to FIG. 4M , but will understand FIG. 4A to FIG. 4M The disclosed structure is not limited to the method 300, but can be an independent structure independent of the method 300. FIG. 4A to FIG. 4M The method 300 is described, but it will be appreciated that the method 300 is not limited to FIG. 4A to FIG. 4M The disclosed structure can be independent of FIG. 4A to FIG. 4M The disclosed structure.

[0038] Figure 4A A cross-sectional view of a portion of the GAA structure 100 during an intermediate manufacturing stage corresponding to operation 310 is illustrated in accordance with some embodiments. During operation 310, a substrate, such as Figure 4A The substrate 110 is shown.

[0039] FIG. 4B to FIG. 4C A cross-sectional view of a portion of the GAA structure 100 during an intermediate manufacturing stage corresponding to operation 320 is shown in accordance with some embodiments. During operation 320, isolation regions are formed, such as isolation regions 112a to 112c formed in the substrate 110. FIG. 4B to FIG. 4C As shown. Referring to FIG. B, grooves 114a to 114c are formed in substrate 110. Grooves 114a to 114c extend from the front side 110f of substrate 110 into substrate 110. Grooves 114a to 114c may be formed by a patterning and etching process. The patterning and etching process may include forming a mask layer on the front side 110f of substrate 110. The mask layer may be patterned using lithography techniques. Typically a photoresist material (not shown) is deposited over the mask layer. The photoresist material is irradiated (exposed) by radiation (e.g., light) through a patterned reticle, thereby causing a reaction in the portion of the photoresist material exposed to the energy. The photoresist material is developed to remove a portion of the photoresist material, wherein the remaining photoresist material protects the underlying material of substrate 110 from subsequent processing operations (e.g., etching).

[0040] refer to Figure 4C , an isolation material is deposited in the trenches 114a to 114c to form corresponding isolation regions 112a to 112c in the substrate 110. In at least one embodiment, the isolation material is deposited using a process such as chemical vapor deposition (CVD), flow CVD (FCVD), or spin-on-glass, but other acceptable processes may be used. The isolation regions 112a to 112c may then be subjected to one or more of a mask removal process and a planarization process for removing portions of the isolation regions 112a to 112c extending above the front side 110f of the substrate 110, such as an etching process, a chemical mechanical polishing (CMP) process, or the like. The planarization process may be performed so that the top surfaces 113t of the isolation regions 112a to 112c are coplanar or substantially coplanar with the front side 110f of the substrate 110.

[0041] Figure 4DA cross-sectional view of a portion of the GAA structure 100 during an intermediate manufacturing stage corresponding to operation 330 according to some embodiments is illustrated. During operation 330, recesses (e.g., recesses 120a-120b) are formed in the substrate 110. The recesses 120a-120b may be formed by a patterning and etching process. The recesses 120a-120b extend from the front side 110f of the substrate 110 into the substrate 110. The recesses 120a-120b are defined by the sidewalls 113s of the isolation regions 112a-112c. For example, as shown in FIG. Figure 4D As shown, the recess 120a is defined by the sidewall 113s of the isolation region 112a and the sidewall 113s of the isolation region 112b, and the recess 120b is defined by the sidewall 113s of the isolation region 112b and the sidewall 113s of the isolation region 112c. The recesses 120a to 120b may be formed by a patterning and etching process. The etching process may be a selective etching process that selectively removes the material (e.g., silicon) of the substrate 110 relative to the material (e.g., oxide, such as silicon oxide) of the isolation regions 112a to 112c to form the recesses 120a to 120b.

[0042] Figure 4E A cross-sectional view of a portion of the GAA structure 100 during an intermediate manufacturing stage corresponding to operation 340 according to some embodiments is illustrated. During operation 340, the recesses 120a to 120b are filled with a strain relaxed buffer (SRB) material to form buffer regions 118a to 118b. The buffer regions 118a to 118b are formed by filling the recesses 120a to 120b with the SRB material. The buffer regions 118a to 118b include a top surface 119t and a bottom surface 119b. In at least one embodiment, the strain relaxed buffer material has a gradient concentration of at least one component, such as germanium. In at least one embodiment, the SRB material includes a Group IV material, such as silicon and germanium. In one example, the SRB material includes Si 1-x Ge x , where x is the germanium concentration. The germanium concentration (atomic percentage) in the buffer regions 118a to 118b may be gradient. In at least one embodiment, the SRB material is deposited into the recesses 120a to 120b by an epitaxial chemical vapor deposition process. The epitaxial deposition process provides precise control of the germanium content of each of the buffer regions 118a to 118b and the subsequently formed buffer layer 134, thereby providing favorable control of the lattice match with the substrate 110, the subsequently deposited superlattice structure 141, or both the substrate 110 and the subsequently deposited superlattice structure 141. In one example, a relaxed epitaxial Si(1-x)Ge(x) buffer material is grown in the recesses 120a to 120b such that the dislocations disappear on the sidewalls 113s of the isolation regions 112a to 112c.

[0043] In at least one embodiment, the buffer regions 118a-118b include Si with a gradient germanium concentration. 1-x Ge x The material, wherein the germanium concentration at the interface between the bottom surface 119b of the buffer regions 118a to 118b and the substrate 110 is similar to the germanium concentration of the substrate 110 (e.g., 0 at%), the germanium concentration at the interface between the top surface 119t of the buffer regions 118a to 118b and the backside surface 134b of the buffer layer 134' is similar to the uniform or substantially uniform germanium concentration of the buffer layer 134' (e.g., 10-15 at%), and the uniform or substantially uniform germanium concentration of the buffer layer 134' is similar to the germanium concentration of the adjacent SiGe layer in the superlattice structure (e.g., 10-15 at%).

[0044] Figure 4F A cross-sectional view of a portion of the GAA structure 100 during an intermediate manufacturing stage corresponding to operation 350 according to some embodiments is illustrated. During operation 350, a buffer layer 134' is formed. The buffer layer 134' is formed on the front side 110f of the substrate 110. The buffer layer 134' has a backside surface 134b and a frontside surface 134f (also referred to as a front surface) opposite the backside surface 134b (also referred to as a back surface). The backside surface 134b contacts the front side 110f of the substrate 110, the top surface 113t of the isolation regions 112a to 112c, and the top surface 119t of the buffer regions 118a to 118b. In at least one embodiment, the buffer layer 134' is formed via an epitaxial chemical vapor deposition process. In at least one embodiment, the buffer layer 134' is formed via the same epitaxial deposition process used to form the buffer regions 118a to 118b. In another embodiment, the buffer layer 134' is formed via a different epitaxial deposition process.

[0045] The epitaxial deposition process provides precise control over the germanium content of each of the buffer regions 118a-118b and the buffer layer 134, thereby providing advantageous control over the lattice matching with the substrate 110, the subsequently deposited superlattice structure 141, or both.

[0046] In at least one embodiment, the buffer layer 134' comprises a crystalline material selected from silicon, silicon germanium, or a combination of silicon and silicon germanium. In at least one embodiment, the buffer layer 134' has a germanium concentration gradient. The germanium concentration gradient may increase from the backside surface 134b of the buffer layer 134' to the frontside surface 134f of the buffer layer 134'. The buffer layer 134' may be a SiGe spacer layer.

[0047] In at least one embodiment, the germanium concentration of the buffer layer 134' may be the lowest near the interface with the front side 110f of the substrate 110 (e.g., near the backside surface 134b of the buffer layer 134'), and increase to the highest near the interface with the superlattice structure 141. In another embodiment, the germanium concentration of the buffer layer 134' may be the highest near the interface with the front side 110f of the substrate 110 (e.g., near the backside surface 134b of the buffer layer 134), and decrease to the lowest near the interface with the superlattice structure 141.

[0048] In at least one embodiment, the buffer layer 134' includes silicon germanium, and the silicon germanium has a uniform or substantially uniform germanium concentration equal to or substantially equal to the germanium concentration "x" in the relaxed Si(1-x)Ge(x) material at the top surface 119t of the buffer regions 118a-118b.

[0049] In at least one embodiment, the buffer regions 118a-118b include Si with a gradient germanium concentration. 1-x Ge x The material comprises a germanium concentration at an interface between a bottom surface 119b of the buffer regions 118a to 118b and the substrate 110 that is similar to the germanium concentration of the substrate 110 (e.g., 0 at%), and a germanium concentration at an interface between a top surface 119t of the buffer regions 118a to 118b that is similar to the germanium concentration of a rear surface 134b of the buffer layer 134', and a germanium concentration at a front surface 134f of the buffer layer 134' that is similar to the uniform or substantially uniform germanium concentration of a subsequently deposited superlattice structure 141 (e.g., 10-15 at%).

[0050] In at least one embodiment, the gradient germanium concentration of the buffer layer 134' has a germanium content that increases in the range of about 0% to about 20%, or in the range of about 0% to about 15%, or in the range of about 0.1% to about 15%, or in the range of about 0.5% to about 15%, or in the range of about 1% to about 15%, or in the range of about 1% to about 10%. The silicon content of the buffer layer 134' may be in the range of about 80% to about 100%, or in the range of about 85% to about 100%, or in the range of about 85% to about 99.9%, or in the range of about 85% to about 99.5%, or in the range of about 90% to about 99%. The buffer layer 134' may have a maximum germanium content equal to or less than 10%, equal to or less than 15%, or equal to or less than 20%.

[0051] A planarization process may be performed on the buffer layer 134'. In at least one embodiment, the front side surface 134f of the buffer layer 134' has a high surface roughness. Such a high surface roughness of the front side surface 134f of the buffer layer 134' makes it difficult for the buffer layer 134' to be used as a template for subsequently growing the superlattice structure 141 on the buffer layer 134'. The planarization process removes a portion of the front side surface 134f of the buffer layer 134' to form a smooth surface. Any suitable planarization process may be used. The planarization process may be a chemical mechanical polishing (CMP) process or an etch-back process.

[0052] Figure 4G A cross-sectional view of a portion of the gate-all-around structure 100 during an intermediate manufacturing stage corresponding to operation 360 according to some embodiments is illustrated. During operation 360, a superlattice structure (e.g., superlattice structure 141) is formed over substrate 110 (e.g., on buffer layer 134'). Superlattice structure 141 includes at least one pair of layers, each pair including a first material layer 142' and a second material layer 144'. Although Figure 4G The illustrated example shows three pairs, but each pair includes a first material layer 142' and a second material layer 144' (alternating pairs, each pair includes a first material layer 142' and a second material layer 144'). The number of pairs may vary based on different process requirements that require additional first material layers 142 or second material layers 144 or no additional first material layers 142 or second material layers 144.

[0053] The first material layer 142' is an amorphous material layer. In at least one embodiment, the first material layer 142' is a Ge-containing layer, such as a SiGe layer, a Ge layer, or other suitable layer. Alternatively, the first material layer 142' is a doped silicon layer, including a p-type doped silicon layer or an n-type doped layer. In another embodiment, the first material layer 142' is a III-V group material, such as a GaAs layer. The first material layer 142' is formed using an epitaxial deposition process performed in an epitaxial deposition chamber.

[0054] The second material layer 144' is a crystalline material layer, such as a single crystal, polycrystalline or monocrystalline silicon layer. The second material layer 144' is formed using an epitaxial deposition process performed in an epitaxial deposition chamber. Alternatively, the second material layer 144' is a doped silicon layer, including a p-type doped silicon layer or an n-type doped silicon layer. Suitable p-type dopants include B dopants, Al dopants, Ga dopants, In dopants, or the like. Suitable n-type dopants include N dopants, P dopants, As dopants, Sb dopants, or the like. In another alternative, the second material layer 144 is a III-V material, such as a GaAs layer.

[0055] Figure 4HA cross-sectional view of a portion of the GAA structure 100 during an intermediate manufacturing stage corresponding to operation 365 according to some embodiments is illustrated. Optionally, an oxide layer 150' is formed in operation 365. The oxide layer 150' may be formed over the superlattice structure 141. In at least one embodiment, the oxide layer 150' may be formed by a deposition process, such as thermal oxidation, CVD, sputtering, or any other method known and used in the art for forming a dummy gate oxide layer. In at least one embodiment, the oxide layer 150' may be formed of the same material as the isolation regions 112a to 112c. In at least another embodiment, the oxide layer 150' may be made of one or more suitable materials such as silicon oxide, silicon nitride, a low dielectric constant dielectric (such as carbon doped oxide), an ultra-low dielectric constant dielectric (such as porous doped silicon dioxide), a polymer (such as polyimide), the like, or a combination thereof. In another embodiment, the oxide layer 150' includes a dielectric material having a high dielectric constant (k value) greater than 3.9 (for example). The materials may include silicon nitride, oxynitride, metal oxides such as HfO2, HfZrOx, HfSiOx, HfTiOx, HfAlOx, combinations thereof, multilayers thereof, or the like.

[0056] Fig. 4I A cross-sectional view of a portion of the GAA structure 100 during an intermediate manufacturing stage corresponding to operation 370 according to some embodiments is illustrated. In operation 370, a patterning and etching process is performed to form source / drain recesses 412a-412b in the multi-material layer 130 including the buffer layer 134', the superlattice structure 141, and optionally the oxide layer 150 (if present). In at least one embodiment, as Fig. 4IAs shown, the source / drain recesses 412a to 412b are defined by sidewalls 413s and bottom surfaces 413b. Sidewalls 413s are defined by the buffer layer 134, the superlattice structure 141, and the oxide layers 150a to 150c (if present) of the fins 140a to 140c. Bottom surface 413b is defined by the top surface 119t of the buffer regions 118a to 118b. The patterning and etching process of operation 370 may include forming a hard mask layer on the top surface of the superlattice structure 141 or on the top surface of the oxide layer 150' (if present). In at least one embodiment, the hard mask layer is patterned using lithography techniques. Typically a photoresist material (not shown) is deposited above the hard mask layer. The photoresist material is irradiated (exposed) by radiation (e.g., light) through a patterned reticle, thereby causing a reaction in the portion of the photoresist material exposed to the energy. The photoresist material is developed to remove a portion of the photoresist material, wherein the remaining photoresist material protects the underlying material from subsequent processing operations (e.g., etching). In at least one embodiment, the etching process is a reactive ion etching (RIE) process or the like. In one example, the RIE process is performed using a chlorine, bromine, or fluorine based chemistry to anisotropically etch the superlattice structure.

[0057] like Fig. 4I As shown, after the etching process is performed on the superlattice structure 141, the remaining area of ​​the superlattice structure 141 and the underlying substrate 110 form fins, such as a first fin 140a, a second fin 140b, and a third fin 140c. Fig. 4I It can be seen that the fins 140a to 140c include a portion of the buffer layer 134, a portion of the superlattice structure 141 (eg, a portion of the first material layer 142' (eg, a silicon layer) and a portion of the second material layer 144' (eg, a SiGe layer)), and a portion of the oxide layers 150a to 150c. Fig. 4I Three fins 140a - 140c are shown, but it will be appreciated that any suitable number and type of fins may be used.

[0058] Figure 4J A cross-sectional view of a portion of the GAA structure 100 during an intermediate manufacturing stage corresponding to operation 380 is illustrated in accordance with some embodiments. In operation 380, internal spacers, such as spacer 146, are formed. Figure 4JAs shown, the spacer 146 is formed adjacent to the end of the first material layer 142 and can be considered as a part of the first material layer 142. The spacer 146 is a dielectric spacer, an air gap, or both a dielectric spacer and an air gap. The spacer 146 can be formed by etching away a portion of each of the first material layers 142 using an etching precursor so as to form a recess at the end of each of the first material layers 142. The spacer 146 is formed in the recess adjacent to each of the first material layers 142. Prior to the deposition of the spacer 146, a liner layer (not shown) may be additionally formed in the recess. The spacer 146 is formed of a dielectric material and separates each of the nanowires or nanosheets formed as the second material layer 144. In at least one embodiment, the spacer 146 is selected to be a silicon-containing material, such as a low dielectric constant material, that can reduce the parasitic capacitance between the gate and the source / drain structure in the GAA nanowire structure. The silicon-containing material or low dielectric constant material may be silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, a doped silicon layer, or other suitable material, such as Black Diamond® material available from Applied Materials. In one example, the spacer 146 is a low dielectric constant material (e.g., a dielectric constant of less than 4) or a material containing silicon oxide / silicon nitride / silicon carbide. In another example, the spacer 146 is an air gap.

[0059] Figure 4K A cross-sectional view of a portion of the GAA structure 100 during an intermediate manufacturing stage corresponding to operation 395 according to some embodiments is illustrated. In operation 395, source / drain regions 160a-160b are formed in the source / drain recesses 412a-412b. The source / drain region 160a fills the source / drain recess 412a between the first fin 140a and the second fin 140b, and the source / drain region 160b fills the source / drain recess 412b between the second fin 140b and the third fin 140c. In at least one embodiment, as shown in FIG. Figure 4L As shown, the source / drain regions 160 a - 160 b contact the sidewalls of the fins 140 a - 140 c and the top surfaces 119 t of the buffer regions 118 a - 118 b .

[0060] The source / drain regions 160a to 160b may be formed via an epitaxial deposition process. The use of epitaxially grown materials in the source / drain regions 160a to 160b allows the source / drain regions 160a to 160b to apply stress in the channel region. The materials used for the source / drain regions 160a to 160b may be different for n-type FinFETs and p-type FinFETs, so that one type of material is used for n-type FinFETs to apply tensile stress in the channel region, and another type of material is used for p-type FinFETs to apply compressive stress. For example, SiP or SiC may be used to form n-type FinFETs, and SiGe or Ge may be used to form p-type FinFETs. However, any suitable material may be used. The epitaxial source / drain regions 160a to 160b may be doped by an implantation process for implanting suitable dopants or by in-situ doping as the material grows. In at least one embodiment, the first source / drain region 160a is formed of SiC or SiP doped with phosphorus (P) to form an n-type FinFET device, and the second source / drain region 160b is formed of SiGe or Ge doped with boron (B) to form a p-type FinFET device.

[0061] Figure 4L A cross-sectional view of a portion of the GAA structure 200 is illustrated during an intermediate manufacturing stage corresponding to optional operation 390 , in accordance with some embodiments. Figure 4L The GAA structure 200 shown is similar to Figure 4KThe GAA structure 100 is shown, except that the gate-all-around structure 200 includes a bottom dielectric isolation layer 210a-210b, which is formed before the source / drain deposition in operation 395. In optional operation 390, the bottom dielectric isolation layer 210a-210b is formed. The bottom dielectric isolation layer 210a-210b is formed at the bottom of the source / drain recesses 412a-412b. The bottom dielectric isolation layer 210a-210b isolates the subsequently deposited source / drain regions 160a-160b from the buffer regions 118a-118b, the buffer layer 134, and the substrate 110. In at least one embodiment, the bottom dielectric isolation layer 210a-210b includes a dielectric material. In one example, the dielectric material includes, consists of, or consists essentially of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a low-k dielectric such as carbon-doped oxide, an ultra-low-k dielectric such as porous carbon-doped silicon dioxide, a polymer such as polyimide, a combination thereof, or the like. In one particular embodiment, the isolation material includes, consists of, or consists essentially of silicon oxide. In at least one embodiment, the dielectric material of the bottom dielectric isolation layers 210a-210b is formed by a process such as CVD, flow CVD (FCVD), or spin-on-glass, although other suitable processes may be used. The dielectric material of the bottom dielectric isolation layers 210a-210b includes, consists of, or consists essentially of the same material as the isolation regions 112a-112c.

[0062] Figure 4M A cross-sectional view of a portion of the gate-all-around structure 200 during an intermediate manufacturing stage corresponding to operation 395 according to some embodiments is illustrated. In operation 395, source / drain regions 160a-160b are formed in the source / drain recesses 412a-412b. The source / drain region 160a fills the source / drain recess 412a between the first fin 140a and the second fin 140b, and the source / drain region 160b fills the source / drain recess 412b between the second fin 140b and the third fin 140c. In at least one embodiment, as shown in FIG. Figure 4L As shown, the source / drain regions 160 a - 160 b contact the sidewalls of the fins 140 a - 140 c and the bottom dielectric isolation layers 210 a - 210 b .

[0063] Figure 5is a plan view of a cluster tool 500 according to another embodiment described. The cluster tool 500 is characterized by at least one epitaxial deposition chamber. An example of a cluster tool 500 is a CENTURA® EPI system available from Applied Materials, Inc. of Santa Clara, California. Cluster tools manufactured by other companies may also be used. A transfer robot 504 of any feasible type is disposed in a transfer chamber 502 of the cluster tool 500. A load lock 506 having two load lock chambers 506A, 506B is coupled to the transfer chamber 502. A plurality of processing chambers 508, 510, 512, 514, and 516 are also coupled to the transfer chamber 502. In at least one aspect, the plurality of processing chambers 508, 510, 512, 514, and 516 include at least one of a pre-cleaning chamber, a material deposition chamber (e.g., an epitaxial deposition chamber), and a thermal treatment chamber (e.g., an annealing, degassing, or oxidation chamber).

[0064] Processing chamber 508 may be a pre-clean chamber configured to clean a substrate prior to epitaxial deposition of a material, such as a buffer material, a strain relaxation buffer material, or a superlattice structure. The pre-clean chamber may be configured to perform an Applied Materials SICONI™ pre-clean process. Processing chambers 510 and / or 514 may be material deposition chambers, such as epitaxial deposition chambers capable of performing an epitaxial growth process. Processing chambers 512 and / or 516 may be additional material deposition chambers, or thermal treatment chambers capable of performing a thermal treatment process.

[0065] The system controller 557 communicates with the transfer robot 504 and the plurality of processing chambers 508, 510, 512, 514, and 516. The system controller 557 may be any suitable component capable of controlling the processing chambers and the robot. For example, the system controller 557 may be a computer including a central processing unit (CPU) 592, a memory 594, an input / output 596, suitable circuits 598, and a memory.

[0066] The process can generally be stored as a software routine in the memory of the system controller 557, which, when executed by the processor, causes the processing chamber to perform the process of the present disclosure. The software routine can also be stored and / or executed by a second processor (not shown) remotely located from the hardware and controlled by the processor. Some or all of the methods of the present disclosure can also be performed in hardware. Thus, the process can be implemented in software and the process can be performed in hardware using a computer system as (for example) a special application integrated circuit or other type of hardware embodiment or as a combination of software and hardware. When executed by the processor, the software routine converts a general-purpose computer into a special application computer (controller), which controls the operation of the chamber so that the process is performed.

[0067] In at least one embodiment, the system controller 557 has a configuration to control the epitaxial growth chamber to grow epitaxial material such as at least one of the buffer regions 118a-118b, the buffer layer 134', the superlattice structure 141, and the source / drain regions 160a-160b.

[0068] The cluster tool 500 can be used to perform at least a portion of the method 300 described above. During processing, a substrate to be processed can arrive at the cluster tool 500 in a pod (not shown). The substrate is transferred from the pod to a vacuum-compatible load lock chamber 506A, 506B by a factory interface robot. The substrate is then picked up by a transfer robot 504 in the transfer chamber 502, which is usually kept under a vacuum state. The transfer robot 504 then loads the substrate into the processing chamber 508 for cleaning. The transfer robot 504 then picks up the substrate from the processing chamber 508 and loads the substrate into the processing chamber 510 or 514 (whichever is available) for epitaxial deposition. The described epitaxial material can be grown on the cleaned substrate in the processing chamber 510 or 514. The transfer robot 504 then picks up the substrate from the processing chamber 510 or 514 and transfers the substrate to the processing chamber 512 or 516 (whichever is available), which are thermal processing chambers. A rapid heating / cooling process may then be performed on the epitaxial material.The transfer robot 504 then picks up the substrate from the processing chamber 512 or 516 and transfers the substrate to the processing chamber 514 for deposition of additional material over the epitaxial material.

[0069] In the summary of the invention, detailed description, claims and drawings, reference is made to specific features (including method operations) of the present disclosure. It should be understood that the disclosure in this specification includes all possible combinations of these specific features. For example, when a specific feature is disclosed in the context of a particular aspect, embodiment or example of the present disclosure or a particular claim, that feature may also be combined with and / or used in the context of other specific aspects and embodiments of the present disclosure as much as possible, and is generally used in the present disclosure.

[0070] The term "comprising" and its grammatical equivalents are used to mean that other components, ingredients, operations, etc. are optionally present. For example, an item with the article "comprising" (or "which comprises") ingredients A, B, and C may consist of ingredients A, B, and C (i.e., only contain), or contain not only ingredients A, B, and C, but also one or more other ingredients. In addition, when a composition, element, or element of a group is preceded by the transition phrase "comprising" and its grammatical equivalents, it should be understood that the same composition or element of the group is considered to be preceded by the transition phrase "essentially consisting of...", "including", "selected from the group consisting of...", or "is" before the recitation of the composition, element, or multiple elements.

[0071] When reference is made to a method that includes two or more defined operations, the defined operations may be performed in any order or concurrently (unless the context excludes that possibility), and the method may include one or more other operations performed before any defined operation, between two defined operations, or after all defined operations (unless the context excludes that possibility).

[0072] When introducing elements of the present disclosure or exemplary aspects or embodiments thereof, the articles “a,” “an,” “the,” and “said” are intended to mean that there are one or more of the elements.

[0073] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope of the disclosure, the scope of which is determined by the claims that follow.

Claims

1. A semiconductor device, the semiconductor device include: A substrate, comprising: a plurality of isolation regions formed in the substrate, the plurality of isolation regions comprising an isolation material; and a buffer region formed in the substrate, the buffer region separating adjacent isolation regions; and A plurality of fins, each fin being formed on a corresponding isolation region among the plurality of isolation regions, each fin comprising: a buffer layer contacting the isolation material; and A plurality of silicon layers and a plurality of silicon germanium layers are alternately arranged in a plurality of stacked pairs on the buffer layer. 2 . The semiconductor device of claim 1 , wherein the buffer region comprises a relaxed Si(1-x)Ge(x) material, wherein x represents a germanium concentration. 3 . The semiconductor device of claim 2 , wherein the buffer layer comprises a crystalline material selected from silicon, silicon germanium, or a combination of silicon and silicon germanium.

4. The semiconductor device of claim 3, wherein the germanium concentration "x" in the relaxed Si(1-x)Ge(x) material forms a germanium concentration gradient in the buffer region.

5. The semiconductor device of claim 4 , wherein the crystalline material comprises the silicon germanium, and the silicon germanium has a substantially uniform germanium concentration that is equal to or substantially equal to the germanium concentration “x” in the relaxed Si(1-x)Ge(x) material at the top surface of the buffer region. 6 . The semiconductor device of claim 1 , further comprising source / drain regions formed in source / drain recesses defined by adjacent fins. 7 . The semiconductor device of claim 6 , further comprising a dielectric isolation layer separating the source / drain regions from a top surface of the buffer region. 8 . The semiconductor device according to claim 1 , wherein a thickness of the isolation region is greater than a thickness of the buffer region.

9. A method of forming a semiconductor device, include: forming a plurality of isolation regions in a silicon substrate, wherein the isolation regions comprise an isolation material; removing portions of the silicon substrate to form recesses between adjacent isolation regions; filling the recess with a cushioning material to form a cushioning area; growing a buffer layer over the silicon substrate, the isolation material, and the buffer material; forming a superlattice structure on the buffer layer, wherein the superlattice structure includes a plurality of silicon layers and a plurality of silicon germanium layers alternately arranged in a plurality of stacked pairs; patterning and etching the superlattice structure and the buffer layer to form a fin from the superlattice structure and the buffer layer, wherein the fin is aligned with the isolation region and the fin defines a source / drain recess; as well as The source / drain recesses are filled with epitaxial material to form source / drain regions.

10. The method of claim 9, further comprising: include: A dielectric isolation layer is formed in the source / drain recesses before filling the source / drain recesses with the epitaxial material.

11. The method of claim 9, wherein the cushioning material is used to fill the recess to form the cushioning area. include: Epitaxially grown Si(1-x)Ge(x) material, where x represents the germanium concentration.

12. The method of claim 11, wherein the buffer layer is grown over the silicon substrate, the isolation material, and the buffer material. include: A crystalline material is epitaxially grown, the crystalline material being selected from silicon, silicon germanium, or a combination of silicon and silicon germanium.

13. The method of claim 12, wherein the germanium concentration "x" in the relaxed Si(1-x)Ge(x) material forms a germanium concentration gradient in the buffer region.

14. The method of claim 13, wherein the crystalline material comprises the silicon germanium and the silicon germanium has a substantially uniform germanium concentration equal to or substantially equal to the germanium concentration "x" in the relaxed Si(1-x)Ge(x) material at the top surface of the buffer region.

15. The method of claim 12, wherein the crystalline material selectively grows vertically from the buffer region and subsequently grows laterally over the isolation region.

16. A method of forming a semiconductor device, include: forming a plurality of isolation regions in a silicon substrate, wherein the isolation regions comprise an isolation material; removing portions of the silicon substrate to form recesses between adjacent isolation regions; epitaxially growing a buffer material in the recess to form a buffer region; epitaxially growing a buffer layer over the buffer region and the isolation region, wherein the buffer layer is epitaxially grown from the buffer region; forming a superlattice structure on the buffer layer, wherein the superlattice structure includes a plurality of silicon layers and a plurality of silicon germanium layers alternately arranged in a plurality of stacked pairs; patterning and etching the superlattice structure and the buffer layer to form a fin from the superlattice structure and the buffer layer, wherein the fin is aligned with the isolation region and the fin defines a source / drain recess; forming a spacer on an outer surface of the silicon germanium layer; as well as The source / drain recesses are filled with epitaxial material to form source / drain regions.

17. The method of claim 16, wherein the buffer material is epitaxially grown in the recess include: Epitaxially grown Si(1-x)Ge(x) material, where x represents the germanium concentration.

18. The method of claim 17, wherein the buffer layer is epitaxially grown over the buffer region and the isolation region. include: A crystalline material is epitaxially grown, the crystalline material being selected from silicon, silicon germanium, or a combination of silicon and silicon germanium.

19. The method of claim 18, wherein the germanium concentration "x" in the relaxed Si(1-x)Ge(x) material forms a germanium concentration gradient in the buffer region.

20. The method of claim 19, wherein the crystalline material comprises the silicon germanium and the silicon germanium has a substantially uniform germanium concentration equal to or substantially equal to the germanium concentration "x" in the relaxed Si(1-x)Ge(x) material at the top surface of the buffer region.

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