Universal detection system and method for providing different types of connection interfaces

Abstract

The invention discloses a universal detection system and method for providing different types of connection interfaces, and the method comprises the steps: simulating a boundary scanning element through an FPGA chip of a universal test card, and cooperating with an RC circuit and a differential signal mode conversion element; therefore, different types of to-be-tested interfaces can be provided, the same general test card can be used for pin detection of an input and output pin, a grounding pin, a differential signal pin, a power supply pin and a differential clock signal pin, and the technical effect of universal detection of different types of connection interfaces can be achieved.

Description

Technical Field

[0001] A detection system and method thereof, in particular, refers to a universal detection system and method thereof providing different types of connection interfaces. Background Art

[0002] In the known testing method of providing boundary scan (BS) components, different types of test cards need to be electrically connected when different types of interfaces such as DIMM, PCIE, USB, SATA, etc. on the motherboard are connected. The main reason is that different hardware protocols supported by different interfaces to be tested are different, and the connection method of each pin / pin on the interface is different, so the test method is also different, which leads to the need to design a different test card for each pin / pin to be tested to make it comply with the corresponding hardware protocol.

[0003] When testing a board, a large number of each test card is used, which increases the test cost. In addition, the electrical connection between the test card and the interface to be tested is complex. If different types of test cards are mistakenly electrically connected to the interface to be tested, both the test card and the interface to be tested will be damaged, resulting in an increase in both production cost and test cost.

[0004] In summary, it can be seen that the prior art has long had the problem that different types of test cards are required to test different types of interfaces to be tested, and the testing process is complicated and the testing cost is high. Therefore, it is necessary to propose improved technical means to solve this problem. Summary of the invention

[0005] In view of the problem in the prior art that different types of interfaces to be tested need to be tested using different types of test cards, which results in a complicated test process and high test cost, the present invention discloses a universal detection system and method for providing different types of connection interfaces, wherein:

[0006] The invention discloses a universal detection system providing different types of connection interfaces, which includes: a test board, at least one universal test card, a test access port (TAP) controller, and a test data generating device. The test board has multiple test interfaces.

[0007] The universal test card also includes: a Field Programmable Gate Array (FPGA) chip, an RC circuit (resistor-capacitor circuit), a differential signal mode conversion element, a JTAG input interface, a JTAG output interface and a gold finger interface. The gold finger interface includes multiple input and output pins, multiple ground pins, multiple differential signal pins, multiple power pins and multiple differential clock signal pins.

[0008] The FPGA chip is electrically connected to an RC circuit, a differential signal mode conversion component, a JTAG input interface, a JTAG output interface, input / output pins, ground pins, differential signal pins, and power pins respectively. The differential clock signal pin is electrically connected to the differential signal mode conversion component.

[0009] The FPGA chip simulates a boundary scan (BS) component; the differential signal mode conversion component provides the conversion of HCSL differential signals to LVDS differential signals.

[0010] The gold finger interface of at least one general test card is electrically connected to the corresponding interface to be tested on the board to be tested; at least one general test card is electrically connected to each other through their respective JTAG input interfaces and JTAG output interfaces to form a general test card serial chain; and the boundary scan component simulated by the FPGA chip uses test signals in JTAG format to perform pin detection on the corresponding input / output pins, ground pins, differential signal pins, power pins, and differential clock signal pins of the corresponding interface to be tested and feedback test result signals in JTAG format.

[0011] The TAP controller is electrically connected to the JTAG input interface at the head end and the JTAG output interface at the tail end in the general test card serial chain respectively, converts test data into test signals in JTAG format to provide to the corresponding general test card serial chain, receives test result signals in JTAG format from the general test card serial chain and converts them into response data.

[0012] The test data generation device is electrically connected to the TAP controller, provides test data to the TAP controller, and receives response data corresponding to the interface to be tested from the TAP controller.

[0013] The general detection method for providing different types of connection interfaces disclosed in the present invention includes the following steps:

[0014] First, the motherboard to be tested has multiple interfaces to be tested; next, at least one general-purpose test card has an FPGA chip, an RC circuit, a differential signal mode conversion component, a JTAG input interface, a JTAG output interface, and a gold finger interface. The gold finger interface includes multiple input / output pins, multiple ground pins, multiple differential signal pins, multiple power pins, and multiple differential clock signal pins; next, the FPGA chip is electrically connected to the RC circuit, the differential signal mode conversion component, the JTAG input interface, the JTAG output interface, the input / output pins, the ground pins, the differential signal pins, and the power pins respectively. The differential clock signal pins are electrically connected to the differential signal mode conversion component; next, the FPGA chip simulates a boundary scan component; next, the differential signal mode conversion component provides the conversion of HCSL differential signals to LVDS differential signals; next, the gold finger interface of at least one general-purpose test card is electrically connected to the corresponding interface to be tested on the motherboard to be tested; next, at least one general-purpose test card forms an electrical connection with each other through its respective JTAG input interface and JTAG output interface to form a general-purpose test card cascade chain; next, the TAP controller is electrically connected to the JTAG input interface at the head end and the JTAG output interface at the tail end in the general-purpose test card cascade chain respectively; next, the test data generation device is electrically connected to the TAP controller to provide test data to the TAP controller; next, the TAP controller converts the test data into a JTAG format test signal to provide it to the corresponding general-purpose test card cascade chain; next, the boundary scan component simulated by the FPGA chip of at least one general-purpose test card in the general-purpose test card cascade chain uses the JTAG format test signal to perform pin detection on the corresponding input / output pin positions, ground pin positions, differential signal pin positions, power pin positions, and differential clock signal pin positions of the corresponding interface to be tested and feedbacks a JTAG format test result signal back to the TAP controller; next, the TAP controller receives the JTAG format test result signal from the general-purpose test card cascade chain and converts it into response data; finally, the test data generation device receives the response data corresponding to the interface to be tested from the TAP controller.

[0015] As described above, the system and method disclosed in the present invention use the FPGA chip of the general-purpose test card to simulate the boundary scan component, and then cooperate with the RC circuit and the differential signal mode conversion component, so that different types of interfaces to be tested can use the same general-purpose test card to perform pin detection on the input / output pin positions, ground pin positions, differential signal pin positions, power pin positions, and differential clock signal pin positions.

[0016] Through the above technical means, the present invention can achieve the technical effect of providing general-purpose detection of different types of connection interfaces. Description of the Drawings

[0017] Figure 1It is a system block diagram of a general detection system for providing different types of connection interfaces according to the present invention.

[0018] Figure 2 It is a block diagram of a general test card for general detection of different types of connection interfaces provided by the present invention.

[0019] Figure 3 It is a block diagram of an analog boundary scan element for general detection of different types of connection interfaces provided by the present invention.

[0020] Figure 4 It is a test architecture diagram for general detection of different types of connection interfaces provided by the present invention.

[0021] Figures 5A to 5C It is a method flow chart of a general detection method for different types of connection interfaces provided by the present invention.

[0022] Figure 6 It is a detailed flow chart of a general detection method for different types of connection interfaces provided by the present invention.

[0023] The description of the reference numerals is as follows:

[0024] 10: Printed circuit board under test

[0025] 11: Interface under test

[0026] 12: Boundary scan element

[0027] 20: General test card

[0028] 21: FPGA chip

[0029] 211: Instruction register

[0030] 212: Identification register

[0031] 213: Power register

[0032] 214: Differential clock signal register

[0033] 215: First boundary scan register

[0034] 216: Second boundary scan register

[0035] 22: RC circuit

[0036] 23: Differential signal mode conversion element

[0037] 24: JTAG input interface

[0038] 25: JTAG output interface

[0039] 26: Gold finger interface

[0040] 261: Input / Output Pin

[0041] 262: Ground Pin

[0042] 263: Differential Signal Pin

[0043] 264: Power Supply Pin

[0044] 265: Differential Clock Signal Pin

[0045] 30: TAP Controller

[0046] 40: Test Data Generation Device

[0047] 50: Adapter Card

[0048] Step 501: The board to be tested has multiple interfaces to be tested

[0049] Step 502: At least one general test card has an FPGA chip, an RC circuit, a differential signal mode conversion component, a JTAG input interface, a JTAG output interface, and a gold finger interface. The gold finger interface includes multiple input / output pins, multiple ground pins, multiple differential signal pins, multiple power supply pins, and multiple differential clock signal pins

[0050] Step 503: The FPGA chip is electrically connected to the RC circuit, the differential signal mode conversion component, the JTAG input interface, the JTAG output interface, the input / output pins, the ground pins, the differential signal pins, and the power supply pins respectively. The differential clock signal pin is electrically connected to the differential signal mode conversion component

[0051] Step 504: The FPGA chip simulates a boundary scan component

[0052] Step 505: The differential signal mode conversion component provides the conversion of HCSL differential signals to LVDS differential signals

[0053] Step 506: The gold finger interface of at least one general test card is electrically connected to the corresponding interface to be tested on the board to be tested

[0054] Step 507: At least one general test card forms an electrical connection with each other through their respective JTAG input interfaces and JTAG output interfaces to form a general test card serial chain

[0055] Step 508: The TAP controller is electrically connected to the JTAG input interface at the head end and the JTAG output interface at the tail end in the general test card serial chain respectively

[0056] Step 509: The test data generation device is electrically connected to the TAP controller and provides test data to the TAP controller

[0057] Step 510: The TAP controller converts the test data into test signals in JTAG format to be provided to the corresponding general test card cascade chain.

[0058] Step 511: The boundary scan elements simulated by the FPGA chips of at least one general test card in the general test card cascade chain use the test signals in JTAG format to perform pin detection on the corresponding input / output pins, ground pins, differential signal pins, power supply pins, and differential clock signal pins of the corresponding interface to be tested and feedback the test result signals in JTAG format back to the TAP controller.

[0059] Step 512: The TAP controller receives the test result signals in JTAG format from the general test card cascade chain and converts them into response data.

[0060] Step 513: The test data generation device receives the response data corresponding to the interface to be tested from the TAP controller.

[0061] Step 601: Analyze the type of each interface to be tested and the definition of pins / pin positions.

[0062] Step 602: The general test card receives the Start-capture expansion instruction to read the differential clock frequency and the signals of the power supply pins.

[0063] Step 603: Determine the pin type.

[0064] Step 604: The general test card receives the Read-power expansion instruction to read the power supply value, and then determines whether the power supply value of the actual power supply pin is correct, and abandons the remaining power supply values.

[0065] Step 605: The general test card receives the Read-CLK expansion instruction to read the differential clock frequency, and then determines whether the differential clock frequency of the actual differential clock pin is correct, and abandons the remaining differential clock frequencies.

[0066] Step 606: The general test card receives the sample expansion instruction to read the signal of the GND pin, and then determines whether the signal is 0.

[0067] Step 607: Determine the interface type.

[0068] Step 608: The general test card receives Switch-BSR to switch to the second boundary scan register.

[0069] Step 609: Determine the pin type.

[0070] Step 610: Complete the differential interconnection test using the 1149.6 EXTEST_PULSE instruction.

[0071] Step 611: Complete the IO interconnection test using the 1149.6 EXTEST instruction

[0072] Step 612: Obtain the test results and perform coverage analysis Detailed implementation manner

[0073] The following will describe in detail the implementation manner of the present invention in conjunction with the drawings and embodiments, so as to fully understand how the present invention applies technical means to solve technical problems and achieve the realization process of technical effects and implement accordingly.

[0074] First, the general detection system for providing different types of connection interfaces disclosed by the present invention will be described, and please refer to Figure 1 as shown Figure 1 which is a system block diagram of the general detection system for providing different types of connection interfaces according to the present invention.

[0075] The general detection system for providing different types of connection interfaces disclosed by the present invention includes: a motherboard 10 to be tested, at least one general test card 20, a TAP controller 30, and a test data generation device 40.

[0076] The motherboard 10 to be tested has a plurality of interfaces 11 to be tested. The interfaces 11 to be tested include Dual In-line Memory Module (DIMM), Peripheral Component Interconnect Express (PCIE), Universal Serial Bus (USB), and Serial Advanced Technology Attachment (SATA) interfaces... etc. This is only for illustrative purposes and does not limit the application scope of the present invention.

[0077] Please refer to Figure 2 as shown Figure 2 which is a block diagram of the general test card for general detection of different types of connection interfaces provided by the present invention.

[0078] The general test card 20 also includes: a Field Programmable Gate Array (FPGA) chip 21, an RC circuit (resistor–capacitor circuit, which can also be referred to as an RC network / RC network) 22, a differential signal mode conversion component 23, a JTAG input interface 24, a JTAG output interface 25, and a gold finger interface 26. The gold finger interface 26 includes multiple input / output pins 261, multiple ground pins 262, multiple differential signal pins 263, multiple power pins 264, and multiple differential clock signal pins 265. The gold finger interface 26 also includes interfaces such as DIMM, PCIE, USB, and SATA... etc. This is only for illustrative purposes and does not limit the application scope of the present invention.

[0079] The FPGA chip 21 is electrically connected to the RC circuit 22, the differential signal mode conversion component 23, the JTAG input interface 24, the JTAG output interface 25, the input / output pins 261, the ground pins 262, the differential signal pins 263, and the power pins 264 respectively. The differential clock signal pin 265 is electrically connected to the differential signal mode conversion component 23.

[0080] In the general test card 20, the power pins 264 cooperate with the RC circuit 22 so that the FPGA chip 21 can implement the function of ADC reading. The differential clock signal pin 265 needs to convert the HCSL differential signal of the differential signal mode conversion component 23 into an LVDS differential signal so that the FPGA chip 21 can read the differential clock signal. The conversion of the HCSL differential signal of the RC circuit 22 and the differential signal mode conversion component 23 into an LVDS differential signal can refer to the description of the prior art and will not be elaborated herein.

[0081] Since the definitions and position distributions of the pins / pin positions of the DIMM, PCIE, USB, and SATA interfaces are different, the gold finger interface 26 will design a part of the pins as common pins. Specifically, taking 288 pins as an example, 20 pins out of the 288 pins are selected and designed to be directly connected to the FPGA chip 21 and cooperate with the auxiliary RC circuit 22, so that the selected 20 pins can support the testing of both the input / output circuit and the power circuit at the same time; 6 pins out of the 288 pins are selected and designed to be directly connected to the FPGA chip 21 and cooperate with the differential signal mode conversion component 23, so that the selected 6 pins can support the testing of both the input / output circuit and the differential clock line at the same time. Through the above pin configuration, the testing requirements of the DIMM, PCIE, USB, and SATA interfaces can be met. This is only for illustrative purposes and does not limit the application scope of the present invention.

[0082] Please refer to Figure 3 as shown Figure 3 which is a block diagram of an analog boundary scan element for general detection of different types of connection interfaces provided by the present invention.

[0083] In the present invention, an FPGA chip 21 is used to simulate a boundary scan element. The boundary scan element simulated by the FPGA chip 21 includes an Instruction Register 211, an Identification Register 212, a Power Register 213, a Differential CLK Register 214, a first Boundary-scan register 215, and a second Boundary-scan register 216.

[0084] The Identification Register 212 records the IDCODE value of the boundary scan element simulated by the FPGA chip 21, and the Identification Register 212 is a 32-bit register.

[0085] The Power Register 213 records the power value read from the power pin 264. Each power pin 264 needs to occupy 8 bits to record the power value. The Power Register 213 uses corresponding bit registers according to the different numbers of power pins 264. Specifically, if there are 20 power pins 264, the Power Register 213 is a 160-bit register.

[0086] The Differential CLK Register 214 records the differential clock frequency of the differential clock signal pin 265. Each differential clock signal pin 265 needs to occupy 8 bits to record the differential clock frequency. The Differential CLK Register 214 also uses corresponding bit registers according to the different numbers of differential clock signal pins 265. Specifically, if there are 6 differential clock signal pins 265, the Differential CLK Register 214 is a 48-bit register.

[0087] The first Boundary-scan register 215 configures all the pins of the edge connector interface 26 as input / output functions / ground functions. Each pin has an input cell, an output cell, and a control cell. The first Boundary-scan register 215 also uses corresponding bit registers according to the number of all the pins of the edge connector interface 26. Specifically, if the number of all the pins of the edge connector interface 26 is 288, the first Boundary-scan register 215 is an 864-bit register, and the first Boundary-scan register 215 is provided for the general test card 20 to test the DIMM interface.

[0088] The second boundary scan register 216 configures some pins of the gold finger interface 26 as input / output functions and some pins as differential functions. For the pins configured as differential functions, half of them are configured as TX and half as RX. A relatively classic configuration method is to select 32 pins to be configured as differential TX, select 32 pins to be configured as differential RX, and the remaining pins are configured as input / output functions. Each pin configured as an input / output function has an input unit, an output unit, and a control unit. Each pin configured as TX DP has an output unit. Each pin configured as TX DN has an observe-only unit. Each pin configured as RX DP and RX DN has an input unit. The second boundary scan register 216 also uses corresponding bit registers according to the configurations corresponding to all the pins of the gold finger interface 26. Specifically, if the gold finger interface 26 has a classic configuration, the second boundary scan register 216 is a 736-bit register, and the second boundary scan register 216 is used to provide the general test card 20 to test PCIE, USB, and SATA interfaces.

[0089] In addition to standard JTAG instructions (such as: IDCODE, BYPASS, EXTEST, EXTEST_PULSE..., etc., which are only for illustrative purposes here and do not limit the application scope of the present invention), the boundary scan elements simulated by the FPGA chip 21 can also execute extended instructions such as Start-capture, Read-power, Read-CLK, and Switch-BSR..., etc., which are only for illustrative purposes here and do not limit the application scope of the present invention.

[0090] The above Start-capture extended instruction is used to provide a one-time reading of the differential clock frequencies of all differential signal pins 263 and the signals of the power pins 264 and record them in the power register 213 and the differential clock signal register 214 to provide subsequent Read-power and Read-CLK extended instructions to read the power values and differential clock frequencies; the above Read-power extended instruction is used to provide reading of the power values of the power pins recorded in the power register 213; the above Read-CLK extended instruction is used to provide reading of the differential clock frequencies of the differential signal pins 263 recorded in the differential clock signal register 214; the above Switch-BSR extended instruction is used to provide switching between the first boundary scan register 215 and the second boundary scan register 216.

[0091] The gold finger interface 26 of at least one general test card 20 is electrically connected to the corresponding interface to be tested 11 of the board to be tested 10; at least one general test card 20 forms an electrical connection with each other through its respective JTAG input interface 24 and JTAG output interface 25 to form a serial connection chain of general test cards. Specifically, the first JTAG output interface of the first general test card is electrically connected to the second JTAG input interface of the second general test card, the second JTAG output interface of the second general test card is electrically connected to the third JTAG input interface of the third general test card, and the third JTAG output interface of the third general test card is electrically connected to the fourth JTAG input interface of the fourth general test card, thereby connecting the first general test card, the second general test card, the third general test card, and the fourth general test card into a serial connection chain of general test cards.

[0092] Please refer to Figure 4 as shown in Figure 4 which is a test architecture diagram of general detection with different types of connection interfaces provided by the present invention.

[0093] The general test card 20 forms an electrical connection with the corresponding interface to be tested 11 of the board to be tested 10 through the gold finger interface 26. It should be noted that the gold finger interface 26 of the general test card 20 can also be electrically connected to the corresponding interface to be tested 11 of the board to be tested 10 through a riser card 50.

[0094] The TAP controller 30 is electrically connected to the JTAG input interface at the head end and the JTAG output interface at the tail end in the serial connection chain of general test cards respectively. The test data generation device 40 is electrically connected to the TAP controller 30. The test data generation device 40 provides test data to the TAP controller 30, and the TAP controller 30 converts the test data into test signals in JTAG format to provide to the corresponding serial connection chain of general test cards. It should be noted that the TAP controller 30 can also be directly electrically connected to the boundary scan element 12 on the board to be tested 10.

[0095] The boundary scan element simulated by the FPGA chip 21 uses test signals in JTAG format to detect the corresponding input / output pin positions, ground pin positions, differential signal pin positions, power pin positions, and differential clock signal pin positions of the corresponding interface to be tested 11 and feedbacks test result signals in JTAG format back to the TAP controller 30.

[0096] The TAP controller 30 receives test result signals in JTAG format from the serial connection chain of general test cards, converts them into response data, and then provides the response data to the test data generation device 40 to complete the test of the interface to be tested 11.

[0097] Next, the operation method of the present invention will be described below, and please also refer to Figures 5A to 5C as shown Figures 5A to 5C which is a flowchart of a general detection method for providing different types of connection interfaces according to the present invention.

[0098] The general detection method for providing different types of connection interfaces disclosed in the present invention includes the following steps:

[0099] First, the motherboard to be tested has a plurality of interfaces to be tested (step 501); then, at least one general test card has an FPGA chip, an RC circuit, a differential signal mode conversion element, a JTAG input interface, a JTAG output interface, and a gold finger interface. The gold finger interface includes a plurality of input / output pins, a plurality of ground pins, a plurality of differential signal pins, a plurality of power pins, and a plurality of differential clock signal pins (step 502); then, the FPGA chip is electrically connected to the RC circuit, the differential signal mode conversion element, the JTAG input interface, the JTAG output interface, the input / output pins, the ground pins, the differential signal pins, and the power pins respectively, and the differential clock signal pins are electrically connected to the differential signal mode conversion element (step 503); then, the FPGA chip simulates a boundary scan element (step 504); then, the differential signal mode conversion element provides the conversion of HCSL differential signals to LVDS differential signals (step 505); then, the gold finger interface of at least one general test card is electrically connected to the corresponding interface to be tested on the motherboard to be tested (step 506); then, at least one general test card forms an electrical connection with each other through its respective JTAG input interface and JTAG output interface to form a general test card cascade chain (step 507); then, the TAP controller is electrically connected to the JTAG input interface at the head end and the JTAG output interface at the tail end in the general test card cascade chain respectively (step 508); then, the test data generation device is electrically connected to the TAP controller to provide test data to the TAP controller (step 509); then, the TAP controller converts the test data into a JTAG format test signal to provide to the corresponding general test card cascade chain (step 510); then, the boundary scan element simulated by the FPGA chip of at least one general test card in the general test card cascade chain uses the JTAG format test signal to perform pin detection on the corresponding input / output pin positions, ground pin positions, differential signal pin positions, power pin positions, and differential clock signal pin positions of the corresponding interface to be tested and feedbacks a JTAG format test result signal back to the TAP controller (step 511); then, the TAP controller receives the JTAG format test result signal from the general test card cascade chain and converts it into response data (step 512); finally, the test data generation device receives the response data corresponding to the interface to be tested from the TAP controller (step 513).

[0100] Please refer toFigure 6 As shown Figure 6 It is a detailed flowchart showing the general detection method for different types of connection interfaces provided by the present invention.

[0101] First, analyze the type of each interface to be tested and the definition of pins / pin positions (step 601); then, the general test card receives the Start-capture expansion instruction to read the differential clock frequency and the signals of the power pins (step 602); then, determine the pin type (step 603); then, the general test card receives the Read-power expansion instruction to read the power value, and then determine whether the power value of the actual power pin is correct, and discard the remaining power values (step 604); then, the general test card receives the Read-CLK expansion instruction to read the differential clock frequency, and then determine whether the differential clock frequency of the actual differential clock pin is correct, and discard the remaining differential clock frequencies (step 605); then, the general test card receives the sample expansion instruction to read the signal of the GND pin, and then determine whether the signal is 0 (step 606); then, determine the interface type (step 607); then, the general test card receives Switch-BSR to switch to the second boundary scan register (step 608); then, determine the pin type (step 609); then, use the 1149.6 EXTEST_PULSE instruction to complete the differential interconnection test (step 610); then, use the 1149.6 EXTEST instruction to complete the IO interconnection test (step 611); finally, obtain the test results and perform coverage analysis (step 612).

[0102] In summary, by simulating the boundary scan element with the FPGA chip of the general test card, and then cooperating with the RC circuit and the differential signal mode conversion element, it is possible to use the same general test card to detect the pin positions of input / output pin positions, ground pin positions, differential signal pin positions, power pin positions, and differential clock signal pin positions for different types of interfaces to be tested.

[0103] By this technical means, it is possible to solve the problems existing in the prior art that different types of interfaces to be tested need to use different types of test cards for testing, resulting in a complex test process and a high test cost, and thus achieve the technical effect of providing general detection for different types of connection interfaces.

[0104] Although the embodiments disclosed in the present invention are as above, the content described is not intended to directly limit the scope of patent protection of the present invention. Any person of ordinary skill in the art can make some modifications in the form of implementation and details without departing from the spirit and scope disclosed in the present invention. The scope of patent protection of the present invention shall still be subject to the scope defined by the appended claims.

Claims

1. A general detection system providing different types of connection interfaces, comprising: A circuit board to be tested, having a plurality of interfaces to be tested; At least one general test card, and each general test card further comprises: A field programmable gate array chip to simulate a boundary scan element; An RC circuit, electrically connected to the field programmable gate array chip; A differential signal mode conversion element, electrically connected to the field programmable gate array chip, and the differential signal mode conversion element provides conversion of HCSL differential signals to LVDS differential signals; A JTAG input interface, electrically connected to the field programmable gate array chip; A JTAG output interface, electrically connected to the field programmable gate array chip; and A gold finger interface, comprising a plurality of input / output pins, a plurality of ground pins, a plurality of differential signal pins, a plurality of power pins, and a plurality of differential clock signal pins. The input / output pins are electrically connected to the field programmable gate array chip, the ground pins are electrically connected to the field programmable gate array chip, the differential signal pins are electrically connected to the field programmable gate array chip, the power pins are electrically connected to the field programmable gate array chip, and the differential clock signal pins are electrically connected to the differential signal mode conversion element; Wherein, The gold finger interface of the at least one general test card is electrically connected to the corresponding interface to be tested of the circuit board to be tested; The at least one general test card is electrically connected to each other through their respective JTAG input interfaces and JTAG output interfaces to form a serial connection chain of general test cards; and The boundary scan element simulated by the field programmable gate array chip uses test signals in JTAG format to perform pin detection on the corresponding input / output pin positions, ground pin positions, differential signal pin positions, power pin positions, and differential clock signal pin positions of the corresponding interface to be tested and feedbacks a test result signal in JTAG format; A test access port controller, electrically connected to the JTAG input interface at the head end and the JTAG output interface at the tail end in the serial connection chain of general test cards respectively, converts test data into the test signals in JTAG format to provide to the corresponding serial connection chain of general test cards, receives the test result signals in JTAG format from the serial connection chain of general test cards and converts them into response data; and A test data generation device, electrically connected to the test access port controller, provides the test data to the test access port controller, and receives the response data corresponding to the interface to be tested from the test access port controller.

2. The general detection system providing different types of connection interfaces according to claim 1, wherein the gold finger interface of the at least one general test card is electrically connected to the corresponding interface to be tested of the circuit board to be tested through an adapter card.

3. The general detection system for providing different types of connection interfaces as claimed in claim 1, wherein the motherboard to be tested further has a motherboard boundary scan component, the test access port controller is electrically connected to the motherboard boundary scan component, and the motherboard boundary scan component receives the test signal in JTAG format from the test access port controller for detection and feeds back the test result signal in JTAG format to the test access port controller.

4. The general detection system for providing different types of connection interfaces as claimed in claim 1, wherein the boundary scan component includes an instruction register, an identification register, a power register, a differential clock signal register, a first boundary scan register, and a second boundary scan register.

5. The general detection system for providing different types of connection interfaces as claimed in claim 1, wherein the interface to be tested and the gold finger interface include DIMM, PCIE, USB, and SATA interfaces.

6. A general detection method for providing different types of connection interfaces, comprising the following steps: The motherboard to be tested has a plurality of interfaces to be tested; At least one general test card has a field programmable gate array chip, an RC circuit, a differential signal mode conversion component, a JTAG input interface, a JTAG output interface, and a gold finger interface, and the gold finger interface includes a plurality of input / output pins, a plurality of ground pins, a plurality of differential signal pins, a plurality of power pins, and a plurality of differential clock signal pins; The field programmable gate array chip is electrically connected to the RC circuit, the differential signal mode conversion component, the JTAG input interface, the JTAG output interface, the input / output pins, the ground pins, the differential signal pins, and the power pins respectively, and the differential clock signal pins are electrically connected to the differential signal mode conversion component; The field programmable gate array chip simulates a boundary scan component; The differential signal mode conversion component provides conversion of HCSL differential signals to LVDS differential signals; The gold finger interface of the at least one general test card is electrically connected to the corresponding interface to be tested of the motherboard to be tested; The at least one general test card is electrically connected to each other through their respective JTAG input interfaces and JTAG output interfaces to form a serial chain of general test cards; A test access port controller is electrically connected to the JTAG input interface at the head end and the JTAG output interface at the tail end in the serial chain of general test cards respectively; A test data generation device is electrically connected to the test access port controller to provide test data to the test access port controller; The test access port controller converts the test data into a test signal in JTAG format to provide to the corresponding serial chain of general test cards; The boundary scan element simulated by the field programmable gate array chip of at least one general test card in the general test card cascade chain uses the test signal in JTAG format to perform pin detection on the corresponding input / output pins, ground pins, differential signal pins, power supply pins, and differential clock signal pins of the corresponding interface to be tested and feedback the test result signal in JTAG format back to the test access port controller; The test access port controller receives the test result signal in JTAG format from the general test card cascade chain and converts it into response data; and The test data generation device receives the response data corresponding to the interface to be tested from the test access port controller.

7. The general detection method for providing different types of connection interfaces as claimed in claim 6, wherein the gold finger interface of the at least one general test card is electrically connected to the corresponding interface to be tested of the board to be tested through an adapter card.

8. The general detection method for providing different types of connection interfaces as claimed in claim 6, wherein the board to be tested further has a board boundary scan element, the test access port controller is electrically connected to the board boundary scan element, and the board boundary scan element receives the test signal in JTAG format from the test access port controller for detection and feedbacks the test result signal in JTAG format back to the test access port controller.

9. The general detection method for providing different types of connection interfaces as claimed in claim 6, wherein the boundary scan element includes an instruction register, an identification register, a power supply register, a differential clock signal register, a first boundary scan register, and a second boundary scan register.

10. The general detection method for providing different types of connection interfaces as claimed in claim 6, wherein the interface to be tested and the gold finger interface include DIMM, PCIE, USB, and SATA interfaces.

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