A preparation and coupling optimization method of a bar-shaped SOI waveguide using end face coupling

Abstract

A preparation and coupling optimization method of bar SOI waveguide using end face coupling belongs to the field of micro-nano fine structure processing and optical precision measurement. Through two-step photoetching and two-step etching, on one hand, the base section plane highly coinciding with the waveguide end face can be etched, and on the other hand, the etching widening of the Si base etching channel cannot cause the waveguide below to be hollowed out. By using the DC magnetron sputtering Cr mask, the waveguide material can be prevented from being etched and damaged in the deep silicon etching process. Through the ion beam etching process, the waveguide end face and the base etching sidewall are completely coincided, so that part of the light spot is avoided from being scattered by the Si base in the optical fiber coupling process, and the coupling efficiency of the waveguide is improved. By combining the FDTD simulation results, the ICP-PECVD is used to deposit the low internal stress SiO2+Si3N4 antireflection film with a suitable thickness on the waveguide end face, the light spot is avoided from being reflected on the waveguide end face, and the light spot coupling efficiency is maximized.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of micro-nano fine structure processing and optical precision measurement, and relates to a preparation and coupling optimization method of a strip-shaped SOI waveguide adopting end face coupling. BACKGROUND

[0002] Due to the higher transmission rate and lower transmission loss of light relative to electrons, silicon-based waveguides provide a new foundation for the miniaturization and integration of near-infrared electromagnetic wave quantum optical circuits. In addition, silicon-based waveguides are compatible with complementary metal oxide semiconductor (COMS) technology, which provides a basis and scalability for their large-scale application. For example, in the field of artificial intelligence, the high transmission speed of silicon-based waveguides is expected to improve the operation speed of artificial intelligence chips. In the field of silicon-based chips, due to the robustness of its mechanical properties, light has a more stable transmission path during propagation, which greatly reduces the crosstalk in the light transmission process and increases the accuracy in the light interference measurement process. The waveguide based on SiO2 can achieve sub-wavelength stability in the direction of the optical path, which enables the linear optical network formed thereby to achieve high-contrast interference of single photons or classical light.

[0003] The structure of a general SOI (Silicon-On-Insulator) substrate mainly presents a sandwiched structure similar to a sandwich, that is, the top layer material (such as Si, LiTaO3, LiNbO3, Si3N4, SiO2, etc.), an insulating layer, and a silicon substrate in turn from top to bottom. Due to the high refractive index and low transmission loss of the top layer film of the SOI substrate, the optical waveguide prepared based on the SOI structure generally has a high quality factor. In the SOI waveguide, there is a few microns of SiO2 insulating layer between the Si substrate and the waveguide, but the bottom layer Si etching edge in the micro-nano processing and etching process presents strong isotropic etching, while the SiO2 intermediate layer has weak isotropic etching. Due to the difference in etching properties of the two materials, the SiO2 edge and the Si substrate edge at the etching edge of the SOI waveguide often cannot coincide, which will result in that the fiber spot cannot be fully coupled with the waveguide end face in the subsequent fiber coupling process, and finally lead to a low optical coupling efficiency of the waveguide.

[0004] Due to the high refractive index of Si and the strong transparency of Si in the 1.1-1.5 μm waveband, Si waveguides have stronger confinement ability and lower transmission loss for light than SiO2 and Si3N4 waveguides. However, Si is more easily etched by fluorine-containing gas than SiO2 and Si3N4, which makes Si waveguides more likely to be damaged during etching due to insufficient mask coverage.

[0005] In the past SOI waveguide end face processing technology, often use scribe machine to sample scribing to make waveguide end face exposed in the silicon wafer edge, and then use optical fiber end face coupling. But due to the scribe machine scribing position uncertainty is larger (error ~ 10 μm), it is difficult to accurately cut to the waveguide end face, resulting in low optical coupling efficiency, and easy to cause waveguide sample damage. In addition to waveguide-fiber direct coupling, waveguide-grating coupling is also a common waveguide coupling mode, but due to the grating optical mode field and waveguide between there is a certain mismatch problem, which usually means that the grating coupling efficiency is lower than the fiber end face coupling. In addition, some research, through photo etching, evaporation Cr mask, the sample is immersed in etching liquid to realize the pattern transfer. But due to the strong anisotropy of wet etching, it is difficult to realize high resolution pattern transfer and has poor etching precision, and it is difficult to ensure that the SOI waveguide is effectively protected. In the past SOI waveguide end face processing technology, often use mechanical + chemical method to polish the waveguide end face after slicing. But due to the abrasive particles used in mechanical polishing itself has a certain roughness, resulting in the roughness of the waveguide end face is difficult to control to a lower value.

[0006] The traditional use of dry etching out of the SOI waveguide coupling end face through photoresist mask, fiber end face etching waveguide end face alignment to couple electromagnetic wave. But due to the diffraction effect of ultraviolet light and the photoresist sidewall edge has poor steepness, and subject to the photoresist mask has lower selectivity and etching sidewall roughness, which will lead to the substrate sidewall etched as a mask has poor steepness and roughness. And because the fiber cladding diameter is generally about 100 μm size, and the fiber end face and waveguide end face need to be in the 4 μm below the spacing to realize the mode coupling, which requires the control of the waveguide end face in the substrate section within one micron, to avoid single mode fiber and waveguide coupling when there is a large mode field mismatch.

[0007] In the past research, often use phosphoric acid, nitric acid and other chemical methods to polish the etching sidewall and waveguide end face. Or use in hydrogen gas with high temperature annealing process to improve the Si waveguide surface atomic migration rate, so that the Si waveguide surface becomes smoother. But because SiO2, Si3N4 in high temperature is easy to be reduced by hydrogen, so the above method is not suitable for SiO2, Si3N4 and other Si nitrogen, oxygen compounds constitute the waveguide. And hydrogen gas high temperature annealing process needs to strictly control the temperature, gas flow, vacuum degree, etc., which greatly increases the complexity of the process.

[0008] In the past research, in the etching waveguide end face is usually directly coupled with the fiber end face, such as using lensed fiber, tapered fiber and waveguide end face direct alignment coupling, and the fiber end face and waveguide end face there is a few microns of air gap, which makes the waveguide end face there is a certain light reflection, which reduces the optical coupling efficiency. SUMMARY

[0009] The application aims to provide a preparation and coupling optimization method of strip SOI waveguide with end face coupling, which can realize efficient fiber end face alignment of strip SOI waveguide, improve waveguide coupling precision, and realize efficient coupling of SOI waveguide and fiber end face.

[0010] The application is realized by the following technical scheme:

[0011] The application discloses a preparation and coupling optimization method of strip SOI waveguide with end face coupling, characterized by comprising the following steps,

[0012] Step one: spin-coat positive photoresist on the SOI waveguide sample, ultraviolet exposure sample and develop the waveguide end face to transfer the mask strip pattern to the waveguide, wherein the photoresist edge is hundreds of nanometers away from the waveguide end face. A chromium film is deposited on the sample by using a direct current magnetron sputtering, and the photoresist is removed by heating and soaking for several hours, wherein the thickness of the chromium film is greater than the height of the waveguide but less than the thickness of the photoresist, so as to realize the stripping of the metal film. By using ICP-RIE continuous etching process, SF6, Ar and O2 etching gas is introduced to etch the SiO2 film in the etching channel hundreds of nanometers away from the waveguide end face to the thickness of hundreds of nanometers. The sample surface residual Cr is removed by soaking in a chromium etching solution for a sufficient time.

[0013] Step two: spin-coat positive photoresist on the sample again, and transfer the etching channel pattern near the waveguide end face by ultraviolet exposure. The strip etching channel pattern is moved out relative to the etching channel in step one by ultraviolet exposure, and the waveguide end face is controlled to be 5-10 microns away from the etching channel photoresist mask edge. The step considers the etching widening of the channel in the Bosch etching process. Cr film is deposited on the sample after ultraviolet exposure again, and the mask thickness is the same as that in step three. The residual SiO2 film and the underlying Si substrate in the etching channel are etched by using the Bosch etching process of ICP-RIE. The etching channel is disconnected from the substrate by using the mechanical dissociation method.

[0014] Step three: the sample is embedded in molten epoxy resin in advance to fix the sample. First, the ion beam is perpendicular to the sample sidewall, and the ion beam etching is used to polish the substrate section. Secondly, the ion beam and the substrate section are at a small angle to polish the waveguide end face and the Si substrate. The waveguide end face outside the substrate is thinned to tens of nanometers, and finally the waveguide end face and the substrate section are aligned. The sidewall roughness of the substrate is reduced by step three, and the fiber alignment precision is increased.

[0015] Step four: depositing SiO2+Si3N4 with a preset thickness on the sample section using ICP-PECVD. The thickness of each thin film is determined according to the equivalent medium model and the FDTD (Finite-Difference Time-Domain) simulation results. After each ICP-PECVD deposition of a thin film, an ellipsometer is used to measure the actual thickness and optical constants of the deposited thin film to more closely approximate the FDTD simulation results.

[0016] Step five: removing the residual chromium thin film on the surface of the sample using a chromium etching solution. A lensed optical fiber or a tapered optical fiber fixed by a nanometer displacement stage is used for end-face coupling of the waveguide. The movement in the X and Y directions of the nanometer displacement stage and the spatial pitch of the displacement stage need to be adjusted to achieve the best coupling efficiency.

[0017] Preferably, in step one, the photoresist in the channel is removed by soaking in a stripping solution at 85°C for two hours.

[0018] Preferably, in step one, 10% of the channel is left unetched to avoid continuous etching of the Si substrate in the channel, which would cause the etched channel to widen significantly.

[0019] Preferably, in step two, the distance between the end face of the waveguide and the edge of the etched photoresist mask is controlled to be 1 μm.

[0020] Preferably, in step two, the surface is treated with a stripper before the photoresist is applied.

[0021] Advantages:

[0022] 1. The preparation and coupling optimization method of a strip-shaped SOI waveguide using end-face coupling disclosed in the present application can etch a substrate section that is highly coincident with the end face of the waveguide through two-step photolithography and two-step etching. On the one hand, it can ensure that the etching of the Si substrate channel does not cause the waveguide below to be hollowed out. On the other hand, it can improve the surface mobility of Cr atoms on the waveguide sidewall and internal holes by using a direct current magnetron sputtering Cr mask, avoid the decomposition of a thick Cr mask due to a large internal stress difference between the Cr mask and the substrate, and ultimately avoid the damage to the waveguide material caused by etching during deep silicon etching.

[0023] 2. The preparation and coupling optimization method of a strip-shaped SOI waveguide using end-face coupling disclosed in the present application can make the waveguide end face and the substrate etching sidewall completely coincident through the ion beam etching process, thereby avoiding the scattering of part of the light spots by the Si substrate during fiber coupling and improving the coupling efficiency of the waveguide.

[0024] 3. The preparation and coupling optimization method of the bar-shaped SOI waveguide using end face coupling, which combines the FDTD simulation results, uses the ICP-PECVD to deposit the low internal stress anti-reflection film with appropriate thickness on the waveguide end face, avoids the reflection of the light spot on the waveguide end face, and makes the light spot coupling efficiency reach the maximum.

[0025] 4. The preparation and coupling optimization method of the bar-shaped SOI waveguide using end face coupling, which uses the PECVD technology to deposit the SiO2+Si3N4 film with appropriate thickness on the waveguide end face according to the equivalent medium model, realizes the interference cancellation of the reflected light on the waveguide end face, and realizes the highest light coupling efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 It is a schematic diagram for the first ultraviolet exposure pattern transfer of the SOI waveguide end face.

[0027] Figure 2 It is a schematic diagram for the preparation of the waveguide Cr mask by using the direct current magnetron sputtering.

[0028] Figure 3 It is a schematic diagram for the etching of the SiO2 film by using the ICP-RIE continuous etching process.

[0029] Figure 4 It is a schematic diagram for the deep silicon etching by using the ICP-RIE Bosch process after the second ultraviolet exposure, development, and Cr plating.

[0030] Figure 5 It is a schematic diagram for the thinning of the substrate of the waveguide outside protruding part by using the IBE.

[0031] Figure 6 It is a schematic diagram for the deposition of the anti-reflection film on the waveguide end face by using the ICP-PECVD.

[0032] Figure 7 It is a schematic diagram for the alignment of the lensed optical fiber after the sample is removed from the Cr.

[0033] In the figure: 101-SOI top layer waveguide, 102-SOI middle insulating layer, 103-SOI bottom layer silicon, 104-etching area photoresist mask, 105-magnetron sputtering schematic diagram, 106-Cr mask, 107-ion beam bombardment device, 108-ICP-PECVD device, 109-SiO2+Si3N4 anti-reflection film, 110-incidence light, 111-optical fiber cladding, 112-optical fiber core. DETAILED DESCRIPTION

[0034] In order to better illustrate the purpose and advantages of the present application, the content of the application is further explained below in combination with the drawings and examples.

[0035] Example 1:

[0036] The embodiment discloses a preparation and coupling optimization method of a bar-shaped SOI waveguide using end face coupling, and the implementation steps are as follows:

[0037] Step one: using positive photoresist ultraviolet exposure, the mask bar pattern is transferred to the vicinity of the waveguide end face, so that the edge of the developed bar photoresist is hundreds of nanometers away from the waveguide end face, as shown in FIG. 1. Figure 1 A thin film of chromium with a suitable thickness is deposited on the sample by using a direct current magnetron sputtering, and the photoresist above the etching channel is removed by a metal stripping technique, as shown in FIG. 2. Figure 2 The ICP-RIE continuous etching process is used to etch the micrometer-thick SiO2 film in the etching channel away from the waveguide end face to a thickness of hundreds of nanometers. The sample surface is immersed in a chromium etching solution for a sufficient time to remove the residual Cr on the sample surface, and deionized water is used to rinse the sample surface to remove surface contamination, as shown in FIG. 3. Figure 3

[0038] Step two: the positive photoresist is spin-coated on the sample again, and the etching channel pattern is transferred away from the vicinity of the waveguide end face by using ultraviolet exposure, and the distance between the waveguide end face and the edge of the etching channel photoresist mask is controlled to be 5-10 μm. The Cr thin film is deposited on the sample after ultraviolet exposure again, and the mask thickness is the same as in step three. The residual SiO2 film in the etching channel and the underlying Si substrate are etched by using the Bosch etching process (etching + passivation) of ICP-RIE, as shown in FIG. 4. Figure 4 The etching channel is disconnected by using a mechanical cleavage method.

[0039] Step three: the sample after mechanical cleavage is first embedded in molten epoxy resin, but the state of the sample sidewall exposed is ensured. After the epoxy resin is cooled and solidified, the sidewall etched by ICP-RIE of the substrate is polished by using ion beam etching technology (Ion Beam Etching, IBE).

[0040] By controlling the appropriate sputtering ion beam current, argon flow, sputtering ion beam energy and sample self-rotation speed, the best etching rate and sidewall roughness are achieved, and finally the protruding part of the waveguide end face outside is thinned to nanometer level, so that the waveguide end face and the etched sidewall of the substrate are aligned, as shown in FIG. 5. Figure 5 This step also reduces the sidewall roughness of the substrate, thereby increasing the optical fiber alignment accuracy.

[0041] ​In the first ion bombardment stage, a relatively high ion energy and beam current are used, and the ion beam is placed at a 90° angle to the sample sidewall to achieve a preliminary thinning effect. In the second ion bombardment stage, a lower ion energy and beam current are used, and the ion beam is placed at a smaller angle to the sample sidewall to polish the waveguide end face and the substrate sidewall, and to expose the waveguide end face.

[0042] Step 4: To reduce the reflection of incident light 110 at the waveguide end face, an antireflection film 109 of appropriate thickness is deposited on the waveguide end face and the etched sidewalls of the sample using ICP-PECVD. Figure 6 As shown. The refractive index and internal stress of SiO2 and Si3N4 need to be controlled by adjusting the partial pressures of oxygen and ammonia during the ICP-PECVD deposition process. The relative thicknesses of the two dielectric films are calculated based on the equivalent dielectric model, the incident light wavelength, and FDTD (Finite-Difference Time-Domain) simulation results.

[0043] This process requires using an atomic force microscope to measure the roughness of the waveguide end face and the antireflection coating, and then inputting this data into the FDTD model. Furthermore, after each step of ICP-PECVD film deposition, an ellipsometer is used to measure the actual thickness and optical constants of the deposited film to more closely approximate the FDTD simulation results.

[0044] Step 5: First, dissolve the epoxy resin coating the sample using acetone. Then, remove any residual chromium film from the sample surface using a chromium etching solution. Finally, end-face coupling of the waveguide is performed using a lensed (with microlenses at the ends) or tapered fiber fixed by a nano-displacement stage. Figure 7 As shown in the figure. This requires adjusting the movement of the nano-displacement stage in the X and Y directions, as well as the spatial pitch of the stage, to achieve the optimal coupling efficiency.

[0045] The above chromium removal process uses 3 grams of cerium ammonium nitrate powder dissolved in 100 ml of distilled water to prepare the chromium etching solution. The chromium removal time is controlled between 10 and 20 minutes, and the chromium removal temperature is room temperature.

[0046] The above detailed description further illustrates the purpose, technical solution, and beneficial effects of the invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating and optimizing the coupling of a strip SOI waveguide employing end-face coupling, characterized in that: Includes the following steps, Step 1: Spin-coat positive photoresist onto the SOI waveguide sample, expose the sample with ultraviolet light and develop it to transfer the mask strip pattern to the vicinity of the waveguide end face. After development, the edge of the photoresist is made hundreds of nanometers away from the waveguide end face. Deposit a chromium film on the sample using DC magnetron sputtering, and then heat and soak it in a resist remover solution for several hours to remove the channel photoresist. The thickness of the chromium film is greater than the height of the waveguide but less than the thickness of the photoresist to achieve metal film stripping. Use an ICP-RIE continuous etching process, introducing SF6, Ar, and O2 etching gases, to etch the SiO2 film in the etching channel hundreds of nanometers away from the waveguide end face to a thickness of hundreds of nanometers. Use a chromium etchant solution to soak for a sufficient time to remove residual Cr from the sample surface. Step 2: Spin-coat positive photoresist onto the sample and transfer the etched channel pattern near the waveguide end face using UV exposure. Control the distance between the waveguide end face and the edge of the photoresist mask for the etched channel to be 5-10 μm. This pattern transfer step takes into account the etch broadening of the channel in the Bosch etching process. Deposit a Cr film again on the UV-exposed sample, with the same mask thickness as in Step 3. Use the Bosch etching process of ICP-RIE to etch the residual SiO2 film in the channel and the underlying Si substrate. Use mechanical dissociation to disconnect the substrate on both sides of the etched channel. Step 3: Embed the sample in molten epoxy resin in advance to fix the sample; First, make the ion beam perpendicular to the side wall of the sample and use ion beam etching to polish the substrate cross-section. Then, make the ion beam and the substrate cross-section at a small angle to polish the waveguide end face and Si substrate, thinning the outer side of the waveguide end face protruding from the substrate to the tens of nanometer level, and finally align the waveguide end face and the substrate cross-section. Step 4: Deposit SiO2+Si3N4 of a predetermined thickness on the sample cross-section using ICP-PECVD; the thickness of each film is calculated and determined based on the equivalent medium model and the finite-difference time-domain (FDTD) simulation results; after each ICP-PECVD film deposition step, an ellipsometry is used to measure the actual thickness and optical constants of the deposited film to more closely approximate the FDTD simulation results; Step 5: Remove the residual chromium film on the sample surface using chromium etching solution; perform end-face coupling of the waveguide using a lensed fiber or tapered fiber fixed by a nano-displacement stage; the movement of the nano-displacement stage in the X and Y directions and the spatial pitch of the stage need to be adjusted to achieve the best coupling efficiency.

2. The fabrication and coupling optimization method of a strip SOI waveguide employing end-face coupling as described in claim 1, characterized in that: In step one, the channel photoresist is removed by soaking in a stripper solution at 85°C for two hours.

3. The fabrication and coupling optimization method of a strip SOI waveguide employing end-face coupling as described in claim 1, characterized in that: In step one, by leaving 10% of the etched channel, the continuous etching process avoids etching into the Si substrate inside the channel, which would cause severe widening of the etched channel.

4. The fabrication and coupling optimization method of a strip SOI waveguide employing end-face coupling as described in claim 1, characterized in that: In step two, the distance between the waveguide end face and the edge of the photoresist mask of the etching channel is controlled to be 1 μm.

5. The fabrication and coupling optimization method of a strip SOI waveguide employing end-face coupling as described in claim 1, characterized in that: In step two, the surface is treated with a glue remover before the glue is evenly applied.

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