Cache data replacement method and related equipment

Abstract

The embodiment of the invention discloses a cache data replacement method and related equipment, which are used for determining a CL for preferentially performing data replacement. In the application, in the operation process of the second process, a second access request for the second data sent by the target application is received. And if each CL in a cache does not store the second data, a plurality of CLs to be replaced in the cache are determined, and the plurality of CLs comprise the first CL. If the first hint state information carried by the first CL in the plurality of CLs is a first hint id and the hint state mapped by the first hint id in the second hint mapping table is an expelling state, replacing the first data in the first CL with the second data, and accessing the second data from the first CL, the first data is data accessed by a first process, and the first process is a process before the second process in the target application.

Description

Technical Field

[0001] This application relates to the field of data storage, and in particular, to a cache data replacement method and related devices. Background Art

[0002] A cache is a memory in a central processing unit (CPU). When the CPU accesses a piece of data, it first checks whether the data is stored in the cache. If so, the CPU directly accesses the data from the cache; otherwise, the CPU accesses the data from other storage modules and stores it in the cache.

[0003] The smallest unit of data stored in the cache is a cache line (CL), that is, the entire storage capacity of the cache is divided into multiple CLs of the same size (for example, 64 bytes). A CL can be maintained and loaded as a whole. Since the cache capacity is limited, when a new piece of data is stored in the cache, there is often no free CL in the cache. At this time, a CL needs to be selected through a cache replacement algorithm, the data in it is evicted, and the new data is stored in this CL, which is called data replacement for the CL. In the current cache replacement algorithm, each CL has a retention priority. When selecting the CL to be replaced by data, the CL with the lowest retention priority is selected.

[0004] However, in many applications, their execution presents multiple different stages, and the data accessed in each stage is different. Based on the existing cache replacement algorithm, when one stage ends and enters the next stage, the CL where the data frequently accessed in the previous stage is still has a high retention priority, making it not easily selected as the CL to be replaced by data, resulting in the CL where the data more frequently accessed in the current stage being more easily selected for data replacement, causing performance degradation. Summary of the Invention

[0005] Embodiments of this application provide a cache data replacement method and related devices for determining the CL that is preferentially replaced by data.

[0006] The first aspect of the present application provides a method for replacing cached data. In the present application, before the second process runs, a second hint mapping table is received. The second hint mapping table includes a hint id and the mapped hint status. The second process is the process of a target application. During the running of the second process, a second access request for the second data sent by the target application is received. If none of the CLs in the cache Cache store the second data, then multiple CLs to be replaced in the Cache are determined. The multiple CLs include a first CL. If the first hint status information carried by the first CL in the multiple CLs is the first hint id, and the hint status mapped by the first hint id in the second hint mapping table is eviction, then the second data is used to replace the first data in the first CL, and the second data is accessed from the first CL. The first data is the data accessed by the first process, and the first process is the process in the target application before the second process.

[0007] In an embodiment of the present application, by writing the second hint mapping table during the second process, it is realized that the first CL where the first data that does not need to be accessed in the second process is located is preferentially replaced with data, so as to overcome the situation that when the process of the target application changes and the data originally accessed is not required to be accessed in the current process, these data can be evicted as soon as possible, avoiding the situation that these data are retained for a long time, and thus improving the performance.

[0008] In some possible implementation manners, before the first process runs, a first replacement configuration is received. The first replacement configuration includes a first address range and a first hint mapping table. The first hint mapping table includes the hint id and the mapped hint status. In the first hint mapping table, the hint status mapped by the first hint id is collection; during the running of the first process, a first access request for the first data sent by the target application is received, and the first data is accessed from the first CL; if the address of the first data belongs to the first address range, then the first hint status information is set to the first hint id. Thus, it is realized that the first CL where the currently accessed first data is located is marked, which is convenient for subsequent data replacement of the first CL.

[0009] In some possible implementation manners, during the running of the first process, an access request for the shared data sent by the target application is received, and the shared data is accessed from the shared CL, where the shared data is data accessed by both the first process and the second process; if the address of the shared data does not belong to the first address range, the shared hint status information carried by the shared CL is set to unconfigured. Thereby, marking the shared CL is avoided, and thus the first CL and the shared CL are distinguished.

[0010] In some possible implementation manners, the hint status mapped by other hint ids except the first hint id in the first hint mapping table is eviction, thereby achieving marking only the first CL currently.

[0011] In some possible implementation manners, by receiving a second replacement configuration, the second replacement configuration includes the second hint mapping table, and the hint status mapped by the first hint id in the second hint mapping table is eviction, thereby obtaining the second hint mapping table.

[0012] In some possible implementation manners, the second replacement configuration further includes a second address range, the hint status mapped by a second hint id in the second hint mapping table is collection, and after accessing the second data from the first CL, if the address of the second data belongs to the second address range, the first hint status information carried by the first CL is set to the second hint id, achieving marking the second CL while performing data replacement on the first CL.

[0013] In some possible implementation manners, the hint status information is carried in the label information of the CL where it is located.

[0014] A second aspect of this application provides a processor, and the processor is used to execute the method described in any one of the foregoing first aspects.

[0015] A third aspect of this application provides a computer-readable storage medium, and instructions are stored in the computer-readable storage medium. When the instructions run on a computer, the computer is enabled to execute the method provided in the foregoing first aspect or any one of the possible implementation manners of the first aspect.

[0016] A fourth aspect of this application provides a computer program product, which includes computer-executable instructions stored in a computer-readable storage medium. At least one processor of the device can read the computer-executable instructions from the computer-readable storage medium, and the execution of the computer-executable instructions by at least one processor causes the device to implement the method provided in the above first aspect or any possible implementation manner of the first aspect.

[0017] A fifth aspect of this application provides a chip system, which includes a processor for supporting the implementation of the functions involved in the above first aspect or any possible implementation manner of the first aspect.

[0018] In a possible design, the chip system may further include a memory for storing necessary program instructions and data. The chip system may be composed of chips or may include chips and other discrete devices.

[0019] Among them, the technical effects brought by the second to fifth aspects or any possible implementation manner thereof can refer to the technical effects brought by the first aspect or different possible implementation manners of the first aspect, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1-1 It is a schematic diagram of the composition structure of a storage system provided by an embodiment of this application;

[0021] Figure 1-2 It is a schematic diagram of accessing data based on a storage system provided by an embodiment of this application;

[0022] Figure 2-1 It is a schematic flowchart of a cache data replacement method provided by an embodiment of this application;

[0023] Figure 2-2 It is another schematic diagram of accessing data based on a storage system provided by an embodiment of this application;

[0024] Figure 2-3 It is another schematic diagram of accessing data based on a storage system provided by an embodiment of this application;

[0025] Figure 2-4 It is a schematic diagram of the address arrangement of data provided by an embodiment of this application;

[0026] Figure 2-5 It is a schematic diagram of multiple processes executed in sequence provided by an embodiment of this application;

[0027] Figure 3-1 It is a schematic flowchart of a cache data replacement method provided by an embodiment of this application;

[0028] Figure 3-2Schematic diagram of the address arrangement of the data provided by the embodiments of the present application;

[0029] Figure 3-3 Schematic diagram of the sequential execution of multiple processes provided by the embodiments of the present application;

[0030] Figure 4 Schematic diagram of the structure of a processor provided by the embodiments of the present application. Detailed implementation manners

[0031] The embodiments of the present application provide a cache data replacement method and related devices for determining a CL for preferentially performing data replacement.

[0032] The embodiments of the present application will be described below with reference to the accompanying drawings.

[0033] Terms such as "first", "second", etc. in the specification, claims and the above-mentioned drawings of the present application are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. It should be understood that such terms can be interchanged under appropriate circumstances, which is only a way of distinguishing objects with the same attributes when describing the embodiments of the present application. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion, so that a process, method, system, product or device including a series of units does not have to be limited to those units, but may include other units not clearly listed or inherent to these processes, methods, products or devices.

[0034] The present application can be applied to a storage system. Please refer to Figure 1-1 , which is a schematic diagram of the structure of the storage system 100. As Figure 1-1 shown, the storage system 100 includes a Cache 110 and a memory 120.

[0035] In some possible implementation manners, the storage system 100 can be applied to a server or a user device, etc., and no limitation is made here.

[0036] Among them, the server is a device that provides computing services and / or storage services. Since the server needs to respond to service requests and process them to provide reliable services, generally speaking, the server should have the ability to undertake and guarantee services, and this server needs to have strong processing capabilities, high stability, high reliability, high security, scalability, and manageability. In the embodiment of the present application, the server may be an x86 server. An x86 server is also called a complex instruction set (CISC) architecture server, that is, the commonly referred to personal computer (PC) server. It is a server based on the PC architecture, using an Intel or other processor chip compatible with the x86 instruction set and the Windows operating system.

[0037] Among them, the user equipment may be a terminal, a mobile station (MS), a mobile terminal (MT), etc. Among them, the terminal may be a mobile phone, a tablet computer (Pad), a computer with wireless transceiver function, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, and so on. The embodiments of the present application do not limit the specific technologies and specific device forms adopted by the user equipment. The user equipment and the server can be directly or indirectly connected through wired or wireless communication methods, and the present application does not limit this here.

[0038] In the embodiment of the present application, Cache 110 is a part of the processor and can be regarded as the internal memory of the processor. Cache 110 can be read and written at any time, and the speed is very fast. It is usually used as a temporary data storage medium for the operating system or other running programs. Although Cache 110 improves the read and write speed of the storage system 100, Cache 110 is expensive and has a small capacity (usually from dozens of kilobytes (KB) to several megabytes (MB), which is much smaller than the capacity of the memory or the hard disk).

[0039] In some possible implementations, the processor can be a single-core processor or a multi-core processor, which is not limited here. In some possible implementations, the processor can be a general-purpose processor, such as a Central Processing Unit (CPU), a graphics processing unit (GPU), a microprocessor, or a coprocessor, etc., which is not limited here. In some possible implementations, the processor can also be a dedicated processor, such as a Digital Signal Processor (DSP), a neural processing unit (NPU), an Application Specific Integrated Circuit (ASIC), and a Field Programmable Gate Array (FPGA), etc., which is not limited here.

[0040] Memory 120 is a memory outside the processor, which is used to temporarily store the operation data in the processor and exchange data with other external memories. Memory 120 is a bridge for the hard disk to communicate with the processor, and all programs in the device run in memory 120. As long as the device starts running, the operating system will transfer the data to be operated from memory 120 to the processor for operation. The capacity of memory 120 is much larger than that of Cache 110, and the data reading speed is much higher than that of the hard disk. Usually, a Solid State Disk (SSD) is used as memory 120.

[0041] In the above storage system 100, when accessing a piece of data, first check whether the data exists in Cache 110. If it exists, directly access the data from Cache 110. Otherwise, obtain the data from memory 120 and store it in Cache 110. Based on this mechanism, as the storage system 110 runs, the data can be gradually stored in Cache 110, enabling faster access to this data and helping to improve the execution performance.

[0042] In some possible implementations, there is a multi-level cache mechanism between Cache 110 and memory 120, that is, there are multiple levels of caches between Cache 110 and memory 120. The so-called "obtain the data from memory 120" includes obtaining the data from any level of the multi-level cache. If the data is not stored in any level of cache between Cache 110 and memory 120, obtain the data from memory 120.

[0043] The smallest unit of data stored in the Cache is the CL. That is, the storage capacity of the entire Cache is divided into multiple CLs of the same size (e.g., 64 bytes). A CL can be maintained as a whole for status and data loading. Since the capacity of the Cache is limited, when a new piece of data is stored in the Cache, there is often no free CL in the Cache. At this time, a CL needs to be selected through the Cache replacement algorithm, the data in it is evicted, and the new data is stored in this CL, which is called data replacement for the CL. In the current Cache replacement algorithm, each CL has a retention priority. When selecting the CL to be replaced by data, the CL with the lowest retention priority will be selected.

[0044] The design goal of the Cache replacement algorithm is to try to identify or speculate on data that will not be frequently used in the future. The current mainstream Cache replacement algorithms mainly include: 1. First Input First Output (FIFO) strategy, which is used to evict the data that was written into the Cache earliest; 2. Least Recently Used (LRU) strategy, which is used to evict the data that has not been accessed in the Cache for the longest time; 3. Least Frequently Used (LFU) strategy, which is used to evict the data that has been accessed the fewest times in the Cache; 4. Re-Reference Interval Prediction (RRIP) strategy, which is used to maintain re-reference prediction values (RRPVs) for each CL. The RRPV represents the predicted time interval for the next access of this CL. The CL with the largest RRPV will be replaced first.

[0045] However, in many applications, their execution shows multiple different stages, and the data accessed in each stage is different. In the existing Cache replacement algorithms, when one stage ends and enters the next stage, the CL where the data that was frequently accessed in the previous stage is still has a high retention priority, making it not easy to be selected as the CL to be replaced by data, resulting in the CL where the data accessed more frequently in the current stage being more likely to be selected for data replacement, causing performance degradation.

[0046] Exemplarily, the target application includes a first process and a second process. The first process is executed first, and after the execution of the first process ends, the second process starts to execute. Among them, when the first process runs, it needs to access the first data and the shared data, and when the second process runs, it needs to access the second data and the shared data. Then, when the first process ends and the second process runs, since the first data is no longer accessed, a better Cache replacement policy should be to select the CL corresponding to the first data, so as to evict the first data from the Cache. However, the existing Cache replacement algorithms cannot recognize the change in access habits. Then, when the first process runs, as the first data is accessed, the Cache replacement algorithm will assign a higher retention priority to the CL where the first data is located, making it not easy to perform data replacement. After the second process runs, the retention priority of the first data will still generally be higher than that of the shared data, resulting in some shared data being more likely to be replaced than the CL where the first data is located, and then causing Cache misses when accessing these shared data subsequently, leading to performance degradation.

[0047] For this reason, the present application proposes a cache data replacement method and related devices for determining the CLs for which data replacement is to be preferentially performed.

[0048] During the running of the second process, receive a second access request for the second data sent by the target application. If none of the CLs in the cache Cache stores the second data, determine multiple CLs to be replaced in the Cache, and the multiple CLs include a first CL. If the first hint status information carried by the first CL in the multiple CLs is the first hint id, and the hint status mapped by the first hint id in the second hint mapping table is eviction, then replace the first data in the first CL with the second data, and access the second data from the first CL. The first data is the data accessed by the first process, and the first process is the process before the second process in the target application.

[0049] In the embodiments of the present application, by writing the second hint mapping table during the second process, it is realized that the first CL where the first data that is not required to be accessed in the second process is preferentially replaced, thereby overcoming the situation that when the process of the target application changes and the data originally accessed is not required to be accessed in the current process, these data can be evicted as soon as possible, avoiding the situation that these data are retained for a long time, and thus improving the performance.

[0050] In an embodiment of the present application, a configuration interface and a configuration storage module can be provided in a processor. Then, based on the configuration interface, a cache management program can configure replacement configurations (such as a first replacement configuration and a second replacement configuration) written in the storage module. In addition, a control circuit can be built in the processor, and the control circuit can be used to receive and process access requests for data in the CL, and can also execute a Cache replacement algorithm. In some possible implementation manners, the control circuit can include a Cache control circuit and a replacement control circuit, wherein the Cache control circuit is used to receive and process access requests for data in the CL, and the replacement control circuit is used to execute the Cache replacement algorithm.

[0051] In some possible implementation manners, the cache management program can be a software entity running on the processor. Exemplarily, the program file of the storage management program can be stored in a hard disk, and the processor reads the program file from the hard disk to run the cache management program. In some possible implementation manners, the cache management program can provide an interaction interface, and a user can operate the cache management program through the interaction interface to implement the above-mentioned cache data replacement method. In some possible implementation manners, the cache management program can be an independent program on the device, and by interacting with the target application, obtain the running time period of the first process, so as to execute the above-mentioned cache data replacement method; in some possible implementation manners, the cache management program can also be a part of the target application, and the cache management program can be used as one of the functions of the target application to execute the above-mentioned cache data replacement method, which is not limited here.

[0052] Exemplarily, as Figure 1-2 shown, the control circuit includes a Cache control circuit and a replacement control circuit, wherein the Cache control circuit is used to receive an access request for data sent by the target application, and the replacement control circuit is used to execute the Cache replacement algorithm according to the replacement configuration (such as a first replacement configuration or a second replacement configuration) written by the cache management program.

[0053] Please refer to Figure 2-1 , a cache data replacement method provided in Embodiment 1 of the present application mainly includes the following steps:

[0054] 201. Before the first process runs, the cache management program writes a first replacement configuration in the control circuit. The first replacement configuration includes a first address range and a first hint mapping table, and the first hint mapping table includes the hint id and the mapped hint status.

[0055] It should be noted that the first address range includes one or more address value intervals in the memory, and the one or more address values can be continuous or discontinuous, which is not limited here.

[0056] It should be noted that, as Figure 2-2 shown, each CL can carry a hint status information. The value of the hint status information can be unconfigured or a hint id. The hint id is used to determine the mapped hint status according to the replacement configuration, and the hint status can be collection or expulsion. In a hint mapping table, if the hint status mapped by a hint id is collection, it means that the CL with the hint status information of this hint id is marked, and this CL needs to perform data replacement in the next process; in a hint mapping table, if the hint status mapped by a hint id is expulsion, it means that data replacement needs to be performed on the CL with the hint status information of this hint id within the current process. If the hint status information of a CL is unconfigured, no processing needs to be performed on this CL.

[0057] In some possible implementation manners, in the first hint mapping table, the hint status mapped by the first hint id is collection, and the hint statuses mapped by other hint ids except the first hint id are all expulsion.

[0058] Exemplarily, one or more hint ids include 3 hint ids, namely the first hint id, the second hint id, and the third hint id. Exemplarily, as shown in Table 1, the first hint id = 1, the second hint id = 2, and the third hint id = 3. In the first hint mapping table, the hint status mapped by the first hint id with a value of 1 is collection, the hint status mapped by the second hint id with a value of 2 is expulsion, and the hint status mapped by the third hint id with a value of 3 is expulsion.

[0059] Table 1

[0060]

[0061] In some possible implementation manners, in the first hint mapping table, at most only 1 hint id has a mapped hint status of collection at the same time, and the hint statuses mapped by other hint ids are all expulsion. In some possible implementation manners, in the first hint mapping table, 2 or more hint ids can also have a corresponding hint status of collection at the same time, and the hint statuses corresponding to other hint ids are all expulsion, which is not limited here. In some possible implementation manners, in the first hint mapping table, all hint ids can also have a corresponding hint status of expulsion at the same time, which is not limited here.

[0062] It should be noted that the execution of the target application needs to be achieved by executing multiple processes, including a first process and a second process. The first process is used to access the first data and perform operations to obtain a first operation result; the second process is used to access the second data and perform operations to obtain a second operation result. In some possible implementation manners, the first process and / or the second process may be a process or other types of execution processes, which are not limited herein.

[0063] In some possible implementation manners, the first data is a part of the data to be accessed by the first process, and the second data is a part of the data to be accessed by the second process. Exemplarily, the first process is to access data 1a, data 1b, data 1c, and data d, and the second process is to access data 2a, data 2b, data 2c, and data d. Among them, the first data is data 1a, the second data is data 2a, and the shared data is data d.

[0064] In some possible implementation manners, the second data may also be a part of the data that the second process needs to access, rather than a part of the accessed data, which is not limited herein. In the following examples, the case where the second data is a part of the data accessed by the second process is taken as an example for description.

[0065] In the embodiments of the present application, after the first process ends, in order to quickly evict the first data accessed only by the first process and retain the shared data accessed by both the first process and the second process, it is necessary to mark the first CL storing the first data. For this purpose, before executing the first process, it is necessary to first define a first address range including the first data. Since the first replacement configuration includes the first address range where the first data is located, then when the first process accesses the first data, obtain the address of the first data, and based on the first replacement configuration, determine that the address of the first data belongs to the first address range, then the first CL where the first data is located can be marked based on the first hint mapping table, that is, set the first hint status information of the first CL to the first hint id, and the hint status of the first hint id in the first hint mapping table is collection.

[0066] In some possible implementation manners, the cache management program can obtain the running time period of the first process, then write the first replacement configuration on the control circuit before the first process runs. In some possible implementation manners, the cache management program can communicate with the target application to obtain the currently running process and the upcoming running process of the target application, which are not limited herein.

[0067] Exemplarily, such as Figure 2-3As shown, the target application includes a first process and a second process that are executed sequentially. Among them, when the first process runs, it needs to access first data and shared data, and when the second process runs, it needs to access second data and shared data.

[0068] As Figure 2-3 shown, before the first process runs, the cache management program can write a first replacement configuration in the control circuit. The first address range in the first replacement configuration includes the address of the first data, but does not include the address of the shared data. Then, the control circuit can mark the first CL where the first data accessed by the first process is located, that is, set the value of the first hint status information of the first CL to the first hint id.

[0069] In some possible implementation manners, according to the prior knowledge of the software design of the target application, during the writing stage of the software design or before the first process runs at runtime, the content of the shared data, the first data, and the second data is identified in advance, and they are arranged in different address ranges in the memory. In some possible implementation manners, as Figure 2-4 shown, the first address range includes the first data, but does not include the shared data or the second data, which is not limited here.

[0070] 202. During the running of the first process, the control circuit receives a first access request for the first data sent by the target application.

[0071] In some possible implementation manners, when the first process runs and needs to access the first data, the target application can send a first access request for the first data to the control circuit, and the first access request can carry the address of the first data in the memory.

[0072] 203. The control circuit accesses the first data from the first CL based on the first access request.

[0073] In some possible implementation manners, when the first process accesses the first data, first, based on the address of the first data indicated in the first access request, it queries in the Cache which CL stores the first data. If the first CL stores the first data, then the first process can access the first data from the first CL. In some possible implementation manners, if the first data is not stored in any CL, the first process can obtain the first data from the memory, then store it in the first CL, and then access the first data from the first CL, which is not limited here.

[0074] Exemplarily, the process of the first process accessing the first data can be as shown in the following steps S1 to S7:

[0075] S1. The control circuit traverses each CL of the Cache to determine whether there is a CL storing the first data.

[0076] Exemplarily, the Cache includes a first CL, a second CL, and a third CL. The control circuit traverses the first CL, the second CL, and the third CL to determine whether the first data is stored in the first CL, the second CL, or the third CL.

[0077] S2. If the first data is stored in the first CL of the Cache, the control circuit accesses the first data from the first CL.

[0078] S3. If the first data is not stored in any CL of the Cache, the control circuit fetches the first data from the memory.

[0079] S4. If there is an idle first CL in the Cache, the control circuit stores the first data in the first CL and accesses the first data from the first CL.

[0080] S5. If there is no idle CL in the Cache, the control circuit determines multiple CLs to be replaced based on the current Cache replacement algorithm.

[0081] S6. If the first CL among the multiple CLs carries first hint status information, the value of the first hint status information is the second hint id, and the hint status mapped by the second hint id in the first hint mapping table is eviction, the control circuit replaces the data in the first CL with the first data.

[0082] S7. The control circuit updates the retention priorities of the multiple CLs.

[0083] 204. If the address of the first data belongs to the first address range, the control circuit sets the first hint status information to the first hint id.

[0084] In some possible implementation manners, each CL in the Cache carries corresponding tag information, and the tag information further includes the hint status information of the CL, which is not limited here.

[0085] In some possible implementation manners, the value of the hint status information carried by a CL may be a hint id or not configured. The hint id is used to determine the mapped hint status based on a hint mapping table, and the hint status is collection or eviction. Exemplarily, when accessing first data from a first CL, if the control circuit determines that the address of the first data in the first CL belongs to a first address range, the control circuit sets the first hint status information carried by the first CL to a first hint id, where the first hint id is the hint id whose mapped hint status in the first hint mapping table is collection, thereby marking the first CL.

[0086] It should be noted that since the control circuit needs to set the first hint status information carried by the first CL to the hint id whose mapped hint status in the first hint mapping table is collection, it is also necessary to determine that there is a hint id whose mapped hint status in the first hint mapping table is collection.

[0087] Exemplarily, during the running of a first process, the value of the first hint status information carried by the first CL is 2, that is, a second hint id, and the mapped hint status in the first hint mapping table is eviction. Since the address of the first data belongs to the first address range and the hint status mapped by the first hint id in the first hint mapping table is collection, the control circuit can set the first hint status information carried by the first CL to 1, that is, the first hint id, and the hint status mapped by the first hint id in the first hint mapping table is collection, thereby marking the first CL, that is, collecting the first data in the first CL that needs to be evicted in the next process.

[0088] 205. During the running of the first process, the control circuit receives an access request for shared data sent by a target application and accesses the shared data from a shared CL, where the shared data is the data accessed by both the first process and the second process.

[0089] In some possible implementation manners, when the first process accesses the shared data, it first queries in the Cache which CL stores the shared data. If the shared CL stores the shared data, the first process can access the shared data from the shared CL. In some possible implementation manners, if the shared data is not stored in any CL, the first process can obtain the shared data from the memory, then store it in the shared CL, and then access the shared data from the shared CL, which is not limited herein.

[0090] 206. If the address of the shared data does not belong to the first address range, the control circuit sets the shared hint status information carried by the shared CL to unconfigured.

[0091] In some possible implementation manners, when the first process accesses other data that does not belong to the first address range from the CL, the hint status information of the CL can be set to unconfigured. Exemplarily, when the first process accesses the shared data from the shared CL and the shared data stored in the shared CL does not belong to the first address range, then the control circuit sets the shared hint status information corresponding to the shared CL to 0, that is, unconfigured.

[0092] 207. Before the second process runs, the cache management program writes a second replacement configuration in the control circuit. The second replacement configuration includes a second address range and a second hint mapping table. The second hint mapping table includes a hint id and the mapped hint status.

[0093] In the embodiments of the present application, the cache management program can first obtain the running time period of the second process. Then, before the second process runs, the second replacement configuration can be written in the control circuit.

[0094] In some possible implementation manners, when the first process finishes running, the second process can run immediately. In some possible implementation manners, before the second process runs, the cache management program can modify the first replacement configuration to the second replacement configuration. The second replacement configuration includes a second hint mapping table. Compared with the first hint mapping table, in the second hint mapping table, the hint status mapped by the first hint id is eviction, and the hint status mapped by the second hint id in the second hint mapping table is collection. Then, the hint status corresponding to the first CL is eviction. When the second process runs, the control circuit can quickly replace the data of the first CL.

[0095] In some possible implementation manners, in the second hint mapping table, the hint status mapped by the second hint id is collection, and the hint statuses mapped by other hint ids except the second hint id are all eviction.

[0096] Exemplarily, the second hint mapping table is shown in Table 2. The first hint id = 1, the second hint id = 2, and the third hint id = 3. In the second mapping table, the hint state mapped by the first hint id with a value of 1 is eviction, the hint state mapped by the second hint id with a value of 2 is collection, and the hint state mapped by the third hint id with a value of 3 is eviction. Then, since the value of the first hint state information carried in the first CL is 1, the hint state mapped in the first hint mapping table is collection, and the hint state mapped in the second hint mapping table is changed to eviction.

[0097] Table 2

[0098]

[0099] In some possible implementation manners, in the second hint mapping table, at most only 1 hint id has a mapped hint state of collection at the same time, and the hint states mapped by other hint ids are all eviction. In some possible implementation manners, in the second hint mapping table, there can also be 2 or more hint ids with corresponding hint states of collection at the same time, and the hint states corresponding to other hint ids are all eviction, which is not limited here.

[0100] In the embodiment of the present application, after the second process ends, in order to quickly evict the second data accessed only by the second process and retain the shared data accessed by both the first process and the second process, it is necessary to mark the CL storing the second data. For this purpose, before executing the second process, it is necessary to first define a second address range including the second data. Since the second replacement configuration includes the second address range where the second data is located, then when the second process accesses the second data, the address of the second data is obtained, and it is determined based on the second replacement configuration that the address of the second data belongs to this second address range, then the CL where the second data is located can be marked based on the second hint mapping table, that is, the hint state information of the CL where the second data is located is set to the second hint id, and the hint state of this second hint id in the second hint mapping table is collection.

[0101] Therefore, in some possible implementation manners, the second replacement configuration further includes a second address range for replacing the first address range. Wherein, the second data belongs to the second address range, and the hint state mapped by the second hint id (with a value of 2) in the second hint mapping table is collection. Then, when the second process runs and accesses the second data, the control circuit may mark the CL where the second data is located, and preferentially replace the second data in the CL after the second process ends. It should be noted that the second address range includes one or more address value intervals in the memory, and the one or more address values may be continuous or discontinuous, which is not limited herein.

[0102] 208. During the running of the second process, the control circuit receives a second access request for the second data sent by the target application.

[0103] In some possible implementation manners, when the second process accesses the second data, first query from the Cache which CL stores the second data. If the second CL stores the second data, then the second process may access the second data from the second CL. In some possible implementation manners, if the second data is not stored in any CL, then step 209 is executed.

[0104] 209. If none of the CLs in the cache Cache stores the second data, the control circuit determines multiple CLs to be replaced in the Cache, and the multiple CLs include the first CL.

[0105] It should be noted that during the running of the second process, by executing any Cache replacement algorithm, multiple CLs to be replaced can be determined. Exemplarily, the multiple CLs include the first CL, the second CL, and the third CL. Based on the current Cache replacement algorithm, the first CL, the second CL, and the third CL are determined as the CLs with a lower reserved priority.

[0106] 210. If the first hint status information carried by the first CL in the multiple CLs is the first hint id, and the hint status mapped by the first hint id in the second hint mapping table is eviction, the control circuit replaces the first data in the first CL with the second data and accesses the second data from the first CL.

[0107] In some possible implementation manners, the control circuit may traverse each CL in the multiple CLs to be replaced, obtain the hint status information corresponding to each CL, and obtain the mapped hint status from the second hint mapping table based on these hint status information, and perform data replacement on the CL with the hint status of eviction.

[0108] Exemplarily, before the second process runs, the first hint status information of the first CL is the first hint id (for example, the value is 1). Based on the first hint mapping table, the hint status mapped by the first hint id is collection. During the running of the second process, based on the second hint mapping table, the hint status mapped by the first hint id (for example, the value is 1) is eviction. Therefore, the control circuit can preferentially perform data replacement on the first CL during the running of the second process.

[0109] In addition, if the shared CL where the shared data is located is included in multiple CLs, before the second process runs, the shared hint status information of the shared CL is unconfigured (its value is 0); during the running of the second process, the shared hint status information of the shared CL is still unconfigured (its value is 0). Therefore, the shared data will not be preferentially replaced during the running of the second process, achieving the purpose of quickly replacing the first data in the first CL. At the same time, the shared data is retained, and there will be no cache misses when accessing these shared data subsequently, avoiding performance degradation.

[0110] 211. If the address of the second data belongs to the second address range, the control circuit sets the first hint status information carried by the first CL to the second hint id.

[0111] In some possible implementation manners, the second replacement configuration further includes a second address range, and the second address range includes the address of the second data but does not include the address of the shared data. Then, the control circuit can mark the first CL where the second data accessed by the second process is located. Then, after the second process runs to completion subsequently, the second data can be preferentially evicted, that is, data replacement is performed on the first CL.

[0112] In some possible implementation manners, when the second process accesses the second data, first query in the cache which CL stores the second data. If the first CL stores the second data, then the second process can access the second data from the first CL. In some possible implementation manners, if the first data is not stored in any CL, the second process can obtain the second data from the memory, then store it in the first CL, and then access the second data from the first CL, which is not limited herein.

[0113] In some possible implementation manners, when accessing the second data from the first CL, if the control circuit determines that the address of the second data belongs to the second address range, the control circuit sets the first hint status information carried by the first CL to the hint id whose hint status mapped in the second hint mapping table is collection, that is, the second hint id (for example, the value is 2), thereby achieving the marking of the first CL.

[0114] Exemplarily, the value of the first hint status information carried in the first CL is 1, that is, the hint status corresponding to the first hint status information is eviction. When accessing the second data from the first CL, the control circuit determines that the address of the second data in the first CL belongs to the second address range, and the hint status mapped by the second hint id in the second hint mapping table is collection. Then the control circuit sets the first hint status information carried in the first CL to 2, that is, the second hint id, and the hint status mapped by the second hint id in the second hint mapping table is collection, thereby realizing the marking of the first CL, so that after the second process ends, the data replacement of the first CL can be preferentially performed, that is, the second data in the first CL is preferentially evicted.

[0115] In some possible implementation manners, when the second process accesses other data that does not belong to the second address range from the CL, the hint status information of the CL can be set to unconfigured. Exemplarily, when the second process accesses the shared data from the shared CL, and the shared data stored in the shared CL does not belong to the second address range, then the control circuit sets the shared hint status information corresponding to the shared CL to 0, that is, unconfigured.

[0116] Based on the above steps 201 to 211, different hint mapping tables and corresponding replacement configurations can be obtained by multiplexing different hint statuses mapped by several hint ids. Different replacement configurations also include different address ranges. Using different replacement configurations in different processes can realize marking or data replacement of different CLs in different processes. The following is an example.

[0117] Exemplarily, as Figure 2-5 shown, the target application includes multiple processes, and the multiple processes include process 1, process 2, process 3, process 4, and process 5 that run in sequence. Among them, process 1 needs to access data 1 and shared data, process 2 needs to access data 2 and shared data, process 3 needs to access data 3 and shared data, process 4 needs to access data 4 and shared data, and process 5 needs to access data 5 and shared data.

[0118] Before process 1 runs, the cache management program writes replacement configuration 1 on the control circuit. Replacement configuration 1 includes address range 1 and hint mapping table 1. Among them, address range 1 includes data 1 but does not include shared data; hint mapping table 1 is shown in Table 1.

[0119] Then, during the operation of Process 1, when accessing Data 1 from CL 1, since the address of Data 1 in CL 1 belongs to Address Range 1 and the hint status mapped by the first hint id in Hint Mapping Table 1 is "collection", the value of the hint status information 1 carried by CL1 can be set to 1, the first hint id. Since the shared data is not within Address Range 1, no processing will be performed on the shared CL where the shared data is located, and the value of the shared hint status information of the shared CL remains 0, that is, the corresponding hint status is "unconfigured". Thus, the control circuit marks this CL 1 without marking the shared CL.

[0120] After Process 1 finishes running and before Process 2 runs, the cache management program writes Replacement Configuration 2 to the control circuit to replace Replacement Configuration 1. Replacement Configuration 2 includes Address Range 2 and Hint Mapping Table 2. Among them, Address Range 2 includes Data 2 but does not include the shared data, and Hint Mapping Table 2 is shown in Table 2.

[0121] Then, during the operation of Process 2, when determining multiple CLs to be replaced, if the multiple CLs to be replaced include CL 1 and the shared CL, since the value of the hint status information 1 carried by CL 1 is 1, that is, the first hint id, the hint status mapped in Hint Mapping Table 2 is "eviction". And the value of the shared hint status information of the shared CL is 0, that is, the corresponding hint status is "unconfigured". Therefore, the control circuit can preferentially replace the data of CL 1 rather than the shared CL.

[0122] In addition, during the operation of Process 2, when accessing Data 2 from CL 2, since the address of Data 2 in CL 2 belongs to Address Range 2 and the hint status mapped by the second hint id in Hint Mapping Table 2 is "collection", the value of the hint status information 2 carried by CL2 can be set to 2, the second hint id. Since the shared data is not within Address Range 2, no processing will be performed on the shared CL where the shared data is located, and the value of the shared hint status information of the shared CL remains 0, that is, the corresponding hint status is "unconfigured". Thus, the control circuit marks this CL 2 without marking the shared CL.

[0123] After Process 2 finishes running and before Process 3 runs, the cache management program writes Replacement Configuration 3 to the control circuit to replace Replacement Configuration 2. Replacement Configuration 3 includes Address Range 3 and Hint Mapping Table 3. Among them, Address Range 3 includes Data 3 but does not include the shared data, and Hint Mapping Table 3 is shown in Table 3.

[0124] Table 3

[0125]

[0126] Then, during the operation of Process 3, when determining multiple CLs to be replaced, if the multiple CLs to be replaced include CL 1, CL 2, and a shared CL, since the value of the hint status information 2 carried by CL 2 is 2, that is, the second hint id, the hint status mapped in the hint mapping table 3 is eviction; the value of the hint status information 1 carried by CL 1 is 1, that is, the first hint id, and the hint status mapped in the hint mapping table 3 is eviction. The value of the shared hint status information of the shared CL is 0, that is, the corresponding hint status is unconfigured. Therefore, the control circuit can preferentially perform data replacement on CL 1 and CL 2 rather than on the shared CL.

[0127] In addition, during the operation of Process 3, when accessing Data 3 from CL 3, since the address of Data 3 in CL 3 belongs to Address Range 3, and the hint status mapped by the third hint id in the hint mapping table 3 is collection, the value of the hint status information 3 carried by CL3 can be set to 3, the third hint id. Since the shared data is not within Address Range 3, no processing will be performed on the shared CL where the shared data is located, and the value of the shared hint status information of the shared CL remains 0, that is, the corresponding hint status is unconfigured. Then, the control circuit realizes the marking of this CL 3 without marking the shared CL.

[0128] After the operation of Process 3 ends and before the operation of Process 4, the cache management program writes Replacement Configuration 4 on the control circuit to replace Replacement Configuration 3. Replacement Configuration 4 includes Address Range 4 and Hint Mapping Table 4. Among them, Address Range 4 includes Data 4 but does not include the shared data, and Hint Mapping Table 4 is shown in Table 4.

[0129] Table 4

[0130]

[0131] Then, during the operation of Process 4, when determining multiple CLs to be replaced, if the multiple CLs to be replaced include CL 2, CL 3, and the shared CL, since the value of the hint status information 2 carried by CL 2 is 2, that is, the second hint id, the hint status mapped in the hint mapping table 4 is eviction; the value of the hint status information 3 carried by CL 3 is 3, that is, the third hint id, and the hint status mapped in the hint mapping table 4 is eviction. The value of the shared hint status information of the shared CL is 0, that is, the corresponding hint status is unconfigured. Therefore, the control circuit can preferentially perform data replacement on CL 2 and CL 3 rather than on the shared CL.

[0132] It should be noted that although the value of the hint status information 1 carried by CL 1 is still 1, that is, the first hint id, and the hint status mapped in the hint mapping table 4 is collection, since CL 1 has been fully data-replaced and the data in CL 1 is not the data that needs to be accessed in Process 4, it is not certain that data 1 will be accessed from CL 1, that is, it is not certain that CL 1 will be marked.

[0133] In addition, during the operation of Process 4, when accessing data 4 from CL 4, since the address of data 4 in CL 4 belongs to address range 4 and the hint status mapped by the first hint id in the hint mapping table 4 is collection, the value of the hint status information 4 carried by CL4 can be set to 1, the first hint id. Since the shared data is not in address range 4, no processing will be performed on the shared CL where the shared data is located, and the value of the shared hint status information of the shared CL remains 0, that is, the corresponding hint status is unconfigured. Then the control circuit realizes the marking of this CL 4 without marking the shared CL.

[0134] After Process 4 finishes running and before Process 5 runs, the cache management program writes replacement configuration 5 on the control circuit to replace the replacement configuration 4. Replacement configuration 5 includes address range 5 and hint mapping table 5. Among them, address range 5 includes data 5 but does not include the shared data, and the hint mapping table 5 is shown in Table 5.

[0135] Table 5

[0136]

[0137] Then, during the operation of Process 5, when determining multiple CLs to be replaced, if the multiple CLs to be replaced include CL 3, CL 4, and a shared CL. Since the value of the hint status information 3 carried by CL 3 is 3, that is, the third hint id, the hint status mapped in the hint mapping table 5 is eviction; the value of the hint status information 4 carried by CL 4 is 1, that is, the first hint id, and the hint status mapped in the hint mapping table 5 is eviction. While the value of the shared hint status information of the shared CL is 0, that is, the corresponding hint status is unconfigured. Therefore, the control circuit can preferentially perform data replacement on CL 3 and CL 4 rather than on the shared CL first.

[0138] It should be noted that although the value of the hint status information 2 carried by CL 2 is still 2, that is, the second hint id, and the hint status mapped in the hint mapping table 5 is collection, since CL 2 has been fully data-replaced and the data in CL 2 is not the data to be accessed in Process 5, it is not certain that data 2 will be accessed from CL 2, that is, it is not certain that CL 2 will be marked.

[0139] In addition, during the operation of Process 5, when accessing data 5 from CL 5, since the address of data 5 in CL 5 belongs to address range 5 and the hint status mapped by the second hint id in the hint mapping table 5 is collection, the value of the hint status information 5 carried by CL5 can be set to 2, the second hint id. While the shared data is not in address range 5, no processing will be performed on the shared CL where the shared data is located, and the value of the shared hint status information of the shared CL remains 0, that is, the corresponding hint status is unconfigured. Then the control circuit realizes the marking of this CL 5 without marking the shared CL.

[0140] By using different replacement configurations in different processes as described above, the reuse of several hint ids is achieved to mark and perform data replacement on different CLs under different processes, enabling the CL where the data accessed in the previous process is located to be preferentially data-replaced in the current process, and the shared data that needs to be continuously accessed in this process can continue to stay in the Cache.

[0141] In this application, during the operation of the second process, a second access request for the second data sent by the target application is received, where the second data is the data accessed by the second process. If none of the CLs in the cache Cache store the second data, multiple CLs to be replaced in the Cache are determined, and the multiple CLs include a first CL. If the first hint status information carried by the first CL in the multiple CLs is a first hint id, and the hint status mapped by the first hint id in the second hint mapping table is eviction, the second data replaces the first data in the first CL, and the second data is accessed from the first CL. The first data is the data accessed by a first process, and the first process is the process before the second process in the target application.

[0142] In the embodiment of this application, by writing the second hint mapping table during the second process, data replacement of the first CL where the first data that does not need to be accessed in the second process is located is prioritized, thereby overcoming the situation that when the process of the target application changes and the data originally accessed is not needed in the current process, these data can be evicted as soon as possible, avoiding the situation of these data being retained for a long time, and thus improving the performance.

[0143] In the foregoing Embodiment 1, there can be multiple values for the hint id in a hint mapping table. In some possible implementation manners, there can also be only one hint id in a hint mapping table, and the hint status mapped by the hint id is collection or eviction. Exemplarily, please refer to the following Embodiment 2.

[0144] Please refer to Figure 3-1 , a cache data replacement method provided in Embodiment 2 of this application mainly includes the following steps:

[0145] 301. Before the first process runs, the cache management program writes a first replacement configuration in the control circuit. The first replacement configuration includes a first address range and a first hint mapping table, and the first hint mapping table includes the hint id and the mapped hint status.

[0146] It should be noted that the first address range includes one or more address value intervals in the memory, and the one or more address values can be continuous or discontinuous, and no limitation is made here.

[0147] It should be noted that as Figure 2-2As shown, each CL can carry a hint status information. The value of the hint status information can be unconfigured or a hint id. The hint id is used to determine the mapped hint status according to the replacement configuration, and the hint status can be collection or eviction. In a hint mapping table, if the hint status mapped by a hint id is collection, it means that the CL with its hint status information being this hint id is marked, and this CL needs to perform data replacement in the next process; in a hint mapping table, if the hint status mapped by a hint id is eviction, it means that data replacement needs to be performed on the CL with its hint status information being this hint id within the current process. If the hint status information of a CL is unconfigured, no processing needs to be performed on this CL.

[0148] In some possible implementation manners, in the first hint mapping table, the hint status mapped by the first hint id is collection, and the hint statuses mapped by other hint ids except the first hint id are all eviction.

[0149] Exemplarily, one or more hint ids include 1 hint id, that is, the first hint id. Exemplarily, as shown in Table 6, the first hint id = 1. In the first hint mapping table, the hint status mapped by the first hint id with a value of 1 is collection.

[0150] Table 6

[0151]

[0152] It should be noted that executing the target application needs to be implemented by executing multiple processes. The multiple processes include a first process and a second process. The first process is used to access the first data and perform operations to obtain a first operation result; the second process is used to access the second data and perform operations to obtain a second operation result. In some possible implementation manners, the first process and / or the second process can be a process or other types of execution processes, which are not limited herein.

[0153] It should be noted that the first data is a part of the data to be accessed by the first process, and the second data is a part of the data to be accessed by the second process. Exemplarily, the first process is to access data 1a, data 1b, data 1c, and data d, and the second process is to access data 2a, data 2b, data 2c, and data d. Among them, the first data is data 1a, the second data is data 2a, the shared data is data d. The first data is stored in the first CL (or the first data is not stored in any CL. When accessing the first data, the first data can be obtained from the memory and stored in the first CL), the second data is stored in the second CL (or the second data is not stored in any CL. When accessing the second data, the second data can be obtained from the memory and stored in the second CL), and the shared data is stored in the shared CL (or the shared data is not stored in any CL. When accessing the shared data, the shared data can be obtained from the memory and stored in the shared CL).

[0154] In the embodiment of the present application, after the first process ends, in order to quickly evict the first data accessed only by the first process and retain the shared data that both the first process and the second process need to access, it is necessary to mark the first CL storing the first data. For this purpose, before executing the first process, it is necessary to first define a first address range including the first data. Since the first replacement configuration includes the first address range where the first data is located, then when the first process accesses the first data, obtain the address of the first data, and based on the first replacement configuration, determine that the address of the first data belongs to this first address range, then the first CL where the first data is located can be marked based on the first hint mapping table, that is, set the first hint status information of the first CL to the first hint id, and the hint status of the first hint id in the first hint mapping table is collection.

[0155] In some possible implementation manners, the cache management program can obtain the running time period of the first process, then, before the first process runs, write the first replacement configuration on the control circuit. In some possible implementation manners, the cache management program can communicate with the target application to obtain the current running process of the target application and the process to be run soon, which is not limited here.

[0156] Exemplarily, as Figure 2-3 shown, the target application includes a first process and a second process executed successively. Among them, when the first process runs, it needs to access the first data and the shared data, and when the second process runs, it needs to access the second data and the shared data.

[0157] As Figure 2-3As shown, before the first process runs, the cache management program can write the first replacement configuration into the control circuit. The first address range in the first replacement configuration includes the address of the first data but does not include the address of the shared data. Then, the control circuit can mark the first CL where the first data accessed by the first process is located, that is, set the value of the first hint status information of the first CL to the first hint id.

[0158] In some possible implementation manners, according to the prior knowledge of the software design of the target application, during the writing stage of the software design or before the first process runs at runtime, the content of the shared data, the first data, and the second data is identified in advance, and they are arranged in different address ranges in the memory. In some possible implementation manners, as Figure 2-4 shown, the first address range includes the first data but does not include the shared data or the second data, which is not limited here.

[0159] In some possible implementation manners, the address range does not necessarily distinguish between the first data and the second data. Exemplarily, as Figure 3-2 shown, the first address range includes the first data and the second data but does not include the shared data, which is not limited here.

[0160] 302. During the running of the first process, the control circuit receives the first access request for the first data sent by the target application and accesses the first data from the first CL.

[0161] Please refer to step 202, which will not be elaborated here.

[0162] 303. The control circuit accesses the first data from the first CL based on the first access request.

[0163] Please refer to step 203, which will not be elaborated here.

[0164] 304. If the address of the first data belongs to the first address range, the control circuit sets the first hint status information to the first hint id.

[0165] In some possible implementation manners, each CL in the Cache carries corresponding tag information, and the tag information also includes the hint status information of the CL, which is not limited here.

[0166] In some possible implementations, the value of the hint status information carried by a CL can be a hint id or not configured. The hint id is used to determine the mapped hint status based on the hint mapping table, and the hint status is collect or evict. Exemplarily, when accessing the first data from the first CL, if the control circuit determines that the address of the first data in the first CL belongs to the first address range, the control circuit sets the first hint status information carried by the first CL to the first hint id, where the first hint id is the hint id whose mapped hint status in the first hint mapping table is collect, thereby marking the first CL.

[0167] It should be noted that since the control circuit needs to set the first hint status information carried by the first CL to the hint id whose mapped hint status in the first hint mapping table is collect, it is also necessary to determine that there is a hint id whose mapped hint status in the first hint mapping table is collect.

[0168] Exemplarily, during the operation of the first process, the value of the first hint status information carried by the first CL is 0, that is, not configured. Since the address of the first data belongs to the first address range and the hint status mapped by the first hint id in the first hint mapping table is collect, the control circuit can set the first hint status information carried by the first CL to 1, that is, the first hint id, and the hint status mapped by the first hint id in the first hint mapping table is collect, thereby marking the first CL, that is, collecting the first data in the first CL that needs to be evicted in the next process.

[0169] 305. During the operation of the first process, the control circuit receives an access request for shared data sent by the target application and accesses the shared data from the shared CL, where the shared data is the data accessed by both the first process and the second process.

[0170] Please refer to step 205, which will not be elaborated here.

[0171] 306. If the address of the shared data does not belong to the first address range, the control circuit sets the shared hint status information carried by the shared CL to not configured.

[0172] Please refer to step 206, which will not be elaborated here.

[0173] 307. Before the second process runs, the cache management program writes a second replacement configuration in the control circuit. The second replacement configuration includes a second hint mapping table, and the second hint mapping table includes hint ids and the mapped hint statuses.

[0174] In the embodiment of the present application, the cache management program may first obtain the running time period of the second process. Then, before the second process runs, the second replacement configuration may be written in the control circuit.

[0175] In some possible implementation manners, when the first process ends, the second process may run immediately. In some possible implementation manners, before the second process runs, the cache management program may modify the first replacement configuration to the second replacement configuration. Among them, the second replacement configuration includes a second hint mapping table. Compared with the first hint mapping table, in the second hint mapping table, the hint state mapped by the first hint id is eviction. Then, the hint state corresponding to the first CL is eviction. When the second process runs, the control circuit can quickly replace the data of the first CL.

[0176] Exemplarily, the second hint mapping table is shown in Table 7, and the first hint id = 1. In the second mapping table, the hint state mapped by the first hint id with a value of 1 is eviction. Then, since the value of the first hint state information carried in the first CL is 1, the hint state mapped in the first hint mapping table is collection, and the hint state mapped in the second hint mapping table is changed to eviction.

[0177] Table 7

[0178]

[0179] 308. During the running of the second process, the control circuit receives a second access request for the second data sent by the target application.

[0180] Please refer to step 208, which will not be elaborated here.

[0181] 309. If none of the CLs in the cache Cache stores the second data, the control circuit determines multiple CLs to be replaced in the Cache, and the multiple CLs include the first CL.

[0182] Please refer to step 209, which will not be elaborated here.

[0183] 310. If the first hint state information carried in the first CL among the multiple CLs is the first hint id, and the hint state mapped by the first hint id in the second hint mapping table is eviction, the control circuit replaces the first data in the first CL with the second data and accesses the second data from the first CL.

[0184] Please refer to step 210, which will not be elaborated here.

[0185] Due to the small capacity and high price of the Cache, by reducing the number of hint IDs, the capacity required for the first hint mapping table can be reduced, thereby reducing the capacity of the first replacement configuration, and thus reducing the demand for the storage amount in the Cache. Similarly, data replacement for the CL where the data accessed in the previous process is located can be achieved, achieving a balance between performance and cost.

[0186] Through the above steps 301 to 310, different hint mapping tables and corresponding replacement configurations can be obtained through different hint states mapped by 1 hint ID. Different replacement configurations also include different address ranges. Using different replacement configurations in different processes can achieve marking or data replacement for different CLs under different processes. The following is an example.

[0187] Exemplarily, as Figure 3-3 shown, the target application includes multiple processes, and the multiple processes include process 1, process 2, process 3, and process 4 that run in sequence. Among them, process 1 needs to access data 1 and shared data, process 2 needs to access data 2 and shared data, process 3 needs to access data 3 and shared data, and process 4 needs to access data 4 and shared data.

[0188] Before process 1 runs, the cache management program writes replacement configuration 1 on the control circuit. Replacement configuration 1 includes address range 1 and hint mapping table 1. Among them, address range 1 includes data 1 but does not include shared data; hint mapping table 1 is shown in Table 6.

[0189] Then, during the running of process 1, when accessing data 1 from CL 1, since the address of data 1 in CL 1 belongs to address range 1, and the hint state mapped by the first hint ID in hint mapping table 1 is collection, the value of hint state information 1 carried by CL1 can be set to 1, the first hint ID. And the shared data is not in address range 1, so no processing will be performed on the shared CL where the shared data is located, and the value of the shared hint state information of the shared CL remains 0, that is, the corresponding hint state is unconfigured. Then the control circuit realizes the marking of this CL 1 without marking the shared CL.

[0190] When process 1 finishes running, before process 2 runs, the cache management program writes replacement configuration 2 on the control circuit to replace this replacement configuration 1. Replacement configuration 2 includes hint mapping table 2, and hint mapping table 2 is shown in Table 7.

[0191] Then, during the operation of Process 2, when determining multiple CLs to be replaced, if the multiple CLs to be replaced include CL 1 and the shared CL, since the value of the hint status information 1 carried by CL 1 is 1, i.e., the first hint id, the hint status mapped in the hint mapping table 2 is eviction. And the value of the shared hint status information of the shared CL is 0, i.e., the corresponding hint status is unconfigured. Therefore, the control circuit can preferentially perform data replacement on CL 1 rather than on the shared CL.

[0192] After Process 2 finishes running and before Process 3 runs, the cache management program writes replacement configuration 3 to the control circuit to replace the replacement configuration 2. The replacement configuration 3 includes address range 3 and hint mapping table 3. Among them, the address range 3 includes data 3 but does not include the shared data, and the hint mapping table 3 is shown in Table 6.

[0193] Then, during the operation of Process 3, when accessing data 3 from CL 3, since the address of the data 3 in CL 3 belongs to the address range 3 and the hint status mapped by the third hint id in the hint mapping table 3 is collection, the value of the hint status information 3 carried by CL3 can be set to 1, the first hint id. And the shared data is not within the address range 3, so no processing will be performed on the shared CL where the shared data is located, and the value of the shared hint status information of the shared CL remains 0, i.e., the corresponding hint status is unconfigured. Then the control circuit realizes the marking of this CL 3 without marking the shared CL.

[0194] After Process 3 finishes running and before Process 4 runs, the cache management program writes replacement configuration 4 to the control circuit to replace the replacement configuration 3. The replacement configuration 4 includes hint mapping table 4, and the hint mapping table 4 is shown in Table 7.

[0195] Then, during the operation of Process 4, when determining multiple CLs to be replaced, if the multiple CLs to be replaced include CL 4 and the shared CL, since the value of the hint status information 4 carried by CL 4 is 1, i.e., the first hint id, the hint status mapped in the hint mapping table 4 is eviction. And the value of the shared hint status information of the shared CL is 0, i.e., the corresponding hint status is unconfigured. Therefore, the control circuit can preferentially perform data replacement on CL 4 rather than on the shared CL.

[0196] Compared with the first embodiment, in the technical solution of the second embodiment, the storage amount required in the Cache is the smallest. By using the second process as an interval process, the control circuit has enough time to evict the first data accessed by the first process, and there is no need to change the replacement configuration during the gap between the two processes, which realizes low cost and low difficulty. Moreover, the second embodiment does not require overly precise distinction of the address ranges of the data. For example, the first data and the second data can be arranged in the same address range without the need to distinguish and arrange them. The data within the address range accessed during the operation of the first process is naturally recognized as the first data, and the same applies to the second process, which can reduce the modification difficulty of the software and expand the application scenarios.

[0197] It should be noted that for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that this application is not limited by the described action sequence, because according to this application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0198] To facilitate better implementation of the above solutions of the embodiments of this application, the following also provides related devices for implementing the above solutions.

[0199] Please refer to Figure 4 As shown, a processor 400 provided by an embodiment of this application may include:

[0200] A receiving module 401, configured to receive a second hint mapping table before the second process runs, where the second hint mapping table includes a hint id and the mapped hint status, and the second process is a process of a target application; the receiving module 401 is further configured to receive a second access request for the second data sent by the target application during the running of the second process; a processing module 402, configured to determine a plurality of CLs to be replaced in the Cache if none of the CLs in the cache Cache stores the second data, and the plurality of CLs includes a first CL; the processing module 402 is further configured to replace the first data in the first CL with the second data if the first hint status information carried by the first CL in the plurality of CLs is the first hint id, and the hint status mapped by the first hint id in the second hint mapping table is eviction, where the first data is the data accessed by the first process, and the first process is the process of the target application before the second process; the processing module 402 is further configured to access the second data from the first CL.

[0201] In some possible implementation manners, the receiving module 401 is further configured to receive a first replacement configuration before the first process runs, where the first replacement configuration includes a first address range and a first hint mapping table, the first hint mapping table includes the hint id and the mapped hint status, and in the first hint mapping table, the hint status mapped by the first hint id is collection; the receiving module 401 is further configured to receive a first access request for the first data sent by the target application during the running of the first process, and access the first data from the first CL; the processing module 402 is further configured to set the first hint status information to the first hint id if the address of the first data belongs to the first address range.

[0202] In some possible implementation manners, the receiving module 401 is further configured to receive an access request for the shared data sent by the target application during the running of the first process, and access the shared data from the shared CL, where the shared data is the data accessed by the first process and the second process respectively; the processing module 402 is further configured to set the shared hint status information carried by the shared CL to unconfigured if the address of the shared data does not belong to the first address range.

[0203] In some possible implementation manners, the receiving module 401 is specifically configured to receive a second replacement configuration, where the second replacement configuration includes the second hint mapping table, and in the second hint mapping table, the hint status mapped by the first hint id is eviction.

[0204] In some possible implementation manners, the second replacement configuration further includes a second address range, the hint status mapped by a second hint id in the second hint mapping table is collection, and the receiving module 401 is further configured to set the first hint status information carried by the first CL to the second hint id if the address of the second data belongs to the second address range.

[0205] It should be noted that, for the information interaction, execution process, etc. between the above device modules / units, since they are based on the same concept as the method embodiments of the present application, the technical effects brought by them are the same as those of the method embodiments of the present application. For the specific content, reference can be made to the description in the foregoing method embodiments of the present application, and details are not described herein again.

[0206] The embodiment of the present application further provides a computer storage medium, where the computer storage medium stores a program, and the program executes some or all of the steps recorded in the foregoing method embodiments.

[0207] In another possible design, when the processor 400 includes a processing unit and a communication unit, the processing unit may be, for example, a processor, and the communication unit may be, for example, an input / output interface, a pin, or a circuit. The processing unit can execute the computer-executable instructions stored in the storage unit to cause the chip in the terminal to execute the method for sending wireless reporting information according to any one of the above first aspects.

[0208] Wherein, the processor mentioned anywhere above may be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the above methods.

[0209] In addition, it should be noted that the device embodiments described above are only illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in the attached drawings of the device embodiments provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be specifically implemented as one or more communication buses or signal lines.

[0210] Through the description of the above embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware. Of course, it can also be implemented by dedicated hardware including dedicated integrated circuits, dedicated CPUs, dedicated memories, dedicated components, etc. Generally, functions completed by computer programs can be easily implemented by corresponding hardware, and the specific hardware structures for implementing the same function can also be various, such as analog circuits, digital circuits, or dedicated circuits. However, for this application, software program implementation is a better implementation method in more cases. Based on such an understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a floppy disk, a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disc of a computer, and includes several instructions to cause a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in various embodiments of this application.

[0211] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product.

[0212] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are all or partially generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that includes one or more integrated available media. The available medium may be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)).

Claims

1. A cache data replacement method, characterized in that, it includes: Before the second process runs, receive a second hint mapping table, where the second hint mapping table includes a hint id and the mapped hint status, and the second process is the process of the target application; During the running of the second process, receive a second access request for the second data sent by the target application; If each CL in the cache Cache does not store the second data, determine multiple CLs to be replaced in the Cache, and the multiple CLs include a first CL; If the first hint status information carried by the first CL in the multiple CLs is the first hint id, and the hint status mapped by the first hint id in the second hint mapping table is eviction, then replace the first data in the first CL with the second data, where the first data is the data accessed by the first process, and the first process is the process before the second process in the target application; Access the second data from the first CL.

2. The method according to claim 1, characterized in that, the method further includes: Before the first process runs, receive a first replacement configuration, where the first replacement configuration includes a first address range and a first hint mapping table, and the first hint mapping table includes the hint id and the mapped hint status. In the first hint mapping table, the hint status mapped by the first hint id is collection; During the running of the first process, receive a first access request for the first data sent by the target application, and access the first data from the first CL; If the address of the first data belongs to the first address range, set the first hint status information to the first hint id.

3. The method according to claim 2, characterized in that, the method further includes: During the running of the first process, receive an access request for the shared data sent by the target application, and access the shared data from the shared CL, where the shared data is the data accessed by both the first process and the second process; If the address of the shared data does not belong to the first address range, set the shared hint status information carried by the shared CL to unconfigured.

4. The method according to claim 2 or 3, characterized in that, The hint status mapped by other hint ids except the first hint id in the first hint mapping table is eviction.

5. The method according to any one of claims 1-4, characterized in that, the receiving the second hint mapping table includes: Receiving a second replacement configuration, where the second replacement configuration includes the second hint mapping table, and in the second hint mapping table, the hint status mapped by the first hint id is eviction.

6. The method according to claim 5, characterized in that, The second replacement configuration further includes a second address range, and the hint status mapped by the second hint id in the second hint mapping table is collection. After accessing the second data from the first CL, the method further includes: If the address of the second data belongs to the second address range, set the first hint status information carried by the first CL to the second hint id.

7. The method according to any one of claims 1-6, characterized in that, the hint status information is carried in the label information of the CL where it is located.

8. A processor, characterized in that, comprises: a receiving module, configured to receive a second hint mapping table before the second process runs, the second hint mapping table including a hint id and the mapped hint status, and the second process is the process of the target application; the receiving module is further configured to receive a second access request for the second data sent by the target application during the running of the second process; a processing module, configured to determine a plurality of CLs to be replaced in the Cache if the second data is not stored in each CL in the cache Cache, and the plurality of CLs include a first CL; the processing module is further configured to, if the first hint status information carried by the first CL in the plurality of CLs is the first hint id, and the hint status mapped by the first hint id in the second hint mapping table is eviction, replace the first data in the first CL with the second data, where the first data is the data accessed by the first process, and the first process is the process before the second process in the target application; the processing module is further configured to access the second data from the first CL.

9. The processor according to claim 8, characterized in that, the receiving module is further configured to receive a first replacement configuration before the first process runs, the first replacement configuration including a first address range and a first hint mapping table, the first hint mapping table including the hint id and the mapped hint status, and in the first hint mapping table, the hint status mapped by the first hint id is collection; the receiving module is further configured to receive a first access request for the first data sent by the target application during the running of the first process, and access the first data from the first CL; the processing module is further configured to set the first hint status information to the first hint id if the address of the first data belongs to the first address range.

10. The processor according to claim 9, characterized in that, the receiving module is further configured to receive an access request for the shared data sent by the target application during the running of the first process, and access the shared data from the shared CL, where the shared data is the data accessed by the first process and the second process respectively; The processing module is further configured to set the shared hint status information carried by the shared CL to unconfigured if the address of the shared data does not belong to the first address range.

11. The processor according to any one of claims 8-10, wherein, The receiving module is specifically configured to: Receive a second replacement configuration, the second replacement configuration includes the second hint mapping table, and the hint status mapped by the first hint id in the second hint mapping table is eviction.

12. The processor according to claim 11, wherein, The second replacement configuration further includes a second address range, the hint status mapped by the second hint id in the second hint mapping table is collection, The receiving module is further configured to set the first hint status information carried by the first CL to the second hint id if the address of the second data belongs to the second address range.

13. A computer-readable storage medium, wherein, The computer-readable storage medium stores a program, and the program causes a computer device to execute the method according to any one of claims 1-7.

14. A computer program product, wherein, The computer program product includes computer-executable instructions, and the computer-executable instructions are stored in a computer-readable storage medium; at least one processor of the device reads the computer-executable instructions from the computer-readable storage medium, and the at least one processor executes the computer-executable instructions to cause the device to execute the method according to any one of claims 1-7.

15. A communication device, wherein, The communication device includes at least one processor, a memory, and a communication interface; The at least one processor is coupled to the memory and the communication interface; The memory is used to store instructions, the processor is used to execute the instructions, and the communication interface is used to communicate with other communication devices under the control of the at least one processor; When the instructions are executed by the at least one processor, the at least one processor is caused to execute the method according to any one of claims 1-7.

16. A chip system, wherein, The chip system includes a processor and a memory, the memory and the processor are interconnected by a line, the memory stores instructions, and the processor is used to execute the method according to any one of claims 1-7.

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