Master-slave device data transmission method, device, equipment and storage medium

Abstract

The invention discloses a master-slave equipment data transmission method and device, equipment and a storage medium, and relates to the technical field of equipment simulation verification, and the method comprises the steps: obtaining a plurality of verification instructions issued by a host verification program, and determining a queue channel corresponding to each verification instruction; the verification instruction is a master-slave device simulation verification instruction generated based on an ESPI protocol; sequentially writing verification data packets corresponding to the verification instruction into the queue channel based on a write enable signal corresponding to the queue channel; the queue depth corresponding to the queue channel is dynamically adjusted based on the channel occupancy rate of the queue channel in the data packet writing process; and receiving the verification data packet flowing out of the queue channel by using a preset register, and driving the verification data packet to the target slave end by using a preset ESPI serial bus, so that the target slave end performs simulation verification based on the verification data packet. Therefore, the working efficiency of simulation verification personnel can be remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of device simulation verification, and particularly to a master-slave device data transmission method, device, equipment and storage medium. Background Art

[0002] The ESPI (Enhanced Serial Peripheral Interface, a bus interface) bus, as a new type of low-speed bus, occupies fewer pins and has lower power consumption, and is widely used for transmitting information between the x86 chipset and the espi_slave (ESPI slave device). Therefore, the verification of the espi slave component is usually an important part of the overall verification work of the soc chip (System on Chip).

[0003] The espi slave simulation verification requires an efficient and complete host model, and the existing host models have two disadvantages. 1) When the host side sends data packets, it adopts the method of delaying one command cycle, and it needs to wait until the entire data packet is completely driven to the slave side before it can continue to send the next data packet; 2) When writing each data packet, all data is written into the model at once on the rising edge of the clock of the command to be sent. The above two disadvantages will result in a lower overall simulation verification efficiency of the model and are prone to introducing errors during the simulation process.

[0004] Obviously, how to improve the overall simulation verification efficiency of the model is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] To solve the above technical problems, embodiments of the present invention provide a master-slave device data transmission method, device, equipment and storage medium, which can improve the overall simulation verification efficiency of the model. The specific solutions are as follows:

[0006] In a first aspect, the present application discloses a master-slave device data transmission method, including:

[0007] Obtaining a number of verification instructions issued by a host verification program, and respectively determining the queue channels corresponding to the verification instructions; the verification instructions are master-slave device simulation verification instructions generated based on the ESPI protocol;

[0008] Sequentially writing the verification data packets corresponding to the verification instructions into the queue channels based on the write enable signals corresponding to the queue channels; the queue depth corresponding to the queue channel is dynamically adjusted based on the channel occupancy rate of the queue channel during the data packet writing process;

[0009] Receive the verification data packets flowing out of the queue channel using a preset register, and drive the verification data packets to the target slave end using a preset ESPI serial bus, so that the target slave end can perform simulation verification based on the verification data packets.

[0010] Optionally, obtain a number of verification instructions issued by the host verification program, and respectively determine the queue channels corresponding to the verification instructions, including:

[0011] Obtain a number of verification instructions issued by the host verification program and the address identifiers corresponding to each first-in-first-out queue channel;

[0012] Determine the target address fields corresponding to the number of verification instructions, and respectively determine the target first-in-first-out queue channels corresponding to the number of verification instructions based on the comparison results between the target address fields and the address identifiers.

[0013] Optionally, write the verification data packets corresponding to the verification instructions into the queue channel in sequence based on the write enable signal corresponding to the queue channel, including:

[0014] Obtain the current verification data packet corresponding to the verification instruction based on the write enable signal corresponding to the queue channel;

[0015] Write the current verification data packet into the queue channel; the current verification data packet is the data packet determined from the data packets to be written based on a preset data sending order; the data packets to be written are the data packets in all the verification data packets that have not been written into the queue channel;

[0016] Read the current count value of the channel operation counter of the queue channel, and read the maximum queue depth corresponding to the queue channel from a preset status register;

[0017] Determine the channel occupancy rate of the queue channel based on the current count value and the maximum queue depth;

[0018] Adjust the maximum queue depth corresponding to the queue channel based on the channel occupancy rate to obtain a new maximum queue depth;

[0019] Judge whether there are data packets in all the verification data packets that have not been written into the queue channel;

[0020] If there are data packets in all the verification data packets that have not been written into the queue channel, then jump to the step of obtaining the current verification data packet corresponding to the verification instruction based on the write enable signal corresponding to the queue channel.

[0021] Optionally, determine the channel occupancy rate of the queue channel based on the current count value and the maximum queue depth, including:

[0022] Determine the current usage depth of the queue channel based on the current count value, and substitute the current usage depth and the maximum queue depth into a preset occupancy rate determination model to determine the channel occupancy rate of the queue channel.

[0023] Optionally, before adjusting the maximum queue depth corresponding to the queue channel based on the channel occupancy rate to obtain a new maximum queue depth, it further includes:

[0024] Substitute the maximum queue depth into a preset high water level determination formula and a preset low water level determination formula respectively to obtain the current high water level and the current low water level corresponding to the maximum queue depth;

[0025] Correspondingly, adjusting the maximum queue depth corresponding to the queue channel based on the channel occupancy rate to obtain a new maximum queue depth includes:

[0026] Compare the channel occupancy rate with the current high water level and the current low water level respectively to obtain the current comparison result;

[0027] If the current comparison result indicates that the channel occupancy rate is greater than or equal to the current high water level, perform a depth expansion on the maximum queue depth based on a preset depth update value to obtain a new maximum queue depth;

[0028] If the current comparison result indicates that the channel occupancy rate is less than or equal to the current low water level, perform a depth reduction on the maximum queue depth based on a preset depth update value to obtain a new maximum queue depth.

[0029] Optionally, use a preset register to receive the verification data packet flowing out of the queue channel, and use a preset ESPI serial bus to drive the verification data packet to the target slave end, so that the target slave end can perform simulation verification based on the verification data packet, including:

[0030] Use a preset register to receive the verification data packet flowing out of the queue channel to obtain a target verification data field; the target verification data field includes a target verification address, target verification data, and a target cyclic redundancy check code; the target verification address, target verification data, and target cyclic redundancy check code are arranged based on the message format corresponding to the ESPI protocol;

[0031] Drive the target verification data field based on a preset output signal enable to send the target verification data field to the target slave end through a preset ESPI serial bus, so that the target slave end can perform simulation verification based on the verification data packet.

[0032] Optionally, use a preset register to receive the verification data packet flowing out of the queue channel, and use a preset ESPI serial bus to drive the verification data packet to the target slave end, so that the target slave end can perform simulation verification based on the verification data packet, including:

[0033] Receive the verification data packet flowing out of the queue channel through a preset register, and perform protocol encapsulation on the verification data packet based on the ESPI protocol to obtain an ESPI bus data frame;

[0034] Drive the ESPI bus data frame using a preset ESPI serial bus, and drive the verification data packet to the target slave end based on a preset bus clock frequency, so that the target slave end can perform simulation verification based on the verification data packet.

[0035] In a second aspect, the present application discloses a master-slave device data transmission device, including:

[0036] A verification instruction acquisition module, configured to acquire a plurality of verification instructions issued by a host verification program, and respectively determine the queue channels corresponding to the verification instructions; the verification instructions are master-slave device simulation verification instructions generated based on the ESPI protocol;

[0037] A data writing module, configured to sequentially write the verification data packets corresponding to the verification instructions into the queue channel based on the write enable signal corresponding to the queue channel; the queue depth corresponding to the queue channel is dynamically adjusted based on the channel occupancy rate of the queue channel during the data packet writing process;

[0038] A data driving module, configured to receive the verification data packet flowing out of the queue channel using a preset register, and drive the verification data packet to the target slave end using a preset ESPI serial bus, so that the target slave end can perform simulation verification based on the verification data packet.

[0039] In a third aspect, the present invention discloses an electronic device, including:

[0040] A memory, configured to store a computer program;

[0041] A processor, configured to execute the computer program to implement the foregoing master-slave device data transmission method.

[0042] In a fourth aspect, the present invention discloses a computer-readable storage medium, configured to store a computer program, and when the computer program is executed by a processor, the foregoing master-slave device data transmission method is implemented.

[0043] It can be seen that in the present invention, a plurality of verification instructions issued by the host verification program are obtained, and the queue channels corresponding to the respective verification instructions are determined respectively; the verification instructions are master-slave device simulation verification instructions generated based on the ESPI protocol; the verification data packets corresponding to the verification instructions are sequentially written into the queue channels based on the write enable signals corresponding to the queue channels; the queue depth corresponding to the queue channel is dynamically adjusted based on the channel occupancy rate of the queue channel during the data packet writing process; a preset register is used to receive the verification data packets flowing out of the queue channel, and the verification data packets are driven to the target slave device end by using a preset ESPI serial bus, so that the target slave device end can perform simulation verification based on the verification data packets.

[0044] As can be seen from the above technical solutions, the present invention can implement the simultaneous execution of multiple commands by using a multi-channel mechanism, that is, allocating corresponding queue channels for corresponding verification instructions for information transmission. During the master-slave device simulation verification, multi-channel parallel transmission can be adopted to significantly improve the data transmission efficiency; thereby improving the simulation verification efficiency. Moreover, by dynamically adjusting the queue depth during the queue data writing process, in this way, by dynamically adjusting the queue depth, resource waste can be avoided, thereby improving the hardware utilization rate. In addition, it can also ensure that the queue depth always meets the transmission requirements, reducing data loss and transmission delay. Brief Description of the Drawings

[0045] In order to more clearly illustrate the embodiments of the present invention, the drawings required to be used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0046] Figure 1 It is a data flow chart of an ESPI host model for sending data in the prior art disclosed by the present invention;

[0047] Figure 2 It is a data flow chart of an ESPI host model for sending data in the prior art disclosed by the present invention;

[0048] Figure 3 It is a flow chart of a master-slave device data transmission method disclosed by the present invention;

[0049] Figure 4 It is a schematic diagram of host verification data disclosed by the present invention;

[0050] Figure 5 It is a schematic diagram of the serial bus interface of an ESPI host model disclosed by the present invention;

[0051] Figure 6 It is a schematic diagram of the structure of a master-slave device data transmission device disclosed by the present invention;

[0052] Figure 7 This is a structural diagram of an electronic device disclosed by the present invention. Specific embodiments

[0053] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work belong to the protection scope of the present invention.

[0054] The terms "including" and "having" in the specification of the present invention and the accompanying drawings above, and any variations related to "including" and "having", are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may include steps or units not listed.

[0055] To enable those skilled in the art of this technology to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0056] The existing process of the ESPI host model for sending data is as Figure 1 and Figure 2 shown. During the write operation, data is written into the corresponding register through a general I / O (Input / Output) port at the rising edge of the clock. Among them, temp_data1 to temp_data16 are the address, data, and CRC (Cyclic Redundancy Check) check code that the host needs to send to the slave side, temp_command is the command, and first_begin_signal and tx_end_bytes are the host-related control information. The host side drives the data to the slave. After waiting for the set delay time time (this time can ensure that a complete data packet is driven to the slave side), the next data packet is sent according to the foregoing steps, and wait for all n data packets to be sent. This model drives the data to the slave side when a command needs to be sent by delaying time, and its time value needs to be continuously switched according to the change of the command mode, and all data cannot be written at one time. Therefore, the efficiency of master-slave device verification is relatively low. The present invention will specifically introduce a master-slave device data transmission method, which can improve the efficiency of master-slave device verification.

[0057] See Figure 3 shown. The embodiments of the present application disclose a master-slave device data transmission method, including:

[0058] Step S11: Obtain a number of verification instructions sent by the host verification program, and respectively determine the queue channels corresponding to the verification instructions; the verification instructions are master-slave device emulation verification instructions generated based on the ESPI protocol.

[0059] In this embodiment, obtaining a number of verification instructions sent by the host verification program and respectively determining the queue channels corresponding to the verification instructions includes: obtaining a number of verification instructions sent by the host verification program and the address identifiers corresponding to each first-in-first-out queue channel; determining the target address domains corresponding to the number of verification instructions, and respectively determining the target first-in-first-out queue channels corresponding to the number of verification instructions based on the comparison results between the target address domains and the address identifiers. That is, in this embodiment, multiple queue channels are first constructed, and each channel contains an independent queue. This queue can be a first-in-first-out queue (FIFO, i.e., First Input First Output) during actual use. Different queue channels receive data corresponding to different verification instructions. Therefore, when performing master-slave device verification, first obtain various verification instructions sent by the host verification program and the address identifiers corresponding to the first-out queue channels corresponding to the instructions, and then determine the first-out queue channel whose address identifier is consistent with the target address domain corresponding to the verification instruction as the target first-out queue channel corresponding to the verification instruction. It should be noted here that the verification instructions mentioned in this embodiment are all master-slave device emulation verification instructions generated for the ESPI protocol, and the address identifier is the AHB (Advanced High Performance Bus) address.

[0060] Step S12: Based on the write enable signal corresponding to the queue channel, sequentially write the verification data packets corresponding to the verification instructions into the queue channel; the queue depth corresponding to the queue channel is dynamically adjusted based on the channel occupancy rate of the queue channel during the data packet writing process.

[0061] In this embodiment, the verification data packets corresponding to the verification instructions are sequentially written into the queue channel based on the write enable signal corresponding to the queue channel, including: obtaining the current verification data packet corresponding to the verification instruction based on the write enable signal corresponding to the queue channel; writing the current verification data packet into the queue channel; the current verification data packet is the data packet determined from the data packets to be written based on the preset data sending order; the data packets to be written are the data packets in all the verification data packets that have not been written into the queue channel; reading the current count value of the channel operation counter of the queue channel, and reading the maximum queue depth corresponding to the queue channel from the preset status register; determining the channel occupancy rate of the queue channel based on the current count value and the maximum queue depth; adjusting the maximum queue depth corresponding to the queue channel based on the channel occupancy rate to obtain a new maximum queue depth; determining whether there are data packets in all the verification data packets that have not been written into the queue channel; if there are data packets in all the verification data packets that have not been written into the queue channel, then jump to the step of obtaining the current verification data packet corresponding to the verification instruction based on the write enable signal corresponding to the queue channel. That is, through the write enable signal corresponding to the queue channel, the current verification data packet (package) corresponding to the corresponding verification instruction is obtained, and then the current verification data packet is sequentially written into the queue channel according to the preset data sending order corresponding to the current verification data. During the writing process, the channel operation counter of the queue channel will count sequentially according to the data volume of the currently written data. For example: when writing a data packet, the channel operation counter will increase from 0 to 1. And, after the count value of the channel operation counter changes, the channel occupancy rate of the queue channel can be determined by the current count value of the channel operation counter and the maximum queue depth. Then, the current maximum queue depth is adjusted based on the channel occupancy rate to obtain a new maximum queue depth. The above steps are used to process each verification data packet corresponding to the current verification instruction until all the verification data packets corresponding to the current verification instruction are written into the corresponding first-in-first-out queue.

[0062] Further, determining the channel occupancy rate of the queue channel based on the current count value and the maximum queue depth includes: determining the current usage depth of the queue channel based on the current count value, and substituting the current usage depth and the maximum queue depth into a preset occupancy rate determination model to determine the channel occupancy rate of the queue channel. That is, obtaining the current count value corresponding to the channel operation counter, and determining the current usage depth corresponding to the queue channel based on the current count value, and then substituting the current usage depth and the maximum queue depth into the preset occupancy rate determination model to determine the channel occupancy rate of the queue channel. Among them, the preset occupancy rate determination model is:

[0063] Channel occupancy rate = current count value ÷ maximum queue depth × 100%;

[0064] It should be noted here that if only one verification data packet is written in the current queue, the maximum queue depth at this time is the initial queue depth set according to the actual situation. Generally, in the actual operation process, the initial queue depth is 10. If multiple verification data packets are written in the current queue, the maximum queue depth at this time is the queue depth after the dynamic adjustment of the channel depth after the previous verification data packet is written.

[0065] In fact, the process of adjusting the queue depth is as follows. Before adjusting the maximum queue depth corresponding to the queue channel based on the channel occupancy rate to obtain a new maximum queue depth, it also includes: substituting the maximum queue depth into the preset high water level line determination formula and the preset low water level line determination formula respectively to obtain the current high water level line and the current low water level line corresponding to the maximum queue depth; correspondingly, adjusting the maximum queue depth corresponding to the queue channel based on the channel occupancy rate to obtain a new maximum queue depth, including: comparing the channel occupancy rate with the current high water level line and the current low water level line respectively to obtain the current comparison result; if the current comparison result indicates that the channel occupancy rate is greater than or equal to the current high water level line, expanding the depth of the maximum queue depth based on the preset depth update value to obtain a new maximum queue depth; if the current comparison result indicates that the channel occupancy rate is less than or equal to the current low water level line, reducing the depth of the maximum queue depth based on the preset depth update value to obtain a new maximum queue depth. That is, first obtain the maximum queue depth corresponding to the current queue, and then substitute the maximum queue depth into the preset high water level line determination formula and the preset low water level line determination formula respectively. Among them, the preset high water level line determination formula is as follows:

[0066] Current high water level line = maximum queue depth × 80%;

[0067] The preset low water level line determination formula is as follows:

[0068] Current low water level line = maximum queue depth × 20%;

[0069] Then, compare the channel occupancy rate calculated in the above steps with the current high water level line and the current low water level line respectively to obtain the current comparison result. If the channel occupancy rate is greater than or equal to the current high water level line, expand the depth of the maximum queue depth based on the preset depth update value to obtain a new maximum queue depth; if the channel occupancy rate is less than or equal to the current low water level line, reduce the depth of the maximum queue depth based on the preset depth update value to obtain a new maximum queue depth. It should be noted here that the preset depth update value is set according to the actual length of the data packet, and it is necessary to ensure that the new verification data packet can still be placed in the queue after the depth expansion or reduction.

[0070] Step S13: Receive the verification data packet flowing out of the queue channel by using a preset register, and drive the verification data packet to the target slave end by using a preset ESPI serial bus, so that the target slave end performs simulation verification based on the verification data packet.

[0071] In this embodiment, receiving the verification data packet flowing out of the queue channel by using a preset register, and driving the verification data packet to the target slave end by using a preset ESPI serial bus, so that the target slave end performs simulation verification based on the verification data packet, includes: receiving the verification data packet flowing out of the queue channel by using a preset register to obtain a target verification data field; the target verification data field includes a target verification address, target verification data, and a target cyclic redundancy check code; the target verification address, target verification data, and target cyclic redundancy check code are arranged based on the message format corresponding to the ESPI protocol; driving the target verification data field based on a preset output signal enable to send the target verification data field to the target slave end through the preset ESPI serial bus, so that the target slave end performs simulation verification based on the verification data packet. Specifically, the data flowing out of the FIFO is Figure 4 received by the register shown in, where temp_data1 to temp_data16 are 8-bit wide and are the address / data / CRC check code that the host side needs to send to the slave side. The specific format includes different message formats according to four different commands of the ESPI protocol. temp_command is 8-bit wide and is the command field. first_begin_signal is 1-bit wide and tx_end_bytes is 32-bit wide and are the control fields.

[0072] In this embodiment, receiving the verification data packet flowing out of the queue channel by using a preset register, and driving the verification data packet to the target slave end by using a preset ESPI serial bus, so that the target slave end performs simulation verification based on the verification data packet, includes: receiving the verification data packet flowing out of the queue channel through a preset register, and performing protocol encapsulation on the verification data packet based on the ESPI protocol to obtain an ESPI bus data frame; driving the ESPI bus data frame by using a preset ESPI serial bus, and driving the verification data packet to the target slave end based on a preset bus clock frequency, so that the target slave end performs simulation verification based on the verification data packet. Specifically, the data in the register is driven to the slave side through the ESPI serial bus, as Figure 5As shown, where data_out is 4-bit wide and is the output bus, data_in is 4-bit wide and is the input bus, and data_oe is 4-bit wide and is the output signal enable. In addition, when performing protocol encapsulation, a lightweight encryption algorithm or a hash signature can be introduced. By protecting the protocol, the security of the verification data can be ensured. Moreover, in this application, data driving is based on a preset bus clock frequency. During the actual operation process, a slave-end feedback signal receiving component can be designed at the host end. Through the slave-end feedback signal receiving component, a real-time feedback signal of the slave-end receiving verification data can be obtained. After receiving the corresponding feedback signal, the data driving process can be adjusted in real time, which can reduce the power consumption of data transmission between the master and slave devices.

[0073] Next, the technical solutions in the present invention will be specifically introduced through the actual operation situation. First, during the actual operation process, the present invention is set as follows:

[0074] It totally includes 4 FIFO channels, and parallel transmission is implemented by using a multi-channel FIFO design. The initial depth of each FIFO is 10, and the width is 6×32 bits. One data packet is written to each AHB address;

[0075] A dynamic FIFO depth adjustment mechanism, and each FIFO channel includes an operation counter / a status register;

[0076] The status register includes fields including:

[0077] FIFO occupancy rate field = counter÷Depth_Max×100%;

[0078] The maximum depth (Depth_Max) = 10 (initial depth);

[0079] The current FIFO depth (Depth_Current) = the maximum depth (Depth_Max) = 10 (initial depth);

[0080] The high water mark = Depth_Max×80% = 8;

[0081] The low water mark = Depth_Max×20% = 2.

[0082] Implement a multi-channel parallel transmission mechanism. Packets are transmitted in parallel through multiple channels, and each channel contains an independent FIFO. This model introduces 4 FIFO channels for 4 types of commands of the ESPI protocol. Each channel receives the packages of a certain command, caches and receives packets independently. Each FIFO channel corresponds to an independent AHB address and write enable signal. The specific implemented commands are PUT_IOWR_SHORT, PUT_IORD_SHORT, PUT_NP, and GET_PC.

[0083] The following process takes the PUT_IOWR_SHORT and PUT_IORD_SHORT commands as examples, and 8 packets are sent for each command. The other commands are similar:

[0084] The host verification program writes the packets to be sent to the slave side through the AHB_PUT_IOWR_SHORT address. Each packet contains 6 × 32-bit data, including fields such as command / data / CRC check / control, etc. At the same time, the external writes the packets to be sent to the slave side through the AHB_PUT_IORD_SHORT address. Each packet contains 6 × 32-bit data, including fields such as command / data / CRC check / control, etc.

[0085] Taking AHB_PUT_IOWR_SHORT as an example, the operation counter of the PUT_IOWR_SHORT ifo channel increments to 8, and 8 packages are written into the FIFO corresponding to this channel. During the writing process, the following operation steps are included.

[0086] The status register records: the current FIFO depth (Depth_Current) / the maximum depth (Depth_Max) / the high water mark (80%) / the low water mark (20%);

[0087] Depth extension operation. When the FIFO occupancy rate >= the high water mark, update the maximum depth of the FIFO, Depth_Max = Depth_Current + ΔDepth (4);

[0088] Depth reduction operation. When the FIFO occupancy rate <= the low water mark, update the maximum depth of the FIFO, Depth_Max = Depth_Current – Δdepth (4).

[0089] Here, the preset depth update value is 4.

[0090] After the data packets corresponding to each command are written into the queue, the data flowing out of the FIFO is received by the register. The specific format contains different message formats according to the four different commands of the ESPI protocol. temp_command is 8 bits wide and is the command field. first_begin_signal is 1 bit wide and tx_end_bytes is 32 bits wide, which are control fields. Then it is driven to the slave side through the ESPI serial bus. After the slave side receives the data packets of multiple channels, they are reorganized in the sending order.

[0091] Among them, the process of queue depth update is exemplified as follows:

[0092] If only one verification data packet is written in the current queue, the maximum queue depth at this time is the initial queue depth set according to the actual situation. Generally, in the actual operation process, the initial queue depth is 10. The calculation process is as follows: the initial Depth_Max = 10, Depth_Current = 10, then the high water mark is 8, and the low water mark is 2; the data is written into the FIFO 8 times; calculate the FIFO occupancy rate = 8 / 10×100% = 80%; since the FIFO occupancy rate >= 80%, Depth_Max = 10 + 4 = 14, Depth_Current = 14, the high water mark = 0.8×Depth_Max = 11, and the low water mark = 14×0.2 = 3. Then when writing the next data packet, calculate the FIFO occupancy rate = 3 / 14×100% = 20%; since the FIFO occupancy rate <= 20%, Depth_Max = 14 - 4 = 10, Depth_Current = 10, the high water mark = 0.8×Depth_Max = 8, and the low water mark = 10×0.2 = 2.

[0093] It can be seen that in this embodiment, several verification instructions sent by the host verification program are obtained, and the queue channels corresponding to each verification instruction are determined respectively; the verification instructions are master-slave device simulation verification instructions generated based on the ESPI protocol; the verification data packets corresponding to the verification instructions are written into the queue channels in sequence based on the write enable signals corresponding to the queue channels; the queue depth corresponding to the queue channel is dynamically adjusted based on the channel occupancy rate of the queue channel during the data packet writing process; the verification data packets flowing out of the queue channel are received by a preset register, and the verification data packets are driven to the target slave end by using a preset ESPI serial bus, so that the target slave end can perform simulation verification based on the verification data packets.

[0094] As can be seen from the above technical solutions, in this embodiment, by using a multi-channel mechanism, that is, allocating corresponding queue channels for corresponding verification instructions for information transmission, multiple commands can be executed simultaneously. When performing master-slave device simulation verification, multi-channel parallel transmission can be used to significantly improve the data transmission efficiency; thereby improving the simulation verification efficiency. Moreover, by dynamically adjusting the queue depth during the process of writing queue data, in this way, by dynamically adjusting the queue depth, resource waste can be avoided, thereby improving the hardware utilization rate. In addition, it can also ensure that the queue depth always meets the transmission requirements, reducing data loss and transmission delay.

[0095] Reference Figure 6 , this embodiment of the present application also correspondingly discloses a master-slave device data transmission device, including:

[0096] A verification instruction acquisition module 11, configured to acquire a plurality of verification instructions issued by a host verification program and respectively determine the queue channels corresponding to the verification instructions; the verification instructions are master-slave device simulation verification instructions generated based on the ESPI protocol;

[0097] A data writing module 12, configured to sequentially write the verification data packets corresponding to the verification instructions into the queue channels based on the write enable signals corresponding to the queue channels; the queue depth corresponding to the queue channels is dynamically adjusted based on the channel occupancy rate of the queue channels during the process of writing data packets;

[0098] A data driving module 13, configured to receive the verification data packets flowing out of the queue channels by using a preset register and drive the verification data packets to the target slave device end by using a preset ESPI serial bus, so that the target slave device end performs simulation verification based on the verification data packets.

[0099] It can be seen that in this embodiment, by using a multi-channel mechanism, that is, allocating corresponding queue channels for corresponding verification instructions for information transmission, multiple commands can be executed simultaneously. When performing master-slave device simulation verification, multi-channel parallel transmission can be used to significantly improve the data transmission efficiency; thereby improving the simulation verification efficiency. Moreover, by dynamically adjusting the queue depth during the process of writing queue data, in this way, by dynamically adjusting the queue depth, resource waste can be avoided, thereby improving the hardware utilization rate. In addition, it can also ensure that the queue depth always meets the transmission requirements, reducing data loss and transmission delay.

[0100] Furthermore, this embodiment of the present application also discloses an electronic device, Figure 7 which is a structural diagram of an electronic device shown according to an exemplary embodiment, Figure 7The content herein should not be considered as any limitation on the scope of use of this application. The electronic device may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the master-slave device data transmission method disclosed in any of the foregoing embodiments. Additionally, the electronic device in this embodiment may specifically be an electronic computer.

[0101] In this embodiment, the power supply 23 is used to provide working voltages for each hardware device on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and specific limitations are not imposed on it here; the input / output interface 25 is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application needs, and no specific limitations are made here.

[0102] In addition, as a carrier for resource storage, the memory 22 can be a read-only memory, a random access memory, a disk, or an optical disc, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0103] Among them, the operating system 221 is used to manage and control each hardware device and the computer program 222 on the electronic device, and it can be Windows Server, Netware, Unix, Linux, etc. The computer program 222, in addition to including a computer program capable of completing the master-slave device data transmission method executed by the electronic device disclosed in any of the foregoing embodiments, may further include a computer program capable of completing other specific tasks.

[0104] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the master-slave device data transmission method disclosed above. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details are not repeated here.

[0105] Furthermore, this application also discloses a computer program product including a computer program / instructions; wherein, when the computer program / instructions are executed by a processor, they implement the alarm aggregation method disclosed above. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details are not repeated here.

[0106] In this specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method section.

[0107] Those skilled in the art can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been generally described according to their functions in the above description. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0108] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be directly implemented by hardware, software modules executed by a processor, or a combination of the two. The software modules can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0109] Finally, it should also be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

[0110] The above has introduced the technical solutions provided by this application in detail. Specific examples are used in this article to elaborate on the principles and implementation manners of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. A master-slave device data transmission method, characterized in that: include: Obtaining several verification instructions issued by the host verification program, and determining the queue channel corresponding to each of the verification instructions; The verification instruction is a master-slave device simulation verification instruction generated based on the ESPI protocol; Based on the write enable signal corresponding to the queue channel, the verification data packet corresponding to the verification instruction is sequentially written into the queue channel; during the data packet writing process, the queue depth corresponding to the queue channel is dynamically adjusted based on the channel occupancy rate of the queue channel; The verification data packet flowing out of the queue channel is received by using a preset register, and the verification data packet is driven to the target slave end by using a preset ESPI serial bus, so that the target slave end performs simulation verification based on the verification data packet.

2. The master-slave device data transmission method according to claim 1, characterized in that: The obtaining of a plurality of verification instructions issued by the host verification program and respectively determining a queue channel corresponding to each of the verification instructions includes: Obtain several verification instructions issued by the host verification program and address identifiers corresponding to each first-in-first-out queue channel; The target address domains corresponding to the plurality of verification instructions are determined, and the target first-in-first-out queue channels corresponding to the plurality of verification instructions are respectively determined based on the comparison result of the target address domains with the address identifiers.

3. The master-slave device data transmission method according to claim 1, characterized in that: The step of sequentially writing the verification data packets corresponding to the verification instructions into the queue channel based on the write enable signal corresponding to the queue channel includes: Acquire a current verification data packet corresponding to the verification instruction based on a write enable signal corresponding to the queue channel; Writing the current verification data packet into the queue channel; the current verification data packet is a data packet determined from the data packets to be written based on a preset data sending order; the data packet to be written is a data packet among all the verification data packets that has not been written into the queue channel; Reading a current count value of a channel operation counter of the queue channel, and reading a maximum queue depth corresponding to the queue channel from a preset status register; Determine a channel occupancy rate of the queue channel based on the current count value and the maximum queue depth; Adjusting the maximum queue depth corresponding to the queue channel based on the channel occupancy rate to obtain a new maximum queue depth; Determine whether there is a data packet that has not been written into the queue channel among all the verification data packets; If there are data packets among all the verification data packets that have not been written into the queue channel, jump to the step of obtaining the current verification data packet corresponding to the verification instruction based on the write enable signal corresponding to the queue channel.

4. The master-slave device data transmission method according to claim 3, characterized in that: The determining the channel occupancy of the queue channel based on the current count value and the maximum queue depth includes: The current usage depth of the queue channel is determined based on the current count value, and the current usage depth and the maximum queue depth are substituted into a preset occupancy determination model to determine the channel occupancy of the queue channel.

5. The master-slave device data transmission method according to claim 4, characterized in that: Before adjusting the maximum queue depth corresponding to the queue channel based on the channel occupancy rate to obtain a new maximum queue depth, the method further includes: Substituting the maximum queue depth into a preset high water mark determination formula and a preset low water mark determination formula respectively to obtain a current high water mark and a current low water mark corresponding to the maximum queue depth; Accordingly, adjusting the maximum queue depth corresponding to the queue channel based on the channel occupancy to obtain a new maximum queue depth includes: Comparing the channel occupancy rate with the current high water mark and the current low water mark respectively to obtain a current comparison result; If the current comparison result indicates that the channel occupancy rate is greater than or equal to the current high watermark, depth-expanding the maximum queue depth based on a preset depth update value to obtain a new maximum queue depth; If the current comparison result indicates that the channel occupancy rate is less than or equal to the current low watermark, the maximum queue depth is reduced based on the preset depth update value to obtain a new maximum queue depth.

6. The master-slave device data transmission method according to claim 1, characterized in that: The method of receiving the verification data packet flowing out of the queue channel by using a preset register, and driving the verification data packet to a target slave end by using a preset ESPI serial bus, so that the target slave end performs simulation verification based on the verification data packet, includes: The verification data packet flowing out of the queue channel is received by using a preset register to obtain a target verification data field; the target verification data field includes a target verification address, a target verification data and a target cyclic redundancy check code; the target verification address, the target verification data and the target cyclic redundancy check code are arranged based on a message format corresponding to the ESPI protocol; The target verification data field is driven based on a preset output signal enable to send the target verification data field to the target slave end through a preset ESPI serial bus, so that the target slave end performs simulation verification based on the verification data packet.

7. The master-slave device data transmission method according to any one of claims 1 to 6, characterized in that: The method of receiving the verification data packet flowing out of the queue channel by using a preset register, and driving the verification data packet to a target slave end by using a preset ESPI serial bus, so that the target slave end performs simulation verification based on the verification data packet, includes: Receiving the verification data packet flowing out of the queue channel through a preset register, and performing protocol encapsulation on the verification data packet based on the ESPI protocol to obtain an ESPI bus data frame; The ESPI bus data frame is driven by a preset ESPI serial bus, and the verification data packet is driven to a target slave end based on a preset bus clock frequency, so that the target slave end performs simulation verification based on the verification data packet.

8. A master-slave device data transmission device, characterized in that: include: A verification instruction acquisition module is used to acquire a number of verification instructions issued by the host verification program, and respectively determine the queue channel corresponding to each of the verification instructions; The verification instruction is a master-slave device simulation verification instruction generated based on the ESPI protocol; A data writing module, used for writing the verification data packets corresponding to the verification instructions into the queue channel in sequence based on the write enable signal corresponding to the queue channel; the queue depth corresponding to the queue channel is dynamically adjusted based on the channel occupancy rate of the queue channel during the data packet writing process; The data driving module is used to receive the verification data packet flowing out of the queue channel by using a preset register, and drive the verification data packet to the target slave end by using a preset ESPI serial bus, so that the target slave end performs simulation verification based on the verification data packet.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the master-slave device data transmission method as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the master-slave device data transmission method according to any one of claims 1 to 7 are implemented.

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