Simulation evaluation method of semiconductor device

Abstract

The invention provides a simulation evaluation method of a semiconductor device, which comprises the following steps of: a first judgment step: comparing an output result of simulation of a first device adopting the minimum size of the semiconductor device with an output result of actual measurement of the first device, judging whether the simulation result of the first device is accurate or not; and a second judgment step: for a second device adopting the actual size of the semiconductor device, simulating the second device through device parameters extracted by a layout parasitic extraction technology, and comparing an output result of the simulation of the second device with an output result of the actual measurement of the second device, and judging whether the simulation result of the second device is accurate or not. The unexpected effect of the invention is that whether the simulation of the semiconductor device is accurate or not and the existing problems can be correctly evaluated.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly relates to a simulation evaluation method for semiconductor devices. Background Art

[0002] Currently, there is a known technology for evaluating the simulation of semiconductor devices using a Ring Oscillator (ROSC). A ring oscillator is an oscillating circuit, in which an inverting circuit using PMOS transistors and NMOS transistors is cascaded into an odd number of inverting stages, and the output of the last inverter is fed back to the input terminal of the first inverter to form a loop. An inverting circuit is a circuit that inverts the input signal and then outputs it. When the input is "1" (high level), the output is "0" (low level); vice versa. In a ring oscillator, by making the number of series inverting circuit stages odd, the overall output is in an inverse relationship with the input, and since the feedback signal is continuously inverted repeatedly, oscillation is generated.

[0003] In each inverting circuit, due to reasons such as transistor characteristics and line parasitic capacitance, there will be a small delay (propagation delay time). Under the action of this delay, it takes time for the output of each inverting circuit to propagate to the next inverting circuit. Thus, as the signal circulates and propagates within the ring oscillator, the delay and the inverting action of the inverter are superimposed round by round, generating continuous oscillation. At this time, the oscillation frequency f is expressed as f = 1 / (2Ntpd) in terms of the number of inverting stages N and the delay time tpd of each stage. The oscillation frequency f (the reciprocal of the signal circulation propagation speed) depends on the structure of the ring oscillator and the delay of each inverting circuit. Therefore, by inputting a pulse signal into the ring oscillator to generate oscillation and measuring the oscillation frequency with an oscilloscope or a frequency counter, the device characteristics and the influence of line delay can be determined based on the oscillation frequency.

[0004] However, it is believed that the differences between the simulation results and the actual measurement results of semiconductor devices are mostly due to the RC extraction technology and the dependence on the MOS layout. In the RC technology, parasitic resistors (R) and parasitic capacitors (C) are extracted from the patterns of the circuit layout. The values of the parasitic resistors (R) and parasitic capacitors (C) extracted by the RC technology depend on various layout factors such as the length and width of the lines, the distance between layers, and the distance between adjacent lines. In addition, the MOS central model is a model obtained by modeling the representative device characteristics measured on a test chip (Testkey) and is used to represent the characteristics of MOS transistors. In the simulation and actual testing of semiconductor devices using the MOS central model, a standard device structure with specific L (gate length) and W (gate width) such as the minimum size is used. The central model only reflects the ideal situation and does not reflect the influence of the actual device layout and lines, resulting in differences between the simulation and the actual measurement due to layout dependence. Summary of the Invention

[0005] An object of the present invention is to provide a simulation evaluation method for semiconductor devices to improve the accuracy of semiconductor device simulation.

[0006] To solve the above technical problems, one aspect of the present invention is a simulation evaluation method for semiconductor devices, including: a first judgment step: comparing the output result of the simulation of a first device using the minimum size of the semiconductor device with the output result of the actual measurement of the first device to judge whether the result of the simulation of the first device is accurate; and a second judgment step: when it is judged in the first judgment step that the simulation of the first device is inaccurate, for a second device using the actual size of the semiconductor device, performing a simulation on the second device with the device parameters extracted by the layout parasitic extraction technology, and comparing the output result of the simulation of the second device with the output result of the actual measurement of the second device to judge whether the result of the simulation of the second device is accurate, wherein, in the first judgment step, when it is judged that the result of the simulation of the first device is accurate, it is judged that the simulation using the minimum size of the semiconductor device is accurate; in the first judgment step, when it is judged that the result of the simulation of the first device is inaccurate and it is judged in the second judgment step that the result of the simulation of the second device is accurate, it is judged that the layout parasitic extraction technology using the actual size of the semiconductor device and the simulation using the extracted device parameters are accurate; in the second judgment step, when it is judged that the result of the simulation of the second device is inaccurate, it is judged that the layout parasitic extraction technology using the actual size of the semiconductor device needs to be corrected.

[0007] Optionally, the semiconductor device is a MOSFET.

[0008] Optionally, in the first determination step, the first device using a ring oscillator is simulated and actually measured, and based on the oscillation frequency of the ring oscillator, it is determined whether the result of the simulation of the first device is accurate.

[0009] Optionally, in the second determination step, the second device using a ring oscillator is simulated and actually measured, and based on the oscillation frequency of the ring oscillator, it is determined whether the result of the simulation of the second device is accurate.

[0010] Optionally, the first determination step includes: Simulating the first device to obtain a simulation result of the first device; Actually measuring the first device to obtain an actual measurement result of the first device; Determining whether the simulation result of the first device is accurate.

[0011] Optionally, the step of determining whether the simulation result of the first device is accurate includes: Comparing the simulation result of the first device with the actual measurement result of the first device; if the difference between the two results does not reach a predetermined reference value, it is determined that the simulation using the first device is accurate; if the difference between the two results is greater than or equal to the predetermined reference value, it is determined that the simulation using the first device is inaccurate.

[0012] Optionally, the first device is a ring oscillator constructed based on the layout of an inverter with the minimum size.

[0013] Optionally, the second determination step includes: Simulating the second device to obtain a simulation result of the second device; Actually measuring the second device to obtain an actual measurement result of the second device; Determining whether the simulation result of the second device is accurate.

[0014] Optionally, the step of determining whether the simulation result of the second device is accurate includes: Comparing the simulation result of the second device with the actual measurement result of the second device; if the difference between the two results does not reach a predetermined reference value, it is determined that the simulation using the second device is accurate; if the difference between the two results is greater than or equal to the predetermined reference value, it is determined that the simulation using the second device is inaccurate.

[0015] Optionally, the second device is a ring oscillator constructed based on the layout of an inverter with the actual size.

[0016] In the simulation evaluation method of a semiconductor device provided by the present invention, it includes: a first judgment step: comparing the output result of the simulation of a first device using the minimum size of the semiconductor device with the output result of the actual measurement of the first device to judge whether the result of the simulation of the first device is accurate; and a second judgment step: for a second device using the actual size of the semiconductor device, performing a simulation on the second device with the device parameters extracted by the layout parasitic extraction technology, and comparing the output result of the simulation of the second device with the output result of the actual measurement of the second device to judge whether the result of the simulation of the second device is accurate. The unexpected effect of the present invention is that it can correctly evaluate whether the simulation of the semiconductor device is accurate and its existing problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention.

[0018] Figure 1 It is a flowchart of the simulation evaluation method of the semiconductor device according to the embodiment of the present invention.

[0019] Figure 2 It is an inverter structure according to the embodiment of the present invention.

[0020] Figure 3 It is a ring oscillator structure according to the embodiment of the present invention.

[0021] Figure 4 It is an inverter layout structure based on the actual size according to the embodiment of the present invention.

[0022] In the drawings: 10: power supply line; 12: ground line; 14: signal line; 16: P-type source; 18: P-type drain; 20: N-type source; 22: N-type drain; 24: gate; 100: inverter; 200: ring oscillator. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] To make the objectives, advantages, and features of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and not drawn to scale, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the drawings are often a part of the actual structures. In particular, the focus that each drawing needs to show is different, and sometimes different scales are used.

[0024] As used in the present invention, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more", in addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features. In addition, as used in the present invention, an element being disposed on another element generally only means that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the two elements may be directly or indirectly connected, coupled, cooperated or transmitted through an intermediate element, rather than being construed as indicating or implying a spatial position relationship between the two elements, that is, an element may be inside, outside, above, below or on one side of another element in any orientation, unless otherwise explicitly stated in the content. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0025] The simulation evaluation method of the semiconductor device according to the embodiment of the present invention is executed according to Figure 1 the flowchart shown below. Hereinafter, with reference to Figure 1 the following, the simulation evaluation method of the semiconductor device will be described.

[0026] Among them, a ring oscillator (ROSC) is used to evaluate the simulation of the semiconductor device. Figure 2 The following shows a structural example of the inverter 100 that constitutes the ring oscillator. Figure 3 The following shows the ring oscillator 200 formed by combining the inverters 100 and a partial enlarged view thereof.

[0027] The inverter 100 is formed by combining a PMOS and an NMOS. The inverter 100 includes a power supply line 10, a ground line 12, a signal line 14, a P-type source 16, a P-type drain 18, an N-type source 20, an N-type drain 22, and a gate 24. The P-type source 16 of the PMOS is connected to the power supply line 10. The N-type source 20 of the NMOS is connected to the ground line 12. The gate 24 shared by the PMOS and the NMOS is connected to the signal line 14. The P-type drain 18 of the PMOS is connected to the N-type drain 22 of the NMOS.

[0028] In the inverter 100, when the signal applied on the signal line 14 is at a low state (0V), the PMOS is in the conducting state and the NMOS is in the off state, and the output terminal is pulled to the power supply voltage (VDD) and thus is at a high state (VDD). When the signal applied on the signal line 14 is at a high state (VDD), the PMOS is in the off state and the NMOS is in the conducting state, and the output terminal is grounded and thus is at a low state (GND).

[0029] The ring oscillator 200 is formed by combining a plurality of inverters 100, and these inverters 100 are cascaded into an odd number of inverter stages. The ring oscillator 200 forms a loop by feeding back the output of the last inverter 100 to the input terminal of the first inverter 100. In the ring oscillator 200, by making the number of stages of the serially connected inverters 100 odd, the overall output and the input are in an inverse relationship. In addition, the feedback signal is continuously reversed repeatedly, thereby generating oscillation.

[0030] As described above, the oscillation frequency f of the ring oscillator 200 is expressed as f = 1 / (2Nt_pd) in terms of the number of inverter stages N and the delay time t_pd of each stage. The oscillation frequency f (the reciprocal of the signal cyclic propagation speed) depends on the structure of the ring oscillator 200 and the delay of each inverter 100. Therefore, by inputting a pulse signal into the ring oscillator 200 to generate oscillation and measuring the oscillation frequency f with an oscilloscope or a frequency counter, the influence of device characteristics and line delay can be determined according to the oscillation frequency.

[0031] When evaluating a simulation tool for semiconductor devices, the simulation result of the ring oscillator 200 is compared with the measured value during the actual operation of the ring oscillator 200 to determine whether it oscillates at the designed frequency and what the error is between the simulation result and the measured result. When the error is large, the accuracy of the device model and parasitic elements in the simulation can be re-evaluated. Among them, the predetermined reference value for judging the error size can be appropriately set according to the required simulation accuracy.

[0032] In step S10, a ring oscillator 200 is constructed using the layout of the inverter 100 based on the standard design rule (minimum size), and the ring oscillator 200 is simulated. That is to say, the ring oscillator 200 formed by connecting inverters 100 with the minimum size allowed by the process is simulated. Among them, for example, the oscillation frequency f of the ring oscillator 200 is simulated. The simulation can be carried out, for example, with SPICE (Simulation Program with Integrated Circuit Emphasis).

[0033] In step S12, an inverter 100 layout based on standard design rules (minimum size) is used to construct a ring oscillator 200, and the operation of the ring oscillator 200 is actually measured. For example, the oscillation frequency f of the ring oscillator 200 is actually measured.

[0034] In step S14, it is determined whether the result of the simulation is accurate. Specifically, the result of the simulation performed in step S10 is compared with the result of the actual measurement performed in step S12. If the difference between the two results does not reach a predetermined reference value, it is determined that the simulation using the minimum size of the semiconductor device is accurate (judgment result 1). That is to say, judgment result 1 indicates that the simulation based on standard design rules (minimum size) is accurate and no correction is required. In contrast, if the difference between the two results is equal to or greater than the predetermined reference value, it is determined that the simulation using the minimum size of the semiconductor device is inaccurate, and the process proceeds to step S16 for corresponding processing.

[0035] In step S16, a ring oscillator 200 is constructed using an inverter 100 layout based on the actual size, and the ring oscillator 200 is simulated. That is, the simulation is performed on a ring oscillator 200 whose layout parameters of the inverter 100 are exactly the same as the device center model (Model Testkey: a model obtained by modeling the device characteristics of the device under test for the purpose of measuring the characteristics of the device under test). For example, the oscillation frequency f of the ring oscillator 200 is simulated. The simulation can be performed using, for example, SPICE.

[0036] Specifically, as Figure 4 shown, the above parameters are the following layout-dependent parameters: gate length (Lg) and gate width (W); diffusion region length (Length of Diffusion, LOD); well proximity effect (WPE); influence of surrounding circuits and shallow trench isolation structure (Shallow Trench Isolation, STI).

[0037] Subsequently, for the inverter 100 using the layout based on the actual size, a layout parasitic extraction (LayoutParasitic Extraction, LPE) technique is used to extract parasitic elements (mainly parasitic resistors R and parasitic capacitors C) generated by the circuits and devices, so as to generate an RC netlist of the ring oscillator 200 model, and the RC netlist is used to perform accurate simulation. Taking the LPE technique as an example, the parasitic extraction tool is, for example, Calibre, Assura, StarRC, etc.

[0038] The RC netlist is used to describe circuit information that takes into account the parasitic resistances (R) and parasitic capacitances (C) contained in the lines and devices in circuit design and simulation. In this way, a simulation that reflects the actual physical effects can be achieved. A netlist is a file that describes the circuit components (transistors, resistors, capacitors, inductors, etc.) and the connection relationships between these components in text form.

[0039] In step S18, a ring oscillator 200 is constructed using the layout of the inverter 100 based on the actual dimensions, and the operation of the ring oscillator 200 is actually measured. Among them, for example, the oscillation frequency f of the ring oscillator 200 is actually measured.

[0040] In step S20, it is judged whether the result of the simulation is accurate. Among them, the result of the simulation performed in step S16 is compared with the result of the actual measurement performed in step S18. If the difference between the two results does not reach a predetermined reference value, it is judged that the simulation using the actual dimensions of the semiconductor device is accurate (judgment result 2). That is to say, judgment result 2 means that although the simulation based on the standard design rules (minimum dimensions) is inaccurate, the model correction based on the actual dimensions is accurate.

[0041] On the contrary, if the difference between the two results is equal to or greater than the predetermined reference value, it is judged that the simulation using the actual dimensions of the semiconductor device is inaccurate (judgment result 3). That is to say, there may be problems with the extraction of parasitic resistances (R) and parasitic capacitances (C) or the device center model performed by the LPE technology. Accordingly, it can be judged that correction is required.

[0042] As described above, according to this embodiment, it is possible to correctly evaluate whether the simulation of the semiconductor device is accurate and the problems existing therein.

[0043] In summary, in the simulation evaluation method of a semiconductor device provided by the present invention, it includes: a first judgment step: comparing the output result of the simulation of a first device using the minimum dimensions of the semiconductor device with the output result of the actual measurement of the first device to judge whether the result of the simulation of the first device is accurate; and a second judgment step: for a second device using the actual dimensions of the semiconductor device, performing a simulation on the second device with the device parameters extracted by the layout parasitic extraction technology, and comparing the output result of the simulation of the second device with the output result of the actual measurement of the second device to judge whether the result of the simulation of the second device is accurate. An unexpected effect of the present invention is that it is possible to correctly evaluate whether the simulation of the semiconductor device is accurate and the problems existing therein.

[0044] In addition, it should be recognized that although the present invention has been disclosed above in preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible variations and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or it can be modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A simulation evaluation method for a semiconductor device, characterized in that: include: A first judgment step: comparing an output result of a simulation performed on a first device using the minimum size of a semiconductor device with an output result of an actual measurement performed on the first device to judge whether a result of the simulation performed on the first device is accurate; as well as A second judging step: when it is judged in the first judging step that the simulation of the first device is inaccurate, a second device using the actual size of the semiconductor device is simulated using device parameters extracted by the layout parasitic extraction technology, and an output result of the simulation of the second device is compared with an output result of an actual measurement of the second device to judge whether the result of the simulation of the second device is accurate; Wherein, in the first judging step, when it is judged that the result of the simulation performed on the first device is accurate, it is judged that the simulation using the minimum size of the semiconductor device is accurate; In the first judging step, when it is judged that the result of the simulation of the first device is inaccurate and in the second judging step, it is judged that the result of the simulation of the second device is accurate, then it is judged that the simulation using the layout parasitic extraction technology of the actual size of the semiconductor device and the extracted device parameters is accurate; In the second determination step, when it is determined that the result of the simulation of the second device is inaccurate, it is determined that the layout parasitic extraction technology using the actual size of the semiconductor device needs to be corrected.

2. The semiconductor device simulation evaluation method according to claim 1, wherein: The semiconductor device is a MOSFET.

3. The simulation evaluation method for a semiconductor device according to claim 2, wherein: In the first judgment step, simulation and actual measurement are performed on the first device using a ring oscillator, and whether the result of the simulation on the first device is accurate is judged based on the oscillation frequency of the ring oscillator.

4. The semiconductor device simulation evaluation method according to claim 2 or 3, characterized in that: In the second judgment step, simulation and actual measurement are performed on the second device using a ring oscillator, and whether the simulation result of the second device is accurate is judged based on the oscillation frequency of the ring oscillator.

5. The semiconductor device simulation evaluation method according to claim 1, wherein: The first determination step comprises: Simulating the first device to obtain a simulation result of the first device; Performing actual measurement on the first device to obtain an actual measurement result of the first device; Determine whether the simulation result of the first device is accurate.

6. The simulation evaluation method for a semiconductor device according to claim 5, wherein: The step of determining whether the simulation result of the first device is accurate comprises: Compare the simulation result of the first device with the actual measurement result of the first device; if the difference between the two results does not reach a predetermined reference value, judge that the simulation using the first device is accurate; if the difference between the two results is above the predetermined reference value, judge that the simulation using the first device is inaccurate.

7. The simulation evaluation method for a semiconductor device according to claim 5, wherein: The first device is a ring oscillator constructed based on a minimum-sized inverter layout.

8. The simulation evaluation method for a semiconductor device according to claim 1, wherein: The second determination step comprises: simulating the second device to obtain a simulation result of the second device; Performing actual measurement on the second device to obtain an actual measurement result of the second device; Determine whether the simulation result of the second device is accurate.

9. The simulation evaluation method for a semiconductor device according to claim 8, wherein: The step of determining whether the simulation result of the second device is accurate comprises: Compare the simulation result of the second device with the actual measurement result of the second device; if the difference between the two results does not reach a predetermined reference value, determine that the simulation using the second device is accurate; if the difference between the two results is above the predetermined reference value, determine that the simulation using the second device is inaccurate.

10. The semiconductor device simulation evaluation method according to claim 1 or 8, characterized in that: The second device is a ring oscillator constructed based on a practical-sized inverter layout.

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