A model-based chip debugging system

Abstract

The present application relates to the field of chip verification technology, and in particular to a model-based chip debugging system. The system adds a virtual module, which only needs to implement the functions of some hardware modules without the need to specifically abstract the interface definition of the hardware module. According to the target level corresponding to the target debugging information, a chip debugging model is formed by a hardware module whose first module level is less than or equal to the target level and a virtual module whose second module level is equal to the target level. This improves the efficiency of debugging using the chip debugging model while ensuring the functional accuracy of the chip debugging model, that is, improves the efficiency of chip debugging.

Description

Technical Field

[0001] The present invention relates to the technical field of chip debugging, and in particular to a chip debugging system based on a model. Background Art

[0002] In the chip design and verification scenario, Cmodel can refer to a model written in C or C++. Cmodel can be used to quickly model and verify the functions and behaviors of the chip in the early stages of chip design. It can also serve as a bridge between hardware and software during the chip design process, so that when the hardware has not yet been fully implemented, software development and debugging can be carried out based on Cmodel, and the interface and interaction logic between software and hardware can be verified in advance. In addition, by modeling the key functional modules of the chip in Cmodel, the performance of different algorithm implementations and architectural designs can be conveniently evaluated and compared, providing a basis for chip optimization.

[0003] In the existing technology, the expected behavior of all hardware modules is usually described in C or C++ language. The interface definition of each hardware module needs to be abstracted to support hardware performance verification, module-level co-simulation and other processing. However, describing all hardware modules will lead to poor debugging efficiency of Cmodel, which makes it difficult to meet the high-speed requirements of software for chip debugging.

[0004] Therefore, how to improve the efficiency of chip debugging has become an urgent problem to be solved. Summary of the Invention

[0005] In view of the above technical problems, the technical solution adopted by the present invention is:

[0006] A chip debugging system based on a model, the system comprises: M hardware modules {a1, a2, ..., a m ,…,a M}、N virtual modules {b1,b2,…,b n ,…,b N}, a processor and a memory storing a computer program, wherein a m is the mth hardware module, m is an integer in the range [1, M], b n is the nth virtual module, where n is an integer in the range [1, N], the hardware module corresponds to the first module level, the virtual module corresponds to the second module level, and when the computer program is executed by a processor, the following steps are implemented:

[0007] S101, obtaining target debugging information, and determining a target level d according to the target debugging information.

[0008] S102 , forming a chip debugging model by using all hardware modules whose first module level is less than or equal to d and virtual modules whose second module level is equal to d.

[0009] S103: Use the chip debugging model to debug the target debugging information.

[0010] Compared with the prior art, the present invention has significant advantages. By utilizing the above technical solution, the model-based chip debugging system provided by the present invention can achieve considerable technological advancement and practicality, and has wide industrial application value. It has at least the following advantages:

[0011] The present invention provides a model-based chip debugging system, which includes: M hardware modules {a1, a2, ..., a m ,…,a M}、N virtual modules {b1,b2,…,b n ,…,b N}, a processor and a memory storing a computer program, wherein a m is the mth hardware module, m is an integer in the range [1, M], b n The nth virtual module is a hardware module corresponding to a first module level, and the virtual module corresponds to a second module level. When the computer program is executed by a processor, the following steps are implemented: S101, obtaining target debugging information, and determining a target level d based on the target debugging information; S102, forming a chip debugging model by including all hardware modules whose first module level is less than or equal to d and virtual modules whose second module level is equal to d; S103, using the chip debugging model to debug the target debugging information.

[0012] It can be seen that a new virtual module is added, and the virtual module only needs to implement the functions of some hardware modules without the need to specifically abstract the interface definition of the hardware module. According to the target level corresponding to the target debugging information, a chip debugging model is formed by a hardware module whose first module level is less than or equal to the target level and a virtual module whose second module level is equal to the target level. This improves the efficiency of debugging using the chip debugging model while ensuring the functional accuracy of the chip debugging model, that is, improves the efficiency of chip debugging. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A schematic diagram of a flow chart of a computer program being executed by a processor in a model-based chip debugging system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0016] This embodiment provides a model-based chip debugging system. Figure 1 , is a flow chart of a computer program being executed by a processor in a model-based chip debugging system provided by an embodiment of the present invention, wherein the system comprises: M hardware modules {a1, a2, ..., a m ,…,a M}、N virtual modules {b1,b2,…,b n ,…,b N}, a processor and a memory storing a computer program, wherein a m is the mth hardware module, m is an integer in the range [1, M], b n is the nth virtual module, where n is an integer in the range [1, N], the hardware module corresponds to the first module level, the virtual module corresponds to the second module level, and when the computer program is executed by a processor, the following steps are implemented:

[0017] S101, obtaining target debugging information, and determining a target level d according to the target debugging information;

[0018] S102, forming a chip debugging model by using all hardware modules whose first module level is less than or equal to d and virtual modules whose second module level is equal to d;

[0019] S103: Use the chip debugging model to debug the target debugging information.

[0020] Among them, the hardware module and the virtual module are both implemented in C language or C++ language, and are not physical modules. The hardware module corresponds to the first module level. The first module levels corresponding to different hardware modules can be different or the same. When the first module levels corresponding to different hardware modules are the same, it means that the different hardware modules belong to the same module level.

[0021] The virtual module corresponds to the second module level, and different virtual modules correspond to different second module levels.

[0022] Target debugging information may refer to the debugging content that the software needs to execute through the chip debugging model. Different target debugging information may correspond to different target levels. The implementer may pre-record the module levels corresponding to each type of target debugging information. After receiving the target debugging information provided by the software, the implementer may determine the module level corresponding to the target debugging information as the target level.

[0023] Specifically, in this embodiment, the value ranges of the first module level, the second module level and the target level can all be [0, K], so that the first module level or the second module level can be directly compared with the target level to determine the qualified hardware modules and virtual modules.

[0024] In a specific embodiment, the virtual modules whose second module level is equal to d correspond to all hardware modules whose first module level is greater than d.

[0025] Among them, the functions implemented by the virtual module with the second module level equal to d are the same as the functions implemented by all hardware modules with the first module level greater than d, thereby ensuring the functional accuracy of the chip debugging model.

[0026] Specifically, for a hardware module, the functional implementation of the hardware module may be included in several virtual modules.

[0027] In a specific embodiment, the first module level and the second module level both belong to a reference level set, and the reference level set includes K+1 reference levels, where K is a positive integer.

[0028] In this embodiment, the value range of the reference level may be [0, K], and correspondingly, the value ranges of the first module level and the second module level may both be [0, K].

[0029] In a specific embodiment, the M hardware modules correspond to a target chip, and the target chip includes a cache with I cache levels, where I is a positive integer;

[0030] I and K satisfy the condition: K=I+1.

[0031] Among them, M hardware modules can refer to the functional implementation of each module in the target chip. The target chip can include caches with I cache levels. For example, the memory in the DPC unit, the L1 cache in the DPC unit, the L2 cache in the chip, etc. correspond to different cache levels respectively. The cache level can represent the complexity of accessing the corresponding cache from software.

[0032] Specifically, in this embodiment, each cache level corresponds to a reference level, and the value range of the reference level corresponding to I cache levels is [1, I].

[0033] I and K satisfy the condition: K=I+1, that is, the first reference level among the K+1 reference levels is 0, and the second reference level to the K+1th reference level are 1 to I respectively.

[0034] In a specific embodiment, for any hardware module, if the hardware module belongs to a functional layer in the target chip, the first module level corresponding to the hardware module is the first reference level in the reference level set;

[0035] If the hardware module does not belong to the functional layer in the target chip, the cache level corresponding to the cache that the hardware module can directly access is used as the reference level corresponding to the hardware module.

[0036] Among them, the functional layer may include modules with actual functions.

[0037] Specifically, if the hardware module belongs to the functional layer, the first module level corresponding to the hardware module is the first reference level in the reference level set, that is, the reference level corresponding to the hardware module is 0;

[0038] If the hardware module does not belong to the functional layer in the chip, the cache level corresponding to the cache that the hardware module can directly access is used as the reference level corresponding to the hardware module. For example, the hardware module can directly access the L2 cache. In this embodiment, the cache level of the L2 cache is 3, and the reference level corresponding to the hardware module is 3.

[0039] In a specific implementation, the hardware module includes several sub-modules, and the sub-modules correspond to the first module level.

[0040] Any hardware module may include multiple sub-modules, and the first module levels corresponding to the sub-modules included in the same hardware module may be different.

[0041] In a specific embodiment, forming a chip debugging model by all hardware modules whose first module level is less than or equal to d and virtual modules whose second module level is equal to d includes:

[0042] A chip debugging model is formed by all submodules whose first module level is less than or equal to d and virtual modules whose second module level is equal to d, wherein the virtual modules whose second module level is equal to d correspond to all submodules whose first module level is greater than d.

[0043] Among them, this embodiment forms a chip debugging model by all sub-modules whose first module level is less than or equal to d and virtual modules whose second module level is equal to d, wherein the virtual modules whose second module level is equal to d correspond to all sub-modules whose first module level is greater than d, thereby improving the granularity of the chip debugging model formed by hardware modules and virtual modules, and can further improve the efficiency of chip debugging.

[0044] In a specific implementation, the virtual module is implemented using C language.

[0045] Among them, the virtual module can also be implemented through C++ language.

[0046] It can be seen that this embodiment adds a virtual module, which only needs to implement the functions of some hardware modules without the need to specifically abstract the interface definition of the hardware module. According to the target level corresponding to the target debugging information, a chip debugging model is formed by a hardware module whose first module level is less than or equal to the target level and a virtual module whose second module level is equal to the target level. This improves the efficiency of debugging using the chip debugging model while ensuring the functional accuracy of the chip debugging model, that is, improves the efficiency of chip debugging.

[0047] Although some specific embodiments of the present invention have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A model-based chip debugging system, characterized in that: The system includes: M hardware modules {a1, a2, ..., a m ,…,a M }、N virtual modules {b1,b2,…,b n ,…,b N }, a processor and a memory storing a computer program, wherein a m is the mth hardware module, m is an integer in the range [1, M], b n is the nth virtual module, where n is an integer in the range [1, N], the hardware module corresponds to the first module level, the virtual module corresponds to the second module level, and when the computer program is executed by a processor, the following steps are implemented: S101, obtaining target debugging information and a module level corresponding to the target debugging information, and determining the module level corresponding to the target debugging information as a target level d; S102: forming a chip debugging model by including all hardware modules whose first module level is less than or equal to d and virtual modules whose second module level is equal to d, wherein the virtual modules whose second module level is equal to d correspond to all hardware modules whose first module level is greater than d, and the functions implemented by the virtual modules whose second module level is equal to d are the same as the functions implemented by all hardware modules whose first module level is greater than d; S103: Use the chip debugging model to debug the target debugging information.

2. The model-based chip debugging system according to claim 1, characterized in that: The first module level and the second module level both belong to a reference level set, and the reference level set includes K+1 reference levels, where K is a positive integer.

3. The model-based chip debugging system according to claim 2, characterized in that: The M hardware modules correspond to a target chip, and the target chip includes a cache with I cache levels, where I is a positive integer; I and K satisfy the condition: K=I+1.

4. The model-based chip debugging system according to claim 3, characterized in that: For any hardware module, if the hardware module belongs to a functional layer in the target chip, the first module level corresponding to the hardware module is the first reference level in the reference level set; If the hardware module does not belong to the functional layer in the target chip, the cache level corresponding to the cache that the hardware module can directly access is used as the reference level corresponding to the hardware module.

5. The model-based chip debugging system according to claim 1, characterized in that: The hardware module includes several sub-modules, and the sub-modules correspond to the first module level.

6. The model-based chip debugging system according to claim 5, characterized in that: The chip debugging model is formed by all hardware modules whose first module level is less than or equal to d and virtual modules whose second module level is equal to d, including: A chip debugging model is formed by all submodules whose first module level is less than or equal to d and virtual modules whose second module level is equal to d, wherein the virtual modules whose second module level is equal to d correspond to all submodules whose first module level is greater than d.

7. The model-based chip debugging system according to claim 1, characterized in that: The virtual module is implemented using C language.

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