Display panel, display device, and control method for display device

Abstract

The present application discloses a display panel, a display device, and a control method for a display device. The display panel includes: a plurality of data signal lines extending along a first direction, and the plurality of data signal lines are arranged in sequence along a second direction; a plurality of fan-out lines for respectively providing data signals corresponding to at least two data signal lines within at least two source signal intervals corresponding to each pixel row in a first data frame; a plurality of signal gating circuits, each signal gating circuit being electrically connected to one fan-out line and at least two data signal lines; the signal gating circuit is configured to connect the fan-out line to the corresponding data signal line during a first period of the source signal interval; wherein, the duration of the source signal interval is h, the duration of the first period is t1, and 0.5*h < t1 < h. According to the embodiments of the present application, by pre-charging the fan-out lines, the charging difference between the data signal lines in different regions can be reduced, and the vertical stripe defect can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, a display device, and a control method for the display device. Background Technology

[0002] Currently, to better enhance the user experience, the refresh rates of electronic display devices such as smartphones and tablets are constantly increasing. For example, high refresh rates such as 120Hz and 144Hz are gradually becoming common in various display devices.

[0003] In order to save costs while achieving high refresh rate driving function, a multi-channel strobe (MUX) design is usually adopted, which uses a single fan-out line to provide data signals to multiple data signal lines in a time-division output manner.

[0004] However, during high-frequency display, the varying lengths of the fan-out traces result in a significant difference in resistance between the fan-out traces connecting the data signal lines on the sides of the display area and those connected to the fan-out traces in the center area. In certain scenes, such as heavy-load scenes, the difference in resistance between the fan-out traces on the sides and the center area leads to a substantial difference in the actual received data signal voltage, resulting in vertical stripes on the display. Summary of the Invention

[0005] This application provides a display panel, a display device, and a control method for the display device, which can improve the technical problem of vertical stripes appearing on high-frequency display screens in related technologies.

[0006] In a first aspect, embodiments of this application provide a display panel, the display panel comprising:

[0007] Multiple data signal lines extend along a first direction, and multiple data signal lines are arranged sequentially along a second direction; wherein the first direction and the second direction intersect.

[0008] Multiple fan-out traces are used to provide data signals corresponding to at least two data signal lines in at least two source signal intervals corresponding to each pixel row in the first data frame.

[0009] Multiple signal gating circuits, each of which is electrically connected to a fan-out trace and at least two data signal lines;

[0010] The signal gating circuit is used to connect the fan-out trace with the corresponding data signal line during the first time period of the source signal interval; wherein,

[0011] The duration of the source signal interval is h, and the duration of the first time interval is t1.

[0012] 0.5*h <t1<h。

[0013] In a second aspect, embodiments of this application provide a display device, including a driver chip and a display panel as described in the first aspect, wherein the driver chip is electrically connected to multiple fan-out traces;

[0014] In the first data frame, the driver chip is used to provide at least two corresponding data signals to each fan-out trace within at least two source signal intervals corresponding to each pixel row.

[0015] Thirdly, embodiments of this application provide a control method for a display device, applied to the display device of the second aspect, the method comprising:

[0016] In the first data frame, within the two source signal intervals corresponding to each pixel row, two corresponding data signals are provided to each fan-out trace;

[0017] During the first time period of the two source signal intervals corresponding to each pixel row, a first gating signal and a second gating signal are provided to the signal gating circuit, respectively; wherein the first gating signal and the second gating signal are used to drive the two gating units in the signal gating circuit.

[0018] Compared with the prior art, the display panel, display device, and control method of the display device provided in this application, by setting a signal gating circuit to determine the relationship between the first time period of the fan-out trace and the corresponding data signal line and the size of the source signal interval, enables the fan-out trace to perform a pre-charging function and provides data signals to the data signal lines during the first time period after pre-charging. After sufficient pre-charging, the charging effect caused by the trace resistance of the fan-out trace in different areas can be reduced, thereby improving the charging difference between data signal lines in different areas and thus improving the vertical stripe phenomenon of the display panel. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application;

[0021] Figure 2 This is a timing diagram of the source signal range provided in an embodiment of this application;

[0022] Figure 3 This is a timing diagram of the source signal range provided in another embodiment of this application;

[0023] Figure 4 This is a schematic diagram of the structure of a display panel provided in another embodiment of this application;

[0024] Figure 5 This is a schematic diagram of the structure of a display panel provided in another embodiment of this application;

[0025] Figure 6 This is a partial structural schematic diagram of a display panel provided in one embodiment of this application;

[0026] Figure 7 This is a timing diagram of the source signal range provided in another embodiment of this application;

[0027] Figure 8 This is a schematic diagram of the structure of a display device provided in an embodiment of this application.

[0028] In the attached image:

[0029] 10. Pixel circuit; 20. Signal gating circuit; Fanout; Data line; 100. Display panel; 1000. Display device. Detailed Implementation

[0030] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0031] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0032] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The embodiments will now be described in detail with reference to the accompanying drawings.

[0033] Currently, to better enhance the user experience, the refresh rates of electronic display devices such as smartphones and tablets are constantly increasing. For example, high refresh rates such as 120Hz and 144Hz are gradually becoming common in various display devices.

[0034] In order to save costs while achieving high refresh rate driving function, a multi-channel strobe (MUX) design is usually adopted, which uses a single fan-out line to provide data signals to multiple data signal lines in a time-division output manner.

[0035] However, during high-frequency display, due to the difference in the length of each fan-out trace, there is a significant difference in resistance between the fan-out traces connected to the data signal lines on the sides of the display area and those connected to the fan-out traces in the center area. In certain scenes, such as heavy-load scenes, the data signal lines on the sides and the center area are affected by the different resistance values ​​of the fan-out traces, resulting in a significant difference in the actual received data signal voltage, thus causing vertical stripes on the display. As an example, the aforementioned heavy-load scene could be a white screen with two bright lines and two dark lines, or a red / green / blue screen with two bright lines and two dark lines.

[0036] To address the aforementioned technical problems, embodiments of this application provide a display panel, a display device, and a method for controlling the display device. The display panel provided in the embodiments of this application will be described first.

[0037] Figure 1A schematic diagram of a display panel according to an embodiment of this application is shown. The display panel includes multiple data signal lines, multiple fanout lines, and multiple signal gating circuits 20.

[0038] In the diagram, the X direction is the first direction X, and the Y direction is the second direction Y. The first direction X and the second direction Y intersect the thickness direction of the display panel in pairs. Optionally, the first direction X and the second direction Y can be perpendicular to the thickness direction of the display panel in pairs.

[0039] Data lines can extend along a first direction, while multiple data lines are arranged sequentially along a second direction. The first and second directions intersect.

[0040] As an optional implementation, a single data signal line (Dataline) can be connected to the pixel circuits 10 in the same column when extending along a first direction within the display area of ​​the display panel. Combined with the progressive scan signals Scan1-ScanN provided by the scan signal lines, the data signal line (Dataline) can sequentially write corresponding data signals to a column of pixel circuits 10.

[0041] In the plurality of signal gating circuits 20, each signal gating circuit 20 can be electrically connected to a fanout trace and at least two data signal lines. A single signal gating circuit 20 can connect the fanout trace to one of the data signal lines, so that the voltage signal provided by the fanout trace is written to the corresponding pixel circuit 10 through the connected data signal line.

[0042] In one example, if a single signal gating circuit 20 is connected to one fanout line and two data lines, the display panel is a 1:2 MUX design; if a single signal gating circuit 20 is connected to one fanout line and four data lines, the display panel is a 1:4 MUX design.

[0043] Please refer to Figure 2 In the first data frame, the fanout can provide data signals corresponding to at least two data signal lines (Datalines) within at least two source signal intervals (h) corresponding to each pixel row. For example, taking a single signal gating circuit 20 connected to one fanout and two data signal lines (Datalines), the single fanout can be connected to one of the two data signal lines (Datalines) through the signal gating circuit 20.

[0044] For example, in the first data frame, taking a fanout trace connected to data signal lines A and B via signal gating circuit 20 as an example, each pixel row can correspond to two source signal intervals h. The fanout trace provides a data signal corresponding to data signal line A in one of the source signal intervals h, and the data signal can be written to the pixel circuit 10 corresponding to data signal line A in the pixel row through signal gating circuit 20 and data signal line A; the fanout trace provides a data signal corresponding to data signal line B in the other source signal interval h, and the data signal can be written to the pixel circuit 10 corresponding to data signal line B in the pixel row through signal gating circuit 20 and data signal line B.

[0045] In the first data frame, within the multiple source signal intervals h corresponding to any pixel row, the fanout trace can provide multiple data signals to be written to the pixel circuit 10 of that pixel row. After the data signals of the pixel circuit 10 of that pixel row are written, the data signals of the pixel circuit 10 of the next pixel row can be written by the scan signal driven line by line. After the data signals of all pixel rows are written, the first data frame is completed.

[0046] like Figure 2 As shown, the signal gating circuit 20 can connect the fanout trace to the corresponding data signal line Dataline in response to the MUX signal during the first time period t1 of the source signal interval h, so that the data signal provided by the fanout trace Fanout can be written to the data signal line Dataline through the signal gating circuit 20 during the first time period t1.

[0047] Understandably, during the first time period t1, if the pixel circuit 10 of a certain pixel row receives a valid scan signal from the control data writing transistor, the data signal provided by the fanout trace can also be written to the gate of the driving transistor of the pixel circuit 10 simultaneously. This data signal writing method is called direct charge writing. During the first time period t1, if the pixel circuit 10 does not receive a valid scan signal from the control data writing transistor, the data signal provided by the fanout trace can only be written to the data signal line Dataline. After the first time period t1, when the pixel circuit 10 receives a valid scan signal, the charge stored on the data signal line Dataline can be written to the gate of the driving transistor of the pixel circuit 10, which can also realize the writing of the data signal. This data signal writing method is called line charge writing.

[0048] The duration of a single source signal interval can be h, and the duration of the first time interval within that interval can be t1. The duration t1 of the first time interval can be set as follows:

[0049] 0.5*h <t1<h。

[0050] The duration h of the aforementioned source signal interval is the duration during which the driver chip provides data signals to the fanout trace, i.e., the duration during which the fanout trace is filled with data signals. The first time period t1 is the connection duration between the fanout trace and a certain data signal line. To avoid the connection duration between the fanout trace and the data signal line being too short, which would prevent effective charging of the pixel circuit 10, the duration of the first time period should be set to be greater than the duration h of the source signal interval.

[0051] When the duration t1 of the first time period is less than the total duration h of a single source signal interval, and the starting time node of the source signal interval does not coincide with the starting time node of the first time period t1, since there is already a data signal voltage on the fanout trace within the source signal interval, the data signal on the fanout trace can precharge the fanout trace during the time interval before the first time period t1.

[0052] Understandably, within the non-display area corresponding to the fanout trace, the fanout trace extends in a fan shape and connects to each column of pixel circuits 10. Therefore, the trace length of the fanout trace corresponding to a column of pixel circuits 10 in the middle area is usually shorter than that of the fanout trace corresponding to a column of pixel circuits 10 in the edge area. Consequently, the fanout trace connected to the edge area typically has a higher trace impedance. Furthermore, since the resistivity of the metal layer where the fanout trace is located is usually higher than that of the metal layer where the data signal line is located, the trace impedance of the fanout trace is further increased compared to the data signal line. For two fanout traces with significantly different trace resistances, a noticeable charging difference will occur during charging, resulting in vertical lines appearing on the display panel when displaying heavy-load images.

[0053] By increasing the pre-charge level of the fanout traces, the fanout traces can be fully pre-charged, thereby reducing the charging difference between fanout traces with different trace resistances and thus improving the vertical stripe phenomenon on the display panel.

[0054] Please refer to Figure 3 In some embodiments, the aforementioned single source signal interval h may further include a second time period t2 and a third time period t3. The second time period t2 is before the first time period t1, and the third time period t3 is after the first time period t1.

[0055] During the second time period t2 and the third time period t3 within each source signal interval h, the signal gating circuit 20 disconnects the fanout trace from the corresponding data signal line Dataline.

[0056] Within a single source signal interval h, the intervals are, in sequence, the second time period t2, the first time period t1, and the third time period t3.

[0057] The second time period t2 can be considered the pre-processing stage. During the second time period t2, the driver chip has already provided the corresponding data signal to the fanout trace. At this time, since the signal gating circuit 20 is not turned on, the signal voltage of this data signal can only pre-charge the fanout trace. That is, the fanout trace can be fully pre-charged during the second time period t2.

[0058] The third time period t3 can be a subsequent time period. During the third time period t3, data signals still exist on the fanout trace. At the end of the third time period t3, the data signal can jump to the signal voltage corresponding to the next pixel circuit 10. Since the signal gating circuit 20 has been disconnected, it will not affect the data signal written to the pixel circuit 10.

[0059] By setting the first time period t1 as the middle stage of the source signal interval h, the fanout traces can be fully pre-charged before the first time period t1, thereby reducing the charging difference between the various fanout traces.

[0060] In some embodiments, the duration of the second time period t2 is t2, the duration of the third time period t3 is t3, and the second time period t2 and the third time period t3 can be set as follows:

[0061] t2 <t1,t3<t1。

[0062] Since the signal gating circuit 20 is turned on during the first time period t1, the data signal provided by the fanout routing can flow into the corresponding data signal line Dataline. That is, the duration of the first time period is the charging pulse width market. In order to fully charge the data signal line Dataline, the first time period t1 should be set to the longest of the three time periods, i.e., t2. <t1,t3<t1。

[0063] In some embodiments, the second time period t2 and the third time period t3 can satisfy the following relationship:

[0064] t2>t3;

[0065] During the second time period t2, the data signal on the fanout trace can fully precharge the fanout trace, thereby reducing the charging difference between the fanout traces that were precharged during the first time period t1. Therefore, increasing the duration of the second time period t2 can improve the pre-charging degree of the fanout trace.

[0066] In the third time period t3, since the signal gating circuit 20 has been disconnected, and the data signal on the fanout trace in the next source signal interval h will change based on the target brightness of the next pixel circuit 10, the third time period t3 cannot improve the vertical stripe phenomenon on the display panel.

[0067] Therefore, within a single source signal interval h, the duration of the second time period t2 can be set to be greater than the duration of the third time period t3, so that the second time period can fully realize the pre-charging function and the first time period can fully realize the data writing function.

[0068] In some embodiments, the duration percentage of each of the above time periods within a single source signal interval h can satisfy the following condition:

[0069] t1 / h is 13 / 24 to 19 / 24;

[0070] t2 / h is 1 / 12 to 1 / 3;

[0071] t3 / h is 1 / 8;

[0072] In this embodiment, based on the duration constraints of each time period in the above embodiments, the duration proportion of the first time period t1 within a single source signal interval h can be set to 13 / 24 to 19 / 24, and the duration proportion of the third time period t3 within a single source signal interval h can be set to 1 / 8. The remaining duration of the single source signal interval h is then the duration of the second time period t2. Therefore, the duration proportion of the second time period t2 within a single source signal interval h is set to 1 / 12 to 1 / 3. For example, when the duration proportion of the first time period t1 is 13 / 24 and the duration proportion of the third time period t3 is 1 / 8, the corresponding duration proportion of the second time period t2 is 1 / 3; while when the duration proportion of the first time period t1 is 19 / 24 and the duration proportion of the third time period t3 is 1 / 8, the corresponding duration proportion of the second time period t2 is 1 / 12.

[0073] As an optional implementation, the duration of the first time period t1 can be 3 / 4, and the durations of the second time period t2 and the third time period t3 can be 1 / 8. Taking a refresh rate of 144Hz for the display panel as an example, when the signal gating circuit 20 is connected to the two data signal lines Dataline, during the data signal writing stage of a single pixel row, the fanout trace Fanout can provide corresponding data signals to the two data signal lines Dataline in the two source signal intervals h respectively. Taking a duration of 1.2μs for a single source signal interval as an example, based on the duration proportions of the above-mentioned time periods, the duration of the first time period t1 can be set to 0.9μs, and the durations of the second time period t2 and the third time period t3 can be set to 0.15μs.

[0074] It is understandable that, since the data signal writing stage corresponding to a single pixel row includes two source signal intervals h, the duration of the data signal writing stage corresponding to a single pixel row is 2.4μs.

[0075] At a refresh rate of 144Hz, the duration of the data signal writing phase for all pixel rows in a single image frame is approximately 1 / 144s, or 6.9ms.

[0076] Please refer to Figure 4 In some embodiments, the signal gating circuit 20 described above may include a plurality of gating units 21.

[0077] The first end of the gating unit 21 is electrically connected to the fanout line corresponding to the signal gating circuit 20, and the second end of the gating unit 21 is connected to the corresponding data signal line.

[0078] The gating unit 21 can turn on in response to the gating signal when it receives the corresponding gating signal MUX1 / MUX2.

[0079] Taking a signal gating circuit 20 connected to a fanout trace and two data signal lines as an example, the signal gating circuit 20 may include two gating units 21. By turning on the two gating units 21 respectively during the first time period t1 of the two source signal intervals h, the two data signals provided by the fanout trace in the two source signal intervals h can be written to the two data signal lines Datalines respectively.

[0080] Please refer to Figure 5 In some embodiments, the signal gating circuit 20 can be connected between a fanout trace and four data signal lines, in which case a single signal gating circuit 20 may include four gating units 21.

[0081] like Figure 6As shown, in the first data frame, within the first time period t1 of the two source signal intervals h corresponding to the i-th pixel row, the signal gating circuit 20 can connect the fanout trace Fanout to the first data signal line Data1 and the second data signal line Data2 respectively, where i≥1 and i is a positive integer;

[0082] During the first time period t1 of the two source signal intervals h corresponding to the (i+1)th pixel row, the signal gating circuit 20 can connect the fanout trace Fanout to the third data signal line Data3 and the fourth data signal line Data4, respectively.

[0083] In this embodiment, a single fanout can provide data signals for four data lines respectively.

[0084] As an optional implementation, the display panel may include a first sub-pixel, a second sub-pixel, and a third sub-pixel with different emitted light colors.

[0085] In the i-th pixel row, the first data signal line Data1 is connected to the corresponding first sub-pixel, and the second data signal line Data2 is connected to the corresponding third sub-pixel;

[0086] In the (i+1)th pixel row, the third data signal line Data3 is connected to the corresponding second sub-pixel, and the fourth data signal line Data4 is connected to the corresponding third sub-pixel.

[0087] As an example, such as Figure 6 As shown, taking the first sub-pixel as red sub-pixel R, the second sub-pixel as green sub-pixel G, and the third sub-pixel as blue sub-pixel B as an example, the pixel arrangement of the display panel is RGBG. Figure 7 The corresponding signal timing diagram is shown.

[0088] like Figure 6 As shown, when the two pixels in the i-th pixel row are RG, the signal gating circuit 20 is connected to the first data signal line Data1 and the second data signal line Data2 through the first gating unit M1 and the second gating unit M2 respectively. The first data signal line Data1 is connected to R in the i-th row, and the second data signal line Data2 is connected to G in the i-th row.

[0089] Similarly, when the two pixels in the (i+1)th pixel row are BG, the signal gating circuit 20 is connected to the third data signal line Data3 and the fourth data signal line Data4 through the third gating unit M3 and the fourth gating unit M4, respectively. The third data signal line Data3 is connected to B in the (i+1)th pixel row, and the fourth data signal line Data4 is connected to G in the (i+1)th pixel row.

[0090] In the above embodiment, during the process of providing scan signals row by row, a single fanout trace can provide data signals for two rows and two columns, totaling four pixels. At this time, as... Figure 6 As shown, the pixel circuits in the i-th and (i+1)-th rows are both connected to the same scan signal line. That is, a single scan signal can drive two rows of pixels to write data signals. Therefore, the number of fanout traces in the display panel can be set to half the number of columns, and the number of shift register units providing scan signals can also be set to half the number of rows.

[0091] In some embodiments, the signal gating circuit 20 described above can be connected between a fanout trace and two data signal lines. In this case, a single signal gating circuit 20 may include two gating units 21.

[0092] In the first data frame, during the first time period t1 of the two source signal intervals h corresponding to the i-th pixel row, the signal gating circuit 20 can connect the fanout trace Fanout to the first data signal line Data1 and the second data signal line Data2 respectively, where i≥1 and i is a positive integer;

[0093] In this embodiment, a single fanout trace can provide data signals to two pixels in two columns while providing scan signals row by row. Therefore, the number of fanout traces in the display panel can be set to half the number of columns, thereby effectively reducing the hardware requirements of the driver chip.

[0094] In some embodiments, the display panel may include a display area and a non-display area surrounding the display area.

[0095] Data lines can be placed in the display area and extend along the first direction, while multiple data lines are arranged sequentially along the second direction.

[0096] The fanout trace can be set in the non-display area, and the signal gating circuit 20 can be set in the edge area of ​​the non-display area near the display area.

[0097] This application also provides a display device; please refer to [link to relevant documentation]. Figure 8 The display device 1000 can be a PC, television, monitor, mobile terminal, tablet computer, or wearable device, etc. The display device 1000 may include driving signals and the display panel 100 provided in the above embodiments of this application.

[0098] The driver chip can be electrically connected to multiple fanout traces.

[0099] In the first data frame, the driver chip can provide at least two corresponding data signals to each fanout line within at least two source signal intervals h corresponding to each pixel row, so that the two data signals are written into the two pixel circuits 10 respectively.

[0100] This application also provides a control method for a display device, applied to the display device in the above embodiments. The method may include the following steps:

[0101] S110, in the two source signal intervals corresponding to each pixel row in the first data frame, provide two corresponding data signals to each fan-out trace respectively;

[0102] S120, during the first time period of the two source signal intervals corresponding to each pixel row, a first gating signal and a second gating signal are respectively provided to the signal gating circuit; wherein, the first gating signal and the second gating signal are respectively used to drive the two gating units in the signal gating circuit.

[0103] In this embodiment, by providing two data signals to the fan-out traces within the two source signal intervals corresponding to each pixel row, the fan-out traces can provide the two data signals to the two data signal lines respectively through the signal gating circuit during the first time period of the two source signal intervals. The pixel circuit in this pixel row can turn on the data writing transistor and other associated transistors when it receives a data write control signal, thereby writing the data signal to the gate of the driving transistor.

[0104] The specific implementation methods for each of the above steps are described below.

[0105] In S110, the display device can provide two corresponding data signals to each fan-out trace within the two source signal intervals corresponding to each pixel row in the first data frame.

[0106] Within the first source signal interval, a first data signal can be provided to each fan-out trace. Between two source signal intervals, the provided first data signal can be switched to a second data signal, and the second data signal can be continuously provided to each fan-out trace within the next source signal interval.

[0107] In S120, during the first time period of the two source signal intervals corresponding to each pixel row, the display device can provide a first gating signal and a second gating signal to all signal gating circuits respectively. The first gating signal and the second gating signal can be used to drive two gating units in the signal gating circuits respectively.

[0108] During the first time period of the previous source signal interval, the first gating signal can drive the first gating unit to turn on, so that the fan-out trace provides the first data signal to the first data signal line;

[0109] During the first time period of the second source signal interval, the second gating signal can drive the second gating unit to conduct, so that the fan-out trace provides the second data signal to the second data signal line.

[0110] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0111] It should be noted that, in this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0112] This document uses specific examples to illustrate the principles and implementation methods of this application. The examples are merely for the purpose of helping to understand the method and core ideas of this application. The above are only preferred embodiments of this application. It should be noted that due to the limitations of written expression, and the existence of an infinite number of specific structures, those skilled in the art can make several improvements, modifications, or changes without departing from the principles of this application, and can also combine the above technical features in an appropriate manner. These improvements, modifications, changes, or combinations, or the direct application of the concept and technical solution of this application to other situations without modification, should all be considered within the scope of protection of this application.

Claims

1. A display panel, characterized by, The display panel comprises: a plurality of data signal lines extending along a first direction, the plurality of data signal lines being arranged in sequence along a second direction; wherein the first direction intersects the second direction; a plurality of fan-out wires, the fan-out wires being configured to provide data signals corresponding to at least two data signal lines in each pixel row in a first data frame; a plurality of signal gating circuits, each signal gating circuit being electrically connected to one fan-out wire and at least two data signal lines; the signal gating circuit is configured to, in a first time period of the source signal interval, connect the fan-out wire to the corresponding data signal lines; wherein a length of the source signal interval is h, and a length of the first time period is t1, 0.5*h < t1 < h; the source signal interval further comprises a second time period, the second time period being before the first time period; in the second time period of each source signal interval, the signal gating circuit disconnects the fan-out wire from the corresponding data signal lines.

2. The display panel of claim 1, wherein, the source signal interval further comprises a third time period, the third time period being after the first time period; in the third time period of each source signal interval, the signal gating circuit disconnects the fan-out wire from the corresponding data signal lines.

3. The display panel of claim 2, wherein, a length of the second time period is t2, and a length of the third time period is t3; wherein t2 < t1, t3 < t1.

4. The display panel of claim 3, wherein, t2 > t3.

5. The display panel of claim 3, wherein t1 / h is 13 / 24-19 / 24, t2 / h is 1 / 12-1 / 3, t3 / h is 1 / 8.

6. The display panel of claim 5, wherein t1 / h is 3 / 4, t2 / h is 1 / 8, t3 / h is 1 / 8.

7. The display panel of claim 1, wherein, The signal gating circuit comprises: a plurality of gating units, a first end of each gating unit being electrically connected to a corresponding fan-out wire of the signal gating circuit, a second end of each gating unit being connected to a corresponding data signal line, and each gating unit being configured to be turned on in response to a gate signal.

8. The display panel of claim 7, wherein, The signal gating circuit is connected between one fan-out wire and four data signal lines; in the first time period of the two source signal intervals corresponding to the i-th pixel row in the first data frame, the signal gating circuit connects the fan-out wire to the first data signal line and the second data signal line, respectively; wherein i ≥ 1, i is a positive integer; in the first time period of the two source signal intervals corresponding to the i+1-th pixel row in the first data frame, the signal gating circuit connects the fan-out wire to the third data signal line and the fourth data signal line, respectively.

9. The display panel of claim 8, wherein, The display panel comprises first, second, and third sub-pixels having different light-emitting colors; in the i-th pixel row, the first data signal line is connected to a corresponding first sub-pixel, and the second data signal line is connected to a corresponding third sub-pixel; in the i+1-th pixel row, the third data signal line is connected to a corresponding second sub-pixel, and the fourth data signal line is connected to a corresponding third sub-pixel.

10. The display panel of claim 7, wherein, The signal gating circuit is connected between a fan-out wire and two data signal lines; In a first time period of two source signal intervals corresponding to an i-th pixel row in a first data frame, the signal gating circuit respectively connects the fan-out wire with the first data signal line and the second data signal line; wherein i≥1, i is a positive integer.

11. The display panel of claim 1, wherein, The display panel comprises a display area and a non-display area surrounding the display area; The data signal lines are arranged in the display area, and the data signal lines extend along a first direction, and the plurality of data signal lines are arranged along a second direction in sequence; The fan-out wire is arranged in the non-display area, and the signal gating circuit is arranged in an edge region of the non-display area close to the display area.

12. A display device comprising: The display panel comprises a display panel according to any one of claims 1-11 and a driving chip electrically connected with the plurality of fan-out wires. In a first data frame, the driving chip is configured to provide at least two data signals corresponding to each pixel row to each fan-out wire in at least two source signal intervals corresponding to each pixel row.

13. A control method of a display device, characterized by, The method is applied to the display device of claim 12, and the method comprises: In a first data frame, the driving chip is configured to provide at least two data signals corresponding to each pixel row to each fan-out wire in at least two source signal intervals corresponding to each pixel row. In a first time period of two source signal intervals corresponding to each pixel row, the signal gating circuit is respectively provided with a first gate signal and a second gate signal; wherein the first gate signal and the second gate signal are respectively used to drive two gating units in the signal gating circuit.

Images