Storage device array-oriented charge pump fast transient response compensation circuit and method

Abstract

The invention discloses a register array-oriented charge pump fast transient response compensation circuit and method, and belongs to the field of integrated circuits. Comprising a compensation signal generation circuit and a fast transient response compensation circuit array, and the compensation signal generation circuit calculates the number of needed fast transient response compensation circuits according to the number of WLLS circuits of the drive circuit array turned to the conducting state and generates compensation circuit opening control signals. And the fast transient response compensation circuit array starts a corresponding fast transient response compensation circuit according to the compensation circuit opening control signal to compensate the voltage fluctuation of the charge pump. The fast transient response compensation circuit is additionally arranged at the output end of the charge pump, so that the voltage fluctuation recovery time generated by switching is shortened. The fast transient response compensation circuit is composed of a switching tube and a capacitor, static power consumption is avoided, the structure is simple, and implementation is easy. And the number of the compensation circuits is dynamically adjusted according to the number of WLLS switching, so that the phenomenon of overshoot or undercompensation can be avoided.

Description

Technical Field

[0001] The invention relates to a charge pump fast transient response compensation circuit and method for a storage and computing device array, and belongs to the technical field of integrated circuits. Background Art

[0002] Traditional von Neumann architectures encounter a lot of power consumption and latency bottlenecks when processing data in neural network algorithms. These challenges severely limit the progress of energy efficiency and computing power. Storage and computing arrays are usually organized into two-dimensional arrays, where horizontal lines and vertical lines are usually called word lines (WL) and bit lines (BL), respectively. The control signal generation circuit and the drive circuit control the voltage of WL to turn on and off the devices in each row, and each column of devices accumulates current at the BL end. The device current is converted into a digital signal through the readout system to complete the matrix-vector multiplication operation.

[0003] In the storage-computing integrated architecture, there are three modes of device operation: programming, reading, and erasing, which output, read, and reset the device weights respectively. Matrix-vector multiplication operations mainly occur in the readout mode. For an n×m storage-computing device array, there is a need to switch the voltage of multiple rows of word lines in the readout mode. The driving circuit that controls the transmission of word line voltage is mainly composed of level shifters and switch tubes, and each word line needs to drive a pF-level capacitive load. The high voltage required for the storage-computing device array is generated by a charge pump. The output of the charge pump connects the switch tube of the driving circuit and the pF-level capacitive load at the WL end. When multiple switch tubes of the driving circuit switch from disconnection to conduction, the charge pump instantly charges the pF-level capacitive load at the WL end. At this time, the charge pump output will produce a voltage fluctuation toward the ground level, which is a voltage drop for the positive high-voltage charge pump and a voltage rise for the negative high voltage. Since the voltage fluctuation takes a certain amount of time to recover, this recovery time will greatly reduce the reading speed of the device current, thereby affecting the computing power of the storage-computing integrated chip.

[0004] In the existing technology, the method of improving the transient response of the charge pump for the storage and computing device array includes reducing the leakage current by improving the main circuit of the charge pump, thereby improving the driving capability of the charge pump and reducing the recovery time of the transient response, as reported in the document "A Low Ripple and Fast Transient Response Charge Pump in CMOS Image Sensors", but this method cannot achieve complete transient response compensation, and this method requires adding a two-phase clock to the main pump, which increases the complexity of the clock design; another technology compensates the main pump by adding a compensator, and the compensator is designed by controlling the capacitance value of the compensation capacitor through two current sources, as reported in the document "A Low-Ripple Charge PumpWith Novel Compensator for Transient-Response Improvement in CMOS Image Sensors", but this method will generate static power consumption. Summary of the invention

[0005] In order to solve the above problems, the present invention provides a charge pump fast transient response compensation circuit and method for a storage and computing device array, and the technical solution is as follows:

[0006] As one aspect of the present invention, a charge pump fast transient response compensation circuit for a storage and computing device array is provided, which is applied to a storage and computing device array working circuit. The storage and computing device array working circuit includes a charge pump, a storage and computing device array, a control signal generating circuit and a driving circuit array. The driving circuit array includes a plurality of WL_LS circuits. The charge pump is used to generate the high voltage required by the storage and computing device array. The storage and computing device array is used to store and read out weights to perform matrix-vector multiplication operations. The control signal generating circuit is used to generate a control signal IN. The control signal IN includes a turn-on control signal for turning on the WL_LS circuit in the driving circuit array and a turn-off control signal for turning off the WL_LS circuit in the driving circuit array. The driving circuit array is used to turn on the corresponding WL_LS circuit in response to the turn-on control signal to transmit the high voltage to the storage and computing devices of the corresponding row, and is used to turn off the corresponding WL_LS circuit in response to the turn-off control signal to disconnect the high voltage transmission path and transmit other voltages to the storage and computing devices of the corresponding row. The invention is characterized in that it includes: a compensation signal generating circuit and a fast transient response compensation circuit array. The fast transient response compensation circuit array includes a plurality of fast transient response compensation circuits.

[0007] The charge pump, the fast transient response compensation circuit array, the drive circuit array, the control signal generating circuit, and the compensation signal generating circuit are connected in sequence, the compensation signal generating circuit is connected to the fast transient response compensation circuit array, and the drive circuit array is connected to the storage and computing device array;

[0008] The compensation signal generating circuit is used to calculate the target number of fast transient response compensation circuits required according to the number of conduction control signals, and generate compensation control signals equal to the total number of fast transient response circuits, wherein the compensation control signals include compensation circuit turn-on control signals of the target number;

[0009] The fast transient response compensation circuit array is used to start corresponding fast transient response compensation circuits according to a target number of compensation circuit start control signals to compensate for the voltage fluctuation toward the ground level generated by the charge pump.

[0010] Furthermore, the fast transient response compensation circuit includes: a capacitor C1, a first PMOS transistor PM1 and a first NMOS transistor NM1; one end of the capacitor C1 is connected to the output CPOUT of the charge pump, the other end of the capacitor C1 is respectively connected to the drain end of the first PMOS transistor PM1 and the drain end of the first NMOS transistor NM1, the source end of the first NMOS transistor NM1 is grounded, the source end of the first PMOS transistor PM1 is connected to the power supply voltage VDD, and the gate of the first PMOS transistor PM1 and the gate of the first NMOS transistor NM1 are both connected to the output end corresponding to the phase flip module.

[0011] Further, the compensation signal generating circuit includes: a sparsity counter, a decoder and a phase flip module;

[0012] The sparsity counter, the decoder and the phase flip module are connected in sequence, the sparsity counter is connected to the control signal generating circuit, the phase flip module includes a plurality of output terminals, and the output terminals of the phase flip module are connected to the fast transient response compensation circuit in a one-to-one correspondence;

[0013] The sparseness counter is used to count the number of conduction control signals;

[0014] The decoder is used to calculate the parasitic capacitance C of the WL end of each row of storage and computing devices according to the number of conduction control signals, the number of rows of storage and computing devices array, and the par Calculate a target number of fast transient response compensation circuits required based on the capacitance value of and the capacitance value of capacitor C1, and generate intermediate signals equal to the total number of fast transient response circuits, including target number of compensation circuit turn-on intermediate signals;

[0015] The phase flip module is used to flip the phase of the intermediate signal and output a compensation control signal, which includes a target number of compensation circuit start control signals. The compensation control signal is a high level VDD or a low level 0V.

[0016] Furthermore, the target number of fast transient response compensation circuits required is calculated as:

[0017]

[0018] x=n*C par *η / C1

[0019] Where p is the target number of fast transient response compensation circuits required, n 1 represents the number of conduction control signals, n represents the number of rows of the storage device array, x represents the total number of fast transient response compensation circuits in the fast transient response compensation circuit array, C par Represents the parasitic capacitance C at the WL end of the storage device array par , η represents the correction coefficient, and C1 represents the capacitance value of capacitor C1.

[0020] Furthermore, the charge pump is a positive high voltage charge pump, the drive circuit array includes a plurality of positive high voltage WL_LS circuits, the positive high voltage WL_LS circuits include a positive voltage level shifter and a second PMOS transistor PM SW , the phase flip module includes a first inverter array, and the first inverter array includes a plurality of first inverters;

[0021] The input end of the positive voltage level shifter is connected to the control signal generating circuit to obtain the control signal IN, and the output end of the positive voltage level shifter is connected to the second PMOS transistor PM SW The gate of the second PMOS transistor PM SW The drain of the storage device array WL is connected to the parasitic capacitance C par , the second PMOS transistor PM SW The source of the first inverter is connected to the output terminal CPOUT1 of the positive high-voltage charge pump; the input terminal of each first inverter is connected to the decoder, and the output terminal of each first inverter is connected to the gate of the first PMOS transistor PM1 and the gate of the first NMOS transistor NM1 in the corresponding fast transient response compensation circuit.

[0022] Furthermore, the charge pump is a negative high voltage charge pump, the drive circuit array includes a plurality of negative high voltage WL_LS circuits, the negative high voltage WL_LS circuit includes a negative voltage level shifter and a second NMOS transistor NM SW The phase flip module includes a first inverter array and a second inverter array, the first inverter array includes a plurality of first inverters, and the second inverter array includes a plurality of second inverters;

[0023] The input end of the negative voltage level shifter is connected to the control signal generating circuit to obtain the control signal IN, and the output end of the negative voltage level shifter is connected to the second NMOS transistor NM SW The gate of the second NMOS transistor NM SW The drain of the storage device array WL is connected to the parasitic capacitance C par , the second NMOS transistor NM SWThe source of the first inverter is connected to the output terminal CPOUT2 of the negative high-voltage charge pump; the input terminal of each first inverter is connected to the decoder, the output terminal of each first inverter is correspondingly connected to the input terminal of a second inverter, and the output terminal of each second inverter is respectively connected to the gate of the first PMOS transistor PM1 and the gate of the first NMOS transistor NM1 in the corresponding fast transient response compensation circuit.

[0024] As another aspect of the present invention, a charge pump fast transient response compensation circuit method for a storage and computing device array is provided, which is applied to the charge pump fast transient response compensation circuit for the storage and computing device array, and comprises:

[0025] The target number of fast transient response compensation circuits required is calculated according to the number of conduction control signals by the compensation signal generating circuit, and the target number of compensation circuit turn-on control signals is generated;

[0026] A target number of fast transient response compensation circuits are started up through a fast transient response compensation circuit array according to a target number of compensation circuit start-up control signals to compensate for voltage fluctuations toward the ground level generated by a charge pump.

[0027] The beneficial effects of the present invention are:

[0028] The present invention shortens the voltage fluctuation recovery time caused by switch switching by adding a charge pump fast transient response compensation circuit at the output end of the charge pump. The fast transient response compensation circuit is mainly composed of a switch tube and a capacitor, has no static power consumption, and has a simpler structure and is easy to implement compared to other technologies. The present invention dynamically adjusts the number of compensation circuits according to the number of WL_LS circuit switches to avoid overshoot or undercompensation. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 This is a structural diagram of a traditional storage and computing device array;

[0031] Figure 2 It is a structural diagram of a storage and computing device array with a charge pump fast transient response compensation circuit provided by the present invention;

[0032] Figure 3 It is a structural diagram of a charge pump with a charge pump fast transient response compensation circuit for a storage and computing device array provided by the present invention;

[0033] Figure 4 It is a structural diagram of a positive high-voltage charge pump with a charge pump fast transient response compensation circuit for a storage and computing device array provided by the present invention;

[0034] Figure 5 It is a schematic diagram of a driving circuit for controlling a positive high voltage of a storage and computing device array WL provided by the present invention;

[0035] Figure 6 It is a schematic diagram of the phase relationship between the input signal of the fast transient response compensation circuit provided by the present invention and the input signal of the charge pump load driving circuit;

[0036] Figure 7 It is a comparison diagram of under-compensation simulation results before and after adding a fast transient response compensation circuit provided by the present invention;

[0037] Figure 8 It is a comparison diagram of over-compensation simulation results before and after adding a fast transient response compensation circuit provided by the present invention;

[0038] Fig. 9 It is a comparison diagram of the compensation simulation results before and after adding the fast transient response compensation circuit provided by the present invention;

[0039] Fig.10 It is a structural diagram of a negative high-voltage charge pump with a charge pump fast transient response compensation circuit for a storage and computing device array provided by the present invention;

[0040] Fig.11 It is a schematic diagram of a driving circuit for controlling the negative high voltage of the storage and computing device array WL. DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0042] Embodiment 1:

[0043] The embodiment of the present invention provides a charge pump fast transient response compensation circuit for a storage computing device array. The conventional storage computing device array structure and its working circuit are as follows: Figure 1 As shown in Figure 1, in order to achieve efficient parallel computing, multiple rows of WL_LS circuits need to be activated simultaneously to load multiple input feature vectors, and the control gate of the storage device needs to be frequently high-voltage V WLHV and other voltage switching.

[0044] like Figure 2 and Figure 3As shown, the charge pump fast transient response compensation circuit for the storage and computing device array is applied to the storage and computing device array working circuit, which includes a charge pump, a storage and computing device array, a control signal generating circuit, a driving circuit array and a readout system. The driving circuit array includes several WL_LS circuits. The charge pump is used to generate the high voltage V required by the storage and computing device array. WLHV The storage and computing device array is used to store and read out weights through a number of storage and computing devices to perform matrix-vector multiplication operations. The control signal generating circuit is used to generate a control signal IN. The control signal IN includes a turn-on control signal for turning on the WL_LS circuit in the drive circuit array and a turn-off control signal for turning off the WL_LS circuit in the drive circuit array. The drive circuit array is used to respond to the turn-on control signal to turn on the corresponding WL_LS circuit to transfer the high voltage V WLHV Transmitted to the storage computing device of the corresponding row, and used to disconnect the corresponding WL_LS in response to the disconnect control signal to disconnect the high voltage V WLHV The fast transient response compensation circuit of the charge pump facing the storage and computing device array includes a compensation signal generating circuit and a fast transient response compensation circuit array. The fast transient response compensation circuit array includes a plurality of fast transient response compensation circuits. The charge pump, the fast transient response compensation circuit array, the drive circuit array, the control signal generating circuit, and the compensation signal generating circuit are connected in sequence. The compensation signal generating circuit is connected to the fast transient response compensation circuit array, and the drive circuit array is connected to the storage and computing device array.

[0045] The load of the charge pump is the drive circuit array. The WL_LS circuit in the drive circuit array is the WL drive circuit, which is used to realize the voltage switching of the WL end of the storage device array. The output WL of the drive circuit array 1 , WL 2 ...WL n Connect the WL terminals of all storage and computing devices in the corresponding row in sequence. In different working modes of the storage and computing integrated chip, the control signal generation circuit controls multiple WL_LS circuits to flip, thereby controlling the opening and closing of each row of devices. <1> , IN <2> ,……,IN <n>Controlled by the control signal generating circuit, n is defined as the number of rows of the storage and computing device array, and the number of columns of the storage and computing device array is defined as m.

[0046] The fast transient response compensation circuit includes a capacitor C1, a first PMOS transistor PM1 and a first NMOS transistor NM1; one end of the capacitor C1 is connected to the output CPOUT of the charge pump, the other end of the capacitor C1 is respectively connected to the drain end of the first PMOS transistor PM1 and the drain end of the first NMOS transistor NM1, the source end of the first NMOS transistor NM1 is grounded, the source end of the first PMOS transistor PM1 is connected to the power supply voltage VDD, and the gate of the first PMOS transistor PM1 and the gate of the first NMOS transistor NM1 are both connected to an output end of the phase flip module.

[0047] The compensation signal generating circuit includes: a sparsity counter, a decoder and a phase flip module; the sparsity counter, the decoder and the phase flip module are connected in sequence, the sparsity counter is connected to the control signal generating circuit, the phase flip module includes a plurality of output terminals, and the output terminals of the phase flip module are connected to the fast transient response compensation circuit in a one-to-one correspondence;

[0048] The sparsity counter is used to count the number of WL_LS circuits flipped from off to on by the control signal generation circuit, that is, the number of on-control signals. The sparsity refers to the number of WL_LS circuits flipped from off to on as a percentage of the total number of WL_LS circuits.

[0049] The result of the sparsity counter is output to the decoder, which is used to calculate the parasitic capacitance C of the WL end of each row of storage and computing devices according to the number of conduction control signals, the number of rows of storage and computing devices array, and the par The target number of fast transient response compensation circuits required is calculated based on the capacitance value of and the capacitance value of capacitor C1, and x intermediate signals are generated, where x is defined as the total number of fast transient response compensation circuits in the fast transient response compensation circuit array, and the x intermediate signals should include a target number of compensation circuit start-up intermediate signals. The x intermediate signals are phase-flipped through a phase flip module and output as x compensation control signals, where the x compensation control signals include a target number of compensation circuit start-up control signals for starting the target number of fast transient response compensation circuits, and the remaining compensation control signals control the corresponding fast transient response compensation circuits not to be started.

[0050] Specifically, the total number x of fast transient response compensation circuits is indirectly related to the number m of columns of the memory device array, because the parasitic capacitance C at the WL end of each row of memory devices is par The product of the capacitance value of capacitor C1 in each compensation circuit and the number of compensation capacitors x and the parasitic capacitance C at the WL end of each row of storage devices par There is a relationship with the number of rows n of the storage device array, that is, x*C1=n*C par *η, where η represents the correction factor of the charge pump structure and performance indicators, and its value is related to VDD, CPOUT, the operating frequency of the charge pump and the feedback mechanism. Assume that when there are less than or equal to q WL_LS circuits flipped to the on state, there is 1 compensation control signal as the compensation circuit start control signal, and one fast transient response compensation circuit is turned on; when the number of WL_LS circuits flipped to the on state is between q and 2q, there are 2 compensation control signals as the compensation circuit start control signals, and two fast transient response compensation circuits are turned on, and so on. That is, the calculation method for the target number of fast transient response compensation circuits that need to be turned on is:

[0051]

[0052] Among them, n 1 Represents the number of conduction control signals, that is, the number of WL_LS circuits flipped to the conduction state.

[0053] The control signal generation circuit generates non-overlapping delays, determines the number of fast transient response compensation circuits turned on through a sparse counter and a decoder, and generates x intermediate signals INSW through a decoder. <1> 、INSW <2> ……INSW <x>, where the phase relationship between the intermediate signal INSW and the control signal IN is as Figure 6 shown.

[0054] The output CPOUT of the charge pump is connected to multiple fast transient response compensation circuits, and each transient response compensation circuit is controlled by compensation control signals SW1, SW2... SWx or LSW1, LSW2... LSWx. Specifically, when the charge pump is a positive high-voltage charge pump, the compensation control signals are SW1, SW2... SWx. Among the compensation control signals SW1, SW2... SWx, there are p compensation circuit turn-on control signals, and the compensation circuit turn-on control signals are at a low level of 0V, and the rest are at a high level of VDD; when the charge pump is a negative high-voltage charge pump, the compensation control signals are LSW1, LSW2,..., LSWx. Among the compensation control signals LSW1, LSW2,..., LSWx, there are p compensation circuit turn-on control signals, and the compensation circuit turn-on control signals are at a high level of VDD, and the rest are at a low level of 0V; that is, the compensation control signals of the fast transient response compensation circuits applicable to the positive voltage charge pump and the negative voltage charge pump are opposite.

[0055] The embodiment of the present invention analyzes the WL_LS circuit with a single flip to the on state. When the control signal IN<1> switches to a high level, the charge pump charges the parasitic capacitor C par , and CPOUT fluctuates. At this time, the control signal generation circuit generates non-overlapping delays. The number of fast transient response compensation circuits turned on is determined to be 1 through the sparsity counter and the decoder. The decoder generates x intermediate signals, and the intermediate signals include the compensation circuit turn-on intermediate signal INSW<1>. The compensation circuit turn-on intermediate signal INSW<1> generates the compensation circuit turn-on control signal SW1 or LSW1 through the phase inversion module. SW1 or LSW1 controls the first PMOS transistor PM1 and the first NMOS transistor NM1, so that the lower plate of the capacitor C1 flips. The upper plate of the capacitor C1 had a voltage drop or a voltage rise at the previous moment, and the lower plate of the capacitor C1 flips at the next moment to perform a voltage rise or a voltage drop, thereby reducing the recovery time caused by voltage fluctuations generated by multiple WL_LS switches at the same time.

[0056] The present invention shortens the voltage fluctuation drop recovery time generated by switch switching by adding a charge pump fast transient response compensation circuit at the output end of the charge pump. Among them, the fast transient response compensation circuit is mainly composed of a switching tube and a capacitor, and has no static power consumption. Compared with other technologies, the structure is simpler and easier to implement. And the present invention dynamically adjusts the number of compensation circuits according to the number of WL_LS circuit switches, which can avoid overshoot or under-compensation phenomena.

[0057] Embodiment 2:

[0058] For the memory - in - computing device array under positive high - voltage charge pump, such as Figure 4 shown, the switching between positive high - voltage and 0V is required in the readout mode and programming mode. The scale of the memory - in - computing device array is positively correlated with the parasitic capacitance C par of the WL and BL metal lines. When the switching transistors in the WL_LS circuit switch between positive high - voltage and 0V instantaneously, the positive high - voltage charge pump needs to charge the parasitic capacitance C par of the WL or BL metal line, and at this time, the positive high - voltage charge pump will generate a voltage drop.

[0059] Therefore, a charge - pump fast transient response compensation circuit for a memory - in - computing device array provided by an embodiment of the present invention is applied to the positive high - voltage charge pump of the memory - in - computing device array.

[0060] In this embodiment, the fast transient response compensation circuit includes a capacitor C1, a first PMOS transistor PM1, and a first NMOS transistor NM1; one end of the capacitor C1 is connected to the output CPOUT1 of the positive high - voltage charge pump, the other end of the capacitor C1 is respectively connected to the drain of the first PMOS transistor PM1 and the drain of the first NMOS transistor NM1, the source of the first NMOS transistor NM1 is grounded, and the source of the first PMOS transistor PM1 is connected to the power supply voltage VDD.

[0061] The driving - circuit array includes several positive high - voltage WL_LS circuits, such as Figure 5 shown, the positive high - voltage WL_LS circuit includes a positive voltage translator and a second PMOS transistor PM SW , the input end of the positive voltage translator is connected to the control - signal generation circuit to obtain a control signal IN, the control signal IN is a turn - on control signal or a turn - off control signal, the output end of the positive voltage translator is connected to the gate of the second PMOS transistor PM SW ; the drain of the second PMOS transistor PM SW is connected to the parasitic capacitance C par of the WL end of the memory - in - computing device array, and the source of the second PMOS transistor PM SW is connected to the output end CPOUT1 of the positive high - voltage charge pump.

[0062] The phase - flip module includes a first inverter array, and the first inverter array includes several first inverters; the input end of each first inverter is connected to the decoder, and the output end, i.e., the SW end, of each first inverter is connected to the gate of the first PMOS transistor PM1 and the gate of the first NMOS transistor NM1 in the corresponding fast transient response compensation circuit.

[0063] The output CPOUT1 of the positive high - voltage charge pump is connected to x fast transient response compensation circuits, and each transient response compensation circuit is respectively controlled by the compensation control signals SW1, SW2... SWx output by the first inverter array.

[0064] When the positive high - voltage WL_LS circuit for driving the WLs of the memory - in - computing device switches during the programming mode or the read - out mode, the number of fast transient response compensation circuits to be turned on is determined by the sparsity counter and the decoder, and the voltage drop generated by charging the parasitic capacitance C par is compensated. Designing the compensation circuit according to the capacitance value of the parasitic capacitance and determining the number of fast transient response compensation circuits to be turned on according to the sparsity of the positive high - voltage WL_LS circuit can achieve appropriate compensation for the charge pump, thereby reducing the switching delay of the required voltage input to the memory - in - computing device array.

[0065] For theoretical analysis of a single positive high - voltage WL_LS circuit, when the control signal IN<1> switches to a high level, the positive high - voltage charge pump charges the parasitic capacitance C SW through the second PMOS transistor PM par and a voltage drop is generated at CPOUT1. At this time, the control signal generation circuit generates non - overlapping delays. The number of fast transient response compensation circuits to be turned on is determined by the sparsity counter and the decoder to be 1. An intermediate signal is generated through the decoder. The intermediate signal includes the compensation - circuit - on intermediate signal INSW<1>. The compensation - circuit - on intermediate signal INSW<1> generates a compensation - circuit - on control signal SW1 through the first inverter. SW1 is at a low level of 0V. SW1 controls the first PMOS transistor PM1 and the first NMOS transistor NM1, so that the lower plate of the capacitor C1 changes from the low level of 0V to VDD. The upper plate of the capacitor C1 had a voltage drop at the previous moment, and the lower plate of the capacitor C1 flips at the next moment to raise the voltage, thereby reducing the recovery time caused by voltage fluctuations generated by simultaneous switching of multiple WL_LS circuits.

[0066] As Figure 7 shown, when the number of fast transient response compensation circuits is too small compared to the number of flips of the positive high - voltage WL_LS circuit, the recovery time of the positive high - voltage charge pump output CPOUT1 is shortened, but the voltage OUT input to the memory - in - computing device still takes a long time to reach the required voltage when switching to the high - level waveform. When the number of fast transient response compensation circuits is too large compared to the number of flips of the WL_LS circuit, over - compensation occurs. As Figure 8 shown, during the switching process, CPOUT1 and OUT transiently exceed the required voltage. In the embodiments of the present invention, the decoder calculates the target number of fast transient response compensation circuits required according to the number of conduction control signals, the number of rows of the memory - in - computing device array, the capacitance value of the parasitic capacitance C par at the WL end of each row of the memory - in - computing device array and the capacitance value of the capacitor C1, and based on this, an appropriate number of fast transient response compensation circuits are adopted, and the effect is as Fig. 9 As shown, the recovery time of CPOUT1 is greatly shortened, and the OUT switching to the high-level waveform can smoothly reach the required voltage, with a good compensation effect.

[0067] Embodiment 3:

[0068] For the memory and computing device array under the negative high-voltage charge pump, such as Fig.10 As shown, in the erase mode, it is necessary to switch the negative high voltage and 0V at the WL terminal of the memory and computing device. When the switching transistor switches between the negative high voltage and 0V, the charge pump needs to charge the parasitic capacitance C of the WL metal line par At this time, the charge pump will generate a voltage rise.

[0069] Therefore, the charge pump fast transient response compensation circuit provided by the embodiment of the present invention is applied to the negative voltage charge pump of the memory and computing device array.

[0070] In this embodiment, the fast transient response compensation circuit includes a capacitor C1, a first PMOS transistor PM1, and a first NMOS transistor NM1; one end of the capacitor C1 is connected to the output CPOUT2 of the negative high-voltage charge pump, and the other end of the capacitor C1 is respectively connected to the drain of the first PMOS transistor PM1 and the drain of the first NMOS transistor NM1. The source of the first NMOS transistor NM1 is grounded, and the source of the first PMOS transistor PM1 is connected to the power supply voltage VDD.

[0071] The phase inversion module includes a first inverter array and a second inverter array. The first inverter array includes several first inverters, and the second inverter array includes several second inverters; the input end of each first inverter is connected to the decoder, the output end of each first inverter is correspondingly connected to the input end of a second inverter, and the output end of each second inverter, that is, the LSW terminal, is respectively connected to the gates of the first PMOS transistor PM1 and the first NMOS transistor NM1 in the corresponding fast transient response compensation circuit.

[0072] The output CPOUT2 of the negative high-voltage charge pump is connected to x fast transient response compensation circuits, and each transient response compensation circuit is controlled by the compensation control signals LSW1, LSW2... LSWx output by the second inverter array.

[0073] Such as Fig.11 As shown, when the negative high voltage WL_LS circuit for driving the WLs of the memory and computing device switches in the erase mode, the number of opened fast transient response compensation circuits is determined by the sparsity counter and the decoder to compensate for the voltage drop generated by the charging of the NM SW switching to the parasitic capacitance C par According to the parasitic capacitance C par The compensation circuit is designed according to the capacitance value and the number of fast transient response compensation circuits turned on is determined according to the sparsity of the negative high voltage WL_LS circuit. Appropriate compensation for the negative high voltage charge pump can be achieved, thereby reducing the switching delay of the required voltage input to the array.

[0074] A theoretical analysis is conducted on a single negative high voltage WL_LS circuit. When the control signal IN <1> When switched to high level, the negative high voltage charge pump passes through the second NMOS transistor NM SW is the parasitic capacitance C par Discharge, CPOUT2 generates a voltage transient rise in the direction of the ground level. At this time, the control signal generation circuit generates a non-overlapping delay, and the number of compensation signal activations is determined to be 1 through the sparsity counter and decoder, and x intermediate signals are generated through the decoder. The intermediate signals include the compensation circuit activation intermediate signal INSW <1> , the compensation circuit turns on the intermediate signal INSW <1> The two-stage inverter is controlled to generate a compensation circuit start control signal LSW1, LSW1 is a high level VDD, LSW1 controls the first PMOS transistor PM1 and the first NMOS transistor NM1, so that the lower plate of the capacitor C1 changes from VDD to 0V, the upper plate of the capacitor C1 has a voltage rise at the previous moment, and the lower plate voltage of the capacitor C1 decreases at the next moment, thereby reducing the recovery time of the charge pump.

[0075] Embodiment 4:

[0076] An embodiment of the present invention provides a charge pump fast transient response compensation circuit method for a storage and computing device array, comprising:

[0077] The target number of fast transient response compensation circuits required is calculated according to the number of conduction control signals by the compensation signal generating circuit, and the target number of compensation control signals is generated;

[0078] A target number of fast transient response compensation circuits are started up through a fast transient response compensation circuit array according to a target number of compensation control signals to compensate for the voltage drop generated by the charge pump.

[0079] In the embodiment of the present invention, a sparseness counter is used to count the number of WL_LS circuits that are turned on by the control signal generation circuit, and the number of compensation circuit start control signals in the compensation control signals SW1, SW2, ..., SWx or the number of compensation circuit start control signals in the compensation control signals LSW1, LSW2, ..., LSWx is determined according to the number, so as to reduce the recovery time caused by the voltage drop caused by the simultaneous switching of multiple WL_LS circuits. Specifically, when the charge pump is a positive high-voltage charge pump, the compensation control signals are SW1, SW2 ... SWx, part of which are compensation circuit start control signals, the compensation circuit start control signals are low level 0V, and the rest are high level VDD; when the charge pump is a negative high-voltage charge pump, the compensation control signals are LSW1, LSW2 ... LSWx, part of which are compensation circuit start control signals, the compensation circuit start control signals are high level VDD, and the rest are low level 0V; the compensation control signals of the fast transient response compensation circuit applicable to the positive charge pump and the negative charge pump are opposite. Compared with the prior art, the voltage drop recovery time caused by switch switching is shortened by adding a compensation circuit at the output end of the charge pump. The compensation circuit is mainly composed of a switch tube and a capacitor, has no static power consumption, and has a simpler structure and is easier to implement than other technologies. The present invention dynamically adjusts the number of compensation circuits according to the number of WL_LS circuit switches, which can avoid overshoot.

[0080] The specific principles of a charge pump fast transient response compensation circuit method for a storage and computing device array provided in an embodiment of the present invention can be referred to the above description of the principles of a charge pump fast transient response compensation circuit for a storage and computing device array, and will not be repeated here.

[0081] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.

[0082] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.< / x> < / n>

Claims

1. A charge pump fast transient response compensation circuit for a storage and computing device array, applied to a storage and computing device array working circuit, wherein the storage and computing device array working circuit comprises a charge pump, a storage and computing device array, a control signal generating circuit and a driving circuit array, wherein the driving circuit array comprises a plurality of WL_LS circuits, wherein the charge pump is used to generate the high voltage required by the storage and computing device array, wherein the storage and computing device array is used to store and read out weights for matrix-vector multiplication operations, wherein the control signal generating circuit is used to generate a control signal IN, wherein the control signal IN comprises a turn-on control signal for turning on the WL_LS circuit in the driving circuit array and a turn-off control signal for turning off the WL_LS circuit in the driving circuit array, wherein the driving circuit array is used to turn on the corresponding WL_LS circuit in response to the turn-on control signal to transmit the high voltage to the storage and computing device in the corresponding row, and to turn off the corresponding WL_LS circuit in response to the turn-off control signal to disconnect the high voltage transmission path and transmit other voltages to the storage and computing device in the corresponding row, wherein: include: A compensation signal generating circuit and a fast transient response compensation circuit array, wherein the fast transient response compensation circuit array includes a plurality of fast transient response compensation circuits; The charge pump, the fast transient response compensation circuit array, the drive circuit array, the control signal generating circuit, and the compensation signal generating circuit are connected in sequence, the compensation signal generating circuit is connected to the fast transient response compensation circuit array, and the drive circuit array is connected to the storage and computing device array; The compensation signal generating circuit is used to calculate the target number of fast transient response compensation circuits required according to the number of the conduction control signals, and generate compensation control signals equal to the total number of fast transient response circuits, wherein the compensation control signals include the target number of compensation circuit turn-on control signals; The fast transient response compensation circuit array is used to start corresponding fast transient response compensation circuits according to a target number of compensation circuit start control signals to compensate for voltage fluctuations toward the ground level generated by a charge pump.

2. The charge pump fast transient response compensation circuit for storage and computing device array according to claim 1, characterized in that: The fast transient response compensation circuit includes: a capacitor C1, a first PMOS transistor PM1 and a first NMOS transistor NM1; one end of the capacitor C1 is connected to the output CPOUT of the charge pump, the other end of the capacitor C1 is respectively connected to the drain end of the first PMOS transistor PM1 and the drain end of the first NMOS transistor NM1, the source end of the first NMOS transistor NM1 is grounded, the source end of the first PMOS transistor PM1 is connected to the power supply voltage VDD, and the gate of the first PMOS transistor PM1 and the gate of the first NMOS transistor NM1 are both connected to the output end corresponding to the phase flip module.

3. The charge pump fast transient response compensation circuit for storage and computing device array according to claim 2, characterized in that: The compensation signal generating circuit comprises: a sparsity counter, a decoder and a phase flip module; The sparsity counter, the decoder and the phase flip module are connected in sequence, the sparsity counter is connected to the control signal generating circuit, the phase flip module includes a plurality of output terminals, and the output terminals of the phase flip module are connected to the fast transient response compensation circuit in a one-to-one correspondence; The sparsity counter is used to count the number of the conduction control signals; The decoder is used to determine the parasitic capacitance C of the WL end of each row of the storage computing device according to the number of the conduction control signals, the number of rows of the storage computing device array, and the par The target number of fast transient response compensation circuits required is calculated based on the capacitance value of and the capacitance value of the capacitor C1, and intermediate signals equal to the total number of fast transient response circuits are generated, including intermediate signals of the target number of compensation circuits turned on; The phase flip module is used to flip the phase of the intermediate signal and output a compensation control signal, which includes a target number of compensation circuit start-up control signals, and the compensation control signal is a high level VDD or a low level 0V.

4. The charge pump fast transient response compensation circuit for storage and computing device array according to claim 3, characterized in that: The target amount of fast transient response compensation circuitry required is calculated as: x=n*C par *η / C1 Wherein, p represents the target number of fast transient response compensation circuits required, n1 represents the number of conduction control signals, n represents the number of rows of the storage device array, x represents the total number of fast transient response compensation circuits in the fast transient response compensation circuit array, and C par Represents the parasitic capacitance C at the WL end of the storage device array par , η represents the correction coefficient, and C1 represents the capacitance value of capacitor C1.

5. The charge pump fast transient response compensation circuit for storage and computing device array according to claim 4, characterized in that: The charge pump is a positive high voltage charge pump, the drive circuit array includes a plurality of positive high voltage WL_LS circuits, the positive high voltage WL_LS circuits include a positive voltage level shifter and a second PMOS transistor PM SW , the phase flip module includes a first inverter array, and the first inverter array includes a plurality of first inverters; The input end of the positive voltage level shifter is connected to the control signal generating circuit to obtain the control signal IN, and the output end of the positive voltage level shifter is connected to the second PMOS transistor PM SW The gate of the second PMOS transistor PM SW The drain of the storage device array WL is connected to the parasitic capacitor C par , the second PMOS transistor PM SW The source of the first inverter is connected to the output terminal CPOUT1 of the positive high-voltage charge pump; the input terminal of each of the first inverters is connected to the decoder, and the output terminal of each of the first inverters is connected to the gate of the first PMOS transistor PM1 and the gate of the first NMOS transistor NM1 in the corresponding fast transient response compensation circuit.

6. The charge pump fast transient response compensation circuit for storage and computing device array according to claim 4, characterized in that: The charge pump is a negative high voltage charge pump, the drive circuit array includes a plurality of negative high voltage WL_LS circuits, the negative high voltage WL_LS circuits include a negative voltage level shifter and a second NMOS transistor NM SW , the phase flip module includes a first inverter array and a second inverter array, the first inverter array includes a plurality of first inverters, and the second inverter array includes a plurality of second inverters; The input end of the negative voltage level shifter is connected to the control signal generating circuit to obtain the control signal IN, and the output end of the negative voltage level shifter is connected to the second NMOS transistor NM SW The gate of the second NMOS transistor NM SW The drain of the storage device array WL is connected to the parasitic capacitor C par , the second NMOS transistor NM SW The source of the first inverter is connected to the output terminal CPOUT2 of the negative high-voltage charge pump; the input terminal of each of the first inverters is connected to the decoder, the output terminal of each of the first inverters is correspondingly connected to an input terminal of the second inverter, and the output terminal of each of the second inverters is respectively connected to the gate of the first PMOS transistor PM1 and the gate of the first NMOS transistor NM1 in the corresponding fast transient response compensation circuit.

7. A method for a charge pump fast transient response compensation circuit for a storage and computing device array, applied to a charge pump fast transient response compensation circuit for a storage and computing device array as claimed in any one of claims 1 to 6, characterized in that: include: The target number of fast transient response compensation circuits required is calculated according to the number of the conduction control signals by the compensation signal generating circuit, and the target number of compensation circuit turn-on control signals is generated; A target number of fast transient response compensation circuits are started up through the fast transient response compensation circuit array according to a target number of compensation circuit start-up control signals, so as to compensate for the voltage fluctuation toward the ground level generated by the charge pump.

Images