3D DRAM with vertical bit lines

Abstract

The invention relates to a dynamic random access memory (DRAM). In particular, the present disclosure proposes a 3D DRAM with vertical bit lines. The DRAM includes a block having a 3D array of memory cells. The block includes a plurality of planes stacked along a first axis. Each plane includes a 2D array of memory cells organized in rows extending along a second axis perpendicular to the first axis and columns extending along a third axis perpendicular to the first and second axes. The block is divided into a plurality of sub-blocks arranged along a second axis, each sub-block including a column of memory cells per plane. The DRAM also includes a plurality of bit lines, wherein each bit line extends along the first axis in one of the sub-blocks and is connected to one memory cell in each plane. The DRAM also has a plurality of global bit lines, wherein one or more global bit lines are connected to the bit lines in each sub-block. The DRAM also has a plurality of sense amplifiers, wherein each sense amplifier is connected to one of the global bit lines.

Description

Technical Field

[0001] The present disclosure relates to dynamic random access memory (DRAM). In particular, the present disclosure proposes a 3D DRAM, i.e., a DRAM having a 3D array of memory cells. The 3D DRAM of the present disclosure includes vertical bit lines. Background Art

[0002] Currently, there are difficulties in making DRAM smaller while increasing its storage capacity. In particular, DRAM scaling faces challenges in reducing the memory cell area, increasing the memory cell density, and achieving a higher aspect ratio in the vertical direction of the memory cells. There have been various approaches to create 3D DRAM to address these difficulties. However, most of these conventional approaches only focus on individual memory bit cells and their organization into a memory cell array, without considering the connection between the memory cells and core circuits such as sense amplifiers and word line drivers.

[0003] The first challenge comes from the size difference between a smaller bit line pitch (BLP) and a larger bit line sense amplifier (BLSA). For example, for advanced DRAM technology, the BLP is about 3.4F (44 nm), while the area of the BLSA is estimated to be 284F 2 (88 nm by 6.25 μm). For 2D DRAM, one BLSA can be located between two BLPs on both sides of an array block (MAT). In this setup, multiple BLSAs are arranged similarly to the bit lines in one direction (the x - direction or the y - direction). However, for 3D DRAM, the bit lines are arranged in two directions (the x - direction and the y - direction), which limits the placement and routing of the BLSA. This affects the performance and area efficiency of the 3D DRAM.

[0004] The second challenge comes from the number of BLSAs. For 2D DRAM, each bit line is connected to a BLSA, and all the memory cells on a word line work simultaneously through word line activation. In other words, there should be an equal number of BLSAs and bit lines in the MAT, which results in increased area consumption. Transferring this configuration (i.e., one bit line to one BLSA) to 3D DRAM is problematic because it brings issues related to the placement and connection of the BLSAs and also results in a larger area consumption. Summary of the Invention

[0005] Accordingly, an object of the present disclosure is to provide an improved 3D DRAM. Specifically, the object is to reduce the area consumption in view of the above problems. Another object is to reduce the parasitic bitline load in the 3D DRAM. Yet another object is to reduce the number of wordline drivers in the 3D DRAM. To this end, an object of the present disclosure is to provide a 3D DRAM memory cell array architecture, and a method of separately connecting the 3D DRAM memory cell array to sense amplifiers and wordline drivers. Thereby, the present disclosure aims to implement a one-transistor and one-capacitor (1T1C) memory cell configuration.

[0006] These and other objects are achieved by the solutions of the present disclosure described in the independent claims. Advantageous realizations of these embodiments are described in the dependent claims.

[0007] A first aspect provides a DRAM including: a block including a 3D array of memory cells; wherein the block includes a plurality of planes stacked along a first axis, each plane including a 2D array of memory cells organized in rows extending along a second axis perpendicular to the first axis and columns extending along a third axis perpendicular to the first and second axes; and wherein the block is divided into a plurality of sub-blocks arranged along the second axis, each sub-block including a column of memory cells of each plane; the DRAM further includes: a plurality of bitlines, wherein each bitline extends along the first axis in one of the sub-blocks and is connected to a memory cell in each plane; a plurality of global bitlines, wherein one or more of the global bitlines are connected to the bitlines in each sub-block; and a plurality of sense amplifiers, wherein each sense amplifier is connected to one of the global bitlines.

[0008] A DRAM having a 3D array of its memory cells is a 3D DRAM. The 3D DRAM can be block-addressable and even sub-block-addressable. This can be beneficial for its performance, durability, and energy efficiency, and can also increase the storage density.

[0009] The DRAM of the first aspect includes so-called vertical bitlines because they extend along the first axis, which is considered the vertical axis in the present disclosure. The connection of the vertical bitlines to the global bitlines reduces the area consumption due to the more relaxed placement and routing of the sense amplifiers. In addition, the parasitic bitline load can be reduced in the 3D DRAM of the first aspect.

[0010] In one implementation, each global bitline extends along the third axis, is associated with a corresponding sub-block, and is connected to all the bitlines in the corresponding sub-block.

[0011] In one implementation, each global bitline extends along the third axis, and each sub-block is associated with a corresponding set of global bitlines, and each global bitline in the corresponding set is connected to a corresponding set of bitlines in the sub-block.

[0012] In one implementation, each group of bit lines includes bit lines arranged sequentially along a third axis.

[0013] In one implementation, each group of bit lines includes bit lines arranged staggeredly along a third axis.

[0014] In one implementation, the DRAM further includes a plurality of word lines, where each word line extends along a second axis in one of the planes and is connected to a memory cell in each sub-block.

[0015] In one implementation, each global bit line extends along the second axis and is connected to a bit line in each sub-block of the block.

[0016] In one implementation, each global bit line extends along the second axis, where each global bit line is connected to a bit line in each sub-block of a group of sub-blocks associated with the global bit line, and where different global bit lines are associated with different groups of sub-blocks.

[0017] In one implementation, each group of sub-blocks includes sub-blocks arranged sequentially along the second axis.

[0018] In one implementation, each group of sub-blocks includes sub-blocks arranged staggeredly along the second axis.

[0019] In one implementation, the DRAM further includes a plurality of word lines, where each word line extends along the third axis in one of the planes and is connected to a column of memory cells in the plane.

[0020] In one implementation, the DRAM further includes: a single word line driver shared among all word lines; or a plurality of word line drivers, where each word line driver is shared among all word lines in the same plane.

[0021] In this way, the number of word line drivers can be reduced. This can also result in a reduction in the area consumed by the word line drivers.

[0022] In one implementation, the DRAM further includes: one or more word line selectors configured to selectively connect one or more word line drivers to word lines; where each word line selector includes a plurality of global word lines, and each global word line is connected to a group of word lines.

[0023] In one implementation, if each group of bit lines includes bit lines arranged staggeredly along the third axis, then each group of word lines includes word lines arranged sequentially along the third axis; or, if each group of bit lines includes bit lines arranged sequentially along the third axis, then each group of word lines includes word lines arranged staggeredly along the third axis.

[0024] In one implementation, if each group of bit lines includes bit lines arranged alternately along the second axis, then each group of word lines includes word lines arranged sequentially along the second axis; or if each group of bit lines includes bit lines arranged sequentially along the second axis, then each group of word lines includes word lines arranged alternately along the second axis.

[0025] In one implementation, the DRAM further includes: a single word line selector shared among all word lines; or multiple word line selectors, where each word line selector is shared among all word lines in the same plane; one or more of the word line selectors are configured to selectively connect the output of an address decoder to multiple word line drivers; and multiple word line drivers are connected to multiple word lines.

[0026] In this way, the number of word line selectors can be reduced. This can also result in a reduction in the area consumed by the word line selectors. In this implementation, one or more word line selectors are arranged and connected between the address decoder and the word line drivers. The address decoder can act as a first decoder, and one or more word line selectors can act as a second decoder. The address decoder can be the address decoder used in a conventional DRAM. The address decoder can be a circuit for interpreting a memory address received from, for example, a central processing unit (CPU) to select a location in the memory array to read or write data. For example, the word line driver can be an inverter.

[0027] In summary, the present disclosure focuses on a 3D DRAM architecture based on vertical bit lines (i.e., bit lines extending along the first axis). The present disclosure relates to the core architecture of a memory cell array, but also considers the connection between the bit lines and the sense amplifiers, as well as the connection between the word lines and the word line drivers. The proposed configuration allows for a reduction in the number of sense amplifiers and word line drivers, and thus a reduction in the area consumed. In addition, the parasitic load, especially the parasitic load on the bit lines, can be minimized. Furthermore, the number of planes of the 3D DRAM can be increased while minimizing the impact on the parasitic load and area consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above aspects and implementations are explained in the following detailed description with reference to the accompanying drawings:

[0029] Figure 1 A perspective view and a top view of a DRAM with vertical bit lines according to the present disclosure are shown.

[0030] Figure 2 A perspective view of a first example of a DRAM according to the present disclosure is shown.

[0031] Figure 3 A perspective view of a second example of a DRAM according to the present disclosure is shown.

[0032] Figure 4 A top view of a DRAM showing the first example or the second example is presented.

[0033] Figure 5 A perspective view of a DRAM showing the third example according to the present disclosure is presented.

[0034] Figure 6 A top view of a DRAM showing the third example is presented.

[0035] Figure 7 A perspective view of a DRAM showing the fourth example according to the present disclosure is presented.

[0036] Figure 8 A top view of a DRAM showing the fourth example is presented.

[0037] Figure 9 A perspective view of a DRAM showing the fifth example according to the present disclosure is presented.

[0038] Figure 10 A perspective view of a DRAM showing the sixth example according to the present disclosure is presented.

[0039] Figure 11 A top view of a DRAM showing the fifth example, the sixth example, or the seventh example is presented.

[0040] Figure 12 A perspective view of a DRAM showing the eighth example according to the present disclosure is presented.

[0041] Figure 13 A top view of a DRAM showing the eighth example is presented.

[0042] Figure 14 A perspective view of a DRAM showing the ninth example according to the present disclosure is presented.

[0043] Figure 15 A top view of a DRAM showing the ninth example is presented. Detailed Description

[0044] Figure 1 A DRAM 10 according to the present disclosure is shown. Specifically, Figure 1 in (a), a perspective view of the DRAM 10 is shown, while Figure 1The top view of the DRAM 10 is shown in (b). The DRAM 10 is a 3D DRAM because it includes a block 11 that contains a 3D array of memory cells 13. The DRAM 10 may include more than one such block 11, i.e., it may be arranged by multiple blocks 11, and these blocks can be addressed individually. Each memory cell 13 may include a storage capacitor for storing data in the form of charge, and a transistor connected to the storage capacitor and configured to enable writing data to or reading data from the storage capacitor. Each memory cell 13 may be capable of storing one bit of data (information). The memory cells 13 in the 3D DRAM 10 may be arranged in rows, columns, and stacks.

[0045] Specifically, as Figure 1 shown in (b), the block 11 includes a plurality of planes 12 that are stacked along a first axis (the vertical axis in the present disclosure, which is the z-axis according to the coordinate system shown in the drawings). Each plane 12 includes a 2D array of memory cells 13, and the memory cells 13 are organized in rows extending along a second axis perpendicular to the first axis (the second axis is the x-axis in the coordinate system) and columns extending along a third axis perpendicular to the first axis and the second axis (the third axis is the y-axis in the coordinate system). Therefore, the stacked planes 13 include columns, rows, and stacks of memory cells 13, where the stack of memory cells 13 includes memory cells 13 arranged along the first axis.

[0046] As Figure 1 further schematically shown in (a) and (b), the block 11 is divided into a plurality of sub-blocks 14 arranged along the second axis. Each sub-block 14 contains a column of memory cells 13 of each plane 12. The consecutive arrangement of the sub-blocks 14 defines a row of memory cells 13 along the second axis. In the DRAM 10, each sub-block 14 can be addressed individually.

[0047] The DRAM 10 also includes a plurality of bit lines 15. Each bit line 15 extends along the first axis in one of the sub-blocks 14. Therefore, in the present disclosure, the bit line 15 is referred to as a vertical bit line. Each bit line 15 is connected to a memory cell 13 in each plane 12. In other words, each bit line 15 is connected to a stack of memory cells 13.

[0048] In addition, the DRAM 10 includes a plurality of global bit lines 16. One or more of the global bit lines 16 are connected to the bit lines 15 in each sub-block 14. Only as an example, Figure 1 the illustration in shows one global bit line 16 for each sub-block 14, where the global bit line 16 is connected to all the shown bit lines 15 of the sub-block 14. However, it is also possible to use two or more global bit lines 16 to connect to the bit lines 15 of the corresponding sub-block 14.

[0049] AsFigure 1 As shown in (a), DRAM 10 further includes a plurality of sense amplifiers 17. Each sense amplifier 17 is connected to one of the global bit lines 16 and is configured to sense (detect) the charge on the global bit line. Indirectly, each sense amplifier 17 can thus be connected to a plurality of bit lines 15 through the global bit line 16 and can thus be capable of detecting the charge from at least one bit line 15 on the global bit line 16. In DRAM 10, it is possible to read the charge of a single memory cell 13 of each sub-block 14 using the bit lines 15, the global bit lines 16, and the sense amplifiers 17.

[0050] Hereinafter, more specific examples of DRAM 10 according to the present disclosure are given. All of these examples are based on Figure 1 the DRAM 10 shown. Figure 1 The same elements as those in any of the previous figures share the same reference numerals and can be implemented and / or function similarly. Redundant descriptions are avoided.

[0051] Figure 2 A perspective view showing a first example of DRAM 10 according to the present disclosure is shown. In Figure 2 the DRAM 10 of, the block 11 is called "MAT", and the plurality of sub-blocks 14 are respectively called "sub-MAT" or simply "SM" for short. The sub-blocks 14 are numbered from SM0 to SM31. Thus, in this example, each block 11 is composed of 32 sub-blocks 14. In addition, each sub-block 14 includes 32 vertical bit lines 15, which are called and numbered as SBL0 to SBL31 according to the sub-block 14.

[0052] In this example, in order to improve the connection between the bit lines 15 and the sense amplifiers 17 (such as BLSA), while taking into account the smaller BLP, all the bit lines 15 in each sub-block 14 are connected to a single global bit line 16. In this example, each global bit line 16 extends along the third axis and is associated with a corresponding sub-block 14 among the plurality of sub-blocks 14. Each global bit line 16 is connected to all the bit lines 15 in the corresponding sub-block 14. The global bit lines 16 are called and numbered as GBL0 to GBL31, and in this example, they correspond to SM0 to SM31. Each global bit line 16 is connected to a sense amplifier 17 ( Figure 2 not shown in, but can be seen in Figure 1 )

[0053] Figure 2It is also shown that the DRAM 10 includes a plurality of word lines 21. Each word line 21 extends along a second axis in one of the stacked planes 12. Thus, each word line 21 is connected to a memory cell 13 in each of the plurality of sub-blocks 14. If the word line 21 is active (charged), the memory cell 13 connected to the word line 21 can be activated. For example, a transistor connected to the storage capacitor of the memory cell 13 can be turned on to allow charge to be written to or read from the storage capacitor. Reading and writing can be performed via a bit line 15 connected to the memory cell 13. In this example, there are a total of 32 word lines 21 for each of the 32 planes. The word lines 21 are named and numbered as SWL<0> to SWL<31>, where <#> represents a specific plane numbered # among the 32 planes.

[0054] Figure 2 It is also shown that in addition to the 3D memory cell array, the 3D DRAM 10 also has a plurality of word line drivers 22 (only two "WD" are shown) and a plurality of word line selectors (only two "WLS" are shown). The word line drivers 22 are located on the right (or left) side of the array, that is, they are offset along the second axis from the memory cell array formed by the sub-blocks 14. Thus, as described above, each word line 21 is common to all sub-blocks 14. Each word line driver 22 is shared among all the word lines 21 in the same plane 12. Thus, in this example, there can be 32 word line drivers 22. However, the plurality of planes 12 can also share the word line drivers 22, which can further reduce the number of word line drivers. The word line selector 23 is configured to selectively connect the word line driver 22 to the word line 21. The word line selector 23 allows one word line 21 to be selected from all the word lines 21 in the plane 12. Since only one word line 21 is activated at a time in the block 11, the word line driver 22 can be shared among the plurality of word lines 21.

[0055] Figure 3 A perspective view of a second example of the DRAM 10 according to the present disclosure is shown. Figure 3 The DRAM 10 is very similar to Figure 2 the DRAM 10. Compared with Figure 2 the Figure 3 DRAM 10 includes a single word line driver 22 shared among all the word lines 21. In addition, it includes a single word line selector 23 configured to selectively connect the word line driver 22 to the word line 21. In other words, while in Figure 2 the word line driver 22 is shared by the planes 12 or at the stack level, in Figure 3 the word line driver 22 is shared at the block level. In Figure 3Among them, the word lines 21 are named and numbered as SWL0<0> to SWL31<0> to SWL0<31> to SWL31<31>, where <#> represents the specific plane numbered # among 32 planes, and each plane has 31 word lines 21.

[0056] Figure 4 A top view of the DRAM 10 of the first example or the second example is shown. Specifically, Figure 4 Only one plane 12 among the multiple planes 12 of the DRAM 10 is shown. Figure 4 It shows how the bit lines 15 are connected to the memory cells 13 of the 2D array of this plane 12 on the one hand and to the global bit lines 16 on the other hand. Figure 4 It also shows how the bit lines 21 are connected to the memory cells 13 of the 2D array of this plane 12 on the one hand and to the word line selector 23 on the other hand.

[0057] Figure 4 The shown word line selector 23 is connected to all the word lines 21 of the shown plane 12. Specifically, the word line selector 23 is shown as being connected to all the word lines SWL0<31> to SWL31<31> of the shown plane <31>.

[0058] Figure 3 and Figure 4 The word line drivers 22 in and can be connected to the address decoder of the DRAM 10, that is, they can be arranged and connected between one or more word line selectors 23 and the address decoder. This configuration can also be swapped, that is, one or more word line selectors 23 can be arranged and connected between the address decoder and the multiple word line drivers 22, where the word line drivers 22 are connected to the word lines 21.

[0059] Figure 5 A perspective view of a third example of the DRAM 10 according to the present disclosure is shown. Figure 6 A top view of the DRAM 10 of the third example is shown. In this third example, each global bit line 16 extends along the third axis, as in Figure 2 and Figure 3 However, each sub-block 14 is associated with a corresponding group of global bit lines 16 (for example, GBL(0:3), GBL(4:7), etc.). Each global bit line 16 in the corresponding group is connected to a corresponding group of bit lines 15 in the sub-block 14, as can be seen in Figure 6 and

[0060] In the third example, each group of bit lines 15 includes bit lines 15 arranged sequentially along the third axis. For example, as in Figure 6As shown, in SM0, GBL0 is connected to SBL0, SBL1, SBL6, and SBL7 that are arranged continuously along the third axis. GBL3 is connected to SBL24, SBL25, SBL30, and SBL31 that are also arranged continuously along the third axis.

[0061] As Figure 6 shown, each global word line 41 of each word line selector 23 is connected to a group of word lines 21. In this case, each group of word lines 21 includes word lines 21 that are arranged alternately along the third axis. For example, in the shown plane <31>, GWL0 is connected to SWL0<31> and SWL28<31>, while GWL1 is connected to SWL1<31> and SWL29<31>, GWL2 is connected to SWL2<31> and SWL30<31>, and GWL3 is connected to SWL3<31> and SWL31<31>.

[0062] Figure 5 and Figure 6 correspondingly shows a 3D DRAM memory architecture, where Figure 3 the global bit lines 16 are divided into multiple (specifically four in this case) global bit lines 16 per sub-block 14. This can increase the number of data queues and can reduce the parasitic load on the global bit lines 16. In this case, the connection between the bit lines 15 and the global bit lines 16 is sequential. In the case of sequential connection, consecutive bit lines 15 are connected to the same global bit line 16.

[0063] The connection between the word lines 21 and the word line selector 23 can follow the same arrangement, i.e., sequential or alternate. This third example includes a sequential bit line and an alternate word line arrangement.

[0064] Figure 7 Shows a perspective view of a fourth example of the DRAM 10 according to the present disclosure. Figure 8 Shows a top view of the DRAM 10 of the fourth example. In this fourth example, each global bit line 16 extends along the third axis, as Figure 2 and Figure 3 in. However, each sub-block 14 is associated with a corresponding group of global bit lines 16, as Figure 5 in. Each global bit line 16 in the corresponding group is connected to a corresponding group of bit lines 15 in the sub-block 14, as Figure 8 shown.

[0065] In the fourth example, each group of bit lines 15 includes bit lines 15 that are arranged alternately along the third axis. For example, as Figure 8As shown, in SM0, GBL0 is connected to SBL0 and SBL24, while GBL1 is connected to SBL1 and SBL25, GBL2 is connected to SBL6 and SBL30, and GBL3 is connected to SBL7 and SBL31. Therefore, the corresponding bit lines 15 are not arranged continuously along the third axis, but an interleaved connection is established.

[0066] As Figure 8 shown, each global word line 41 of each word line selector 23 is connected to a group of word lines 21. In this case, each group of word lines 21 includes word lines 21 arranged sequentially along the third axis. For example, GWL0 is connected to SWL0<31>, SWL1<31>, SWL6<31> and SWL7<31>, while GWL3 is connected to SWL24<31>, SWL25<31>, SWL30<31> and SWL31<31> of the shown plane <31>.

[0067] In other words, in this fourth example, there is an interleaved connection between the bit lines 15 and the global bit lines 16. In other words, for the same global bit line 16, the bit lines 15 can be mixed. In addition, the word lines 21 are connected to the global word lines 41 in an interleaved manner. This example thus includes an interleaved bit line and a sequential word line arrangement.

[0068] Figure 9 A perspective view of a fifth example of the DRAM 10 according to the present disclosure is shown. In the fifth example, a plurality of global bit lines 16 are connected to the bit lines 15 in each sub-block 14. Each global bit line 16 extends along the second axis and is connected to one of the bit lines 15 in each sub-block 14 of the block 11.

[0069] Also as Figure 9 shown, the DRAM 10 includes a plurality of word lines 21, where in the fifth example, each word line 21 extends along the third axis in one of the planes 12 and is connected to a column of memory cells 13 in that plane 12. Therefore, each sub-block 14 includes a plurality of word lines 21, one word line in each plane 12. Thus, as shown, each sub-block 14 can include 32 word lines 21. In addition, Figure 9 the DRAM 10 includes a plurality of word line drivers 22, where each word line driver 23 is shared among all the word lines 21 in the same plane 12. The DRAM 10 further includes a plurality of word line selectors 23 configured to selectively connect the word line drivers 22 to the word lines 21.

[0070] In Figure 9 this case, the word line drivers 22 are located in front of or behind the memory cell array, that is, offset from the sub-block 14 along the third axis. In addition, each global bit line 16 is thus parallel to the plurality of sub-blocks 14 extending along the second axis.

[0071] Figure 10 FIG. 2 shows a perspective view of a sixth example of DRAM 10 according to the present disclosure. The DRAM 10 of the sixth example is very similar to the DRAM of the fifth example. However, as shown, Figure 3 as shown, Figure 10 the DRAM 10 only includes a single word line driver 22 and a single word line selector 23. Thus, the placement of the word line driver can be according to the block 11 of the DRAM 10.

[0072] Figure 11 FIG. 3 shows a top view of the DRAM 10 of the fifth, sixth, or seventh example. As can be seen, each global bit line 16 extends along the second axis and is connected to one of the bit lines 15 in each sub-block 14 of the block 11. In addition, each global bit line 16 is connected to a sense amplifier 17 (BLSA0<31> to BLSA0 to BLSA31).

[0073] The word line selector 23 is connected to all the word lines 21 of the shown plane 12. Specifically, the word line selector 23 is connected to SWL0<31> to SWL31<31> in the shown plane <31>, where there is one of these SWLs in each of the 31 sub-blocks 14.

[0074] Figure 12 FIG. 4 shows a perspective view of an eighth example of DRAM 10 according to the present disclosure. Figure 13 FIG. 5 shows a top view of the DRAM 10 of the eighth example. In the eighth example, each global bit line 16 extends along the second axis. In addition, each global bit line 16 is connected to one of the bit lines 15 in each sub-block 14 of a group of sub-blocks 14, where the sub-blocks 14 are associated with the global bit line 16. This is in contrast to the fifth, sixth, or seventh examples, where each global bit line 16 is connected to one of the bit lines 15 in each sub-block 14 within the entire block 11. Different global bit lines 16 in the eighth example are associated with different groups of sub-blocks 14.

[0075] As can be seen in Figure 13 each group of sub-blocks 14 includes sub-blocks 14 arranged sequentially along the second axis. For example, GBL0 is connected to sub-blocks SM0 to SM3, while GBL3 is connected to SM28 to SM31. In addition, each global bit line 16 is connected to a group of bit lines 15 that includes bit lines 15 arranged sequentially along the second axis. For example, GBL0 is connected to SBL0 to SBL3, while GBL3 is connected to SBL28 to SBL31.

[0076] In addition, in the eighth example, each word line selector 23 includes a plurality of global word lines 41, and each global word line 41 is connected to a group of word lines 21. For example, in Figure 13In this case, GWL0 is connected to SWL0 and SWL24, and GWL1 is connected to SWL1 and SWL25, GWL6 is connected to SWL6 and SWL30, and GWL7 is connected to SWF 7 and SWL31. In other words, each group of word lines 21 includes word lines 21 arranged staggeredly along the second axis.

[0077] Figure 14 A perspective view of a ninth example of the DRAM 10 according to the present disclosure is shown. Figure 15 A top view of the DRAM 10 of the ninth example is shown. The ninth example is very similar to the eighth example. However, as can be seen in Figure 15 each group of sub-blocks 14 includes sub-blocks 14 arranged staggeredly along the second axis. For example, GBL0 is associated with SM0 and SM28, and GBL1 is associated with SM1 and SM29, and so on. In addition, each global bit line 16 is connected to a group of bit lines 15, and the group of bit lines includes bit lines 15 arranged staggeredly along the second axis. For example, GBL0 is connected to SBL0 and SBL28, and GBL1 is connected to SBL1 and SBL29, and so on.

[0078] In addition, in the eighth example, each word line selector 23 includes a plurality of global word lines 41, and each global word line 41 is connected to a group of word lines 21. For example, in Figure 15 GWL0 is connected to SWL0, SWL1, SWL6, and SWL7, and GWL3 is connected to SWL24, SWL25, SWL30, and SWL31. In other words, each group of word lines 21 includes word lines 21 arranged sequentially along the second axis.

[0079] Generally speaking, the present disclosure addresses the challenges faced by DRAM scaling in terms of memory bit cell area, memory density, and vertical aspect ratio. The present disclosure provides a 3D DRAM 10 designed by considering the connections between memory cells 13 and core circuits such as sense amplifiers 17, word line drivers 22, word line selectors 22, and bit line selectors 170. The present disclosure provides a solution based on a 1T1C 3D DRAM memory cell core, and specifically introduces a method of configuring a 3D DRAM memory cell array and its connection with sense amplifiers 17 and word line drivers 22. Therefore, less area consumption, smaller parasitic bit line load, and fewer word line drivers 22 can be achieved in the DRAM 10.

[0080] In the claims as well as in the description of the present disclosure, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. A single element may perform the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A dynamic random access memory DRAM (10), comprising: A block (11) comprising a 3D array of memory cells (13); wherein the block (11) comprises a plurality of planes (12) stacked along a first axis, each plane (12) comprising a 2D array of memory cells (13) organized in rows extending along a second axis perpendicular to the first axis and in columns extending along a third axis perpendicular to the first axis and the second axis; as well as wherein the block (11) is divided into a plurality of sub-blocks (14) arranged along the second axis, each sub-block (14) comprising a column of memory cells (13) in each plane (12); The DRAM (10) further includes: a plurality of bit lines (15), wherein each bit line (15) extends along the first axis in one of the sub-blocks (14) and is connected to one memory cell (13) in each plane (12); a plurality of global bit lines (16), wherein one or more of the global bit lines (16) are connected to the bit lines (15) in each sub-block (14); and A plurality of sense amplifiers (17), wherein each sense amplifier is connected to one of the global bit lines (16).

2. The DRAM (10) according to claim 1, characterized in that Each global bit line (16) extends along the third axis and is associated with a corresponding sub-block (14), and is connected to all bit lines (15) in the corresponding sub-block (14).

3. The DRAM (10) according to claim 1, characterized in that Each global bit line (16) extends along the third axis, and each sub-block (14) is associated with a respective set of global bit lines (16), and each global bit line (16) in a respective set is connected to a respective set of bit lines (15) in the sub-block (14).

4. The DRAM (10) according to claim 3, characterized in that Each group of bit lines (15) includes bit lines (15) arranged sequentially along the third axis.

5. The DRAM (10) according to claim 3, characterized in that Each group of bit lines (15) includes bit lines (15) arranged in a staggered manner along the third axis.

6. The DRAM (10) according to claim 2, characterized in that Also includes: A plurality of word lines (21), wherein each word line (21) extends along the second axis in one of the planes (12) and is connected to one memory cell (13) in each sub-block (14).

7. The DRAM (10) according to claim 1, characterized in that Each global bit line (16) extends along the second axis and is connected to a bit line (15) in each sub-block (14) of the block (11).

8. The DRAM (10) according to claim 1, characterized in that Each global bit line (16) extends along the second axis, wherein each global bit line (16) is connected to a bit line (15) in each sub-block (14) in a group of sub-blocks (14) associated with the global bit line (16), and wherein different global bit lines (16) are associated with different groups of sub-blocks (14).

9. The DRAM (10) according to claim 8, characterized in that Each group of sub-blocks (14) comprises sub-blocks (14) arranged sequentially along the second axis.

10. The DRAM (10) according to claim 8, characterized in that Each group of sub-blocks (14) comprises sub-blocks (14) arranged in a staggered manner along the second axis.

11. The DRAM (10) according to claim 7, characterized in that Also includes: A plurality of word lines (21), wherein each word line (21) extends along the third axis in one of the planes (12) and is connected to a column of memory cells (13) in the plane (12).

12. The DRAM (10) according to claim 6 or 11, characterized in that: Also includes: a single word line driver (22) shared between all word lines (21); or A plurality of word line drivers (22), wherein each word line driver (22) is shared among all word lines (21) in the same plane (12).

13. The DRAM (10) according to claim 12, characterized in that Also includes: one or more word line selectors (23) configured to selectively connect the one or more word line drivers (22) to the word line (21); Each word line selector (23) includes a plurality of global word lines (41), and each global word line (41) is connected to a group of word lines (21).

14. The DRAM (10) according to claim 6 or 11, characterized in that: Also includes: a single word line selector (23) shared between all word lines (21); or A plurality of word line selectors (23), wherein each word line selector (23) is shared between all word lines (21) in the same plane (12); wherein the one or more word line selectors (23) are configured to selectively connect the output of the address decoder to the plurality of word line drivers (22); and The plurality of word line drivers (22) are connected to the plurality of word lines (21).

15. The DRAM (10) according to claim 14 and claim 6, characterized in that: If each group of bit lines (15) includes bit lines (15) arranged in a staggered manner along the third axis, each group of word lines (21) includes word lines (21) arranged sequentially along the third axis; or If each group of bit lines (15) includes bit lines (15) arranged sequentially along the third axis, each group of word lines (21) includes word lines (21) arranged alternately along the third axis.

16. The DRAM (10) according to claims 14 and 11, characterized in that: If each group of bit lines (15) includes bit lines (15) arranged alternately along the second axis, each group of word lines (21) includes word lines (21) arranged sequentially along the second axis; or If each group of bit lines (15) includes bit lines (15) arranged sequentially along the second axis, each group of word lines (21) includes word lines (21) arranged alternately along the second axis.

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