3D dram with bit line selection and precharge transistor

Abstract

The invention relates to a 3D dynamic random access memory (3D DRAM). The DRAM includes a block having a 3D array of memory cells. The block includes a set of planes stacked along a first axis, including a subset of consecutively stacked planes. Each plane in the subset includes a 2D array of memory cells organized in rows and columns. The block is divided into a plurality of sub-blocks arranged along a second axis, each sub-block including a column of memory cells per plane. The DRAM also includes a plurality of bit lines extending along the first axis in one of the sub-blocks and connected to one of the memory cells in each plane, and includes a plurality of global bit lines connected to the bit lines in each of the sub-blocks. A plurality of bit line selector (BLS) transistors of the DRAM are configured to respectively connect one of the bit lines to one of the global bit lines. A plurality of bit line pre-charge (BLP) transistors of the DRAM are respectively configured to connect one of the bit lines to one of the plurality of charge lines to charge the bit line.

Description

Technical Field

[0001] The present disclosure relates to dynamic random access memories (DRAMs). In particular, the present disclosure presents a 3D DRAM, i.e., a DRAM having a 3D array of memory cells. The 3D DRAM of the present disclosure includes bit line selector (BLS) transistors and bit line precharge (BLP) transistors. Background Art

[0002] Currently, there are difficulties in making DRAMs smaller while increasing their storage capacity. In particular, DRAM scaling faces challenges in reducing the memory cell area, increasing the memory cell density, and achieving a higher aspect ratio in the vertical direction of the memory cells. There have been various approaches to create 3D DRAMs to address these difficulties. However, most of these conventional approaches only focus on individual memory bit cells and their organization into a memory cell array, without considering the connection between the memory cells and the core circuits such as sense amplifiers and word line drivers.

[0003] The first challenge comes from the size difference between the smaller bit line pitch and the larger bit line sense amplifier (BLSA). For example, for advanced DRAM technologies, the bit line pitch is about 3.4F (44 nm), while the area of the BLSA is estimated to be 284F 2 (88 nm by 6.25 μm). For 2D DRAMs, one BLSA can be located between two bit line pitches on both sides of an array block (MAT). In this setup, multiple BLSAs are arranged similarly to the bit lines in one direction (the x-direction or the y-direction). However, for 3D DRAMs, the bit lines are arranged in two directions (the x-direction and the y-direction), which limits the placement and routing of the BLSAs. This affects the performance and area efficiency of 3D DRAMs.

[0004] The second challenge comes from the number of BLSAs. For 2D DRAMs, each bit line is connected to a BLSA, and all the memory cells on a word line work simultaneously through word line activation. In other words, there should be an equal number of BLSAs and bit lines in a MAT, which results in increased area consumption. Transferring this configuration (i.e., one bit line for one BLSA) to 3D DRAMs is problematic because it brings issues with the placement and connection of the BLSAs and also results in larger area consumption. Summary of the Invention

[0005] Generally speaking, the object of the present disclosure is thus to provide an improved 3D DRAM. Specifically, the object is to reduce the area consumption in view of the above problems. Another object is to reduce the parasitic load in the 3D DRAM. Yet another object is to reduce the number of word line drivers in the 3D DRAM. To this end, the object of the present disclosure is to provide a 3D DRAM memory cell array architecture and a method for separately connecting the 3D DRAM memory cell array to sense amplifiers and word line drivers. Thus, the present disclosure aims to implement a one-transistor and one-capacitor (1T1C) memory cell configuration.

[0006] These and other objects are achieved by the respective solutions of the present disclosure described in the independent claims. Advantageous implementations of these embodiments are described in the dependent claims.

[0007] A first aspect provides a DRAM, comprising: a block including a 3D array of memory cells; wherein the block includes a set of planes stacked along a first axis, wherein the set of planes includes a subset of coherently stacked planes, and wherein each plane in the subset of planes includes a 2D array of memory cells organized in rows extending along a second axis perpendicular to the first axis and columns extending along a third axis perpendicular to the first axis and the second axis; and wherein the block is divided into a plurality of sub-blocks arranged along the second axis, each sub-block including a column of memory cells of each plane in the subset of planes; the DRAM further includes: a plurality of bit lines, wherein each bit line extends along the first axis in one of the sub-blocks and is connected to one memory cell in each plane in the subset of planes;

[0008] a plurality of global bit lines, wherein one or more of the global bit lines are connected to the bit lines in each sub-block;

[0009] a plurality of BLS transistors, wherein each BLS transistor is configured to connect one of the bit lines to one of the global bit lines; and

[0010] a plurality of BLP transistors, wherein each BLP transistor is configured to connect one of the bit lines to one of a plurality of charging lines to charge the bit line.

[0011] The DRAM with a 3D array of memory cells according to the first aspect is a 3D DRAM. The 3D DRAM can be block-addressable and even sub-block-addressable. This can be beneficial to its performance, durability and energy efficiency, and can also increase its storage density.

[0012] The 3D DRAM of the first aspect includes so-called vertical bit lines as they extend along a first axis which is considered a vertical axis in the present disclosure. The connection of the vertical bit lines to the global bit lines reduces area consumption as a more relaxed placement and routing of sense amplifiers is possible. Additionally, the parasitic bit line load can be reduced in the 3D DRAM of the first aspect.

[0013] Furthermore, in the DRAM of the first aspect, a reduction in the parasitic load on the global bit lines can also be achieved. Specifically, the BLS and BLP transistor schemes are proposed for this reason. The reduction in parasitic load achieved by using the BLS and BLP transistors is even independent of the number of planes of the DRAM. The BLS transistor only allows the charge of the selected bit line to be loaded onto the corresponding global bit line. The BLP transistor pre-charges the bit line to minimize the effect of the parasitic capacitance, which can result in faster and more energy-efficient memory operations. For example, the pre-charging can involve setting the bit line to a known voltage level, such as halfway between a logic "0" and "1". This can reduce the voltage swing required during read and / or write operations.

[0014] The BLS and BLP transistors can be implemented separately in the memory cell array region, which is configured the same as the memory cells in the memory cell array region. For example, the BLS and BLP transistors can be modified memory cells respectively, where the storage capacitor is removed. Therefore, less area consumption can also be predicted.

[0015] In one implementation, one of the planes in the set of planes includes a 2D array of BLS transistors.

[0016] In one implementation, one of the planes in the set of planes includes a 2D array of BLP transistors.

[0017] Integrating the BLS and BLP transistors as arrays in the corresponding planes allows for a reduction in area consumption. Additionally, since the BLS and BLP transistors can be processed largely together with the memory cells, manufacturing benefits are achieved.

[0018] In one implementation, the plane including the 2D array of BLP transistors is arranged on a subset of the planes, where each BLP transistor is associated with one of the bit lines; and the plane including the 2D array of BLS transistors is arranged on the plane including the 2D array, where each BLS transistor is associated with one of the bit lines.

[0019] The BLS and BLP transistors can be arranged on top of or at the bottom of the memory cell array.

[0020] In one implementation, each BLS transistor is connected to one of the global bit lines with one of its two terminals and to one of the plurality of first selection lines with its gate.

[0021] In one implementation, each BLP transistor is connected to one of the charging lines by one of its two terminals, and its gate is connected to one of the plurality of second selection lines.

[0022] Thus, during the operation of the 3D DRAM, the selection lines can be used to operate the BLS transistors and the BLP transistors respectively. This operation selects the bit lines and pre-charges the bit lines.

[0023] In one implementation, the DRAM further includes a plurality of sense amplifiers, each of which is connected to one of the global bit lines.

[0024] This reduces the area consumption because the sense amplifiers can be placed and wired more easily.

[0025] In one implementation, each global bit line extends along a third axis, is associated with a corresponding sub-block, and is connected to a corresponding group of bit lines or all bit lines in the corresponding sub-block.

[0026] In one implementation, the DRAM further includes a plurality of word lines, each of which extends along a second axis in one of the planes and is connected to a memory cell in each sub-block.

[0027] In one implementation, the DRAM further includes: a single word line driver shared among all word lines; or a plurality of word line drivers, each of which is shared among all word lines in the same plane; and, as a supplement to the single word line driver or the plurality of word line drivers, further includes one or more word line selectors configured to selectively connect one or more word line drivers to the word lines.

[0028] In this way, the number of word line drivers can be reduced. This can also result in a reduction in the area consumed by the word line drivers.

[0029] In another implementation, the DRAM further includes a plurality of word line drivers that are directly connected to the plurality of word lines

[0030] In another implementation, the DRAM further includes: a single word line selector shared among all word lines; or a plurality of word line selectors, each of which is shared among all word lines in the same plane; wherein one or more word line selectors are configured to selectively connect the output of the address decoder to the plurality of word line drivers; and wherein the plurality of word line drivers are connected to the plurality of word lines.

[0031] In this way, the number of word line selectors can be reduced. This can also result in a reduction in the area consumed by the word line selectors. In this implementation, one or more word line selectors are arranged and connected between the address decoder and the word line driver. The address decoder can act as the first decoder, and one or more word line selectors can act as the second decoder. The address decoder can be the address decoder used in a conventional DRAM. The address decoder can be a circuit for interpreting a memory address received from, for example, a central processing unit (CPU) to select a location in the memory array to read or write data. For example, the word line driver can be an inverter.

[0032] A second aspect of the present disclosure provides a method for processing dynamic random access memory (DRAM) cells, the method comprising: forming a block that includes a 3D array of memory cells; wherein the block includes a set of planes stacked along a first axis, wherein the set of planes includes a subset of coherently stacked planes, and wherein each plane in the subset of planes includes a 2D array of memory cells organized in rows extending along a second axis perpendicular to the first axis and columns extending along a third axis perpendicular to the first axis and the second axis; and wherein the block is divided into a plurality of sub-blocks arranged along the second axis, each sub-block including a column of memory cells of each plane in the subset of planes; the method further comprising: forming a plurality of bit lines, wherein each bit line extends along the first axis in one of the sub-blocks and is connected to a memory cell in each plane in the subset of planes; forming a plurality of global bit lines, wherein one or more of the global bit lines are connected to the bit lines in each sub-block; forming a plurality of BLS transistors, wherein each BLS transistor is configured to connect one of the bit lines to one of the global bit lines; and forming a plurality of BLP transistors, wherein each BLP transistor is configured to connect one of the bit lines to one of a plurality of charging lines to charge the bit line.

[0033] In one implementation, a 2D array of BLS transistors is formed in one of the planes in the set of planes, and a 2D array of BLP transistors is formed in another one of the planes in the set of planes.

[0034] In one implementation, forming the 2D array of BLS transistors and / or the 2D array of BLP transistors respectively includes: forming a 2D array of dummy memory cells in one of the planes, wherein each dummy memory cell includes a transistor with one of its two terminals connected to a capacitor; removing or short-circuiting the capacitor of each dummy memory cell in one of the planes; and connecting the terminals of the transistor of each dummy memory cell to the global bit line or the charging line respectively.

[0035] The method of the second aspect produces the 3D DRAM of the first aspect and can have various implementations to produce all the implementations of the DRAM of the first aspect. Thus, the method of the second aspect brings the same advantages as the first aspect described above.

[0036] A third aspect of the present disclosure provides a method for operating the DRAM of the first aspect or any of its implementations, the method comprising: selecting the bit line by activating the BLS transistor associated with the bit line, thereby connecting the bit line to the associated global bit line; pre-charging the bit line by activating the BLP transistor associated with the bit line, thereby connecting the bit line to the associated charging line; and sensing the charge on the associated global bit line connected to the bit line via the BLS transistor, or providing charge on the global bit line.

[0037] In one implementation, the method further comprises: driving the word line of the DRAM to activate the memory cell connected to the bit line, thereby transferring data stored in the capacitor of the memory cell between the memory cell and the bit line; wherein the word line is driven before, after, or simultaneously with the selection and pre-charging of the bit line.

[0038] The method of the third aspect reduces the impact of parasitic capacitance in the 3D DRAM and thus allows reducing the load on the global bit line.

[0039] Summarizing the above aspects and implementations, the present disclosure introduces BLS transistors and BLP transistors in a 3D DRAM architecture with vertical bit lines. The present disclosure explores the memory core architecture while considering the connection between the bit line and the sense amplifier via the global bit line and reduces the parasitic load of the bit line and the global bit line. In addition, the impact of increasing the number of planes is also minimized, for example, the impact on the area of the sense amplifier and the corresponding parasitic load. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above aspects and implementations are explained in the following detailed description with reference to the accompanying drawings:

[0041] Figure 1 A perspective view and a top view of a 3D DRAM with vertical bit lines, BLS transistors, and BLP transistors according to the present disclosure are shown.

[0042] Figure 2 A front view of an exemplary 3D DRAM according to the present disclosure is shown.

[0043] Figure 3 A first perspective view of an exemplary 3D DRAM is shown.

[0044] Figure 4Shows a second perspective view of an exemplary 3D DRAM.

[0045] Figure 5 Shows a top view of an exemplary 3D DRAM.

[0046] Figure 6 Shows a method of operating a 3D DRAM according to the present disclosure.

[0047] Figure 7 Shows a possible timing diagram of a method of operating a 3D DRAM.

[0048] Figure 8 Shows a method of manufacturing a 3D DRAM according to the present disclosure. Detailed Description

[0049] Figure 1 Shows DRAM 10 according to the present disclosure. Specifically, Figure 1 (a) shows a perspective view of DRAM 10, while Figure 1 (b) shows a top view of DRAM 10. DRAM 10 is a 3D DRAM because it includes blocks 11 that contain 3D arrays of memory cells 13. DRAM 10 may include more than one such block 11, i.e., it may include an arrangement of multiple blocks 11 that can be individually addressed. Each block 11 may be identical. The following description relates to one block 11. Each memory cell 13 may include a storage capacitor for storing data in the form of charge, and a transistor connected to the storage capacitor and configured to enable writing data to or reading data from the storage capacitor. Each memory cell 13 may be capable of storing one bit of data (information). The memory cells 13 in 3D DRAM 10 may be arranged in rows, columns, and stacks.

[0050] Specifically, as Figure 1 shown in (b), block 11 of DRAM 10 includes a plurality of planes 12 that are stacked along a first axis (the vertical axis in the present disclosure, the z-axis according to the coordinate system shown in the drawings). As can be derived from Figure 1 it, each plane 12 includes a 2D array of memory cells 13, and the 2D array of memory cells 13 is organized in rows extending along a second axis perpendicular to the first axis (the second axis is the x-axis in the coordinate system) and columns extending along a third axis perpendicular to the first axis and the second axis (the third axis is the y-axis in the coordinate system). Thus, the stacked planes 13 include columns, rows, and stacks of memory cells 13, where the stack of memory cells 13 includes memory cells 13 arranged along the first axis.

[0051] As Figure 1As further schematically shown in (a) and (b), block 11 is divided into a plurality of sub - blocks 14 arranged along the second axis. Each sub - block 14 contains a column of memory cells 13 of each plane 12. The coherent arrangement of the sub - blocks 14 defines a row of memory cells 13 along the second axis. In the DRAM 10, each sub - block 14 is separately addressable.

[0052] The DRAM 10 also includes a plurality of bit lines 15. Each bit line 15 extends along the first axis in one of the sub - blocks 14. Thus, in the present disclosure, the bit lines 15 are referred to as vertical bit lines. Each bit line 15 is connected to a memory cell 13 in each plane 12. In other words, each bit line 15 is connected to a stack of memory cells 13.

[0053] In addition, the DRAM 10 includes a plurality of global bit lines 16. One or more of the global bit lines 16 are connected to the bit lines 15 in each sub - block 14. By way of example only, Figure 1 the illustration in shows one global bit line 16 for each sub - block 14, where the global bit line 16 is connected to all the shown bit lines 15 of the sub - block 14. However, it is also possible to use two or more global bit lines 16 to connect to the bit lines 15 of the corresponding sub - block 14. Figure 1 The DRAM 10 also includes a plurality of BLS transistors 17 and a plurality of BLP transistors 18. Each BLS transistor 17 is configured to connect one of the bit lines 15 to one of the global bit lines 16. Each BLP transistor 18 is configured to connect one of the bit lines 15 to one of the plurality of charging lines 19 and can be operated (turned on) to charge the bit line 15. For example, the bit line 15 can be pre - charged to a known voltage level between the voltages of logic “0” and “1”. Thus, such a voltage can be applied to the charging line 19 to pre - charge the bit line 15.

[0054] A particular plane 12 in the set of planes 12 can include a 2D array of BLS transistors 17, while another particular plane 12 in the set of planes 12 can include a 2D array of BLP transistors 18. Each sub - block 14 can include a column of BLS transistors 17 and can include another column of BLP transistors 18, which are respectively associated with one of the bit lines 15 in the sub - block 14.

[0055] In the following, more specific examples of the DRAM 10 according to the present disclosure are given. All of these examples are based on Figure 1 the DRAM 10 shown in. Figure 1 The same reference numerals are shared by the same elements in any of the previous figures and can be implemented and / or function similarly. Redundant descriptions are avoided.

[0056] Figure 2A front / side view of an exemplary DRAM 10 according to the present disclosure is shown. In Figure 2 the DRAM 10, a block 11 is referred to as a "MAT" (memory cell array block), and a plurality of sub-blocks 14 are referred to as "sub-MATs" or simply "SMs", respectively. The sub-blocks 14 are numbered from SM0 to SM(k - 1), where an example is k = 32. Thus, in this example, each block 11 can be composed of 32 sub-blocks 14. In addition, each sub-block 14 includes vertical bit lines 15, for example, 32 vertical bit lines 15. In Figure 2 each sub-block 14, one bit line (BL) is shown and numbered as SBL0.

[0057] Figure 2 It is also shown that the DRAM 10 includes a plurality of word lines 21. Each word line 21 can extend along a second axis in one of the stacked planes 12. Thus, each word line 21 is connected to one memory cell 13 in each of the plurality of sub-blocks 14. If the word line 21 is operative (charged), the memory cell 13 connected to the word line 21 can be activated. For example, a transistor connected to a storage capacitor of the memory cell 13 can be turned on (conducted) to allow charge to be written to or read from the storage capacitor. Reading and writing can be performed via the bit line 15 connected to the memory cell 13. For example, each of the 32 planes of the DRAM 10 can have 32 word lines 21. In Figure 2 each, the word lines 21 are referred to and numbered as WL0<0> to WL0 <l-1>, where <#> represents a specific plane with number #, and L = 32 is an example.

[0058] Figure 2 Also shown are a plurality of global bit lines 16 of the DRAM 10, where each global bit line 16 is connected to a terminal of a BLS transistor 17. In other words, each BLS transistor 17 is connected to one of the global bit lines 16 with one of its two terminals. In this example, the global bit lines 16 are numbered GBL0 to GBL(k - 1).

[0059] The BLS transistors 17 are arranged in Figure 2 the uppermost plane 12 among them. Each BLS transistor 17 is configured to connect one of the bit lines 15 to one of the global bit lines 16. The BLS transistors 17 can thus be operated by a plurality of first selection lines 22, where Figure 2 one of the first selection lines 22 called SBLS(n - 1) (for "sub BL select") is shown in. The gate of each BLS transistor 17 is connected to one of the plurality of first selection lines 22. The BLP transistors 18 are arranged from the top in the second plane 12, that is, they are arranged between the plane 12 including the BLS transistors 17 and a subset of the plane 12 including the memory cells 13. The two planes 12 respectively including the BLS transistors 17 and the BLP transistors 18 are called the BL selection area, while the remaining planes 12 are called the memory cell area. They can together form an array area (AR). In other words, the plane 12 including the BLP transistors 18 can be arranged on a subset of the plane 12 including the memory cells 13, and the plane 12 including the BLS transistors 17 can be arranged on the plane 12 including the BLP transistors 18. Each BLP transistor 18 is associated with one of the bit lines 15, and each BLS transistor 17 is associated with one of the bit lines 15. Specifically, each BLP transistor 18 is configured to connect one of the bit lines 15 to one of the plurality of charge lines 19 to charge the bit line 15. The charge lines are abbreviated as PL in Figure 2 this. For this purpose, each BLP transistor 18 is connected to one of the charge lines 19 with one of its two terminals. In addition, the gate of each BLP transistor 18 is connected to one of the plurality of second selection lines 23. The plurality of second selection lines 23 can be used to operate the BLP transistors, where Figure 2 one of the second selection lines 23 called SBLS(n - 1)B (for inverted SBLS) is shown in. The first selection lines 22 and the second selection lines 23 can be controlled together, where the second selection lines 23 operate in an inverted manner compared to the first selection lines 22.

[0060] Figure 3 A first perspective view of an exemplary DRAM 10 is shown, where Figure 3 Highlights a plane 12 of the DRAM 10, as well as the connections between the first select line 22 and the BLS transistors 17, and between the second select line 23 and the BLP transistors. The first select line 22 is labeled SBLS0 to SBLS(n - 1), while the second select line 23 is labeled SLSOB to SLS(n - 1)B, where an example is n = 32. Each first select line 22 can be used to operate a BLS transistor 17 of each sub - block 14. Each second select line 23 can be used to operate a BLP transistor 18 of each sub - block 14.

[0061] As Figure 3 shown, the DRAM 10 also includes a plurality of bit - line sense amplifiers 31 (BLSA). Each sense amplifier 31 is connected to one of the global bit - lines 16 and is configured to sense (detect) the charge on the global bit - line. Indirectly, each sense amplifier 31 can thus be connected to the plurality of bit - lines 15 through the global bit - lines 16 and can thus be capable of detecting the charge from at least one bit - line 15 on the global bit - line 16. In the DRAM 10, it is possible to read the charge of a single memory cell 13 of each sub - block 14 using the bit - lines 15, the global bit - lines 16, and the sense amplifiers 31. In Figure 3 this example, the sense amplifiers 31 are labeled BLSA0 to BLSA(k - 1).

[0062] In this example, to improve the connection between the bit - lines 15 and the sense amplifiers 31, while taking into account the smaller bit - line pitch, all the bit - lines 15 in each sub - block 14 are connected to a single global bit - line 16. In this example, each global bit - line 16 extends along a third axis and is associated with a corresponding sub - block 14 among the plurality of sub - blocks 14. Each global bit - line 16 is connected to all the bit - lines 15 in the corresponding sub - block 14. Each global bit - line 16 is connected to a sense amplifier 31.

[0063] Figure 4 Shows a second perspective view of an exemplary DRAM, where Figure 4 highlights the plurality of planes 12 of the DRAM 10. As Figure 3 before, Figure 4 shows the connections between the first select line 22 and the BLS transistors 17 and between the second select line 23 and the BLP transistors. Figure 4 Also shows the connection of the storage transistors of the memory cells 13 to the word - lines 21. Specifically, shows the word - line W0 <l-1>to WL(m - 1) <l-1>, one example of which is m = 32. There can be 32 word lines W0 to WL(m-1) in each of the 32 planes <0> to <L-1>.

[0064] Figure 5 Shows a top view of an exemplary DRAM 10. Specifically, Figure 5 Shows only one of the multiple planes 12 of the DRAM 10, i.e., plane 12. Figure 5 Shows how the bit line 15 is connected on one hand to the memory cells 13 of the 2D array of the plane 12 and on the other hand to the global bit line 16. Figure 5 Also shows how the word line 21 is connected to the memory cells 13 in the 2D array of the plane 12. In this example, the global bit line 16 extends along the third axis, the bit line 15 extends along the first axis, and the first selection line 22 and the second selection line 23 extend along the second axis respectively.

[0065] Figure 6 Shows a method 60 for operating a DRAM 10 (such as Figures 1 - 5 the DRAM 10 shown in). The method 60 includes a step 61 of selecting the bit line 15 by activating the BLS transistor 17 associated with the bit line 15. This connects the bit line 15 to the associated global bit line 16. The method 60 also includes a step 62 of precharging the bit line 15 by activating the BLP transistor 18 associated with the bit line 15. This connects the bit line 15 to the associated charging line 19. The method 60 then includes sensing the charge on the associated global bit line 19 connected to the bit line 15 via the BLS transistor 17, or providing charge on the global bit line 16.

[0066] Figure 7 Shows a possible timing diagram that can be applied to Figure 6 the method 60. Generally, the method 60 may also include a step of driving the word line 21 of the DRAM 10 to activate the memory cells 13 connected to the bit line 15. This can cause the data (as charge) stored in the capacitor of the memory cell 13 to be transferred from the memory cell 13 to the bit line 15 (read), or can cause data to be transferred from the bit line 15 to the memory cell 13 (write). Thus, as Figure 7 shown, the word line 21 can be driven before, after, or simultaneously with the selection of the bit line 15 and the precharging of the bit line 15.

[0067] Specifically, Figure 7 In (a), early BLS enabling (and disabling) compared to word line activation is shown. That is, the word line 21 is driven after the selected bit line 15. It can be seen that the first selection line 22 is enabled (SBLSn rises from 0V to "high"), and the second selection line 23 is also enabled (SBLSnB falls from "high" to 0V). Pre-charging is performed by the charge on the charging line 19 (PCHG is set to "high"). After the first selection line 22 and the second selection line 23 are enabled, the word line 21 is activated (WL is "high"). After the word line 21 is deactivated again (WL is "low"), the first selection line 22 and the second selection line 23 are disabled (SBLSn is 0V, SBLSnB is "high").

[0068] Figure 7 In (b), simultaneous BLS enabling (and disabling) compared to word line activation is shown. That is, the word line 21 is driven simultaneously with the selected bit line 15. It can be seen that the first selection line 22 is enabled (SBLSn rises from 0V to "high"), and the second selection line 23 is also enabled (SBLSnB falls from "high" to 0V). The word line 21 is activated while the first selection line 22 and the second selection line 23 are activated (WL is "high"). When the word line 21 is deactivated again (WL is "low"), the first selection line 22 and the second selection line 23 are disabled (SBLSn is 0V, SBLSnB is "high").

[0069] Figure 7 In (c), late BLS enabling (and disabling) compared to word line activation is shown. That is, the word line 21 is driven before the selected bit line 15 and pre-charging the bit line 15. It can be seen that the first selection line 22 is enabled (SBLSn rises from 0V to "high"), and the second selection line 23 is also enabled (SBLSnB falls from "high" to 0V), however, this is after the word line 21 is activated (WL is "high"). Before the word line 21 is deactivated again (WL is "low"), the first selection line 22 and the second selection line 23 are disabled (SBLSn is 0V, SBLSnB is "high").

[0070] Figure 8 Shows the manufacturing of DRAM according to the present disclosure, for example Figures 1 - 5 Method 80 for a DRAM as shown. Method 80 includes step 81 of forming block 11, where block 11 includes a 3D array of memory cells 13. Block 11 includes a set of planes 12 that are stacked along a first axis to build the 3D array. This set of planes 12 includes a subset of planes 12 that are stacked coherently, where each plane 12 in the subset includes a 2D array of memory cells 13 such that the planes 12 in the subset together form the 3D array. The memory cells of each 2D array are organized in rows extending along a second axis perpendicular to the first axis and columns extending along a third axis perpendicular to the first and second axes. Block 11 is also divided into a plurality of sub-blocks 14 arranged along the second axis. Each sub-block 14 contains a column of memory cells 13 of each plane 12 in the subset of planes 12.

[0071] Method 80 also includes step 82 of forming a plurality of bit lines 15, where each bit line 15 extends along the first axis in one of the sub-blocks 14 and is connected to a memory cell 13 in each plane 12 in the subset of planes 12. Method 80 also includes step 83 of forming a plurality of global bit lines 16, where one or more of the global bit lines 16 are connected to the bit lines 15 in each sub-block 14. Method 80 also includes step 84 of forming a plurality of BLS transistors 17, where each BLS transistor 17 is configured to connect one of the bit lines 15 to one of the global bit lines 16. In addition, method 80 includes step 85 of forming a plurality of BLP transistors 18, where each BLP transistor 18 is configured to connect one of the bit lines 15 to one of a plurality of charging lines to charge the bit line 15.

[0072] It is noted that method 80 can be implemented through the process flow for fabricating a DRAM. In addition, the steps of method 80 do not need to be executed in the described order but can be adapted to the process flow. Any step order is possible, and some steps can also be executed simultaneously or in the same stage of the process flow.

[0073] Generally speaking, the present disclosure addresses the challenges faced by DRAM scaling in terms of memory bit cell area, memory density, and vertical aspect ratio. The present disclosure provides a 3D DRAM 10 that is designed by considering the connections between memory cells 13 and core circuits such as sense amplifiers 17, word line drivers 22, word line selectors 22, and bit line selectors 170. The present disclosure provides a solution for a 1T1C-based 3D DRAM memory cell core and specifically introduces a method for configuring a 3D DRAM memory cell array and its connections to sense amplifiers 17 and word line drivers 22. Therefore, less area consumption, smaller parasitic bit line load, and fewer word line drivers 22 can be achieved in the DRAM 10.

[0074] In the claims as well as in the description of the present disclosure, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single element may perform the functions of several entities or items recited in the claims. The mere fact that certain measures are stated in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A dynamic random access memory DRAM (10), comprising: A block (11) comprising a 3D array of memory cells (13); wherein the block (11) comprises a set of planes (12) stacked along a first axis, wherein the set of planes (12) comprises a subset of planes (12) stacked consecutively, and wherein each plane (12) in the subset of planes (12) comprises a 2D array of memory cells (13), the 2D array of memory cells (13) being organized in rows extending along a second axis perpendicular to the first axis and in columns extending along a third axis perpendicular to the first axis and the second axis; and wherein the block (11) is divided into a plurality of sub-blocks (14) arranged along the second axis, each sub-block (14) comprising a column of memory cells (13) for each plane (12) in the subset of planes (12); The DRAM (10) further includes: a plurality of bit lines (15), wherein each bit line (15) extends along the first axis in one of the sub-blocks (14) and is connected to a memory cell (13) in each plane (12) in the subset of planes (12); a plurality of global bit lines (16), wherein one or more of the global bit lines (16) are connected to the bit lines (15) in each sub-block (14); and a plurality of bit line selector (BLS) transistors (17), wherein each BLS transistor is configured to connect one of the bit lines (15) to one of the global bit lines (16); and A plurality of bit line pre-charging BLP transistors (18) are provided, wherein each BLP transistor (18) is configured to connect one of the bit lines (15) to one of a plurality of charging lines (19) to charge the bit line (15).

2. The DRAM (10) according to claim 1, characterized in that One plane (12) of the set of planes (12) comprises a 2D array of BLS transistors (17).

3. The DRAM (10) according to claim 2, characterized in that One plane (12) in the set of planes (12) includes a 2D array of BLP transistors (18).

4. The DRAM (10) according to claim 2 and 3, characterized in that: A plane (12) comprising a 2D array of BLP transistors (18) is arranged on the subset of the plane (12), wherein each BLP transistor (18) is associated with one of the bit lines (15); and A plane (12) comprising a 2D array of BLS transistors (17) is arranged on a plane (12) comprising a 2D array of BLP transistors (18), wherein each BLS transistor (17) is associated with one of the bit lines (15).

5. The DRAM (10) according to any one of claims 1 to 4, characterized in that: Each BLS transistor (17) is connected at one of its two terminals to one of the global bit lines (16) and at its gate to one of a plurality of first selection lines (22).

6. The DRAM (10) according to any one of claims 1 to 5, characterized in that: Each BLS transistor (18) is connected at one of its two terminals to the one of the charging lines (19) and at its gate to one of a plurality of second selection lines (23).

7. The DRAM (10) according to any one of claims 1 to 6, characterized in that: Also included are a plurality of sense amplifiers (31), wherein each sense amplifier (31) is connected to one of the global bit lines (16).

8. The DRAM (10) according to any one of claims 1 to 7, characterized in that: Each global bit line (16) extends along the third axis and is associated with a respective sub-block (14) and is connected to a respective group of bit lines (15) or all bit lines (15) in the respective sub-block (14).

9. The DRAM (10) according to claim 1, characterized in that Also includes: A plurality of word lines (21), wherein each word line (21) extends along the second axis in one of the planes (12) and is connected to one memory cell (13) in each sub-block (14).

10. The DRAM (10) according to claim 9, characterized in that Also includes: a single word line driver shared between all word lines (21); or a plurality of word line drivers, wherein each word line driver is shared between all word lines (21) in the same plane (12); and In addition to the single word line driver or the plurality of word line drivers, the invention further includes one or more word line selectors configured to selectively connect one or more word line drivers to the word line (21).

11. The DRAM (10) according to claim 9, characterized in that Also includes: a single word line selector (23) shared between all word lines (21); or A plurality of word line selectors (23), wherein each word line selector (23) is shared between all word lines (21) in the same plane (12); wherein the one or more word line selectors (23) are configured to selectively connect the output of the address decoder to the plurality of word line drivers (22); and The plurality of word line drivers (22) are connected to the plurality of word lines (21).

12. A method (80) for processing a dynamic random access memory DRAM (10), the method (80) comprising: forming (81) a block (11) comprising a 3D array of memory cells (13); wherein the block (11) comprises a set of planes (12) stacked along a first axis, wherein the set of planes (12) comprises a subset of planes (12) stacked consecutively, and wherein each plane (12) in the subset of planes (12) comprises a 2D array of memory cells (13), the 2D array of memory cells (13) being organized in rows extending along a second axis perpendicular to the first axis and in columns extending along a third axis perpendicular to the first axis and the second axis; and wherein the block (11) is divided into a plurality of sub-blocks (14) arranged along the second axis, each sub-block (14) comprising a column of memory cells (13) for each plane (12) in the subset of planes (12); The method (80) further comprises: forming (82) a plurality of bit lines (15), wherein each bit line (15) extends along the first axis in one of the sub-blocks (14) and is connected to a memory cell (13) in each plane (12) in the subset of planes (12); forming (83) a plurality of global bit lines (16), wherein one or more of the global bit lines (16) are connected to the bit lines (15) in each sub-block (14); and forming (84) a plurality of bit line selector (BLS) transistors (17), wherein each BLS transistor is configured to connect one of the bit lines (15) to one of the global bit lines (16); and A plurality of bit line pre-charge BLP transistors (18) are formed (85), wherein each BLP transistor (18) is configured to connect one of the bit lines (15) to one of a plurality of charge lines (19) to charge the bit line (15).

13. The method (80) according to claim 12, characterized in that: A 2D array of BLS transistors (17) is formed in one of the planes (12) in the set of planes (12), and wherein a 2D array of BLP transistors (18) is formed in another of the planes (12) in the set of planes (12).

14. The DRAM (10) according to claim 13, characterized in that The 2D array of BLS transistors (17) and / or the 2D array of BLP transistors (18) are formed respectively comprising: forming a 2D array of dummy memory cells in said one of the planes (12), wherein each dummy memory cell comprises a transistor connected at one of its two terminals to a capacitor; removing or shorting the capacitor of each dummy memory cell in said one of the planes (12); and The terminals of the transistor of each dummy memory cell are connected to the global bit line (16) or the charge line (19), respectively.

15. A method (60) for operating a dynamic random access memory DRAM (10) as claimed in any one of claims 1 to 10, the method comprising: selecting (61) a bit line (15) by activating a BLS transistor (17) associated with the bit line (15), thereby connecting the bit line (15) to an associated global bit line (16); precharging (62) the bit line (15) by activating a BLP transistor (18) associated with the bit line (15), thereby connecting the bit line (15) to an associated charge line (19); and A charge is sensed (63) on an associated global bit line (19) connected to the bit line (15) via the BLS transistor (17), or a charge is provided on the global bit line (16).

16. The method (60) according to claim 15, characterized in that Also includes: driving a word line (21) of the DRAM (10) to activate a memory cell (13) connected to the bit line (15), thereby transferring data stored in a capacitor of the memory cell (13) between the memory cell (13) and the bit line (15); The word line (21) is driven before, after or simultaneously with selecting and precharging the bit line (15).

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