A circuit implementation method for improving SRAM read-write speed

Abstract

The application provides a circuit implementation method for improving the read-write speed of SRAM, and belongs to the technical field of circuit design, and comprises an SRAM storage unit, wherein the SRAM storage unit comprises a transistor assembly and an inverter assembly, the transistor assembly comprises transistor one, transistor two, transistor three, transistor four, transistor five and transistor six, and the inverter assembly comprises inverter one and inverter two; the application has the beneficial effects that: through the improved design of the architecture and the connection mode, the storage units in the same row are enabled at the same time during reading and writing, and the storage units in the same column share the data transmission line, so that the control logic of the circuit is simplified, the redundant links on the signal transmission path are reduced, the data transmission efficiency is effectively improved, the overall read-write speed is accelerated, the read-write operation is divided into multiple stages, different operation stages of different storage units can be carried out at the same time within one clock cycle, time resources are fully utilized, and the read-write speed is improved.

Description

Technical Field

[0001] This invention relates to the field of circuit design technology, and more specifically, to a circuit implementation method for improving SRAM read / write speed. Background Technology

[0002] With the continuous progress of the times, the demand for storage in applications is also increasing. SRAM (static random access memory) is a commonly used storage device and is widely used in various fields. As the amount of data that applications need to process continues to increase, the read and write speed of storage devices such as SRAM will directly affect the data processing speed.

[0003] In existing technologies, in SRAM read mode, the BL / BLB is pre-charged to VDD voltage by an external control unit. Since one of the Q / QB nodes in a bitcell (the smallest unit in SRAM storing 0 / 1 information) is logic high and the other is logic low, when the WL signal is pulled high, one side of BL / BLB will start discharging. After a sufficient voltage difference is generated between BL / BLB, subsequent circuitry can determine whether the signal stored in the bitcell is logic high or logic low. In SRAM write mode, the external control unit first pulls one side of BL / BLB low and the other side high, for example, BL is pulled low and BLB is pulled high. Then, after the WL signal is pulled high, the Q node will be written to logic low and the QB node will be written to logic high, and vice versa. Therefore, in traditional SRAM architectures, limited by specific process nodes and traditional read / write control timing, it may not be possible to further improve the read / write speed of SRAM. How to invent a circuit implementation method to improve the read / write speed of SRAM and solve these problems has become an urgent problem for those skilled in the art. Summary of the Invention

[0004] To overcome the above shortcomings, this invention provides a circuit implementation method to improve SRAM read and write speed, aiming to solve the problem that traditional SRAM architectures, limited by specific process nodes and traditional read and write control timing, may not be able to further improve SRAM read and write speed.

[0005] This invention is implemented as follows:

[0006] This invention provides a circuit implementation method for improving SRAM read / write speed, comprising: an SRAM storage cell, wherein the SRAM storage cell includes a transistor assembly and an inverter assembly, the transistor assembly includes transistor one, transistor two, transistor three, transistor four, transistor five and transistor six, the inverter assembly includes inverter one and inverter two, transistor two is connected to RWL1, RWL1 is connected to RBL1, transistor three is connected to BL, WWL and Q nodes, transistor four is connected to BLB and QB nodes, transistor five is connected to RWL2, RWL2 is connected to RBL2, and the SRAM storage cell comprises a plurality of SRAM storage cells arranged in an n x m array, and each SRAM storage cell contains a plurality of storage cells (bit cells).

[0007] In the circuit, RWL1 is the first read word line, RBL1 is the first read bit line, BL is the bit line, WWL is the write word line, BLB is the reverse bit line, RWL2 is the second read word line, and RBL2 is the second bit fetch line.

[0008] The specific steps are as follows:

[0009] S1: During the high-level time of the SRAM input clock, address 1 is decoded, and one of RWL11-RWL1n is selected to be turned on. The selected RWL1x is pulled high when the SRAM input clock cuts from high to low. At this time, the address decoding circuit adopts a decoding method that combines parallel and segmented decoding to quickly convert the address signal into a row strobe signal.

[0010] S2: During the low-level period of the SRAM input clock, read and write operations are performed on the selected bit cell. The corresponding data is read through RBL11-RBL1m. At the same time, address 2 is decoded, and one of RWL21-RWL2n is selected to be turned on. The selected RWL2x is pulled high when the SRAM input clock switches from low to high.

[0011] S3: During the time when the SRAM input clock switches to high level again, read and write operations are performed on the currently selected bit cell. The corresponding data is read through RBL21-RBL2m. At the same time, address 3 is decoded, and one of RWL11-RWL1n is selected to be turned on. The selected RWL1x is pulled high when the SRAM input clock switches from high to low.

[0012] S4: Continue following the pipeline algorithm implementation method of S1-S3 above until the last address is read, completing the entire SRAM read and write operation.

[0013] Preferably, the source of transistor one is grounded, the drain of transistor one is connected to the source of transistor two, and the gate of transistor one is connected to inverter one, inverter two and Q node respectively.

[0014] Preferably, the drain of transistor two is connected to the first read bit line, and the gate of transistor two is connected to the first read word line.

[0015] Preferably, the source of transistor three is connected to the bit line, the gate of transistor three is connected to the write word line, the drain of transistor three is connected to the Q node, and the Q node is connected to the output terminal of inverter one and the input terminal of inverter two, respectively.

[0016] Preferably, the source of transistor six is ​​grounded, the gate of transistor six is ​​connected to inverter one, inverter two and QB node respectively, and the drain of transistor six is ​​connected to the source of transistor five.

[0017] Preferably, the gate of transistor five is connected to the second read word line, and the drain of transistor five is connected to the second read bit line.

[0018] Preferably, the source of transistor four is connected to the anti-phase line, the gate of transistor four is connected to the write word line, the drain of transistor four is connected to the QB node, and the QB node is connected to the input terminal of inverter one and the output terminal of inverter two, respectively.

[0019] The beneficial effects of this invention are:

[0020] By improving the architecture and connection method, the horizontal write word line, first read word line, and second read word line are shorted row by row, and the vertical bit line, anti-phase line, first read bit line, and second read bit line are shorted column by column. This design allows memory cells in the same row to be enabled simultaneously during read and write operations, and memory cells in the same column to share data transmission lines. This not only simplifies the control logic of the circuit and reduces redundant links in the signal transmission path, but also effectively reduces signal transmission delay and improves data transmission efficiency, thereby accelerating the overall read and write speed. At the same time, the pipelined operation mode is adopted, dividing the read and write operations into multiple stages, so that each stage is processed in parallel within different clock cycles. This allows different operation stages of different memory cells to be performed simultaneously within one clock cycle, greatly improving the overall data throughput of SRAM, making full use of time resources, and significantly improving the read and write speed. Compared with the traditional bitcell cell structure, using SRAM bitcells suitable for pipelines as memory cells, combined with the algorithm and timing proposed in this invention, can effectively improve the read and write speed of SRAM. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the SRAM bitcell architecture structure of a circuit implementation method for improving SRAM read and write speed provided by an embodiment of the present invention.

[0023] Figure 2 This is a schematic diagram of an improved storage cell structure of a conventional SRAM, which is a circuit implementation method for improving SRAM read and write speed provided by an embodiment of the present invention.

[0024] In the diagram: 1. Transistor 1; 2. Transistor 2; 3. Transistor 3; 4. Inverter 1; 5. Inverter 2; 6. Transistor 4; 7. Transistor 5; 8. Transistor 6. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] Example, refer to Figures 1-2 A circuit implementation method for improving SRAM read / write speed includes: an SRAM storage cell, the SRAM storage cell including a transistor assembly and an inverter assembly, the transistor assembly including transistor 1, transistor 2, transistor 3, transistor 4, transistor 5, and transistor 6, the inverter assembly including inverter 4 and inverter 2, transistor 2 connected to RWL1, RWL1 connected to RBL1, transistor 3 connected to BL, WWL, and Q nodes, transistor 4 connected to BLB and QB nodes, transistor 5 connected to RWL2, RWL2 connected to RBL2, the SRAM storage cell is provided in a plurality of arrays arranged in an n-row m-column array, the plurality of SRAM storage cells containing multiple storage cells (bitcells);

[0027] In the circuit, RWL1 is the first read word line, RBL1 is the first read bit line, BL is a bit line, WWL is the write word line, BLB is the reverse bit line, RWL2 is the second read word line, and RBL2 is the second take bit line.

[0028] Furthermore; the source of transistor 1 is grounded, the drain of transistor 1 is connected to the source of transistor 2, and the gate of transistor 1 is connected to inverter 4, inverter 5, and the Q node respectively; the drain of transistor 2 is connected to the first read bit line, and the gate of transistor 2 is connected to the first read word line; the source of transistor 3 is connected to the bit line, the gate of transistor 3 is connected to the write word line, and the drain of transistor 3 is connected to the Q node, which is connected to the output of inverter 4 and the input of inverter 5 respectively; the source of transistor 3... The gate of transistor 3 is connected to the bit line, the gate of transistor 3 is connected to the write word line, the drain of transistor 3 is connected to the Q node, and the Q node is connected to the output of inverter 4 and the input of inverter 5 respectively; the gate of transistor 5 is connected to the second read word line, and the drain of transistor 5 is connected to the second read bit line; the source of transistor 4 is connected to the anti-phase line, the gate of transistor 4 is connected to the write word line, the drain of transistor 4 is connected to the QB node, and the QB node is connected to the input of inverter 4 and the output of inverter 5 respectively.

[0029] It should be noted that: each memory cell in the memory cell structure consists of at least one pair of complementary inverters and multiple transistors, used to store 1 bit of binary data. The transistors include a gating transistor for controlling data transmission and a storage transistor for maintaining the data state. The signal lines are connected in the vertical direction, and the bit lines (BLx), anti-phase lines (BLBx), first read bit lines (RBL1x), and second read bit lines (RBL2x) of all memory cells are shorted column-wise, implemented through low-impedance metal interconnects to reduce signal transmission delay. The signal lines are connected in the horizontal direction, and all write word lines (WWLx), first read word lines (RWL1x), and second read word lines (RWL2x) are shorted row-wise, realizing unified read and write control for a row of memory cells.

[0030] In terms of architecture and connection methods, the row-column shared signal design has advantages: in the horizontal direction, the write word line (WWLx), the first read word line (RWL1x), and the second read word line (RWL2x) are shorted row by row, while in the vertical direction, the bit line (BLx), the anti-phase line (BLBx), the first read bit line (RBL1x), and the second read bit line (RBL2x) are shorted column by column. This design allows memory cells in the same row to be enabled simultaneously during reading and writing, and memory cells in the same column to share the data transmission line. This not only simplifies the control logic of the circuit and reduces redundant links in the signal transmission path, but also effectively reduces signal transmission delay, improves data transmission efficiency, and thus speeds up the overall read and write speed. Using low-impedance metal interconnects for signal line connections can significantly reduce the resistance and capacitance effects of the signal during transmission. The resistance effect will cause a voltage drop during signal transmission, and the capacitance effect will cause signal delay and distortion. By reducing the impact of these effects, the integrity of the signal and fast transmission are ensured, providing a basic guarantee for high-speed read and write operations.

[0031] Reference Figure 2 Furthermore, during the high-level period of the SRAM input clock, address 1 is decoded, selecting one of RWL11-RWL1n to be enabled. The selected RWL1x is pulled high when the SRAM input clock transitions from high to low. At this time, the address decoding circuit uses a combination of parallel and segmented decoding to quickly convert the address signal into a row selection signal. During the low-level period of the SRAM input clock, read / write operations are performed on the selected bitcell, reading the corresponding data through RBL11-RBL1m. Simultaneously, address 2 is decoded, selecting one of RWL21-RWL2n... One path is selected for activation, and the selected RWL2x is pulled high when the SRAM input clock switches from low to high. During the time when the SRAM input clock switches high again, read and write operations are performed on the currently selected bit cell, and the corresponding data is read through RBL21-RBL2m. At the same time, address 3 is decoded, and one path is selected for activation from RWL11-RWL1n, and the selected RWL1x is pulled high when the SRAM input clock switches from high to low. The pipeline algorithm implementation method of S1-S3 is continued until the last address is read, completing the entire SRAM read and write operation.

[0032] It should be noted that by adopting a pipeline operation mode, the read and write operations are divided into multiple stages, such as address decoding, data reading, and data writing. Each stage is processed in parallel within different clock cycles. This allows different operation stages of different memory cells to be performed simultaneously within one clock cycle, which greatly improves the overall data throughput of SRAM. For example, while reading data from one memory cell, address decoding and other operations can be performed on another memory cell, making full use of time resources and significantly improving read and write speed.

[0033] Advantages of Address Decoding and Read / Write Control: The address decoding circuit adopts a combination of parallel and segmented decoding methods, which can quickly and accurately convert address signals into row selection signals, reducing the time delay of address decoding. During read / write operations, the sensitive amplifier is equipped with a dynamic threshold adjustment circuit, which can dynamically adjust the threshold voltage according to the amplitude of the read bit line signal and the noise level, improving detection accuracy and response speed. The sensitive amplifier has a high-speed differential amplification structure and a dynamic threshold adjustment circuit, which can quickly detect and amplify weak read bit line signals and accurately determine the data status of the memory cell. The write data drive circuit has sufficient driving capability and is equipped with a write equalization circuit to ensure the signal consistency between the bit line and the anti-phase line. All of these ensure that read / write operations can be performed quickly and reliably.

[0034] Furthermore, the inverters within the memory cells can employ a high-speed, low-power structure. Transistor size and threshold voltage are precisely optimized, and the internal signal transmission path is optimized for layout to shorten signal transmission distance and reduce the impact of parasitic parameters. The transistors within the memory cells can utilize novel transistor structures such as Fin-FET or GAA-FET to improve transistor switching speed and drive capability, while reducing parasitic capacitance and leakage current. The advanced transistor structure and precisely optimized inverters within the memory cells provide faster switching speeds and stronger drive capability, enabling data storage and transmission operations to be completed in a shorter time. Simultaneously, the transistor size and threshold voltage of the inverters are optimized to reduce power consumption while ensuring sufficient drive capability, achieving a good balance between speed and power consumption. This allows the memory cells to respond quickly to read and write signals, improving the read and write performance of SRAM. The internal signal transmission path of the memory cells is carefully laid out and optimized to minimize signal transmission distance and reduce the impact of parasitic capacitance and inductance. Parasitic parameters increase signal transmission delay and power consumption; by reducing these parasitic effects, the signal propagation speed within the memory cells can be effectively improved, further accelerating the execution of read and write operations.

[0035] It should be noted that the specific model and specifications need to be selected and determined based on the actual specifications of the device. The specific selection and calculation method adopts the existing technology in this field, so it will not be described in detail here.

[0036] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the invention should be included within the scope of protection of the invention.

Claims

1. A circuit implementation method for improving SRAM read / write speed, comprising: The SRAM storage cell is characterized in that the SRAM storage cell includes a transistor assembly and an inverter assembly. The transistor assembly includes transistor one (1), transistor two (2), transistor three (3), transistor four (6), transistor five (7) and transistor six (8). The inverter assembly includes inverter one (4) and inverter two (5). Transistor two (2) is connected to RWL1. RWL1 is connected to RBL1. Transistor three (3) is connected to BL, WWL and Q nodes. Transistor four (6) is connected to BLB and QB nodes. Transistor five (7) is connected to RWL2. RWL2 is connected to RBL2. The SRAM storage cell is provided in a plurality of units. The plurality of SRAM storage cells are arranged in an n-row m-column array. The plurality of SRAM storage cells contain a plurality of storage cells (bitcells). In the circuit, RWL1 is the first read word line, RBL1 is the first read bit line, BL is the bit line, WWL is the write word line, BLB is the reverse bit line, RWL2 is the second read word line, and RBL2 is the second bit fetch line. The specific steps are as follows: S1: During the high-level time of the SRAM input clock, address 1 is decoded, and one of RWL11-RWL1n is selected to be turned on. The selected RWL1x is pulled high when the SRAM input clock cuts from high to low. At this time, the address decoding circuit adopts a decoding method that combines parallel and segmented decoding to quickly convert the address signal into a row strobe signal. S2: During the low-level period of the SRAM input clock, read and write operations are performed on the selected bit cell. The corresponding data is read through RBL11-RBL1m. At the same time, address 2 is decoded, and one of RWL21-RWL2n is selected to be turned on. The selected RWL2x is pulled high when the SRAM input clock switches from low to high. S3: During the time when the SRAM input clock switches to high level again, read and write operations are performed on the currently selected bit cell. The corresponding data is read through RBL21-RBL2m. At the same time, address 3 is decoded, and one of RWL11-RWL1n is selected to be turned on. The selected RWL1x is pulled high when the SRAM input clock switches from high to low. S4: Continue following the pipeline algorithm implementation method of S1-S3 above until the last address is read, completing the entire SRAM read and write operation.

2. The circuit implementation method for improving SRAM read / write speed according to claim 1, characterized in that, The source of transistor 1 (1) is grounded, the drain of transistor 1 (1) is connected to the source of transistor 2 (2), and the gate of transistor 1 (1) is connected to inverter 1 (4), inverter 2 (5) and Q node respectively.

3. The circuit implementation method for improving SRAM read / write speed according to claim 1, characterized in that, The drain of transistor 2 (2) is connected to the first read bit line, and the gate of transistor 2 (2) is connected to the first read word line.

4. The circuit implementation method for improving SRAM read / write speed according to claim 1, characterized in that, The source of transistor three (3) is connected to the bit line, the gate of transistor three (3) is connected to the write word line, the drain of transistor three (3) is connected to the Q node, and the Q node is connected to the output terminal of inverter one (4) and the input terminal of inverter two (5) respectively.

5. The circuit implementation method for improving SRAM read / write speed according to claim 1, characterized in that, The source of transistor six (8) is grounded, the gate of transistor six (8) is connected to inverter one (4), inverter two (5) and QB node respectively, and the drain of transistor six (8) is connected to the source of transistor five (7).

6. The circuit implementation method for improving SRAM read / write speed according to claim 1, characterized in that, The gate of transistor five (7) is connected to the second read word line, and the drain of transistor five (7) is connected to the second read bit line.

7. The circuit implementation method for improving SRAM read / write speed according to claim 1, characterized in that, The source of transistor four (6) is connected to the anti-phase line, the gate of transistor four (6) is connected to the write line, the drain of transistor four (6) is connected to the QB node, and the QB node is connected to the input terminal of inverter one (4) and the output terminal of inverter two (5) respectively.

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