Memory and electronic device

Abstract

The application discloses a memory and an electronic device. The memory comprises a digit line, a local bit line, a storage unit, a bit line and a word line connected with the storage unit, a first gating transistor and a second gating transistor. At least one of the first gating transistor and the second gating transistor is a P-channel transistor. Compared with the case that both the first gating transistor and the second gating transistor are N-channel transistors, the equivalent parasitic capacitance of the bit line can be reduced at the moment when the storage unit is turned on, so that the duration of the overshoot current is shortened.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a memory and an electronic device. BACKGROUND

[0002] Phase change memory (PCM) is to use the reversible conversion characteristics between crystalline state and amorphous state of phase change material under different heat to realize data storage. For example, when the storage unit is in crystalline state, the data stored is "1"; when the storage unit is in amorphous state, the data stored is "0".

[0003] However, since the conduction time of the storage unit cannot be predicted, it is difficult to suppress the overshoot energy brought by the conduction moment of the storage unit, which increases the interference factors of operation, thereby affecting the performance of the memory. SUMMARY

[0004] The present application provides a memory and an electronic device to alleviate the technical problem of long duration of overshoot current when the storage unit is turned on.

[0005] In a first aspect, the present application provides a memory, which comprises a digit line, a local bit line, a storage unit arranged in an array, a bit line and a word line connected with each storage unit, a first selection transistor and a second selection transistor, the first electrode of the first selection transistor is connected with the bit line, the second electrode of the first selection transistor is connected with the local bit line, and the gate of the first selection transistor is connected with a first selection line; the first electrode of the second selection transistor is connected with the local bit line, the second electrode of the second selection transistor is connected with the digit line, and the gate of the second selection transistor is connected with a second selection line; wherein at least one of the first selection transistor and the second selection transistor is a P-channel transistor.

[0006] In a second aspect, the present application provides an electronic device, which comprises the above-mentioned memory.

[0007] The memory and the electronic device provided by the present application can reduce the equivalent parasitic capacitance of the bit line at the moment when the storage unit is turned on by configuring at least one of the first selection transistor and the second selection transistor as a P-channel transistor, compared with both the first selection transistor and the second selection transistor being N-channel transistors, thereby shortening the duration of the overshoot current. BRIEF DESCRIPTION OF DRAWINGS

[0008] The technical solutions and other beneficial effects of the present application will become apparent from the following detailed description of specific embodiments of the present application, taken in conjunction with the accompanying drawings.

[0009] Figure 1 It is a first structure schematic diagram of the memory in the related art.

[0010] Figure 2 Figure 1 is a schematic diagram of an equivalent circuit of a memory cell in the related art.

[0011] Figure 3 Figure 2 is a schematic diagram of a distribution of threshold voltages of a memory cell in the related art.

[0012] Figure 4 Figure 3 is a schematic diagram of a variation of threshold voltages of a memory cell in the related art.

[0013] Figure 5 Figure 4 is a schematic diagram of a comparative variation of threshold voltages of a memory cell in the related art.

[0014] Figure 6 Figure 5 is a schematic diagram of a comparative distribution of threshold voltages of a memory cell in the related art.

[0015] Figure 7 Figure 6 is a schematic diagram of compensation of time current in the related art.

[0016] Figure 8 Figure 7 is a schematic diagram of a second structure of a memory in the related art.

[0017] Figure 9 Figure 8 is a schematic diagram of a first structure of a memory provided by an embodiment of the present application.

[0018] Figure 10 Figure 9 is a schematic diagram of a second structure of a memory provided by an embodiment of the present application.

[0019] Figure 11 Figure 10 is a schematic diagram of a third structure of a memory provided by an embodiment of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person skilled in the art without creative work fall within the scope of protection of the present application.

[0021] In addition, the terms "first", "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features, so that the features with "first", "second" can explicitly or implicitly include one or more of the features, and in the description of the present application, the meaning of "multiple" is two or more, unless otherwise explicitly and specifically limited.

[0022] Figure 1This is a schematic diagram of a first structure of a memory in the related art. The memory includes bit lines BL, word lines WL, a memory array, word line gating circuit 20, and bit line gating circuit 10. The memory array includes memory cells Mcell distributed in an array. The bit lines BL include, for example, the first bit line BL1, the second bit line BL2, and the third bit line BL3, etc. The word lines WL include, for example, the first word line WL1, the second word line W2L, and the third word line WL3, etc. Each memory cell Mcell is connected to the bit line gating circuit 10 through the bit line BL, and each memory cell Mcell is connected to the word line gating circuit 20 through the word line WL.

[0023] Figure 2 This is a schematic diagram of the equivalent circuit of a memory cell Mcell in related technologies. The first parasitic resistance Rwl is the parasitic resistance of the word line WL. The second parasitic resistance Rbl is the parasitic resistance of the bit line BL. The first parasitic capacitance Cwl is the parasitic capacitance of the word line WL. The second parasitic capacitance Cbl is the parasitic capacitance of the bit line BL. Vwl represents the voltage of the word line WL, and Vwl' represents the voltage of the word line WL considering parasitic capacitive impedance. Vbl represents the voltage of the bit line BL, and Vbl' represents the voltage of the bit line BL considering parasitic capacitive impedance.

[0024] like Figure 3 As shown, Couter represents the number of memory cells Mcells in the memory, and Vth represents the threshold voltage of the memory cell Mcell. In phase-change memory, the memory cells Mcells in the crystalline and amorphous states correspond to different threshold voltages. Specifically, the threshold voltage (Vth_SET) of a memory cell Mcell in the crystalline state is lower than the threshold voltage (Vth_RESET) of a memory cell Mcell in the amorphous state.

[0025] The memory cell Mcell can be switched between a crystalline and amorphous state by applying different forms of heat. The programming operation of writing a "1" to the memory cell Mcell is defined as a SET operation, and the programming operation of writing a "0" to the memory cell Mcell is defined as a RESET operation. By applying a read voltage (Vread) greater than Vth_SET and less than Vth_RESET to the selected memory cell Mcell, the crystalline state of the memory cell Mcell can be opened, but the amorphous state of the memory cell Mcell cannot be opened, thus enabling the reading operation of data in the memory cell Mcell.

[0026] The memory cell Mcell includes a bidirectional threshold switch (Ovonic Threshold Switch, OTS) made of a volatile nonlinear resistive material that can suddenly change from a high resistance state to a low resistance state under the action of a threshold voltage, and in order to maintain the low resistance state, the on voltage (current) needs to be greater than a certain value, which is generally defined as Vhold(Ihold). Due to the above characteristics of the material and its easy integration, and the process node is constantly shrinking without changing the above characteristics, making it a core device of three-dimensional phase change memory.

[0027] Three-dimensional phase change memory generally refers to 3D Cross point PCM or 3D X-point PCM storage that stacks multiple layers of planar cross array, and the memory cell Mcell is a 1T1R structure that integrates the phase change material and the bidirectional threshold switch together, which has the characteristics of scalability and stackability.

[0028] The threshold voltage of the bidirectional threshold switch is offset with the polarity of the applied voltage, and the storage based on the selector only memory (OTS-only memory) of the bidirectional threshold switch also becomes another technical direction of storage.

[0029] After the wafer on which the memory array is located is factory-out (Fab-out), the influence of the flatness that may be introduced by the lower layer as the driving complementary metal oxide semiconductor (CMOS) and the punch is excluded, and the threshold voltages of all memory cells Mcell are uniformly distributed. In other words, the normal distribution curve of the threshold voltage of the initial memory cell Mcell should only be related to each production step in its production process, and will not show the case that the threshold voltages are inconsistent due to different physical positions, which refers to the distance position between the memory cell Mcell and the word line selection circuit 20 and / or the bit line selection circuit 10.

[0030] As shown in Figure 4 The initial threshold voltage (Vth_inital) of the memory cell Mcell is too high to be directly used, and needs to be seasoned (formed / first fired) for a period of time to reach the relatively saturated and stable Vth_SET and Vth_RESET for normal programming and reading and writing. The seasoning process usually applies a certain number of reset (RESET) voltages, currents and times much higher than normal operation to the memory cell Mcell to achieve this purpose, and in some cases, a small amount of set (SET) operation may also be superimposed to achieve the purpose of quickly saturating Vth_SET and Vth_RESET.

[0031] The material properties of current phase change memory determine that the threshold voltage after seasoning is only relatively saturated, and the threshold voltage (Vth) of the memory cell Mcell will decrease slowly with the increase of the operation number (Cycle), and this process will continue throughout the cycle of the memory cell Mcell, and the threshold voltage reduction rate will gradually slow down.

[0032] The energy (E) generated by the programming process of the memory cell Mcell contains two parts, one part is from the inrush current of the memory cell Mcell at the moment of conduction, and the other part is from the set direct current. The calculation method of E is shown in formula 1-1:

[0033]

[0034] Where, R on represents the on-resistance of the memory cell Mcell. I inrush represents the inrush current, t inrush represents the duration of the inrush current. I DC represents the direct current, t DC represents the duration of the direct current.

[0035] The inrush current at time 0 can be approximately expressed by formula 1-2 as follows:

[0036]

[0037] Where, V` wlt0- represents the word line WL voltage at time 0. V` blt0- represents the bit line BL voltage at time 0. V` wlt0 represents the word line WL voltage at time 0. V` blt0 represents the bit line BL voltage at time 0. λ is a constant.

[0038] The inrush current at time t can be approximately expressed by formula 1-3 as follows:

[0039]

[0040] The inrush current at time t can be approximately expressed by formula 1-3 as follows:

[0041]

[0042] Where,

[0043] Wherein, since the direct current and its duration are determined by different chips TBD (Trim by die). From the above expression, it can be seen that the overshoot energy is directly related to the equivalent parasitic resistance and capacitance of the word line WL and the bit line BL. The parasitic resistance of the storage unit Mcell far away from the bit line selection circuit 10 or the word line selection circuit 20 is small, so the overshoot current is small. If the same direct current and its duration are used, the energy must be different.

[0044] As shown in Figure 5 , this will cause the threshold voltage of the storage unit Mcell far away from the bit line selection circuit 10 or the word line selection circuit 20 to have a decreasing trend as shown by the first curve S1, and the threshold voltage of the storage unit Mcell close to the bit line selection circuit 10 or the word line selection circuit 20 to have a decreasing trend as shown by the second curve S2.

[0045] As shown in Figure 6 , Vth_near on the left of the read voltage (Vread) represents the normal distribution curve of the threshold voltage of the storage unit Mcell in the set state and close to the bit line selection circuit 10 or the word line selection circuit 20. Vth_far on the left of the read voltage (Vread) represents the normal distribution curve of the threshold voltage of the storage unit Mcell in the set state and far away from the bit line selection circuit 10 or the word line selection circuit 20. Vth_near on the right of the read voltage (Vread) represents the normal distribution curve of the threshold voltage of the storage unit Mcell in the reset state and close to the bit line selection circuit 10 or the word line selection circuit 20. Vth_far on the right of the read voltage (Vread) represents the normal distribution curve of the threshold voltage of the storage unit Mcell in the reset state and far away from the bit line selection circuit 10 or the word line selection circuit 20.

[0046] Figure 5 The different decreasing trends of the threshold voltage of the storage unit Mcell shown in Figure 6 , will cause the read window loss, i.e. RWM-loss, shown in , and further affect the read accuracy. Therefore, to ensure that the total operation energy is constant, position compensation needs to be performed on the storage unit Mcell to ensure that the operation energy of the storage unit Mcell at each position is as equal as possible.

[0047] Since seasoning is also an energy-intensive programming operation, the seasoning stage also needs to keep the far-end and near-end energies as consistent as possible, otherwise it will also introduce different threshold voltages at different positions similar to the programming stage.

[0048] The overcurrent has large energy, so the direct current in the reset state of the TBD can be reduced, which seems to have benefits from the perspective of power consumption. However, the excessive overcurrent can cause higher energy in an instant, and further cause read disturb and write disturb, thereby affecting the performance of the memory.

[0049] The overcurrent has large energy, and the excessive heat can also cause an increase in the crystallization time during the crystallization operation. The programming time is determined by the crystallization time, and further can cause write delay.

[0050] In addition, the storage unit Mcell is continuously impacted by a large current density, which can also cause element segregation in the OTS. For example, it is observed that the Se element concentration that inhibits crystallization decreases with an increase in the number of operations, causing the threshold voltage to continue to decrease with an increase in the number of operations, and the endurance decreases. Moreover, this effect is irreversible.

[0051] Figure 7 A compensation diagram of the time current in the related art is shown. The third curve S3 represents the change curve of the current pulse received by the storage unit Mcell close to the bit line selection circuit 10 or the word line selection circuit 20, and the fourth curve S4 represents the change curve of the current pulse received by the storage unit Mcell far from the bit line selection circuit 10 or the word line selection circuit 20. The current difference between the third curve S3 and the fourth curve S4 is represented by ΔI, and the time difference between the third curve S3 and the fourth curve S4 is represented by Δt.

[0052] In order to balance the current pulse received by the storage unit Mcell at each position, at least one of the current difference and the time difference can be used.

[0053] Figure 8 A second structure diagram of the memory in the related art is shown. The memory includes a digit line DL, a local bit line LBL, a storage unit Mcell, a bit line BL and a word line WL connected to the storage unit Mcell, a first selection transistor T1, and a second selection transistor T2. The first electrode of the first selection transistor T1 is connected to the bit line BL, the second electrode of the first selection transistor T1 is connected to the local bit line LBL, the first electrode of the second selection transistor T2 is connected to the local bit line LBL, and the second electrode of the second selection transistor T2 is connected to the digit line DL. The first selection transistor T1 and the second selection transistor T2 are both N-channel transistors.

[0054] It should be noted that, Figure 8 The working process of the memory is as follows:

[0055] Before a certain memory cell Mcell is selected, the voltage of the bit line BL is exemplarily V1, the voltage of the local bit line LBL and the voltage of the digit line DL are both exemplarily V1 or V2, V1 is greater than V2, V2 is a negative voltage, the gate voltage of the first select transistor T1 and the gate voltage of the second select transistor T2 are both exemplarily V1 or V2, then the gate-source voltage difference (Vgs) of the first select transistor T1 and the gate-source voltage difference of the second select transistor T2 are both less than or equal to V1, since the threshold voltage (Vth_N) of the N-channel transistor is positive, Vth_N is greater than V1, thus the gate-source voltage difference (Vgs) of the first select transistor T1 and the gate-source voltage difference of the second select transistor T2 are both less than their own threshold voltage, and are in an off state.

[0056] When the memory cell Mcell is selected, the gate voltage of the first select transistor T1 and the gate voltage of the second select transistor T2 are both exemplarily V1 (indicating that the corresponding memory cell Mcell is selected), at this time the voltage of the digit line DL is Vneg (V2), then the Vgs of the second select transistor T2 is greater than its own Vth_N, so the second select transistor T2 is turned on, the drain voltage of the second select transistor T2 is pulled to the voltage equal to its source voltage, i.e. Vneg, and the first select transistor T1 is also turned on for the same reason, the drain voltage of the first select transistor T1 is pulled to the voltage equal to its source voltage, i.e. Vneg.

[0057] Thereafter, the voltage of the word line WL rises to the threshold voltage of the memory cell Mcell, the memory cell Mcell is turned on, and the read / write operation on the memory cell Mcell is started. In this process, since the memory cell Mcell is selected, the first select transistor T1 and the second select transistor T2 are turned on, thus the equivalent parasitic capacitance of the bit line BL is equivalent to the equivalent series capacitance of Cbl, Clbl and Cdl, which increases the equivalent parasitic capacitance of the bit line BL, so that the duration of the overshoot energy is longer when the memory cell Mcell is turned on.

[0058] The embodiment provides a memory, please refer to Figure 9 to Figure 11The memory comprises a digit line DL, a local bit line LBL, a memory cell Mcell arranged in an array, a bit line BL and a word line WL connected to each memory cell Mcell, a first selection transistor T1, and a second selection transistor T2, a first electrode of the first selection transistor T1 is connected to the bit line BL, a second electrode of the first selection transistor T1 is connected to the local bit line LBL, and a gate electrode of the first selection transistor T1 is connected to a first selection line SL1; a first electrode of the second selection transistor T2 is connected to the local bit line LBL, a second electrode of the second selection transistor T2 is connected to the digit line DL, and a gate electrode of the second selection transistor T2 is connected to a second selection line SL2; wherein at least one of the first selection transistor T1 and the second selection transistor T2 is a P-channel transistor.

[0059] It can be understood that the memory provided by the embodiment can reduce the equivalent parasitic capacitance of the bit line BL at the moment when the memory cell Mcell is turned on, compared with the case that both the first selection transistor T1 and the second selection transistor T2 are N-channel transistors, thereby shortening the duration of the overshoot current.

[0060] In some embodiments, as shown in Figure 9 , Figure 10 the channel type of the first selection transistor T1 is different from the channel type of the second selection transistor T2.

[0061] It should be noted that by configuring the channel type of the first selection transistor T1 to be different from the channel type of the second selection transistor T2, compared with the case that both the first selection transistor T1 and the second selection transistor T2 are N-channel transistors, the equivalent parasitic capacitance of the bit line BL can be reduced at the moment when the memory cell Mcell is turned on, thereby shortening the duration of the overshoot current.

[0062] In some embodiments, as shown in Figure 9 the first selection transistor T1 is an N-channel transistor, and the second selection transistor T2 is a P-channel transistor; the drain electrode of the first selection transistor T1 is connected to the bit line BL, and the source electrode of the first selection transistor T1 is connected to the local bit line LBL; the source electrode of the second selection transistor T2 is connected to the local bit line LBL, and the drain electrode of the second selection transistor T2 is connected to the digit line DL.

[0063] It should be noted that before a certain memory cell Mcell is selected, the Vgs of the second selection transistor T2 is less than the absolute value of its own threshold voltage, and the second selection transistor T2 is in an off state. The Vgs of the first selection transistor T1 is less than its own threshold voltage, and therefore the first selection transistor T1 is in an off state.

[0064] When the memory cell Mcell is selected, the gate voltage of the second pass transistor T2 is Vneg (V2), the source voltage of the second pass transistor T2 is VI, and |Vgs| of the second pass transistor T2 = |V2-V1|, which is greater than the absolute value of its threshold voltage, thus the second pass transistor T2 is turned on. Since the voltage of the digit line DL is Vneg, the voltage of the local bit line LBL, i.e. the source voltage of the second pass transistor T2, is pulled to Vneg+|Vth_P|, |Vgs| of the second pass transistor T2 = |V2-(Vneg+|Vth_P|)|, which is equal to the absolute value of its threshold voltage, and the second pass transistor T2 is almost in an off state.

[0065] The gate voltage of the first pass transistor T1 is VI, and the source voltage of the first pass transistor T1 is Vneg+|Vth_P|, thus Vgs of the first pass transistor T1 = VI-(Vneg+|Vth_P|), which is greater than its threshold voltage, and the first pass transistor T1 is turned on. The voltage of the bit line BL, i.e. the drain voltage of the first pass transistor T1, is pulled to the source voltage, i.e. Vneg+|Vth_P|, which is equal to it. This makes Cbl not be in series with Cdl, and the equivalent parasitic capacitance of the bit line BL is Cbl+Clbl, which is smaller than the equivalent parasitic capacitance received by the bit line BL in the prior art, thus the equivalent parasitic capacitance is reduced, and the duration of the overshoot current is also shortened. Figure 8

[0066] As the voltage of the word line WL rises, when the threshold voltage of the memory cell Mcell is reached, the memory cell Mcell is turned on, and the voltage of the bit line BL rises rapidly, thus the source voltage of the second pass transistor T2 also rises rapidly. When |Vgs| of the second pass transistor T2 is greater than |Vth_P| of the second pass transistor T2, the second pass transistor T2 is automatically turned on, and the read / write operation on the memory cell Mcell is started. This shows that although the channel type of the corresponding transistor is changed, it does not affect the normal operation.

[0067] In some embodiments, as shown in Figure 10 the first pass transistor T1 is a P-channel transistor, and the second pass transistor T2 is an N-channel transistor; the source of the first pass transistor T1 is connected with the bit line BL, and the drain of the first pass transistor T1 is connected with the local bit line LBL; the drain of the second pass transistor T2 is connected with the local bit line LBL, and the source of the second pass transistor T2 is connected with the digit line DL.

[0068] ​It is to be noted that before the memory cell Mcell is selected, the voltage of the bit line BL is exemplarily V1, the voltage of the source of the first pass transistor T1 is also V1, the voltage of the gate of the first pass transistor T1 is V1, and the Vgs of the first pass transistor T1 is less than the absolute value of its threshold voltage, i.e. |Vth_P|, so the first pass transistor T1 is in the off state. The voltage of the gate of the second pass transistor T2 is Vneg (V2). The voltage of the digit line DL is Vneg, and the voltage of the source of the second pass transistor T2 is also Vneg, so the Vgs of the second pass transistor T2 is less than its threshold voltage, and the second pass transistor T2 is in the off state.

[0069] When the memory cell Mcell is selected, the voltage of the gate of the second pass transistor T2 is V1, the voltage of the digit line DL is Vneg, the voltage of the source of the second pass transistor T2 is also Vneg (V2), the Vgs of the second pass transistor T2 is V1-V2, which is greater than its threshold voltage, so the second pass transistor T2 is turned on, and the voltage of the local bit line LBL, i.e. the voltage of the drain of the second pass transistor T2, is pulled to Vneg. The voltage of the gate of the first pass transistor T1 is V2, and the voltage of the source of the first pass transistor T1 is V1, so the |Vgs| of the first pass transistor T1 is |V2-V1|, which is greater than the absolute value of its threshold voltage, and the first pass transistor T1 is turned on, and the voltage of the bit line BL, i.e. the voltage of the source of the first pass transistor T1, is pulled down to Vneg+|Vth_P|. At this time, the |Vgs| of the first pass transistor T1 is |V2-(Vneg+|Vth_P|)|, which is equal to the absolute value of its threshold voltage, and the first pass transistor T1 is almost in the off state. This makes Cbl not be connected in series with Clbl and Cdl, and the equivalent parasitic capacitance of the bit line BL is Cbl, which is smaller than the equivalent parasitic capacitance received in the prior art, so the duration of the overshoot current is also shortened. Figure 8

[0070] As the voltage of the word line WL rises, when the threshold voltage of the memory cell Mcell is reached, the memory cell Mcell is turned on, and the voltage of the bit line BL rises rapidly, so the voltage of the source of the first pass transistor T1 also begins to rise. When the |Vgs| of the first pass transistor T1 is greater than |Vth_P| of the first pass transistor T1, the first pass transistor T1 is automatically turned on, and the read / write operation on the memory cell Mcell is started. This shows that although the channel type of the corresponding transistor is changed, it does not affect the normal operation.

[0071] In some embodiments, as shown in FIG. 2, the first pass transistor T1 is a PMOS transistor, and the second pass transistor T2 is an NMOS transistor. Figure 10 ​As shown, the memory also includes a third transistor T3. The first terminal of the third transistor T3 is connected to the bit line BL, the second terminal of the third transistor T3 is connected to the initialization voltage line VSS, and the gate of the third transistor T3 is connected to the third gate line SL3.

[0072] It should be noted that before selecting a memory cell Mcell, the initial voltage of the voltage line VSS can be exemplarily set to V1, the source voltage of the third transistor T3 is V1, and the gate voltage of the third transistor T3 is Vneg(V2). Then, |Vgs| of the third transistor T3 = |V2-V1|, which is greater than |Vth_P| of the third transistor T3. Therefore, the third transistor T3 is turned on, and the voltage of the bit line BL is V1. This allows the third transistor T3 to provide an initial state voltage to the bit line BL, ensuring that the unselected memory cell Mcell is not mistakenly turned on due to the floating voltage of the bit line BL.

[0073] When the memory cell Mcell is selected, the gate voltage of the third transistor T3 is V1. Then, the |Vgs| of the third transistor T3 is less than the |Vth_P| of the third transistor T3 = 0.7V, and the third transistor T3 is turned off.

[0074] The turn-on time of the third transistor T3 is earlier than the turn-on time of the first select transistor T1. Optionally, the channel type of the third transistor T3 is the same as that of the first select transistor T1, for example, both are P-channel transistors.

[0075] In some of these embodiments, such as Figure 11 As shown, the first select transistor T1 is a P-channel transistor, and the second select transistor T2 is a P-channel transistor. The source of the first select transistor T1 is connected to the bit line BL, and the drain of the first select transistor T1 is connected to the local bit line LBL. The source of the second select transistor T2 is connected to the local bit line LBL, and the drain of the second select transistor T2 is connected to the digital line DL.

[0076] It should be noted that before a memory cell Mcell is selected, the voltage of the initialization voltage line VSS can be exemplarily V1, the voltage of the source of the third transistor T3 is V1, the voltage of the gate of the third transistor T3 is Vneg (V2), then |Vgs| of the third transistor T3 = |V2-V1|, which is greater than |Vth_P| of the third transistor T3, the third transistor T3 is turned on, the voltage of the bit line BL is V1, the voltage of the source of the first selection transistor T1 is also V1, the voltage of the gate of the first selection transistor T1 is V1, Vgs of the first selection transistor T1 is less than the absolute value of its threshold voltage, i.e., |Vth_P|, therefore, the first selection transistor T1 is in an off state. The voltage of the gate of the second selection transistor T2 is V1, the voltage of the source of the second selection transistor T2 is V1, therefore, Vgs of the second selection transistor T2 is less than the absolute value of its threshold voltage, and the second selection transistor T2 is in an off state.

[0077] When the memory cell Mcell is selected, the voltage of the gate of the third transistor T3 is V1, then |Vgs| of the third transistor T3 is less than |Vth_P| of the third transistor T3, and the third transistor T3 is turned off.

[0078] The voltage of the gate of the second selection transistor T2 is Vneg (V2), the voltage of the source of the second selection transistor T2 is V1, |Vgs| of the second selection transistor T2 = |V2-V1|, which is greater than its threshold voltage, i.e., |Vth_P|, therefore, the second selection transistor T2 is turned on. Since the voltage of the digital line DL is Vneg, the voltage of the local bit line LBL, i.e., the voltage of the source of the second selection transistor T2, is pulled to Vneg+|Vth_P|, at this time, |Vgs| of the second selection transistor T2 = |V2-(Vneg+|Vth_P|)|, which is equal to the absolute value of its threshold voltage, and the second selection transistor T2 is almost in an off state. This makes Cbl not be connected in series with Cdl, and the equivalent parasitic capacitance of the bit line BL is Cbl+Clbl, which is smaller than the equivalent parasitic capacitance received in the prior art, and therefore the duration of the overshoot current is shortened. Figure 8

[0079] ​The gate voltage of the first selection transistor T1 is V2, the source voltage of the first selection transistor T1 is V1, and thus |Vgs| of the first selection transistor T1 is |V2-V1|, which is greater than the absolute value of the threshold voltage of the first selection transistor T1, and the first selection transistor T1 is turned on. Since the drain voltage of the first selection transistor T1 is Vneg+|Vth_P|, the voltage of the bit line BL, i.e., the source voltage of the first selection transistor T1, is pulled down to Vneg+|Vth_P|+|Vth_P| = Vneg+2|Vth_P|, and at this time, |Vgs| of the first selection transistor T1 is |V2-(Vneg+2|Vth_P|)| = 1.4V, which is greater than the absolute value of the threshold voltage of the first selection transistor T1, and the first selection transistor is turned on.

[0080] With the voltage of the word line WL rising, when the threshold voltage of the storage unit Mcell is reached, the storage unit Mcell is turned on, the voltage of the bit line BL rises rapidly, and thus the source voltage of the first selection transistor T1 also rises rapidly. When |Vgs| of the first selection transistor T1 is greater than |Vth_P| of the first selection transistor T1, the first selection transistor T1 is automatically turned on, and then the source voltage of the second selection transistor T2 begins to rise. When |Vgs| of the second selection transistor T2 is greater than |Vth_P| of the second selection transistor T2, the second selection transistor T2 is automatically turned on, and the read / write operation on the storage unit Mcell is started. This shows that although the channel type of the corresponding transistor is changed, the normal operation is not affected.

[0081] In some embodiments, as shown in Figure 11 the memory further comprises a control module 30 connected with the digit line DL. The control module 30 is configured to have the control logic of the digit line DL to make corresponding compensation in current and / or time.

[0082] It should be noted that, in Figure 8 to Figure 11 Cbl is the parasitic capacitance of the bit line BL. Clbl is the parasitic capacitance of the local bit line LBL. Cdl is the parasitic capacitance of the digit line DL.

[0083] In summary, the present application reduces the duration of the overshoot current as much as possible, and reduces the energy of the overshoot current as much as possible, so as to ensure the operation uniformity of the storage unit Mcell at each position, and the consistent drop of the threshold voltage of the storage unit Mcell. For example, if the energy caused by the overshoot current is negligible, the overshoot energy of the storage unit Mcell at different positions is determined by the designed direct current (the change of the direct current is almost negligible) and the duration of the direct current, which can effectively reduce the design difficulty and the compensation difficulty for achieving the uniformity of the threshold voltage of the storage unit Mcell.

[0084] In some embodiments, the electronic device includes the memory as described above.

[0085] It can be understood that, since the electronic device provided by the embodiments includes the memory as described above, at least one of the first selection transistor T1 and the second selection transistor T2 can be configured as a P-channel transistor, compared with the first selection transistor T1 and the second selection transistor T2 being both N-channel transistors, the equivalent parasitic capacitance of the bit line BL can be reduced at the moment when the memory cell Mcell is turned on, thereby shortening the duration of the overshoot current.

[0086] It should be noted that the memory can be, but is not limited to, a phase change memory or a three-dimensional phase change memory, and can also be other applicable memory chips.

[0087] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0088] The memory and the electronic device provided by the embodiments of the present application are described in detail above, and the principle and implementation manner of the present application are described by applying specific examples in this paper. The above description of the embodiments is only used to help understand the technical solutions of the present application and the core idea thereof; those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory, comprising: The memory comprises: a digit line, a local bit line, a memory cell distributed in an array, and a bit line and a word line connected to each of the memory cells; a first selection transistor, a first electrode of the first selection transistor being connected to the bit line, a second electrode of the first selection transistor being connected to the local bit line, and a gate of the first selection transistor being connected to a first selection line; a second selection transistor, a first electrode of the second selection transistor being connected to the local bit line, a second electrode of the second selection transistor being connected to the digit line, and a gate of the second selection transistor being connected to a second selection line; wherein at least one of the first selection transistor and the second selection transistor is a P-channel transistor.

2. The memory of claim 1, wherein, The channel type of the first selection transistor is different from the channel type of the second selection transistor.

3. The memory of claim 2, wherein, The first selection transistor is an N-channel transistor, and the second selection transistor is a P-channel transistor. The drain of the first selection transistor is connected to the bit line, and the source of the first selection transistor is connected to the local bit line. The source of the second selection transistor is connected to the local bit line, and the drain of the second selection transistor is connected to the digit line.

4. The memory of claim 2, wherein, The first selection transistor is a P-channel transistor, and the second selection transistor is an N-channel transistor. The source of the first selection transistor is connected to the bit line, and the drain of the first selection transistor is connected to the local bit line. The drain of the second selection transistor is connected to the local bit line, and the source of the second selection transistor is connected to the digit line.

5. The memory of claim 4, wherein, The memory further comprises a third transistor, a first electrode of the third transistor being connected to the bit line, a second electrode of the third transistor being connected to an initialization voltage line, and a gate of the third transistor being connected to a third selection line.

6. The memory of claim 5, wherein, The channel type of the third transistor is the same as the channel type of the first selection transistor.

7. The memory of claim 6, wherein, The turn-on time of the third transistor is earlier than the turn-on time of the first selection transistor.

8. The memory of claim 1, wherein, The first selection transistor is a P-channel transistor, and the second selection transistor is a P-channel transistor. The source of the first selection transistor is connected to the bit line, and the drain of the first selection transistor is connected to the local bit line. The source of the second selection transistor is connected to the local bit line, and the drain of the second selection transistor is connected to the digit line.

9. The memory of any of claims 1-8, wherein, The memory further comprises a control module, the control module being connected to the digit line.

10. An electronic device, comprising: The electronic device comprises the memory according to any one of claims 1-9.

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