Real-time self-refreshing error correction method and device of three-state lookup memory and storage medium

Abstract

The invention discloses a real-time self-refreshing error correction method and device for a three-state lookup memory and a storage medium, and the method comprises the following steps: S01, a scheduling step: judging whether a service operation request exists at present or not, delaying a self-refreshing operation request if the service operation request exists, and executing the self-refreshing operation request when no operation exists so as to guarantee normal service performance; and the failure of real-time business operation caused by insertion of self-checking operation is avoided. According to the three-state search memory self-checking method, smaller hardware expenditure and higher robustness are provided for stable and safe operation of a chip for a three-state search memory self-checking technology. According to the method, whether the service operation request exists or not is judged, if yes, the self-refreshing operation request is delayed, and the self-refreshing operation request is executed when no normal service operation exists, so that normal service performance is guaranteed, and the situation that real-time service operation fails due to insertion of self-checking operation is avoided. According to the method, different levels of function security and hardware overhead are considered, and verification tags with different granularities can be configured to cover different levels of function security requirements.

Description

Technical Field

[0001] The present invention relates to the fields of functional safety, chip production testing technology, and storage technology, and in particular to a real-time self-refreshing error correction method, device, and storage medium for a ternary content addressable memory (TCAM). Background Art

[0002] A ternary content addressable memory (TCAM) is a memory that can represent more information based on the extension of a content addressable memory (CAM), and has read / write and search matching functions. Similar to the basic concept of CAM, it provides a keyword (Key) and the memory returns a matching index; but it has an additional state: the X state, also known as "don't care", which can match 0 or 1. This feature gives TCAM the function of fuzzy search and matching, and it is more widely used in search and matching fields such as Ethernet flow filtering and access control lists.

[0003] In the existing chip production testing technology, built-in self-testing methods are mostly used. However, traditional built-in self-testing requires entering the test mode, and it is impossible to judge the quality of internal logic or storage units during the real-time operation of the chip.

[0004] In the existing real-time self-testing technologies, such as the redundant backup scheme, a separate RAM is used to back up the same TCAM content. During testing, TCAM and RAM are read simultaneously to determine whether a fault has occurred inside TCAM. However, this will bring a huge area overhead, and using RAM for redundant backup will introduce new data interference and cause consistency problems. Another example is to use compression algorithms such as hashing to map the TCAM content into shorter data to reduce the backup area, and then restore the compressed data during the real-time operation of the chip and compare it with the internal data of TCAM. However, this scheme still lacks a reasonable and more robust fault handling method and cannot recover abnormal TCAM data. Summary of the Invention

[0005] In order to solve the above problems of the existing technical solutions, the present invention provides a self-test technology for a ternary content addressable memory, and more specifically, a method for real-time self-testing and self-correction of a ternary memory during normal operation of a chip, which provides smaller hardware costs and stronger robustness for the stable and safe operation of the chip to solve the above technical problems.

[0006] To achieve the above object, the present invention adopts the following technical solution: A real-time self-refreshing error correction method for a ternary content addressable memory, comprising the following steps:

[0007] S01, the scheduling step, is used to determine whether there is a service operation request currently, such as a search request, a CPU configuration label operation, etc. If there is, the self-refresh operation request is postponed, and it is sent into the instruction stream for execution when there is no normal service operation, so as to ensure normal service performance and prevent real-time service operations from failing due to the insertion of self-check operations.

[0008] Furthermore, it also includes the following steps:

[0009] S02, the data caching step, is used to configure a TCAM and a check label storage area placed inside the TCAM, for caching the data and check labels returned by the TCAM; S03, the data processing step, combines the built-in table entries of the TCAM, the corresponding check algorithms, and functional safety considerations, and selects the combination with the smallest sum of the table entry and the check label and the one that meets the target functional safety level for the final hardware implementation.

[0010] Furthermore, specifically for S03, the table entry width is split into different sizes, different check algorithms are selected to calculate the checksum for it, then the sum of the checksum size and the corresponding split table entry size is calculated, and parameters such as the diagnostic coverage rate under different check algorithms are calculated, so as to select the optimal combination.

[0011] Furthermore, in S03, in the scheme of dividing an entire TCAM table entry into n sub-table entries, the check results of the sub-table entries are divided into check tags 1, check tags 2, check tags 3... n, and each check result can be further divided into {1-bit error, 2-bit error}. There are four combinations: {0,0} means no check error, {1,0} means there is a 1-bit error but it can be corrected, {0,1} means there is a 2-bit error but it cannot be corrected, {1,1} means an impossible situation so it is marked as gray in the table; then each label result with only a 1-bit error but can be corrected is finally classified as a correctable result, and the results are divided into correctable situations, non-correctable situations, and uncorrectable situations; the final check result selection strategy is determined by the configuration issued by the CPU.

[0012] Furthermore, when n = 3, it is implemented according to the scheme of splitting into 3 sub-blocks. Excluding the impossible situations, there are 27 remaining; if considering providing the most excellent correction strategy, each label result with only a 1-bit error but can be corrected is finally classified as a correctable result. At this time, there are 10 correctable situations, 1 non-correctable situation, and 16 uncorrectable situations; if considering the overall error situation and taking the situation where only a 1-bit error can occur as the correctable strategy, there are 3 correctable situations, 1 non-correctable situation, and 23 uncorrectable situations.

[0013] Furthermore, it also includes the following steps:

[0014] S04 configures an exception handling module, which is used to count the final verification results and record the maintenance exception address table. If the verification result of the same address is marked as uncorrectable, the count is incremented and recorded in the exception address table. When the number exceeds the set threshold, the exception address table is reported to the CPU, including each address and the number of times each is marked as uncorrectable.

[0015] Furthermore, the TCAM exception address table stored in S04 is not recorded with complete address scales. Taking a 128-depth TCAM as an example, the bitmap method is adopted to map each address to 128 bit chains, and the relative position on the bit chain is used to represent the actual internal address of the TCAM to reduce the storage area.

[0016] Furthermore, the S03 includes:

[0017] A verification step, which is used to generate verification tags generated simultaneously with the configuration of the TCAM table entries, and parse the verification tags in the data cache module and perform verification to generate preliminary verification results;

[0018] A verification result processing step, which is used to collect preliminary verification results and mark abnormal addresses, and classify different final verification results according to the number of data blocks, such as uncorrectable, correctable, and error-free; and the verification algorithm can adopt algorithms such as ECC or HASH, etc. The algorithm recommended by the present invention is an algorithm with single-cycle implementation and compressibility;

[0019] A correction execution step, which is used to write the verified and corrected data back to the corresponding address of the original verification table entry according to the final verification result;

[0020] An address update step, which is used to judge the address generation of the next self-refresh operation.

[0021] The present invention also provides a real-time self-refresh error correction device for a three-state search memory, including one or more combinations of the following modules:

[0022] (1) A configuration coordination module, which is used to adjust the self-refresh interval under different service busy levels to meet different performance and power consumption requirements;

[0023] (2) An operation request module, which is used to receive the start enable of the CPU and generate a read operation enable instruction for reading TCAM table entries;

[0024] (3) An instruction scheduling module, which is used to judge the current working state of the TCAM, coordinate self-refresh instructions and service instructions, and avoid conflicts;

[0025] (4) A data cache module, which is used to cache the data and verification tags returned by the TCAM;

[0026] (5) A verification module, which is used to generate verification tags generated when configuring TCAM table entries, and parse and verify the verification tags in the data cache module to generate preliminary verification results;

[0027] (6) A verification result processing module, which is used to collect preliminary verification results and mark abnormal addresses, and classify different final verification results according to the number of data blocks, such as uncorrectable, correctable, and error-free; the verification algorithm can adopt algorithms such as ECC or HASH, and the algorithm recommended by the present invention is an algorithm with single-cycle implementation and compressibility;

[0028] (7) A correction execution module, which is used to write the verified and corrected data back to the corresponding address of the original verification table entry according to the final verification result;

[0029] (8) An address update module, which is used to judge the generation of the address for the next self-refresh operation;

[0030] (9) An exception handling module, which is used to count the final verification results and record and maintain the abnormal address table. If the verification result of the same address is marked as uncorrectable, the count is incremented and recorded in the abnormal address table. When the set threshold is exceeded, the abnormal address table is reported to the CPU, including each address and the number of times each is marked as uncorrectable; the TCAM abnormal address table stored in the exception handling module is not recorded in a complete address scale. Taking a 128-depth TCAM as an example, if a complete address needs to be recorded, each address requires 7 bits to represent, while the present invention adopts the bitmap method to map each address to a 128-bit chain, and uses the relative position on the bit chain to represent the actual internal address of the TCAM to reduce the storage area.

[0031] The present invention also provides a computer-readable storage medium containing a computer program, which, when executed by one or more processors, implements the real-time self-refresh error correction method of the three-state lookup memory described in any one of the above.

[0032] The present invention has the following advantages: The present invention is a self-check technology for three-state lookup memories, which is a method for the three-state memory to perform real-time self-checking and self-correction during the normal operation of the chip, providing smaller hardware costs and stronger robustness for the stable and safe operation of the chip. The scheduling module / scheduling method designed by the present invention, by judging whether there are current service operation requests such as lookup requests and CPU configuration label operations, if so, the self-refresh operation request will be postponed, and then sent into the instruction stream for execution when there is no normal service operation, so as to ensure normal service performance and prevent real-time service operations from failing due to the insertion of self-check operations. Brief Description of the Drawings

[0033] Figure 1Schematic diagram of a real-time self-refresh error correction device for a three-state search memory according to the present invention;

[0034] Figure 2 Schematic flow chart of the present invention. Specific embodiments

[0035] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0036] A real-time self-refresh error correction method for a three-state search memory includes the following steps:

[0037] S01, a scheduling step, used to determine whether there is a current service operation request, such as a search request, a CPU configuration label operation, etc. If so, the self-refresh operation request is postponed, and then sent to the instruction stream for execution when there is no normal service operation, so as to ensure normal service performance and prevent real-time service operations from failing due to the insertion of self-check operations.

[0038] In some embodiments, the method further includes the following steps:

[0039] S02, a data caching step, used to configure a TCAM and a check label storage area placed inside the TCAM for caching the data and check labels returned by the TCAM; considering that the behavior of the same area and device will be more consistent in the event of unexpected harsh conditions such as electromagnetic interference, the check label storage area of the present invention is placed inside the TCAM to improve the consistency of self-checking. At the same time, in order to reduce the hardware area overhead caused by introducing an additional label storage area. S03, a data processing step, in combination with the built-in table entries of the TCAM, the corresponding check algorithms, and functional safety considerations, selects the combination with the smallest sum of the table entry and the check label and meets the target functional safety level for the final hardware implementation.

[0040] Among them, S03 specifically is to split the table entry width into different sizes, select different check algorithms to calculate the checksum for it, then sum the checksum size and the corresponding split table entry size, and then calculate parameters such as the diagnostic coverage rate under different check algorithms, so as to select the optimal combination.

[0041] In S03, for the solution of dividing an entire TCAM table entry into n sub-table entries, the verification results of the sub-table entries are divided into n verification tags, namely verification tag1, verification tag2, verification tag3... n, and each verification result can be further divided into {1-bit error, 2-bit error}, with four combinations: {0,0} indicates no verification error, {1,0} indicates there is a 1-bit error but it can be corrected, {0,1} indicates there is a 2-bit error and it cannot be corrected, {1,1} indicates an impossible situation and is marked as gray in the table; then each label result with only a 1-bit error but can be corrected is finally classified as a correctable result, and the results are divided into correctable situations, situations that do not need to be corrected, and uncorrectable situations; the final verification result selection strategy is determined by the configuration issued by the CPU.

[0042] Taking n as 3 as an example, implemented according to the scheme of splitting into 3 sub-blocks, excluding impossible situations, there are 27 remaining; if considering providing the most excellent correction strategy, each label result with only a 1-bit error but can be corrected is finally classified as a correctable result. At this time, there are 10 correctable situations, 1 situation that does not need to be corrected, and 16 uncorrectable situations; if considering the overall error situation and taking the situation where only 1-bit error can occur as the correctable strategy, there are 3 correctable situations, 1 situation that does not need to be corrected, and 23 uncorrectable situations.

[0043] In some embodiments, the following steps are further included:

[0044] S04, configure an exception handling module, which is used to count the final verification results and record and maintain an exception address table. If the verification result of the same address is marked as uncorrectable, the count is incremented by one and recorded in the exception address table. When the number exceeds the set threshold, the exception address table is reported to the CPU, including each address and the number of times each is marked as uncorrectable.

[0045] The TCAM exception address table stored in S04 is not recorded on a complete address scale. Taking a 128-depth TCAM as an example, if a complete address is to be recorded, each address requires 7 bits to represent. However, the present invention adopts the bitmap method to map each address to a 128-bit chain, and uses the relative position on the bit chain to represent the actual internal address of the TCAM to reduce the storage area.

[0046] In some embodiments, the said S03 includes:

[0047] A verification step, which is used to generate the verification tags generated when configuring the TCAM table entry, and parse the verification tags in the data cache module and perform verification to generate preliminary verification results;

[0048] The verification result processing step is used to collect the preliminary verification results and mark the abnormal addresses, and classify different final verification results according to the number of data blocks, such as uncorrectable, correctable, and error-free. The verification algorithm can adopt algorithms such as ECC or HASH. The algorithm recommended by the present invention is an algorithm with single-cycle implementation and compressibility;

[0049] The correction execution step is used to write the verified and corrected data back to the corresponding address of the original verification table entry according to the final verification result;

[0050] The address update step is used to judge the generation of the address for the next self-refresh operation.

[0051] As Figure 2 shown, the present invention also provides a real-time self-refresh error correction device for a three-state search memory, including one or more combinations of the following modules:

[0052] (1) The configuration coordination module is used to adjust the self-refresh interval under different service busy levels to meet different performance and power consumption requirements;

[0053] (2) The operation request module is used to receive the start enable of the CPU and generate a read operation enable instruction for reading the TCAM table entry;

[0054] (3) The instruction scheduling module is used to judge the current working state of the TCAM, coordinate the self-refresh instruction and the service instruction, and avoid conflicts;

[0055] (4) The data cache module is used to cache the data and verification tags returned by the TCAM;

[0056] (5) The verification module is used to generate the verification tags generated when configuring the TCAM table entry, and parse the verification tags in the data cache module and perform verification to generate preliminary verification results;

[0057] (6) The verification result processing module is used to collect the preliminary verification results and mark the abnormal addresses, and classify different final verification results according to the number of data blocks, such as uncorrectable, correctable, and error-free. The verification algorithm can adopt algorithms such as ECC or HASH. The algorithm recommended by the present invention is an algorithm with single-cycle implementation and compressibility;

[0058] (7) The correction execution module is used to write the verified and corrected data back to the corresponding address of the original verification table entry according to the final verification result;

[0059] (8) The address update module is used to judge the generation of the address for the next self-refresh operation;

[0060] (9) An exception handling module, which is used to count the final verification results and record the maintenance exception address table. If the verification result of the same address is marked as uncorrectable, the count is incremented and recorded in the exception address table. When the number exceeds the set threshold, the exception address table is reported to the CPU, including each address and the number of times each is marked as uncorrectable; the TCAM exception address table stored in the exception handling module is not recorded in the complete address scale. Taking a 128-depth TCAM as an example, if a complete address is to be recorded, each address requires 7 bits to represent. However, the present invention adopts a bitmap method to map each address to a 128-bit chain, and uses the relative position on the bit chain to represent the actual internal address of the TCAM, so as to reduce the storage area.

[0061] Figure 2 The example of [description] provides four listed configurable parameters, but in actual design, there are more than just these four parameters that can be configured. The starting point for configurability is the four points of performance, power consumption, area, and verification function. If the parameter can bring an improvement in any of the above four points, it will be included in the design consideration. Of course, the final configuration implementation is to balance these four points after meeting the basic requirements.

[0062] The present invention also provides a computer-readable storage medium containing a computer program, which when executed by one or more processors, implements the real-time self-refreshing error correction method of the three-state lookup memory described in any one of the above.

[0063] Taking Figure 1 shown as an example, when the chip is powered on and the real-time lookup function is started, an initial address and a TCAM read operation request are generated, and the configured instruction scheduling module judges the state of the TCAM. If the state is Busy, it returns and continues to judge the TCAM state to wait for the next idle state of the TCAM; when it is not, the TCAM array operation is performed, and at the same time, the return data cache and the verification data cache are performed, and then it enters the verification module for verification. Subsequently, the verification results are aggregated and it is determined whether the results are correctable. The correctable ones enter the correction execution module for correction processing, and then return to the instruction scheduling module to judge the state of the TCAM; if the results are uncorrectable, they enter the error flag threshold judgment module. If the threshold is not exceeded, it directly transfers to the address update module for processing. If the threshold is exceeded, it is processed by the exception handling module and then enters the address update module for processing, and at the same time reports to the CPU; after the address update module processes, new TCAM read operation requests and addresses are generated as needed. Through this process, the drawback that other operations usually need to be blocked to test the TCAM itself can be solved, greatly improving the utilization rate of the TCAM and the forwarding efficiency during the operation of the Ethernet chip.

[0064] As shown in the table of Table 1:

[0065]

[0066]

[0067] This example selects the scheme of dividing an entire TCAM entry into 3 sub-entries. The verification results of the sub-entries are divided into three: verifying tag1, verifying tag2, and verifying tag3. And each verification result can be further divided into {1-bit error, 2-bit error}, with four combinations: {0,0} means no verification error, {1,0} means there is a 1-bit error but it can be corrected, {0,1} means there is a 2-bit error but it cannot be corrected, and {1,1} means an impossible situation, so it is marked as gray in the table. When implemented according to the scheme of splitting into 3 sub-blocks, excluding the impossible situations, there are 27 remaining. If considering providing the best correction strategy, each tag result with only a 1-bit error but can be corrected can be finally classified as a correctable result. At this time, there are 10 correctable situations, 1 situation without correction, and 16 uncorrectable situations. And if considering the overall error situation and taking only 1-bit error as the correctable strategy, there are 3 correctable situations, 1 situation without correction, and 23 uncorrectable situations. And the final verification result selection strategy is also determined by the CPU configuration. In the usual design, the selection of the verification tag is directly calculated at the granularity of the entry size. And this large-bitwidth verification algorithm not only occupies more hardware overhead but also has timing limitations, resulting in the chip clock frequency not being able to be too high, thus affecting the chip performance. And this scheme optimizes the selection of the verification algorithm to achieve the balance between hardware overhead and performance. In vehicle functional safety, the requirements for memory failures are different under different functional safety levels. And in the error correction algorithm, only 1 bit can be corrected each time. If you want to achieve a higher fault coverage rate, the error correction operations for each entry will increase accordingly, which will lead to an increase in chip power consumption. Therefore, this configurable error correction granularity is used to meet the functional safety requirements of different levels while minimizing the chip power consumption as much as possible.

[0068] The present invention has the following advantages: The present invention is a tri-state search memory self-check technology, which is a method for the tri-state memory to perform real-time self-check and self-correction during the normal operation of the chip, providing smaller hardware expenses and stronger robustness for the stable and safe operation of the chip. The scheduling module / scheduling method designed by the present invention, by judging whether there are current service operation requests such as search requests, CPU configuration tag operations, etc., if so, it will postpone the self-refresh operation request and send it into the instruction stream to execute when there is no normal service operation, so as to ensure the normal service performance and prevent the real-time service operation from failing due to the insertion of self-check operations.

[0069] In a usual memory built-in self-test scheme, the chip is required to enter the test mode, which may cause failures that may occur during the actual operation of the chip to be not covered. However, the present invention provides a self-test scheme that can be performed while the chip is running without affecting its performance, improving the robustness of the design and the in-vehicle functional safety level of the chip. According to the error correction scheme that weighs check tags and data, the present invention makes a trade-off between hardware overhead and functional safety. Considering different levels of functional safety and hardware overhead, check tags with different granularities can be configured to cover different levels of functional safety requirements. The present invention optimizes the selection of the combination of check tags and TCAM table entries, providing a scheme with less check storage space.

[0070] The present invention optimizes the processing of check results. It will judge whether the statistics of uncorrectable errors reach a threshold before reporting an interrupt and the entire address mapping table of the TCAM, avoiding soft errors introduced by the self-test operation itself and providing more complete fault information that occupies less area.

[0071] The present invention also provides a flexible configuration strategy, which takes into account the balance of performance, power consumption, area, and check function on the basis of achieving the basic design indicators.

[0072] The real-time self-refresh and self-correction scheme of the present invention can be extended to other storage medium fields.

[0073] The process described in the present invention can be implemented on integrated circuits including ASIC, FPGA, CPLD, etc.

[0074] As described above, the above are only the preferred specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution of the present invention and its inventive concept, makes equivalent substitutions or changes, and should be covered by the protection scope of the present invention.

Claims

1. A real-time self-refresh error correction method for a three-state search memory, characterized in that: The following steps are involved: S01, the scheduling step, is used to determine whether there is a business operation request at present. If so, the self-refresh operation request will be postponed and sent to the instruction stream for execution when there is no normal business operation, so as to ensure normal business performance and prevent the real-time business operation from failing due to the insertion of self-check operations.

2. The real-time self-refresh error correction method of the ternary lookup memory according to claim 1, characterized in that: The following steps are also included: S02, a data caching step, for configuring a storage area including the TCAM and a check tag placed inside the TCAM, for caching data and check tags returned by the TCAM; S03, the data processing step, combines the TCAM built-in table items, the corresponding verification algorithm and functional safety considerations, selects the combination with the smallest table item plus the verification tag and meets the target functional safety level for final hardware implementation.

3. The real-time self-refresh error correction method of the ternary lookup memory according to claim 2, characterized in that: S03 specifically involves splitting the table entry width into different sizes, selecting different verification algorithms to calculate and generate a checksum, then summing the checksum size with the corresponding split table entry size, and then calculating parameters such as the diagnostic coverage under different verification algorithms to select the optimal combination.

4. The real-time self-refresh error correction method of the ternary lookup memory according to claim 3, characterized in that: In S03, a whole TCAM table entry is divided into n blocks of sub-table entries, and the verification results of the sub-table entries are divided into verification tag1, verification tag2, verification tag3...n, and each verification result can be divided into {1-bit error, 2-bit error}, and there are four combinations: {0,0} means no verification error, {1,0} means there is a 1-bit error but it can be corrected, {0,1} means there is a 2-bit error but it cannot be corrected, and {1,1} is a situation that cannot happen, so it is marked in gray in the table; then each tag result with only 1-bit error but correctable is finally classified as a correctable result, and the results are divided into correctable situation, non-correctable situation, and uncorrectable situation; the final verification result selection strategy is determined by the configuration issued by the CPU.

5. The real-time self-refresh error correction method of the three-state search memory according to claim 4, characterized in that: When n is 3, the solution of splitting into 3 sub-blocks is implemented. After excluding impossible situations, there are still 27 situations left. If the best correction strategy is considered, each label result with only 1 bit error but correctable will be finally classified as a correctable result. At this time, there are 10 correctable situations, 1 situation that does not need to be corrected, and 16 uncorrectable situations. If the overall error situation is considered, and the strategy of only 1 bit error is taken as a correctable strategy, there are 3 correctable situations, 1 situation that does not need to be corrected, and 23 uncorrectable situations.

6. The real-time self-refresh error correction method of the ternary lookup memory according to claim 5, characterized in that: The following steps are also included: S04, configure the exception handling module to count the final verification results and record and maintain the exception address table. If the verification result of the same address is marked as uncorrectable, the statistical number is increased by one and recorded in the exception address table. When the number exceeds the set threshold, the exception address table is reported to the CPU, including each address and the number of times each address is marked as uncorrectable.

7. The real-time self-refresh error correction method of the ternary lookup memory according to claim 6, characterized in that: The TCAM exception address table stored in S04 is not recorded in full address scale. Taking a 128-depth TCAM as an example, a bitmap method is used to map each address to a 128-bit chain, and the relative position on the bit chain is used to represent the actual TCAM internal address to reduce the storage area.

8. The real-time self-refresh error correction method of a ternary lookup memory according to any one of claims 2 to 7, characterized in that: The S03 includes: A verification step is used to generate a verification tag generated when configuring the TCAM table entry, and to parse the verification tag in the data cache module and perform verification to generate a preliminary verification result; The verification result processing step is used to collect preliminary verification results and mark abnormal addresses, and classify different final verification results according to the number of data blocks, such as uncorrectable, correctable, and error-free; and the verification algorithm can adopt algorithms such as ECC or HASH. The present invention recommends the use of a single-cycle implementation and compressible algorithm; A correction execution step is used to write the corrected data back to the corresponding address of the original check table item according to the final check result; The address update step is used to determine the address generation for the next self-refresh operation.

9. A real-time self-refresh error correction device for a three-state search memory, characterized in that: Includes one or a combination of the following modules: (1) Configure a coordination module to adjust the self-refresh interval under different service busy levels to adapt to different performance and power consumption requirements; (2) an operation request module, used to receive a CPU startup enable and generate a read operation enable instruction for reading a TCAM table entry; (3) Instruction scheduling module, used to determine the current TCAM working status and coordinate self-refresh instructions and business instructions to avoid conflicts; (4) a data cache module, used to cache the data and check tags returned by the TCAM; (5) a verification module, used to generate a verification tag generated when configuring a TCAM table entry, and to parse the verification tag in the data cache module and perform verification to generate a preliminary verification result; (6) a verification result processing module, which is used to collect preliminary verification results and mark abnormal addresses, and classify different final verification results according to the number of data blocks, such as uncorrectable, correctable, and error-free; (7) a correction execution module, used to write the corrected data back to the corresponding address of the original check table entry according to the final check result; (8) an address update module, used to determine the address generation of the next self-refresh operation; (9) An exception handling module is used to count the final verification results and record and maintain the exception address table. If the verification result of the same address is marked as uncorrectable, the statistical number is increased by one and recorded in the exception address table. When the number exceeds the set threshold, the exception address table is reported to the CPU, including each address and the number of times each address is marked as uncorrectable. The TCAM exception address table stored in the exception handling module is not recorded in full address scale. Taking a 128-depth TCAM as an example, a bitmap method is used to map each address to a 128-bit chain, and the relative position on the bit chain is used to represent the actual TCAM internal address to reduce the storage area.

10. A computer-readable storage medium containing a computer program, characterized in that: When the computer program is executed by one or more processors, the real-time self-refresh error correction method for the ternary lookup memory according to any one of claims 1 to 8 is implemented.

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