Flash memory and test method thereof

Abstract

The invention provides a flash memory and a test method thereof. The test method comprises the following steps: executing an erase verification reference value adjustment step, namely adjusting an erase verification current from a normal erase verification current to an erase verification current for fast bit screening, and adjusting a soft programming verification current from a normal soft programming verification current to a soft programming verification current for fast bit screening; performing an erase operation on the plurality of memory cells, wherein a corresponding erase verify is performed using an erase verify current for fast bit screening; performing a soft programming operation on the plurality of memory cells, wherein a soft programming verification current for fast bit screening is used to perform a corresponding soft programming verification; and applying a test voltage to the word lines coupled to the plurality of memory cells so as to judge whether the plurality of memory cells are bad memory cells or normal memory cells according to the obtained cell current.

Description

Technical Field

[0001] The present invention relates to a method for testing a chip, and more particularly to a flash memory capable of reducing the number of memory cells having fast bit and low conductance characteristics and a method for testing the flash memory applicable to the chip probing stage. Background Art

[0002] In the process of manufacturing a flash memory, before the final package test, chip probing is performed on each chip in a wafer to screen out defective chips. For example, the cell current of a memory cell can be tested by applying a test voltage to a word line to which the memory cell is coupled, and defective memory cells can be screened out according to the magnitude of the cell current. In this way, redundant memory cells in the chip can be used to repair defective parts to reduce the manufacturing cost of the chip.

[0003] However, for defective memory cells with fast bit and low conductance characteristics, the starting position of the bit line voltage at which the cell current starts to be generated is small, and the conductance slope formed by the bit line voltage and the cell current is also small, resulting in the intersection of its current-voltage curve with the current-voltage curve of normal memory cells under normal test voltages. Therefore, it is difficult to screen out such defective memory cells.

[0004] With the miniaturization of flash memories, the screening of defective memory cells with fast bit and low conductance characteristics is more difficult to perform, resulting in a decrease in the yield and quality of flash memories. Summary of the Invention

[0005] The present invention provides a flash memory and a method for testing the same, which can improve the problem of poor screening efficiency of defective memory cells in the existing chip probing stage.

[0006] The method for testing the flash memory of the present invention includes the following steps: performing an erase verification reference value adjustment step, including adjusting the erase verification current from a normal erase verification current to an erase verification current for fast bit screening, and adjusting the soft programming verification current from a normal soft programming verification current to a soft programming verification current for fast bit screening, wherein the erase verification current for fast bit screening is greater than the normal erase verification current, and the soft programming verification current for fast bit screening is less than the normal soft programming verification current; performing an erase operation on a plurality of memory cells, wherein the corresponding erase verification is performed on the plurality of memory cells using the erase verification current for fast bit screening; performing a soft programming operation on the plurality of memory cells, wherein the corresponding soft programming verification is performed on the plurality of memory cells using the soft programming verification current for fast bit screening; and applying a test voltage to a word line to which the plurality of memory cells are coupled to determine whether the plurality of memory cells are defective memory cells or normal memory cells according to the obtained cell current.

[0007] The flash memory of the present invention includes a flash memory array and a memory control circuit. The flash memory array includes a plurality of memory cells. The memory control circuit is coupled to a plurality of word lines, a plurality of bit lines, and a plurality of source lines of the flash memory array. The memory control circuit is configured to: during testing, adjust the erase verification current from a normal erase verification current to a fast bit screening erase verification current, and adjust the soft programming verification current from a normal soft programming verification current to a fast bit screening soft programming verification current, wherein the fast bit screening erase verification current is greater than the normal erase verification current, and the fast bit screening soft programming verification current is less than the normal soft programming verification current; perform an erase operation on the plurality of memory cells, wherein the corresponding erase verification is performed on the plurality of memory cells using the fast bit screening erase verification current; perform a soft programming operation on the plurality of memory cells, wherein the corresponding soft programming verification is performed on the plurality of memory cells using the fast bit screening soft programming verification current; and apply a test voltage to the word lines to which the plurality of memory cells are coupled, so as to determine whether the plurality of memory cells are defective memory cells or normal memory cells according to the obtained cell current.

[0008] Based on the above, the flash memory of the present invention and its testing method can ensure that defective memory cells with fast bits and low conductance effects can be screened during the chip probing stage, and the testing time can be reduced. In this way, defective chips can be more easily screened out, thereby improving the repair rate and durability of the chips, and reducing the manufacturing cost of the chips.

[0009] To make the above features and advantages of this case more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings

[0010] Figure 1 It is a block diagram of a flash memory according to an embodiment of the present invention;

[0011] Figure 2 It is a schematic diagram of a summary of a memory cell of a flash memory according to an embodiment of the present invention;

[0012] Figure 3 、 Figure 4 and Figure 6 They are flowcharts of steps of a flash memory testing method according to some embodiments of the present invention;

[0013] Figure 5A It is an example of a current-voltage curve obtained by using the prior art;

[0014] Figure 5B and Figure 7 They are examples of current-voltage curves according to some embodiments of the present invention. Detailed Description of the Embodiments

[0015] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0016] Please refer to Figure 1 , the flash memory 100 includes a flash memory array 110, a memory control circuit 120, a column selection circuit 130, a page buffer and sense circuit 140, and a row selection circuit 150. The flash memory array 110 includes a plurality of memory cells 112. Please refer to Figure 2 , the memory cell 112 includes a floating gate 200, a control gate 210, a substrate 220, a source 230, and a drain 240. The control gate 210 is coupled to a corresponding word line WL, the source 230 is coupled to a corresponding source line SL, and the drain 240 is coupled to a corresponding bit line BL. For example, when a programming operation is performed, according to the decoding results of the address by the column selection circuit 130 and the row selection circuit 150, a programming voltage can be applied to the selected word line WL and bit line BL to change the potential of the corresponding floating gate 200. When an erase operation is performed, according to the decoding result of the address by the column selection circuit 130, an erase voltage can be applied to the selected word line WL to change the potential of the corresponding floating gate 200. Thus, when a read operation is performed, a read voltage can be applied to the word line WL, and the potential of the floating gate 200 can be determined according to the magnitude of the cell current Icell flowing through the source 230 and the drain 240 via the page buffer and sense circuit 140, so as to obtain the logical value stored in the memory cell 112.

[0017] The memory control circuit 120 can be designed by a hardware description language or any other design method of digital circuits well-known to those skilled in the art, and can be implemented by a field programmable gate array or a complex programmable logic device, etc., in addition to being, for example, a central processing unit, or other programmable general-purpose or special-purpose microprocessors, digital signal processors, programmable controllers, application-specific integrated circuits, programmable logic devices, or other similar devices or combinations of these devices.

[0018] Please also refer to Figure 1 and Figure 3 , the test method of the flash memory of this embodiment is applicable to Figure 1of the flash memory 100, and is performed, for example, during the chip probing stage. First, the memory control circuit 120 performs an erase verification reference value adjustment step, which includes adjusting the erase verification current from the normal erase verification current to the fast bit screening erase verification current, and adjusting the soft programming verification current from the normal soft programming verification current to the fast bit screening soft programming verification current (step S300). The fast bit screening erase verification current is greater than the normal erase verification current; the fast bit screening soft programming verification current is less than the normal soft programming verification current. In one example, the fast bit screening erase verification current can be at least 1.25 times the normal erase verification current, but the present invention is not limited thereto. In one example, the normal soft programming verification current can be at least 1.5 times the fast bit screening soft programming verification current, but the present invention is not limited thereto.

[0019] Next, the memory control circuit 120 performs an erase operation on the memory cells 112 in the flash memory array 110, wherein the fast bit screening erase verification current is used to perform corresponding erase verification on the memory cells 112 (step S310). Specifically, please refer to Figure 1 and Figure 4 , the erase operation includes step S400 and step S410. In step S400, the memory control circuit 120 applies an erase voltage to the word line WL coupled to each memory cell 112. Next, in step S410, the memory control circuit 120 can compare the cell current Icell of the memory cell 112 with the fast bit screening erase verification current to determine whether the cell current Icell of each selected memory cell 112 is greater than or equal to the fast bit screening erase verification current. If so, the memory control circuit 120 can end the erase operation. Conversely, when the cell current Icell of any one (or a predetermined number) of the selected memory cells 112 is less than the fast bit screening erase verification current, return to step S400 until the cell current Icell of all the memory cells 112 reaches the fast bit screening erase verification current.

[0020] Next, the memory control circuit 120 performs a soft programming operation on the memory cells 112 in the flash memory array 110, where a soft programming verification current for fast bit screening is used to perform corresponding soft programming verification on the memory cells 112 (step S320). Specifically, in an example of the soft programming operation, first, the memory control circuit 120 applies voltages corresponding to soft programming to the word line WL and the bit line BL coupled to each memory cell 112. Next, the memory control circuit 120 can compare the cell current Icell of the memory cell 112 with the soft programming verification current for fast bit screening to determine whether the cell current Icell of all memory cells 112 at this time is less than or equal to the soft programming verification current for fast bit screening. If so, the memory control circuit 120 can end the soft programming operation. Conversely, when the cell current Icell of any one (or a predetermined number) of these selected memory cells 112 is greater than the soft programming verification current for fast bit screening, the memory control circuit 120 will apply the soft programming voltage again and end the soft programming operation.

[0021] Through steps S300 to S320, it is possible to avoid the current-voltage curve formed by the bit line voltage and the cell current of defective memory cells having fast bits and low conductance effects from intersecting with the current-voltage curve of normal memory cells, and thus it is easier to identify defective memory cells having fast bits and low conductance effects.

[0022] As Figure 5A and Figure 5B shown, the horizontal axis is the word line voltage VWL (unit: volt) of the memory cell, and the vertical axis is the cell current Icell (unit: microampere) of the memory cell. As a control group of an embodiment of the present invention, Figure 5A represents the current-voltage curve graph without performing steps S300 to S320. Figure 5B represents the current-voltage curve graph after performing steps S300 to S320.

[0023] In Figure 5A , the current-voltage curve A1 of defective memory cells having fast bits and low conductance effects and the current-voltage curve A2 of normal memory cells are shown. As Figure 5A shown, when the word line voltage is the test voltage Vtest, the current-voltage curves A1 and A2 will intersect, so it is difficult to distinguish defective memory cells from normal memory cells using the cell current Icell, and screening cannot be carried out smoothly.

[0024] On the contrary, in Figure 5B , the current-voltage curve B1 of defective memory cells having fast bits and low conductance effects and the current-voltage curve B2 of normal memory cells are shown. As Figure 5B shown, the current-voltage curves B1 and B2 compared with Figure 5AThe current-voltage curves A1 and A2 in the figure are shifted (as shown by the arrows in the figure). When the word line voltage is the test voltage Vtest, the current-voltage curves B1 and B2 will not intersect, so the cell current Icell can be used to distinguish bad memory cells from normal memory cells, and screening can be carried out smoothly.

[0025] Please go back Figure 3 In step S330, the memory control circuit 120 applies a test voltage to the word line WL coupled to the memory cell 112 to screen the memory cell 112 according to the obtained cell current Icell. Specifically, when the cell current Icell is greater than or equal to a predetermined threshold value, the memory control circuit 120 determines that the tested memory cell 112 is a normal memory cell, otherwise it is determined to be a defective memory cell.

[0026] Optionally, the flash memory testing method of the present invention further includes step S340 to analyze the conductivity slope of the selected memory cell 112 and further eliminate bad memory cells according to the analysis result to improve the quality of the flash memory. Figure 6 Display the detailed process of step S340, Figure 7 Then display Figure 6 The execution result of Figure 7 In FIG. 1 , the horizontal axis represents the word line voltage VWL applied to the selected memory cell, and the vertical axis represents the cell current Icell read from the selected memory cell.

[0027] Please refer to Figure 1 , Figure 6 and Figure 7 , the memory control circuit 120 may apply M different test voltages Vtest to the N memory cells 112 in the flash memory array 110, respectively, and thereby obtain M cell currents I1-IM of each memory cell 112 corresponding to the M different test voltages Vtest (step S600). In one embodiment, the flash memory 100 may further include a state register 122 and a low conductance bit filter circuit 124, respectively coupled to the memory control circuit 120. The state register 122 is configured to determine whether the low conductance bit filter circuit 124 is enabled, and output an enable control signal Ctrl_EN to the low conductance bit filter circuit 124. For example, the state register 122 may determine whether the test time is less than a predetermined value, and when the test time is less than the predetermined value, output an enable control signal Ctrl_EN for enabling the low conductance bit filter circuit 124 to the low conductance bit filter circuit 124.

[0028] The low-conductance bit screening circuit 124 of this embodiment is coupled to the column selection circuit 130 and the page buffer and sensing circuit 140. For example, in an embodiment where N is 1000 and M is 2, after the low-conductance bit screening circuit 124 is enabled, the column selection circuit 130 can be controlled to apply a first test voltage Vtest A (e.g., 3V) and a second test voltage Vtest B (e.g., 7V) to 1000 memory cells 112 in the flash memory array 110 respectively. Then, through the page buffer and sensing circuit 140, the corresponding first cell current I1 and second cell current I2 are read out from each memory cell 112.

[0029] Next, the low-conductance bit screening circuit 124 can calculate the conductance slope GM_c of each memory cell 112 based on these cell currents I1 to IM (step S610). The conductance slope GM_c of each memory cell 112 is, for example, equal to the difference between the first cell current I1 and the second cell current I2 divided by the first cell current I1.

[0030] Next, the low-conductance bit screening circuit 124 can compare the conductance slope GM_c of each memory cell 112 with a predetermined conductance slope GM_t (step S620). Specifically, since the conductance slope of defective memory cells with fast bits and low-conductance effects is relatively small, the low-conductance bit screening circuit 124 can determine whether the conductance slope GM_c of each memory cell 112 is less than the predetermined conductance slope GM_t, and output the comparison result GM_j to the memory control circuit. Then, the memory control circuit can determine the memory cells with the conductance slope GM_c less than the predetermined conductance slope GM_t as defective memory cells and eliminate them (step S630). Thus, the memory control circuit 120 can further ensure that the remaining normal memory cells have a predetermined conductance slope GM_t, thereby avoiding defective memory cells with low-conductance effects in the flash memory 100.

[0031] In one embodiment, the memory control circuit 120 can apply a first test voltage Vtest A and a second test voltage Vtest B to the normal memory cells, read out a first current reference value Iref A and a second current reference value Iref B from the normal memory cells via the page buffer and sensing circuit 140, and then calculate a predetermined conductance slope GM_t based on the first current reference value Iref A and the second current reference value Iref B.

[0032] In one embodiment, the testing method of the flash memory of the present invention can classify each memory cell according to the comparison result of the first cell current I1 of each memory cell and the first current reference value Iref A, and the comparison result of the second cell current I2 and the second current reference value Iref B. For example, when the first cell current I1 of the memory cell 112 is greater than the first current reference value IrefA, and the second cell current I2 is less than the second current reference value Iref B, it is determined that this memory cell 112 has a fast bit and a low conductance characteristic, and it is determined as a defective memory cell and removed. When the first cell current I1 of the memory cell 112 is greater than the first current reference value Iref A, and the second cell current I2 is greater than the second current reference value Iref B, it is determined that this memory cell 112 has a fast bit and a normal conductance characteristic, and it is determined as a defective memory cell and removed, or no action is taken. When the first cell current I1 of the memory cell 112 is less than the first current reference value Iref A, and the second cell current I2 is less than the second current reference value Iref B, it is determined that this memory cell 112 has a slow bit characteristic, and it is determined as a defective memory cell and removed. When the first cell current I1 of the memory cell 112 is less than the first current reference value Iref A, and the second cell current I2 is greater than the second current reference value Iref B, it is determined that this memory cell 112 has a slow bit and a high conductance characteristic, and no action is taken. The above classification can be performed by the memory control circuit 120 or an appropriate logic circuit, and the present invention is not limited thereto.

[0033] In one embodiment, after step S330, the testing method of the flash memory of the present invention may further include step S350. In step S350, the memory control circuit 120 can adjust the erase verification current from the erase verification current for fast bit screening back to the normal erase verification current, and adjust the soft programming verification current from the soft programming verification current for fast bit screening back to the normal soft programming verification current, so as to perform subsequent tests and processing such as data retention.

[0034] In summary, the flash memory and its testing method of the present invention can ensure the screening of defective memory cells with fast bits and low conductance effects during the chip probing stage, and reduce the testing time. In this way, it is possible to prevent the omission of defective chips during the screening of chips, thereby improving the repair rate and endurance of the chips, and reducing the manufacturing cost of the chips.

[0035] In addition, the flash memory and its testing method of the present invention are beneficial to miniaturization to increase the total number of die on a wafer. Therefore, the present invention can reduce the production cost and energy consumption of manufacturing a single IC, and reduce the production energy consumption of subsequent packaging, thereby reducing the carbon emissions in the flash memory manufacturing process. In addition, since the reliability and endurance of the flash memory of the present invention are improved, a green semiconductor technology is provided.

[0036] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A flash memory testing method, characterized in that: The flash memory includes a plurality of storage units, and the testing method includes the following steps: Executing an erase verification reference value adjustment step, including adjusting an erase verification current from a normal erase verification current to an erase verification current for fast bit screening, and adjusting a soft programming verification current from a normal soft programming verification current to a soft programming verification current for fast bit screening, wherein the erase verification current for fast bit screening is greater than the normal erase verification current, and the soft programming verification current for fast bit screening is less than the normal soft programming verification current; Performing an erase operation on the plurality of memory cells, wherein the fast bit screening erase verification current is used to perform corresponding erase verification on the plurality of memory cells; Performing a soft programming operation on the plurality of memory cells, wherein the fast bit screening soft programming verification current is used to perform corresponding soft programming verification on the plurality of memory cells; as well as A test voltage is applied to the word lines to which the plurality of memory cells are coupled, so as to determine whether the plurality of memory cells are defective memory cells or normal memory cells according to the obtained cell currents.

2. The flash memory testing method according to claim 1, characterized in that: The step of using the fast bit screening erase verification current to perform corresponding erase verification on the plurality of memory cells comprises: Determining whether the cell currents of the plurality of memory cells are greater than or equal to the erasure verification current for fast bit screening; When the cell current of one of the plurality of memory cells is less than the fast bit screening erasure verification current, applying an erase voltage to the word line coupled to each of the memory cells again; and The determining step and the applying step of the erasing voltage are repeated until the cell currents of the plurality of memory cells all reach the erasing verification current for fast bit screening.

3. The flash memory testing method according to claim 1, characterized in that: The step of using the fast bit screening soft programming verification current to perform corresponding soft programming verification on the plurality of memory cells comprises: Determining whether the cell currents of the plurality of memory cells are less than or equal to the fast bit screening soft programming verification current; as well as When the cell current of one of the plurality of memory cells is greater than the fast bit screening soft programming verification current, a soft programming voltage is applied again to the word line and the bit line coupled to each of the memory cells.

4. The flash memory testing method according to claim 1, characterized in that: The method also includes analyzing the conductivity slopes of the plurality of storage cells, and further eliminating the bad storage cells according to the analysis results.

5. The flash memory testing method according to claim 4, characterized in that: The steps of analyzing the conductivity slopes of the plurality of memory cells and further eliminating the bad memory cells according to the analysis results include: Applying a plurality of different test voltages to the N memory cells respectively, thereby obtaining a plurality of cell currents of each of the memory cells corresponding to the plurality of different test voltages; Calculating the conductance slope of each of the memory cells according to the multiple cell currents; comparing the conductivity slope of each of the storage cells with a predetermined conductivity slope; as well as Whether it is the bad memory cell is determined according to the comparison result, and the bad memory cell is removed.

6. The flash memory testing method according to claim 5, characterized in that: The method further includes applying a first test voltage and a second test voltage to the normal memory cell, and calculating the predetermined conductivity slope according to a first current reference value and a second current reference value read from the normal memory cell.

7. The flash memory testing method according to claim 6, characterized in that: The multiple cell currents include a first cell current and a second cell current, and the testing method further includes classifying each of the memory cells according to a comparison result of the first cell current of each of the memory cells with the first current reference value and a comparison result of the second cell current of each of the memory cells with the second current reference value.

8. The flash memory testing method according to claim 7, characterized in that: The step of classifying each of the storage units comprises: When the first cell current of the memory cell is greater than the first current reference value and the second cell current is less than the second current reference value, the memory cell is judged to have fast bit and low conductance characteristics, and the memory cell is judged as the bad memory cell and removed.

9. The flash memory testing method according to claim 8, characterized in that: The step of classifying each of the storage units further includes: When the first cell current of the memory cell is greater than the first current reference value and the second cell current is greater than the second current reference value, the memory cell is judged to have fast bit and normal conductance characteristics, and the memory cell is judged as the bad memory cell and removed, or no action is taken.

10. The flash memory testing method according to claim 9, characterized in that: The step of classifying each of the storage units further includes: When the first cell current of the memory cell is less than the first current reference value, and the second cell current is less than the second current reference value, the memory cell is determined to have a slow bit characteristic, and the memory cell is determined to be the defective memory cell and is removed.

11. The flash memory testing method according to claim 10, characterized in that: The step of classifying each of the storage units further includes: When the first cell current of the memory cell is less than the first current reference value and the second cell current is greater than the second current reference value, it is determined that the memory cell has slow bit and high conductance characteristics and does not act.

12. The flash memory testing method according to claim 1, characterized in that: After the step of applying the test voltage to the word lines to which the plurality of memory cells are coupled, the method further comprises: The erase verification current is adjusted back from the fast bit screening erase verification current to the normal erase verification current, and the soft programming verification current is adjusted back from the fast bit screening soft programming verification current to the normal soft programming verification current.

13. A flash memory, characterized in that: include: A flash memory array including a plurality of storage units; as well as A memory control circuit is coupled to a plurality of word lines, a plurality of bit lines, and a plurality of source lines of the flash memory array, wherein the memory control circuit is configured as follows: During the test, the erase verification current is adjusted from the normal erase verification current to the fast bit screening erase verification current, and the soft programming verification current is adjusted from the normal soft programming verification current to the fast bit screening soft programming verification current, wherein the fast bit screening erase verification current is greater than the normal erase verification current, and the fast bit screening soft programming verification current is less than the normal soft programming verification current; Performing an erase operation on the plurality of memory cells, wherein the fast bit screening erase verification current is used to perform corresponding erase verification on the plurality of memory cells; Performing a soft programming operation on the plurality of memory cells, wherein the fast bit screening soft programming verification current is used to perform corresponding soft programming verification on the plurality of memory cells; as well as A test voltage is applied to the word lines to which the plurality of memory cells are coupled, so as to determine whether the plurality of memory cells are defective memory cells or normal memory cells according to the obtained cell currents.

14. The flash memory according to claim 13, characterized in that: The memory control circuit is further configured to: During the erase operation, determining whether the cell currents of the plurality of memory cells are greater than or equal to the fast bit screening erase verification current; When the cell current of one of the plurality of memory cells is less than the fast bit screening erasure verification current, applying an erase voltage to the word line coupled to each of the memory cells again; and The determining step and the applying step of the erasing voltage are repeated until the cell currents of the plurality of memory cells all reach the erasing verification current for fast bit screening.

15. The flash memory according to claim 13, characterized in that: The memory control circuit is further configured to: During the soft programming operation, determining whether the cell currents of the plurality of memory cells are less than or equal to the fast bit screening soft programming verification current; and When the cell current of one of the plurality of memory cells is greater than the fast bit screening soft programming verification current, a soft programming voltage is applied again to the word line and the bit line coupled to each of the memory cells.

16. The flash memory according to claim 13, characterized in that: Also includes: A low-conductance bit screening circuit, coupled to the memory control circuit, wherein the low-conductance bit screening circuit is configured to analyze the conductance slopes of the plurality of memory cells when enabled, and further eliminate the bad memory cells according to the analysis results; and A status register is coupled to the memory control circuit and the low-conductance bit screening circuit, and is configured to determine whether to enable the low-conductance bit screening circuit and output an enable control signal to the low-conductance bit screening circuit.

17. The flash memory according to claim 16, characterized in that: The low-conductance bit screening circuit is configured to, when enabled, control the application of multiple different test voltages to N memory cells, thereby obtaining multiple cell currents of each memory cell corresponding to the multiple different test voltages, calculating the conductivity slope of each memory cell based on the multiple cell currents, comparing the conductivity slope of each memory cell with a predetermined conductivity slope, and determining whether it is a bad memory cell based on the comparison result, and eliminating the bad memory cell.

18. The flash memory according to claim 17, characterized in that: The memory control circuit is configured to apply a first test voltage and a second test voltage to the normal memory cell, and calculate the predetermined conductance slope according to a first current reference value and a second current reference value read from the normal memory cell.

19. The flash memory according to claim 17, wherein: The memory control circuit is configured to adjust the erase verification current from the fast bit screening erase verification current back to the normal erase verification current and adjust the soft programming verification current from the fast bit screening soft programming verification current back to the normal soft programming verification current after determining that the multiple memory cells are the defective memory cells or the normal memory cells.

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