Capacitor structure and manufacturing method thereof

Abstract

The invention relates to a capacitor structure and a manufacturing method thereof, the capacitor structure comprises a substrate, a thin film layer and a capacitor unit, the thin film layer comprises a first layer of thin film, the first layer of thin film is deposited on the substrate, a through hole penetrating in the thickness direction of the first layer of thin film is formed in the first layer of thin film, and the capacitor unit comprises a first part and a second part which are connected with each other. The first part is attached to the inner surface of the via hole, the second part is attached to the inner surface of the first part, and the inner surface of the second part is used for being electrically connected with the first conductive connecting piece; the capacitor unit comprises a dielectric layer, a first metal layer used for being electrically connected with the first conductive connecting piece and a second metal layer used for being electrically connected with the second conductive connecting piece, and the second metal layer, the dielectric layer and the first metal layer are sequentially arranged in an overlapped mode. Electric fields can be formed in the dielectric layer of the first part and the dielectric layer of the second part, so that accumulation and storage of charges are realized, and the purpose of increasing the capacity of the capacitor unit is achieved.

Description

Technical Field

[0001] The present disclosure relates to the field of capacitor technology, and more particularly, to a capacitor structure and a method for manufacturing the same. Background Art

[0002] Currently, the main types of capacitors are MIM capacitors and MOM capacitors. MIM capacitors are highly restricted, have a small capacitance value, and have a relatively complex processing technology, which increases the process cost during processing; while MOM has the problem of taking up a large amount of space, which will affect the integration degree of integrated circuits. Summary of the Invention

[0003] The purpose of the present disclosure is to provide a capacitor structure and a method for manufacturing the same to solve the technical problems existing in the related art.

[0004] A first aspect of the present disclosure provides a capacitor structure, including a substrate, a thin film layer, and a capacitor unit. The thin film layer includes a first thin film deposited on the substrate. A via hole penetrating along the thickness direction is formed in the first thin film. The capacitor unit includes a first part and a second part connected to each other. The first part is attached to the inner surface of the via hole, and the second part is attached to the inner surface of the first part. The inner surface of the second part is used for electrically connecting to a first conductive connection member.

[0005] The capacitor unit includes a dielectric layer, a first metal layer for electrically connecting to a first conductive connection member, and a second metal layer for electrically connecting to a second conductive connection member. The second metal layer, the dielectric layer, and the first metal layer are stacked in sequence.

[0006] Optionally, the thin film layer further includes a second thin film deposited above the first thin film. The via hole penetrates the first thin film and the second thin film along the thickness direction of the thin film layer.

[0007] Optionally, the capacitor unit further includes a third part connected to an end of the first part away from the second part, and the third part is attached to a partial upper surface of the substrate.

[0008] Optionally, the second part, the first part, and the third part are configured to be integrally formed.

[0009] Optionally, the projection of the capacitor unit in the thickness direction of the thin film layer completely falls within the projection of the second conductive connection member in the thickness direction of the thin film layer.

[0010] A second aspect of the present disclosure provides a method for manufacturing the capacitor structure as described above, including:

[0011] Place a prefabricated capacitor unit on a substrate;

[0012] Deposit a first layer of thin film on the substrate and on the capacitor unit;

[0013] Use an etching process to etch vias inside the first layer of thin film, and make a first part of the capacitor unit adhere to the inner surface of the via, and a second part of the capacitor unit adhere to the inner surface of the first part.

[0014] Optionally, the step of placing a prefabricated capacitor unit on a substrate includes:

[0015] Deposit an insulating medium on the upper surface of the substrate, and etch a first through-hole penetrating along its own thickness direction in the insulating medium by an etching process;

[0016] Attach a first conductive layer on the upper surface of the insulating medium and on the inner surface of the first through-hole;

[0017] Deposit an insulating medium again above the first through-hole and above the insulating medium, remove the first conductive layer attached to the upper surface of the insulating medium and the insulating medium on the substrate, and the remaining part of the first conductive layer forms the first metal layer;

[0018] Deposit a dielectric layer and a second metal layer in sequence, so that the first metal layer, the dielectric layer and the third metal layer together constitute the capacitor unit.

[0019] Optionally, deposit the dielectric layer and the second metal layer on both sides of the first metal layer, so that the side of the first metal layer close to the first through-hole and the dielectric layer and the second metal layer together constitute a second part of the capacitor unit, and the side of the first metal layer far from the first through-hole and the dielectric layer and the second metal layer together constitute a first part of the capacitor unit.

[0020] Optionally, after depositing the first layer of thin film on the substrate and on the capacitor unit, perform a photolithography and / or photoetching operation to remove part of the first layer of thin film and part of the capacitor structure attached to the upper surface of the substrate, and the remaining capacitor structure attached to the upper surface of the substrate and the capacitor structure inside the via together form the capacitor unit.

[0021] Optionally, the method further includes:

[0022] Deposit a second layer of thin film on the upper surface of the first layer of thin film, and the first layer of thin film and the second layer of thin film together form a thin film layer;

[0023] Etch the second layer of film and the first layer of film in sequence to form the via holes on the film layer for the first conductive connector and the second conductive connector with different charges to pass through.

[0024] Through the above technical solution, first, when the first metal layer of the capacitor unit is connected to the first conductive connector and the second metal layer of the capacitor unit is electrically connected to the second conductive connector, the first conductive connector and the second conductive connector carry different charges. In this way, an electric field can be formed in the dielectric layer between the first metal layer and the second metal layer, and the charges are moved by the electric force in the electric field, so as to realize the accumulation and storage of charges.

[0025] Furthermore, since the first part of the capacitor unit is attached to the inner surface of the via hole and the second part is attached to the inner surface of the first part, that is to say, the shapes of the first part and the second part are both matched with the shape of the inner surface of the via hole, so that both the first part and the second part can be formed into a three-dimensional capacitor structure. Under the condition of occupying as little space of the capacitor structure as possible, the relative area between the first metal layer and the second metal layer of the capacitor unit can be further increased, so that the above capacitor unit can have a larger capacitance, and the improvement of structures such as the substrate and the film layer can be reduced, thereby reducing the processing difficulty and processing cost of the above capacitor structure.

[0026] In addition, during the process of assembling the first conductive connector into the via hole, the first part can play a supporting and restraining role on the second part from the outside of the second part, so that the second part can have better stability when contacting with the first conductive connector, and avoid situations such as displacement and misalignment of the second part; on the other hand, due to the existence of the first part, the end of the second part can be prevented from being exposed outside. In this way, during the process of inserting the first conductive connector into the via hole, the problem that the above capacitor unit fails due to the direct contact between the first conductive connector and the upper end surface of the second part (that is, the first conductive connector contacts the first metal layer and the second metal layer of the first part at the same time) can be avoided, thereby improving the error tolerance rate during the assembly process of the first conductive connector.

[0027] Other features and advantages of the present disclosure will be described in detail in the subsequent specific implementation part. Brief Description of the Drawings

[0028] The drawings are used to provide a further understanding of the present disclosure, and constitute a part of the specification. Together with the following specific implementation manners, they are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the drawings:

[0029] Figure 1It is a cross-sectional schematic diagram of a capacitor structure provided by an exemplary embodiment of the present disclosure. Among them, the capacitor structure is arranged in a via, and the first metal layer of the capacitor layer is electrically connected to the first conductive connection member, and the second metal layer of the capacitor layer is electrically connected to the second conductive connection member;

[0030] Figure 2 is Figure 1 an enlarged schematic diagram of part A of;

[0031] Figure 3 It is a cross-sectional schematic diagram corresponding to step S201 of a method for manufacturing a capacitor structure provided by an exemplary embodiment of the present disclosure;

[0032] Figure 4 It is a cross-sectional schematic diagram corresponding to step S202 of a method for manufacturing a capacitor structure provided by an exemplary embodiment of the present disclosure;

[0033] Figure 5 It is a cross-sectional schematic diagram corresponding to step S203 of a method for manufacturing a capacitor structure provided by an exemplary embodiment of the present disclosure;

[0034] Figure 6 It is a cross-sectional schematic diagram corresponding to step S203 of a method for manufacturing a capacitor structure provided by an exemplary embodiment of the present disclosure;

[0035] Figure 7 It is a cross-sectional schematic diagram corresponding to step S203 of a method for manufacturing a capacitor structure provided by an exemplary embodiment of the present disclosure;

[0036] Figure 8 It is a cross-sectional schematic diagram corresponding to steps S204 and S205 of a method for manufacturing a capacitor structure provided by an exemplary embodiment of the present disclosure;

[0037] Figure 9 It is a cross-sectional schematic diagram corresponding to step S206 of a method for manufacturing a capacitor structure provided by an exemplary embodiment of the present disclosure;

[0038] Figure 10 It is a cross-sectional schematic diagram corresponding to step S207 of a method for manufacturing a capacitor structure provided by an exemplary embodiment of the present disclosure;

[0039] Figure 11 It is a cross-sectional schematic diagram corresponding to step S208 of a method for manufacturing a capacitor structure provided by an exemplary embodiment of the present disclosure;

[0040] Figure 12 It is a cross-sectional schematic diagram corresponding to step S209 of a method for manufacturing a capacitor structure provided by an exemplary embodiment of the present disclosure;

[0041] Figure 13It is a schematic flow chart of a method for manufacturing a capacitive structure provided by an exemplary embodiment of the present disclosure;

[0042] Figure 14 It is a schematic flow chart of a method for manufacturing a capacitive structure provided by another exemplary embodiment of the present disclosure.

[0043] Explanation of reference numerals

[0044] 1 - Substrate; 2 - Thin film layer; 21 - First thin film; 22 - Second thin film; 3 - Capacitor unit; 31 - First part; 32 - Second part; 33 - Third part; 310 - First metal layer; 311 - First conductive layer; 320 - Dielectric layer; 330 - Second metal layer; 4 - Insulating dielectric; 41 - First through hole; 5 - Via; 6 - First conductive connector; 7 - Second conductive connector. Detailed description of the specific implementation

[0045] The following will describe the specific implementation of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific implementation described herein is only for the purpose of explaining and illustrating the present disclosure, and is not used to limit the present disclosure.

[0046] In the present disclosure, unless otherwise stated, the orientation or positional relationship indicated by orientation words such as "thickness direction" is defined based on the Figure 1 drawing direction shown in the accompanying drawings. It is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, specific orientation structure and operation. Therefore, it should not be construed as a limitation of the present disclosure. The terms "inner" and "outer" refer to the inside and outside of the corresponding structural contour.

[0047] In addition, it should be noted that the terms such as "first" and "second" are used to distinguish one element from another, and do not have order and importance. In addition, in the description with reference to the accompanying drawings, the same reference numerals in different drawings represent the same elements.

[0048] In the description of the present disclosure, it should also be noted that unless otherwise clearly defined and limited, the terms "arranged", "connected", "coupled", "installed" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0049] Refer to Figures 1 to 14As shown in the figure, the first aspect of the present disclosure provides a capacitive structure, including a substrate 1, a thin film layer 2, and a capacitive unit 3. The thin film layer 2 includes a first thin film 21 deposited on the substrate 1. A via hole 5 penetrating along its thickness direction is formed in the first thin film 21. The capacitive unit 3 includes a first part 31 and a second part 32 connected to each other. The first part 31 is attached to the inner surface of the via hole 5, and the second part 32 is in contact with the inner surface of the first part 31. The inner surface of the second part 32 is used for electrical connection with a first conductive connector 6. The capacitive unit 3 includes a dielectric layer 320, a first metal layer 310 for electrical connection with the first conductive connector 6, and a second metal layer 330 for electrical connection with a second conductive connector 7. The second metal layer 330, the dielectric layer 320, and the first metal layer 310 are stacked in sequence.

[0050] Through the above technical solution, first, when the first metal layer 310 of the capacitive unit 3 is connected to the first conductive connector 6 and the second metal layer 330 of the capacitive unit 3 is electrically connected to the second conductive connector 7, the first conductive connector 6 and the second conductive connector 7 carry different charges. In this way, an electric field can be formed in the dielectric layer 320 between the first metal layer 310 and the second metal layer 330, and the charges are moved by the electric field force in the electric field, thereby realizing the accumulation and storage of charges.

[0051] Furthermore, since the first part 31 of the capacitive unit 3 is attached to the inner surface of the above-mentioned via hole 5 and the second part 32 is in contact with the inner surface of the first part 31, that is to say, the shapes of the first part 31 and the second part 32 are both matched with the shape of the inner surface of the via hole 5, so that both the first part 31 and the second part 32 can be formed into a three-dimensional capacitive structure. Under the condition of occupying as little space of the capacitive structure as possible, the relative area between the first metal layer 310 and the second metal layer 330 of the capacitive unit 3 can be further increased, so that the above capacitive unit 3 can have a larger capacitance, and the improvement of structures such as the substrate 1 and the thin film layer 2 can be reduced, thereby reducing the processing difficulty and processing cost of the above capacitive structure.

[0052] In addition, during the process of assembling the first conductive connector 6 into the via 5, the first portion 31 can support and restrain the second portion 32 from the outside of the second portion 32, enabling the second portion 32 to have better stability when contacting the first conductive connector 6 and avoiding situations such as displacement and misalignment of the second portion 32. On the other hand, due to the existence of the first portion 31, the end of the second portion 32 can be prevented from being exposed outside. In this way, during the process of inserting the first conductive connector 6 into the via 5, the problem of the above-mentioned capacitor unit 3 failing due to the direct contact between the first conductive connector 6 and the upper end surface of the second portion 32 (i.e., the first conductive connector 6 contacting the first metal layer 310 and the second metal layer 330 of the first portion 31 simultaneously) can be avoided, thereby improving the error tolerance rate during the assembly process of the first conductive connector 6.

[0053] In an exemplary embodiment provided by the present disclosure, optionally, both the first metal layer 310 and the second metal layer 330 can be made of titanium nitride. Titanium nitride has physical and chemical properties such as a high melting point, high hardness, high-temperature chemical stability, and excellent thermal and electrical conductivity, which can improve the electrical conductivity and service life of the first metal layer 310 and the second metal layer 330.

[0054] Optionally, as Figure 1 、 Figure 11 and Figure 12 shown, the thin film layer 2 further includes a second thin film 22, and the second thin film 22 is deposited above the first thin film 21. The via 5 penetrates through the first thin film 21 and the second thin film 22 along the thickness direction of the thin film layer 2. In this way, during subsequent etching of the via 5 or polishing of the thin film layer 2, the thin film filled inside the via 5 can protect the capacitor unit 3 located inside the via 5, thereby avoiding the problem of the capacitor unit 3 (the first portion 31 and the second portion 32) located inside the via 5 being damaged during the polishing process.

[0055] In order to further increase the capacitance of the above-mentioned capacitor unit 3, in an exemplary embodiment provided by the present disclosure, optionally, as Figure 1 、 Figures 10 to 12 shown, the capacitor unit 3 may further include a third portion 33. The third portion 33 is connected to the end of the first portion 31 away from the second portion 32, and the third portion 33 adheres to a part of the upper surface of the substrate 1. Since the third portion 33 is connected to the second portion 32, after the first conductive connector 6 is inserted into the via 5, the first portion 31, the second portion 32, and the third portion 33 can simultaneously achieve electrical connection with the first conductive connector 6, that is, the first portion 31, the second portion 32, and the third portion 33 can simultaneously achieve the accumulation and storage of charges, thereby increasing the capacitance of the capacitor unit 3.

[0056] Moreover, since the third part 33 is attached to the upper surface of the substrate 1, during the deposition of the first thin film and the second thin film above the substrate 1, the setting of the third part 33 will not interfere with or disrupt the normal deposition of the thin film layer 2 mentioned above.

[0057] The present disclosure does not limit the method of increasing the capacitance of the capacitance unit 3. For example, in other embodiments provided by the present disclosure, the capacitance can also be increased by increasing the relative area between the first metal layer 310 and the second metal layer 330 of the capacitance unit 3 or by increasing the dielectric constant of the dielectric layer 320, etc. The present disclosure will not elaborate on this here.

[0058] Optionally, as Figure 1 、 Figures 10 to 12 shown, the second part 32, the first part 31, and the third part 33 are configured to be integrally formed. In this way, on the one hand, it is convenient for the manufacturing of the first part 31, the second part 32, and the third part 33 (such as integrally forming by deposition), and it has higher processing accuracy, and can reduce the processing difficulty and processing cost; on the other hand, precisely because the first part 31, the second part 32, and the third part 33 are configured to be integrally formed, there is no need to perform connection and welding operations on the first part 31, the second part 32, and the third part 33, which can make the first part 31, the second part 32, and the third part 33 have higher strength and structural stability, thereby improving the stability during the operation of the capacitance unit 3.

[0059] Optionally, the projection of the capacitance unit 3 in the thickness direction of the thin film layer 2 completely falls within the projection of the second conductive connection member 7 in the thickness direction of the thin film layer 2. Or, the fact that the projection of the capacitance unit 3 in the thickness direction of the thin film layer 2 completely falls within the projection of the second conductive connection member 7 in the thickness direction of the thin film layer 2 can also be understood as that the projection of the capacitance unit 3 in the thickness direction of the thin film layer 2 is less than or equal to the projection of the second conductive connection member 7 in the thickness direction of the thin film layer 2, that is, the arrangement range of the capacitance unit 3 does not exceed the corresponding range of the second conductive connection member 7. In this way, it is possible to avoid the problem that the capacitance unit 3 extends excessively to the surroundings and affects the arrangement of the adjacent second conductive connection member 7 or the first conductive connection member 6.

[0060] In the embodiment where the capacitance structure includes the first part 31, the second part 32, and the third part 33, the fact that the projection of the capacitance unit 3 in the thickness direction of the thin film layer 2 completely falls within the projection of the second conductive connection member 7 in the thickness direction of the thin film layer 2 can be understood as: the projections of the first part 31, the second part 32, and the third part 33 in the thickness direction of the thin film layer 2 all completely fall within the projection of the second conductive connection member 7 in the thickness direction of the thin film layer 2.

[0061] Here, for the convenience of electrically connecting the second conductive connector 7 to the second metal layer 330 of the capacitor unit 3, in the present disclosure, a first connection hole facing the via hole 5 may be formed in the substrate 1. The first connection hole penetrates the substrate 1 along the thickness direction of the substrate 1, and the first metal layer 310 may be at least partially embedded in the first connection hole. In this way, the second conductive connector 7 can achieve electrical connection with the first metal layer 310 through the first connection hole.

[0062] It should be noted that, in an exemplary embodiment provided by the present disclosure, the via holes 5 formed in the first thin film 21 and the second thin film 22 may be formed by means of cell via etch. Generally, the shape of the via hole 5 etched in this way is larger at the top and smaller at the bottom. Based on this, in the present disclosure, optionally, along the direction from bottom to top, the inner diameter of the via hole 5 gradually increases. In this case, in order to enable the first portion 31 to adhere to the outer surface of the via hole 5, the shape of the first portion 31 should also be larger at the top and smaller at the bottom, so as to increase the contact area between the first portion 31 and the inner surface of the via hole 5 and improve the fitting effect between the first portion 31 and the inner surface of the via hole 5.

[0063] Similarly, in order to improve the fitting effect between the first conductive connector 6 and the inner surface of the first portion 31 disposed in the via hole 5, in an exemplary embodiment provided by the present disclosure, the shape of the portion of the first conductive connector 6 inserted into the via hole 5 may also match the shape of the via hole 5, that is, the portion of the first conductive connector 6 inserted into the via hole 5 is also formed to be larger at the top and smaller at the bottom. In this way, when the first conductive connector 6 is inserted into the via hole 5, it can be in close contact with the inner surface of the first portion 31, thereby improving the electrical connection stability between the first conductive connector 6 and the first portion 31.

[0064] In addition, for the convenience of understanding the present disclosure, the present disclosure further describes the structures of the above-mentioned first part 31, second part 32, and third part 33. Specifically, the first part 31 can be formed into a cup shape with an upward opening. The first part 31 can include a first metal layer 310, a second metal layer 330, and a dielectric layer 320 disposed between the first metal layer 310 and the second metal layer 330. The second part 32 can also include a first metal layer 310, a second metal layer 330, and a dielectric layer 320 disposed between the first metal layer 310 and the second metal layer 330. Since the outer peripheral surfaces of the second part 32 and the first part 31 are in contact with each other, in the present disclosure, the second part 32 and the first part 31 can share the same first metal layer 310. In this way, while increasing the capacitance of the capacitor unit 3, one layer of the first metal layer 310 is reduced (that is, when the capacitance is constant, the thickness of the capacitor unit 3 is reduced). Therefore, the space occupied by the second part 32 can be effectively reduced, and the capacitor structure can be made more compact, which is more conducive to improving the integration degree of the integrated circuit.

[0065] Moreover, in order to avoid the problem that the capacitor unit 3 fails due to the direct contact between the first metal layer 310 and the second metal layer 330 bypassing the dielectric layer 320, in an exemplary embodiment provided by the present disclosure, the projection of the dielectric layer 320 in its own thickness direction completely covers the projection of the first metal layer 310 in its own thickness direction, and the projection of the dielectric layer 320 in its own thickness direction completely covers the projection of the second metal layer 330 in its own thickness direction. In this way, the dielectric layer 320 located between the first metal layer 310 and the second metal layer 330 can isolate the first metal layer 310 and the second metal layer 330, preventing the first metal layer 310 from contacting the second metal layer 330 across the dielectric layer 320, and preventing the second metal layer 330 from contacting the first metal layer 310 across the dielectric layer 320.

[0066] The second aspect of the present disclosure provides a method for manufacturing the capacitor structure as described above, as Figure 13 shown, including:

[0067] S101: Dispose the prefabricated capacitor unit 3 on the substrate 1;

[0068] S102: Deposit the first thin film 21 on the substrate 1 and on the capacitor unit 3;

[0069] S103: Use an etching process to etch a via 5 inside the first thin film 21, and make the first part 31 of the capacitor unit 3 adhere to the inner surface of the via 5, and the second part 32 of the capacitor unit 3 adhere to the inner surface of the first part 31.

[0070] Through the above technical solution, first, when the first metal layer 310 of the capacitor unit 3 is connected to the first conductive connector 6 and the second metal layer 330 of the capacitor unit 3 is electrically connected to the second conductive connector 7, the first conductive connector 6 and the second conductive connector 7 carry different charges. In this way, an electric field can be formed in the dielectric layer 320 between the first metal layer 310 and the second metal layer 330, and the charges are moved by the electric force in the electric field, thereby realizing the accumulation and storage of charges.

[0071] Furthermore, since the first part 31 of the capacitor unit 3 is attached to the inner surface of the via hole 5 and the second part 32 is attached to the inner surface of the first part 31, that is to say, the shapes of the first part 31 and the second part 32 are both matched with the shape of the inner surface of the via hole 5. As a result, both the first part 31 and the second part 32 can form a three-dimensional capacitor structure. While occupying as little space of the capacitor structure as possible, the relative area between the first metal layer 310 and the second metal layer 330 of the capacitor unit 3 can be further increased, so that the above capacitor unit 3 can have a larger capacitance, and the improvement of structures such as the substrate 1 and the thin film layer 2 can be reduced, thereby reducing the processing difficulty and processing cost of the above capacitor structure.

[0072] In addition, during the process of assembling the first conductive connector 6 into the via hole 5, the first part 31 can support and restrain the second part 32 from the outside of the second part 32, enabling the second part 32 to have better stability when contacting the first conductive connector 6 and avoiding situations such as displacement and misalignment of the second part 32. On the other hand, due to the existence of the first part 31, the end of the second part 32 can be prevented from being exposed outside. In this way, during the process of inserting the first conductive connector 6 into the via hole 5, the problem of failure of the above capacitor unit 3 caused by the direct contact between the first conductive connector 6 and the upper end surface of the second part 32 (i.e., the first conductive connector 6 simultaneously contacts the first metal layer 310 and the second metal layer 330 of the first part 31) can be avoided, thereby increasing the error tolerance rate during the assembly process of the first conductive connector 6.

[0073] Reference Figure 14 As shown, according to an embodiment of the present disclosure, another method for manufacturing a metal layer capacitor is further provided, including:

[0074] S201, as Figure 3 shown, deposit an insulating dielectric 4 on the upper surface of the substrate 1, and etch a first through hole 41 penetrating along its own thickness direction in the insulating dielectric 4 through an etching process;

[0075] S202, as Figure 4As shown, a first conductive layer 311 is attached to the upper surface of the insulating medium 4 and the inner surface of the first through hole 41; when the first conductive layer 311 is attached to the inner surface of the first through hole 41, the shaping of the first conductive layer 311 can be achieved.

[0076] S203, as Figures 5 to 7 As shown, an insulating medium 4 is deposited again above the first through hole 41 and above the insulating medium 4, and the first conductive layer 311 attached to the upper surface of the insulating medium 4 and the insulating medium 4 located on the substrate 1 are removed. The remaining part of the first conductive layer 311 forms a first metal layer 310; that is to say, through the above operations, the insulating medium 4 and the first conductive layer 311 attached to the upper surface of the insulating medium 4 can be removed completely, that is, only the first conductive layer 311 is left on the substrate 1, thus facilitating the subsequent deposition operation of the first conductive layer 311.

[0077] In an exemplary embodiment provided by the present disclosure, a lithography process can be used to remove the insulating medium 4 and the first conductive layer 311 attached to the upper surface of the insulating mechanism.

[0078] S204, as Figure 8 As shown, a dielectric layer 320 and a second metal layer 330 are deposited in sequence so that the first metal layer 310, the dielectric layer 320, and the third metal layer together form a capacitor unit 3; during the deposition process, the dielectric layer 320 and the third metal layer can sequentially cover the outer surface of the first metal layer 310, so that the first metal layer 310 and the second metal layer 330 are formed on both sides of the dielectric layer 320, and then the above capacitor unit 3 is formed.

[0079] S205, as Figure 8 As shown, the dielectric layer 320 and the second metal layer 330 are deposited on both sides of the first metal layer 310 so that the side of the first metal layer 310 close to the first through hole 41 and the dielectric layer 320 and the second metal layer 330 together form the second part 32 of the capacitor unit 3, and the side of the first metal layer 310 far from the first through hole 41 and the dielectric layer 320 and the second metal layer 330 together form the first part 31 of the capacitor unit 3; that is to say, the second part 32 and the first part 31 can share the same first metal layer 310. In this way, while increasing the capacitance of the capacitor unit 3, one layer of the first metal layer 310 is set less (that is, when the capacitance is certain, the thickness of the capacitor unit 3 is reduced), so that the space occupied by the second part 32 can be effectively reduced, and the capacitor structure can be made more compact, which is more conducive to improving the integration degree of the integrated circuit.

[0080] S206, as Figure 9As shown in the figure, a first layer of thin film 21 is deposited on the substrate 1 and the capacitor unit 3. In this way, during the subsequent etching of the via 5 or the polishing of the thin film layer 2, the first layer of thin film 21 covering the substrate 1 and the capacitor unit 3 can protect the substrate 1 and the capacitor unit 3, thus avoiding the problems of damage and destruction of the substrate 1 and the capacitor unit 3 (the first part 31 and the second part 32) during the polishing process.

[0081] S207. As Figure 10 shown in the figure, perform photolithography and / or photoetching operations to remove a part of the first layer of thin film 21 and a part of the capacitor structure attached to the upper surface of the substrate 1. The remaining capacitor structure attached to the upper surface of the substrate 1 and the capacitor structure located inside the via 5 together form the capacitor unit 3.

[0082] It should be noted that the part of the capacitor structure on the upper surface of the substrate 1 mentioned above is the third part 33 of the capacitor unit 3. And since the third part 33 is attached to the upper surface of the substrate 1, during the deposition of the first thin film and the second thin film above the substrate 1, the setting of the third part 33 will not cause interference or obstruction to the normal deposition of the thin film layer 2.

[0083] S208. As Figure 11 shown in the figure, deposit a second layer of thin film 22 on the upper surface of the first layer of thin film 21. The first layer of thin film 21 and the second layer of thin film 22 together form the thin film layer 2. Similarly, during the subsequent etching of the via 5 or the polishing of the thin film layer 2, the thin film filled inside the via 5 can protect the capacitor unit 3 located inside the via 5, thus avoiding the problems of damage and destruction of the capacitor unit 3 (the first part 31 and the second part 32) located inside the via 5 during the polishing process.

[0084] S209. As Figure 12 shown in the figure, etch the second layer of thin film 22 and the first layer of thin film 21 in sequence to form a via 5 on the thin film layer 2 for the first conductive connector 6 and the second conductive connector 7 with different charges to pass through, and make the first part 31 of the capacitor unit 3 attach to the inner surface of the via 5 and the second part 32 of the capacitor unit 3 attach to the inner surface of the first part 31. After the above-mentioned first conductive connector 6 is inserted into the via 5, the first part 31 and the second part 32 can simultaneously achieve electrical connection with the first conductive connector 6, that is, the first part 31 and the second part 32 can simultaneously achieve the accumulation and storage of charges, thereby increasing the capacitance of the capacitor unit 3.

[0085] The preferred embodiments of the present disclosure have been described in detail above in conjunction with the accompanying drawings. However, the present disclosure is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.

[0086] In addition, it should be noted that, in the various specific technical features described in the above specific embodiments, they can be combined in any suitable manner without conflict. To avoid unnecessary repetition, the present disclosure will not separately describe various possible combination methods.

[0087] Furthermore, any combination can be made between various different embodiments of the present disclosure, as long as it does not violate the idea of the present disclosure, and it should also be regarded as the content disclosed by the present disclosure.

Claims

1. A capacitive structure, characterized in that, it includes a substrate, a thin film layer and a capacitive unit. The thin film layer includes a first thin film deposited on the substrate. A via hole penetrating along its thickness direction is formed in the first thin film. The capacitive unit includes a first part and a second part connected to each other. The first part is attached to the inner surface of the via hole, and the second part is attached to the inner surface of the first part. The inner surface of the second part is used for electrically connecting with a first conductive connector; The capacitive unit includes a dielectric layer, a first metal layer for electrically connecting with a first conductive connector, and a second metal layer for electrically connecting with a second conductive connector. The second metal layer, the dielectric layer and the first metal layer are stacked in sequence.

2. The capacitive structure according to claim 1, characterized in that, the thin film layer further includes a second thin film deposited above the first thin film. The via hole penetrates the first thin film and the second thin film along the thickness direction of the thin film layer.

3. The capacitive structure according to claim 1, characterized in that, the capacitive unit further includes a third part connected to one end of the first part away from the second part, and the third part is attached to a part of the upper surface of the substrate.

4. The capacitive structure according to claim 3, characterized in that, the second part, the first part and the third part are configured to be integrally formed.

5. The capacitive structure according to any one of claims 1-4, characterized in that, the projection of the capacitive unit in the thickness direction of the thin film layer completely falls within the projection of the second conductive connector in the thickness direction of the thin film layer.

6. A method for manufacturing the capacitive structure according to any one of claims 1-5, characterized in that, it includes: placing a prefabricated capacitive unit on a substrate; depositing a first thin film on the substrate and the capacitive unit; using an etching process to etch a via hole inside the first thin film, and making the first part of the capacitive unit attach to the inner surface of the via hole and the second part of the capacitive unit attach to the inner surface of the first part.

7. The manufacturing method according to claim 6, characterized in that, the placing the prefabricated capacitive unit on the substrate includes: depositing an insulating medium on the upper surface of the substrate, and etching a first through hole penetrating along its own thickness direction in the insulating medium by an etching process; attaching a first conductive layer on the upper surface of the insulating medium and the inner surface of the first through hole; depositing an insulating medium again above the first through hole and above the insulating medium, removing the first conductive layer attached to the upper surface of the insulating medium and the insulating medium located on the substrate, and the remaining part of the first conductive layer forms the first metal layer; depositing a dielectric layer and a second metal layer in sequence, so that the first metal layer, the dielectric layer and the third metal layer jointly form the capacitive unit.

8. The manufacturing method according to claim 7, characterized in that, Deposit the dielectric layer and the second metal layer on both sides of the first metal layer, so that the side of the first metal layer close to the first via hole, together with the dielectric layer and the second metal layer, constitutes the second part of the capacitor unit, and the side of the first metal layer far from the first via hole, together with the dielectric layer and the second metal layer, constitutes the first part of the capacitor unit.

9. The manufacturing method according to claim 6, characterized in that after depositing the first layer of film on the substrate and on the capacitor unit, perform a photolithography and / or etching operation to remove part of the first layer of film and part of the capacitor structure attached to the upper surface of the substrate, and the remaining capacitor structure attached to the upper surface of the substrate and the capacitor structure located inside the via hole together form the capacitor unit.

10. The manufacturing method according to claim 9, characterized in that the method further includes: deposit a second layer of film on the upper surface of the first layer of film, and the first layer of film and the second layer of film together form a film layer; etch the second layer of film and the first layer of film in sequence to form the via hole for the first conductive connection member and the second conductive connection member with different charges to pass through on the film layer.

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