Limiting processing sample and limiting processing method of electronic device

Abstract

The invention discloses a limiting processing sample and a limiting processing method of an electronic device, and belongs to the technical field of semiconductors. The limiting processing method of the electronic device comprises the steps that a first electrode layer, a dielectric layer and a second electrode layer are formed on a substrate, the second electrode layer comprises a first electrode and a second electrode, and the first electrode and the second electrode are arranged in the first direction. Forming a conductive structure, wherein the conductive structure is electrically connected with the second electrode and the first electrode layer; forming a first isolation structure; in the first direction, the first isolation structure divides the first electrode into a probe placement part and a limiting area electrode; a connecting electrode is formed on the side, away from the substrate, of the first electrode, and in the first direction, the connecting electrode crosses the first isolation structure and is electrically connected with the probe placement part and the limiting area electrode. After the limiting device is subjected to electric field operation, a transmission electron microscope sample is prepared by using the limited area, so that a microstructure with a changed structure can be conveniently positioned in an observable area of the transmission electron microscope.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and particularly relates to a limited processing sample and a limited processing method for an electronic device. Background Art

[0002] The microstructure of microelectronic devices will change under the influence of an electric field. This phenomenon has a significant impact on the performance and reliability of the devices. However, these changes are usually local and unevenly distributed in the device, which adds a layer of complexity to their detection and analysis. The local structural changes under the action of an electric field are usually caused by uneven electric field distribution or material inhomogeneity within the device. These changes can manifest in various forms, such as atomic displacement, phase change, or the generation and migration of defects. These local structural changes may have a profound impact on the long-term performance and reliability of the device. For example, they can trigger the formation of conductive filaments, leading to device failure due to phenomena such as dielectric breakdown. Therefore, detecting and understanding these subtle local structural changes is crucial for predicting and preventing device failures and optimizing device performance. Summary of the Invention

[0003] Embodiments of this application provide a limited processing sample and a limited processing method for an electronic device. After performing limited processing on a microelectronic device and performing an electric field operation on the limited device, a transmission electron microscope sample is prepared using a defined area, facilitating the localization of the microstructures with structural changes in the observable area of the transmission electron microscope.

[0004] On the one hand, embodiments of this application provide a limited processing method for an electronic device, including sequentially forming a stacked first electrode layer, a dielectric layer, and a second electrode layer on a substrate. The second electrode layer includes a first electrode and a second electrode. The first electrode and the second electrode are arranged along a first direction, and the first direction is parallel to the substrate. A conductive structure is formed, which penetrates the second electrode, the dielectric layer, and the first electrode layer, and the conductive structure is electrically connected to the second electrode and the first electrode layer. A first isolation structure is formed, which penetrates the first electrode, the dielectric layer, and the first electrode layer. In the first direction, the first isolation structure separates the first electrode into a probe placement portion and a limited area electrode. A connection electrode is formed on the side of the first electrode away from the substrate. In the first direction, the connection electrode straddles the first isolation structure and is electrically connected to the probe placement portion and the limited area electrode.

[0005] In some embodiments, after forming the above connection electrode, the above preparation method further includes:

[0006] Forming a second isolation structure, the second isolation structure penetrating the first electrode, the dielectric layer, and the first electrode layer;

[0007] In a second direction, the second isolation structure separates the limiting region electrode from the first electrode; the second direction is parallel to the substrate and intersects with the first direction.

[0008] In some embodiments, the electronic device includes a limiting region. After forming the connecting electrode, the manufacturing method further includes:

[0009] Cut out the portions of the first electrode layer, the dielectric layer, and the second electrode layer located within the limiting region to form a device sample.

[0010] In some embodiments, after forming the device sample, the manufacturing method further includes:

[0011] Thin the thickness of the device sample.

[0012] In some embodiments, after thinning the thickness of the device sample, perform an electric field loading test and a transmission electron microscopy characterization on the device sample.

[0013] In some embodiments, forming the first isolation structure includes:

[0014] Using a focused ion beam, etch the first electrode, the dielectric layer, and the first electrode layer to form an isolation groove penetrating through the first electrode, the dielectric layer, and the first electrode layer;

[0015] Fill the isolation groove with an insulating material to form the first isolation structure.

[0016] In some embodiments, forming the conductive structure includes:

[0017] Using a focused ion beam, etch the second electrode, the dielectric layer, and the first electrode layer to form a via penetrating through the second electrode, the dielectric layer, and the first electrode layer;

[0018] Deposit a conductive material in the via to form the conductive structure.

[0019] In some embodiments, forming the second electrode layer includes:

[0020] Form a conductive thin film on the side of the dielectric layer away from the substrate;

[0021] Using a focused ion beam, etch the conductive thin film to obtain the first electrode and the second electrode.

[0022] The method for limiting the position of an electronic device provided by an embodiment of the present application includes sequentially forming a stacked first electrode layer, a dielectric layer, and a second electrode layer on a substrate. The second electrode layer includes two non-connected electrodes, namely a first electrode and a second electrode arranged along a first direction; forming a conductive structure that penetrates the second electrode, the dielectric layer, and the first electrode layer, and the conductive structure is electrically connected to the second electrode and the first electrode layer, so that the second electrode is short-circuited to the first electrode layer; forming a first isolation structure that penetrates the first electrode, the dielectric layer, and the first electrode layer, and in the first direction, the first isolation structure separates the first electrode into a probe placement part and a limited position area electrode; forming a connection electrode on the side of the first electrode away from the substrate, and in the first direction, the connection electrode straddles the first isolation structure and is electrically connected to the probe placement part and the limited position area electrode.

[0023] After the above-mentioned position-limiting processing of the electronic device, a voltage is applied to the probe placement part and the second electrode to apply a voltage to the first electrode layer and the limited position area electrode for the electric field loading test of the limited position area. After the test, the limited position area is processed into a transmission electron microscope sample, so that the microstructure with structural changes can be accurately located in the observable area of the transmission electron microscope. When analyzing the device performance, failure mechanism or material characteristics, the changes at the microscopic level can be directly observed, which helps to deeply understand the working principle of the device and improve the design.

[0024] On the other hand, an embodiment of the present application also provides a position-limiting processed sample of an electronic device. The position-limiting processed sample includes a substrate, and a first electrode layer, a dielectric layer, and a second electrode layer sequentially stacked on the substrate. The second electrode layer includes a first electrode and a second electrode. The first electrode and the second electrode are arranged along a first direction, and the first direction is parallel to the substrate. The position-limiting processed sample further includes a conductive structure that penetrates the second electrode, the dielectric layer, and the first electrode layer, and the conductive structure is electrically connected to the second electrode and the first electrode layer. The position-limiting processed sample further includes a first isolation structure that penetrates the first electrode, the dielectric layer, and the first electrode layer. In the first direction, the first isolation structure separates the first electrode into a probe placement part and a limited position area electrode. The position-limiting processed sample further includes a connection electrode. In the first direction, the connection electrode straddles the first isolation structure, and the connection electrode is electrically connected to the probe placement part and the limited position area electrode.

[0025] In some embodiments, the position-limiting processed sample further includes a buffer layer, and the buffer layer is disposed between the first electrode layer and the substrate. Description of the Drawings

[0026] The above and / or additional aspects and advantages of the present application will become apparent and easy to understand from the description of the embodiments in conjunction with the following drawings, where:

[0027] Figure 1Structural diagram of a limiting processing sample of an electronic device provided by an embodiment of the present application;

[0028] Figure 2 and Figure 3 Flow chart of a limiting processing method for preparing an electronic device provided by an embodiment of the present application;

[0029] Figures 4 to 12 Diagrams of each step for preparing a limiting processing sample of an electronic device provided by an embodiment of the present application;

[0030] Figure 13 Structural diagram of another limiting processing sample of an electronic device provided by an embodiment of the present application;

[0031] Figure 14 Practical effect diagram of processing a limiting processing sample of an electronic device using FIB provided by an embodiment of the present application: (a) Limiting device processed between the first electrode and the second electrode; (b) Through-cut processing of the second electrode; (c) Conductive material Pt filling and deposition on the second electrode; (d) Limiting processing of the first electrode; (e) Enlarged view of the electric field loading area; (f) SiO2 insulation filling at the split of the limiting area of the first electrode;

[0032] Figure 15 Electrical test results after performing limiting processing on a limiting device provided by an embodiment of the present application;

[0033] Figure 16 Observation by TEM on the basis of a limiting device provided by an embodiment of the present application reveals a structural phase change in the dielectric layer parallel to the electric field direction: (a) TEM bright field phase; (b) TEM dark field phase. Detailed implementation manners

[0034] Next, in conjunction with the accompanying drawings, the technical solutions in some embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0035] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is interpreted in an open, inclusive sense, that is, "including, but not limited to".

[0036] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality" is two or more.

[0037] In describing some embodiments, the term "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral one; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other.

[0038] In addition, the use of "based on" implies openness and inclusiveness, because a process, step, calculation, or other action "based on" one or more of the stated conditions or values may, in practice, be based on additional conditions or values beyond those stated.

[0039] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0040] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are exaggerated for clarity. Thus, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0041] Examples of the embodiments are shown in the drawings, where like or similar reference numerals designate like or similar elements or elements having like or similar functions throughout. The embodiments described below with reference to the drawings are exemplary only for explaining the present application and should not be construed as limiting the present application.

[0042] The microstructure of microelectronic devices changes under the influence of an electric field, and this phenomenon has a significant impact on the performance and reliability of the devices. However, these changes are usually local and unevenly distributed in the device, which adds a layer of complexity to their detection and analysis. Detecting and understanding these subtle local structural changes is crucial for predicting and preventing device failures and optimizing device performance. Therefore, it is crucial to use advanced microscopic characterization techniques such as high-resolution transmission electron microscopy (HRTEM) to detect and understand these subtle local structural changes. These techniques allow for detailed detection of the microstructure at the atomic scale, enabling the detection of these subtle local changes caused by the electric field.

[0043] Generally, the planar size of microelectronic devices is above 10 μm, while the sample preparation area for characterizing the microstructure using a Transmission Electron Microscope (TEM) has a thickness of only 50 - 100 nm and a width of 5 - 20 μm. Among them, the preparation of in-situ TEM samples faces many challenges. This process involves thinning the sample to make it electron transparent, so that the dynamic process at the atomic or nanoscale can be directly observed in real time. The disadvantage of adopting this solution is the great difficulty in sample preparation. The main challenge lies in the need to mount the sample on an in-situ test chip, and the sample needs to be processed to be very thin, usually in the range of dozens to hundreds of nanometers. During this preparation process, it is easy to damage the thin area or the carrier film on the test chip.

[0044] In view of the above problems, an embodiment of the present application provides a limited processing sample and a limited processing method for an electronic device. Figure 1 It is a structural diagram of a limited processing sample of an electronic device provided by an embodiment of the present application.

[0045] As Figure 1 shown, the sample includes a substrate 101, a first electrode layer 102, a dielectric layer 103, and a second electrode layer 104, which are sequentially stacked on the substrate 101. The second electrode layer 104 includes a first electrode 1041 and a second electrode 1042. The first electrode 1041 and the second electrode 1042 are arranged along the first direction X, and the first direction X is parallel to the substrate 101. A conductive structure 107 penetrates through the second electrode 1042, the dielectric layer 103, and the first electrode layer 102, and the conductive structure 107 is electrically connected to the second electrode 1042 and the first electrode layer 102. A first isolation structure 108 penetrates through the first electrode 1041, the dielectric layer 103, and the first electrode layer 102. In the first direction X, the first isolation structure 108 separates the first electrode 1041 into a probe placement portion 111 and a limited area electrode 112. In the first direction X, a connection electrode 106 straddles the first isolation structure 108 and is electrically connected to the probe placement portion 111 and the limited area electrode 112.

[0046] Figure 2 and Figure 3 It is a flowchart of a limited processing method for preparing an electronic device provided by an embodiment of the present application. Figures 4 to 12 It is a diagram of each step of a limited processing sample for preparing an electronic device provided by an embodiment of the present application. The preparation method includes the following steps:

[0047] Step S10: As Figure 4 and Figure 5As shown, a stacked first electrode layer 102, dielectric layer 103, and second electrode layer 104 are sequentially formed on a substrate 101. The second electrode layer 104 includes a first electrode 1041 and a second electrode 1042. The first electrode 1041 and the second electrode 1042 are arranged along a first direction X, and the first direction X is parallel to the substrate 101.

[0048] Exemplarily, as Figure 4 shown, first, the substrate 101 is cleaned and processed. The substrate 101 can be silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), or other semiconductor materials. A layer of conductive material is deposited on the substrate 101 as the first electrode layer 102 by methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or electroplating. In the embodiment of the present application, the material of the first electrode layer 102 is SrTiOx.

[0049] On the surface of the first electrode layer 102 away from the substrate 101, a dielectric material is deposited using a thin film deposition process, such as CVD, PVD, ALD, etc. In the embodiment of the present application, the material of the dielectric layer 103 is SrRuOx. The deposition process is used again, such as PVD, CVD, etc., to deposit a layer of Au material on the surface of the dielectric layer 103 away from the substrate 101 as the second electrode layer 104, as Figure 4 shown. Then, through a photolithography process, the second electrode layer 104 is precisely patterned into a structure including a first electrode 1041 and a second electrode 1042 arranged along the first direction, as shown in the X direction in the figure, that is, parallel to the substrate 101 direction, as Figure 5 shown.

[0050] Step S20: As Figure 6 and Figure 7 shown, a conductive structure 107 is formed. The conductive structure 107 penetrates through the second electrode 1042, dielectric layer 103, and first electrode layer 102, and the conductive structure 107 is electrically connected to the second electrode 1042 and the first electrode layer 102.

[0051] Exemplarily, forming the conductive structure 107 further includes etching the second electrode 1042, dielectric layer 103, and first electrode layer 1041 of the Figure 6 shown structure using FIB. By adjusting the scanning path, energy, and beam current size of the ion beam, a part of the second electrode 1042, dielectric layer 103, and first electrode layer 104 is precisely removed to form a via 109 that penetrates these layers. The actual effect diagram is as Figure 14 (b) shown. This process requires a high degree of precision and control to ensure that the shape, depth, and position of the via 109 meet the design requirements.

[0052] The conductive material platinum (Pt) is filled into the via 109 through chemical vapor deposition (CVD), physical vapor deposition (PVD), or electroplating to form the conductive structure 107, as Figure 7 shown. During the filling process, it is necessary to ensure that the conductive material can be filled into the via 109 evenly and densely to form a good conductive path. After filling, chemical mechanical polishing (CMP) or other planarization processes may be required to remove the excess conductive material around the via and ensure the flatness of the entire surface. The actual effect diagram is as Figure 14 (c) shown.

[0053] And the conductive structure 107 is electrically connected to the second electrode 1042 and the first electrode layer 102, and this process makes the second electrode 1042 and the first electrode layer 102 in a short - circuit state.

[0054] Step S30: As Figure 8 and Figure 9 shown, a first isolation structure 108 is formed. The first isolation structure 108 penetrates through the first electrode 1041, the dielectric layer 103, and the first electrode layer 102; in the first direction, the first isolation structure 108 divides the first electrode 1041 into a probe placement portion 111 and a limiting region electrode 112.

[0055] Exemplarily, as Figure 8 and Figure 9 shown, forming the first isolation structure 108 further includes etching the first electrode 1041, the dielectric layer 103, and the first electrode layer 102 using the Focused Ion Beam (FIB) technology, so as to precisely remove a part of the first electrode 1041, the dielectric layer 103, and the first electrode layer 102, as Figure 8 shown. By adjusting the scanning path and energy of the ion beam, an isolation groove 110 that penetrates through the first electrode 1041, the dielectric layer 103, and the first electrode layer 102 can be formed. The depth and width of the isolation groove 110 can be adjusted according to specific design requirements.

[0056] The material filled in the isolation groove 110 is usually insulating, such as silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ) or other low - dielectric - constant materials to ensure electrical isolation between adjacent electrodes or functional regions. The actual effect diagram is as Figure 14As shown in (f). The filling process can be carried out by chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable deposition techniques. These techniques can ensure that the insulating material is uniformly and densely filled into the isolation trench 110 to form a good isolation structure. After the filling is completed, chemical mechanical polishing (CMP) or other planarization processes are required to remove the excess insulating material and ensure the flatness of the entire surface, facilitating the subsequent processes. At the same time, the first electrode 1041 is divided into two parts along the first direction, i.e., the X direction. One part is located on one side of the isolation structure 108 as the probe placement part 111, and the other part is located on the other side of the isolation structure as the limiting area electrode 112.

[0057] Step S40: As Figure 10 shown, a connection electrode 106 is formed on the side of the first electrode 1041 away from the substrate 101. In the first direction, the connection electrode 106 straddles the first isolation structure 108 and is electrically connected to the probe placement part 111 and the limiting area electrode 112.

[0058] Exemplarily, as Figure 10 shown, the connection electrode 106 is formed on the side of the first electrode 1041 away from the substrate 101 by sputtering, evaporation or electroplating, photolithography and etching. The material of the connection electrode 106 can be platinum (Pt), and in the first direction, i.e., the X direction as shown in the figure, the connection electrode 106 straddles the first isolation structure 108 and is electrically connected to the probe placement part 111 and the limiting area electrode 112.

[0059] Step S50: As Figure 11 shown, a second isolation structure 114 is formed. The second isolation structure 114 penetrates the first electrode 1041, the dielectric layer 103 and the first electrode layer 102; in the second direction, i.e., the Y direction, the second isolation structure separates the limiting area electrode from the first electrode 1041; the second direction is parallel to the substrate 101 and intersects with the first direction X direction.

[0060] Exemplarily, as Figure 11 shown, using photolithography technology, a photoresist is coated on the target area, and the pattern of the second isolation structure 114 is defined through the exposure and development steps. After patterning, wet or dry etching technology is used to etch the first electrode 1041, the dielectric layer 103, and the first electrode layer 102 along the pattern defined by the photoresist. This structure penetrates the first electrode 1041, the dielectric layer 103 and the first electrode layer 102, and separates the limiting area electrode 112 from the first electrode 1041 in the second direction, i.e., the Y direction. The actual effect diagram is as Figure 14 (d) and Figure 14 (e) shown. The second isolation structure 114 is usually made of an insulating material, such as silicon dioxide (SiO 2) Silicon nitride (Si 3 N 4 ) or other suitable high-k materials.

[0061] Step S60: As Figure 12 shown, cut out the portions of the first electrode layer 102, the dielectric layer 103, and the second electrode layer 104 within the limiting region to form a device sample.

[0062] Exemplarily, as Figure 12 shown, use photolithography and etching, such as reactive ion etching, to separate the portions of the first electrode layer 102, the dielectric layer 103, and the second electrode layer 104 within the limiting region. After that, the device sample can also be completely separated by methods such as mechanical cutting, laser cutting, or chemical cutting. The actual effect diagram is as Figure 14 (a) shown.

[0063] Step S70: Thin the thickness of the device sample.

[0064] Exemplarily, ion beam etching can be used to bombard the surface of the device sample with high-energy ion beams along the Z direction to gradually thin it. At the same time, set appropriate process parameters, such as the energy and beam current of the ion beam. Perform the thinning operation in a suitable environment to ensure that the device sample is uniformly thinned to the target thickness. During the thinning process, it is necessary to regularly detect the thickness of the sample to timely adjust the process parameters.

[0065] Step S80: Perform an electric field loading test and transmission electron microscopy (TEM) characterization on the device sample.

[0066] Perform an electric field loading test, i.e., a resistive switching test, on the limited device sample. Apply a positive voltage to the first electrode 1041 for the SET operation and a positive voltage to the first electrode layer 102 for the RESET operation. The test results are as Figure 15 shown. During the SET and RESET operations, the resistance flip of the device can be measured, and it shows the same electrical behavior as the original device. Therefore, the processing method of the limited device designed in this patent can represent the electrical characteristics of the original device.

[0067] Perform conventional TEM sampling and sample preparation on the limited region device sample after the resistive switching test, and then perform transmission electron microscopy observation. The results show that the microstructure of the dielectric layer 103 changes from the original single crystal state to a local columnar crystal phase change, as shown in the bright field phase and dark field phase of Figure 16 . This result indicates that the limited device designed in the present invention can improve the characterization efficiency of the phase change of the positioning structure.

[0068] The limiting processing method of the electronic device provided by the embodiment of the present application includes sequentially forming a stacked first electrode layer 102, a dielectric layer 103, and a second electrode layer 104 on a substrate 101. The second electrode layer 104 includes two non-connected electrodes, namely a first electrode 1041 and a second electrode 1042 arranged along a first direction; forming a conductive structure 107 that penetrates the second electrode 1042, the dielectric layer 103, and the first electrode layer 102, and the conductive structure 107 is electrically connected to the second electrode 1042 and the first electrode layer 102, so that the second electrode 1042 and the first electrode layer 102 are short-circuited; forming a first isolation structure 108 that penetrates the first electrode 1041, the dielectric layer 103, and the first electrode layer 102. In the first direction, the first isolation structure 108 separates the first electrode 1041 into a probe placement part 111 and a limiting area electrode 112; forming a connection electrode 106 on the side of the first electrode 1041 away from the substrate 101. In the first direction, the connection electrode 106 straddles the first isolation structure 108 and is electrically connected to the probe placement part 111 and the limiting area electrode 112.

[0069] After the above limiting processing of the electronic device, needles are inserted into the probe placement part 111 and the second electrode 1042 to apply a voltage, so as to apply a voltage to the first electrode layer 102 and the limiting area electrode 112 for the electric field loading test of the limiting area. After the test, the limiting area is processed into a transmission electron microscope sample, so that the microstructure with structural changes can be accurately located in the observable area of the transmission electron microscope. When analyzing the device performance, failure mechanism or material properties, the changes at the microscopic level can be directly observed, which helps to deeply understand the working principle of the device and improve the design.

[0070] In some embodiments, as Figure 13 shown in the structure, the limiting processing sample further includes a buffer layer 113, and the buffer layer 113 is disposed between the first electrode layer 102 and the substrate 101. Its main function is to prevent or significantly reduce the alloying reaction that may occur between the first electrode layer 102 and the substrate 101 under high temperature or other specific conditions. The buffer layer 113 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD) or other thin film deposition techniques. Common buffer layer materials include metal titanium (Ti), chromium (Cr), nickel-chromium alloy (NiCr), etc., and these materials usually have good adhesion and anti-alloying properties.

[0071] The sample preparation method designed by the present invention has the following two advantages:

[0072] First, the sample preparation method designed in the present invention can reduce the requirements for process preparation in the existing solutions, lower the difficulty of preparing transmission electron microscope (TEM) samples, and efficiently locate the regions where structural phase transitions occur. The significant advantage of focused ion beam (FIB) lies in its ability to perform positioning processing on device structures with an accuracy of 5 nm - 1 μm. Therefore, the region where the electric field is applied can be restricted to a size range of 1 μm wide and 10 μm long by pre-processing the limit through FIB. After that, an electric field is applied to the limited device, and the region where the structural phase transition occurs must exist in the limited device. By preparing TEM samples of the limited device, the probability of successfully locating the structural phase transition can be increased. Compared with in-situ TEM sample preparation, the solution designed in the present invention reduces the thinning difficulty after the sample is transferred to the in-situ chip. In addition, compared with the method of applying an electric field to in-situ TEM samples, the method of applying load tests to the limited samples on a semiconductor tester can achieve more diverse voltage and pulse load tests, reducing the short-circuit risk that may occur in in-situ tests.

[0073] Second, the sample preparation method designed in the present invention can be applied to the limited electric field tests of different device structures and different materials, including two-terminal loading, three-terminal loading, and four-terminal loading tests. As long as the size of the test device is within the size range that can be processed by Ga ion beam, the limited thinking designed in the present invention can adjust a suitable processing scheme according to the specific device structure to reduce the effective working area to the range of TEM sample preparation size. In addition, for three-terminal loading devices and four-terminal loading devices, the processing circuit diagram can be designed according to the device layout. While retaining the test circuit connection layer, the working area can be limited within the TEM test size. The test method of the present invention can be effectively used in the limited tests of HfOx RRAM, HfZrOx FeRAM, and oxide gate structures, and can achieve two-terminal electrode loading tests, three-terminal gate-source-drain tests, and 1T1R four-terminal tests.

[0074] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed in this application who thinks of changes or substitutions should be covered within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claimed rights.

Claims

1. A method for limiting the position of an electronic device, characterized in that: include: A first electrode layer, a dielectric layer, and a second electrode layer are sequentially formed on a substrate, wherein the second electrode layer includes a first electrode and a second electrode, and the first electrode and the second electrode are arranged along a first direction, and the first direction is parallel to the substrate; forming a conductive structure, wherein the conductive structure penetrates the second electrode, the dielectric layer and the first electrode layer, and the conductive structure is electrically connected to the second electrode and the first electrode layer; forming a first isolation structure, wherein the first isolation structure penetrates the first electrode, the dielectric layer, and the first electrode layer; In the first direction, the first isolation structure separates the first electrode into a probe placement portion and a limiting region electrode; A connecting electrode is formed on a side of the first electrode away from the substrate. In the first direction, the connecting electrode crosses the first isolation structure and is electrically connected to the probe placement portion and the limiting region electrode.

2. The limiting processing method according to claim 1, characterized in that: After forming the connecting electrode, the limiting processing method further includes: forming a second isolation structure, wherein the second isolation structure penetrates the first electrode, the dielectric layer and the first electrode layer; In a second direction, the second isolation structure separates the limiting region electrode from the first electrode; the second direction is parallel to the substrate and intersects with the first direction.

3. The limiting processing method according to claim 1, characterized in that: The electronic device includes a limiting region, and after forming the connecting electrode, the limiting processing method further includes: The first electrode layer, the dielectric layer and the second electrode layer are cut out in the limiting region to form a device sample.

4. The limiting processing method according to claim 3, characterized in that: After forming the device sample, the limiting processing method further includes: The thickness of the device sample is reduced.

5. The limiting processing method according to claim 4, characterized in that: After the thickness of the device sample is reduced, the device sample is subjected to an electric field loading test and a transmission electron microscope characterization.

6. The limiting processing method according to claim 1, characterized in that: Forming the first isolation structure includes: Using a focused ion beam, etching the first electrode, the dielectric layer, and the first electrode layer to form an isolation groove penetrating the first electrode, the dielectric layer, and the first electrode layer; The isolation trench is filled with insulating material to form the first isolation structure.

7. The limiting processing method according to claim 1, characterized in that: Forming the conductive structure includes: Using a focused ion beam, etching the second electrode, the dielectric layer, and the first electrode layer to form a via hole penetrating the second electrode, the dielectric layer, and the first electrode layer; Conductive material is placed in the via hole to form the conductive structure.

8. The limiting processing method according to claim 1, characterized in that: The second electrode layer is formed, comprising: forming a conductive film on a side of the dielectric layer away from the substrate; The conductive film is etched by using a focused ion beam to obtain the first electrode and the second electrode.

9. A sample of limited processing of electronic devices, characterized in that: include: substrate; A first electrode layer, a dielectric layer, and a second electrode layer are sequentially stacked on the substrate; the second electrode layer includes a first electrode and a second electrode, the first electrode and the second electrode are arranged along a first direction, and the first direction is parallel to the substrate; a conductive structure, which penetrates the second electrode, the dielectric layer and the first electrode layer, and is electrically connected to the second electrode and the first electrode layer; A first isolation structure, extending through the first electrode, the dielectric layer and the first electrode layer; In the first direction, the first isolation structure separates the first electrode into a probe placement portion and a limiting region electrode; A connecting electrode, in the first direction, the connecting electrode crosses the first isolation structure and is electrically connected to the probe placement portion and the limiting region electrode.

10. The position limiting processing sample according to claim 9, characterized in that: The position-limiting processing sample further includes a buffer layer, and the buffer layer is arranged between the first electrode layer and the substrate.

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