Multilayer epitaxial intelligent semiconductor device and preparation method thereof

Abstract

The multi-layer epitaxial intelligent semiconductor device comprises a main semiconductor and a functional semiconductor, the functional semiconductor comprises a functional isolation region and a functional active region arranged on the inner side of the functional isolation region, and the functional isolation region comprises a second conductive type first functional column arranged in a first conductive type epitaxial layer and a second conductive type second functional column arranged in a second conductive type epitaxial layer. The second conductive type second functional column is arranged on the front surface of the second conductive type first functional column and is connected with the second conductive type first functional column, and the width of the second conductive type second functional column in the first direction is smaller than that of the second conductive type first functional column in the first direction; the functional active region comprises a second conduction type third functional column and is arranged in the first conduction type epitaxial layer, and the width of the second conduction type third functional column in the first direction is larger than that of the second conduction type second functional column in the first direction. And the peak electric field is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular, to a multi-layer epitaxial intelligent semiconductor device and a manufacturing method thereof. Background Art

[0002] A semiconductor device is an electronic device with conductivity between that of a good conductor and an insulator, which utilizes the special electrical properties of semiconductor materials to complete specific functions. It can be used to generate, control, receive, transform, amplify signals, and perform energy conversion. With the rapid development of emerging industries such as new energy, there is an increasing demand for high-power, high-voltage withstand, and high-reliability power semiconductor devices. Among them, as a new type of power device, the superjunction device is widely used in high-voltage and high-power power electronic equipment due to its advantages of low on-resistance and high breakdown voltage.

[0003] An intelligent superjunction semiconductor device is based on a common superjunction device and integrates functional semiconductors such as a sampling semiconductor, a starting semiconductor, and a high-resistance R, or only integrates one of the sampling semiconductor and the starting semiconductor, and their functions are independent of each other and do not affect each other during the working state. The superjunction product is composed of multiple groups of P / N columns connected alternately. To ensure the independence of functional semiconductors from each other, isolation design is required between functional semiconductors. For the isolation design, it is also achieved through the arrangement of P / N columns. When arranging the isolation P / N columns, the isolation voltage between MOSs and the breakdown voltage of the die need to be considered.

[0004] Currently, in the prior art, as shown in Figure 1 For the isolation design of an intelligent superjunction semiconductor device, only by designing horizontal P / N columns between vertical P / N columns for isolation. Although this isolation design can meet the die breakdown voltage requirement, in actual process, after the high-temperature annealing process of the active regions of the sampling semiconductor and the starting semiconductor, they will be connected to the main active region of the device, resulting in unstable isolation voltage with large fluctuations, and even a situation where the voltage is lower than 50V. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a multi-layer epitaxial intelligent semiconductor device to solve the technical problems of unstable isolation voltage, large fluctuations, and low isolation voltage in the prior art.

[0006] The present invention provides a multi-layer epitaxial intelligent semiconductor device, including a main semiconductor and at least one functional semiconductor integrally arranged, the functional semiconductor is arranged in the main semiconductor, and the functional semiconductor includes a functional isolation region and a functional active region arranged inside the functional isolation region; The functional isolation region, the functional active region, and the main semiconductor share a first-conductivity-type substrate and a first-conductivity-type epitaxial layer, and the first-conductivity-type epitaxial layer is disposed on the front surface of the first-conductivity-type substrate; The functional isolation region includes: At least two second-conductivity-type first functional pillars, which are disposed in the first-conductivity-type epitaxial layer; A second-conductivity-type second functional pillar, which is disposed on the front surface of each of the second-conductivity-type first functional pillars and is connected to the second-conductivity-type first functional pillar, and the width of the second-conductivity-type second functional pillar in the first direction is less than the width of the second-conductivity-type first functional pillar in the first direction; The functional active region includes second-conductivity-type third functional pillars, at least two of which are disposed in the first-conductivity-type epitaxial layer, and the width of the second-conductivity-type third functional pillars in the first direction is greater than the width of the second-conductivity-type second functional pillars in the first direction; Each of the second-conductivity-type second functional pillars corresponding to each of the second-conductivity-type first functional pillars has at least two and is connected to the corresponding second-conductivity-type first functional pillar, and the two second-conductivity-type second functional pillars are arranged in parallel, and adjacent two of the second-conductivity-type second functional pillars are separated by the middle first-conductivity-type epitaxial layer; The width of the second-conductivity-type second functional pillar in the first direction is set to be half of the width of the second-conductivity-type first functional pillar in the first direction.

[0007] Optionally, the first-conductivity-type epitaxial layer includes a plurality of sub-epitaxial layers stacked in sequence, the sub-epitaxial layers include a plurality of first sub-epitaxial layers and a plurality of second sub-epitaxial layers, the second sub-epitaxial layers are disposed on the front surfaces of the first sub-epitaxial layers, and the first sub-epitaxial layers and the second sub-epitaxial layers are stacked in sequence; The second-conductivity-type first functional pillars are disposed in the first sub-epitaxial layer and extend towards the second sub-epitaxial layer, the second-conductivity-type second functional pillars are disposed in the second sub-epitaxial layer, and the second-conductivity-type third functional pillars extend from the first sub-epitaxial layer near the first-conductivity-type substrate towards the second sub-epitaxial layer direction until they extend into the second sub-epitaxial layer.

[0008] Optionally, the sub-epitaxial layer includes a plurality of third sub-epitaxial layers, and the plurality of third sub-epitaxial layers are stacked in sequence on the front surface of the second sub-epitaxial layer; The functional isolation region further includes a second-conductivity-type fourth functional pillar, and the second-conductivity-type fourth functional pillar is disposed in the third sub-epitaxial layer and extends along the stacking direction of the plurality of sub-epitaxial layers until it is connected to the corresponding second-conductivity-type functional pillar; The width of the fourth functional pillar of the second conductivity type in the first direction is greater than the width of the second functional pillar of the second conductivity type in the first direction.

[0009] Optionally, N layers of the sub-epitaxial layer are stacked in sequence, where the thickness of the nth sub-epitaxial layer is not greater than the thickness of the (n - 1)th sub-epitaxial layer, and the thickness of the nth sub-epitaxial layer is less than the thickness of the first sub-epitaxial layer.

[0010] Optionally, a field oxide layer is provided on the front surface of the first conductivity type epitaxial layer, and the field oxide layer is provided in the region of the corresponding functional isolation region on the first conductivity type epitaxial layer.

[0011] Optionally, the functional semiconductor is set as a sampling semiconductor and / or a starting semiconductor.

[0012] Optionally, the main semiconductor includes: Second conductivity type main pillars, at least two, extending from the front surface to the back surface of the first conductivity type epitaxial layer; Second conductivity type body region, provided on the front surface of the first conductivity type epitaxial layer and located within the first conductivity type epitaxial layer; First conductivity type source region, provided on the front surface of the second conductivity type body region and located within the second conductivity type body region; Gate structure, provided between two adjacent second conductivity type main pillars and provided on the front surface of the second conductivity type epitaxial layer.

[0013] The present invention also provides a method for manufacturing a multi-layer epitaxial intelligent semiconductor device, including: Select a first conductivity type substrate, and grow a first sub-epitaxial layer on the first conductivity type substrate; Through photolithographic masking, implant second conductivity type ions into the functional isolation region, functional active region, and part of the region of the main semiconductor corresponding to the first sub-epitaxial layer to form a second conductivity type first functional pillar region, a second conductivity type third functional pillar region, and a second conductivity type main pillar region; Continuously epitaxially grow multiple layers of the first sub-epitaxial layer, and continuously implant second conductivity type ions; Continuously epitaxially grow multiple layers of the second sub-epitaxial layer, and implant second conductivity type ions to form multiple rows of second conductivity type second functional pillar regions, second conductivity type third functional pillar regions, and second conductivity type main pillar regions; Continuously epitaxially grow multiple layers of the third sub-epitaxial layer and implant second conductivity type ions in part of the regions of the multiple layers of the third sub-epitaxial layer to form multiple rows of second conductivity type fourth functional pillar regions, second conductivity type third functional pillar regions, and second conductivity type main pillar regions; High-temperature promotion is carried out, and diffusion connection is formed to form the first functional column of the second conduction type, the second functional column of the second conduction type, the third functional column of the second conduction type, the fourth functional column of the second conduction type, and the main column of the second conduction type; A field oxide layer is grown on the front surface of the epitaxial layer of the first conduction type, and the field oxide layer in the main semiconductor and functional active region is etched away; A gate oxide layer is grown on the front surface of the epitaxial layer of the first conduction type at the main semiconductor and functional active region, and polysilicon is deposited on the gate oxide layer to form a gate structure; Ions of the second conduction type are implanted into the front surface of the epitaxial layer of the first conduction type without a gate structure and a field oxide layer, and high-temperature promotion is carried out to form a body region of the second conduction type; Through photolithographic masking, ions of the first conduction type are implanted into a partial region on the front surface of the body region of the second conduction type, and high-temperature promotion is carried out to form a source region of the first conduction type; An insulating dielectric layer is deposited on the front surface of the epitaxial layer of the first conduction type, and metal is deposited on the front surface of the insulating dielectric layer to form a front metal layer, and metal is deposited on the back surface of the substrate of the first conduction type to form a back metal layer, The technical solution of the present invention has the following advantages: 1. For the multi-layer epitaxial intelligent semiconductor device provided by the present invention, by providing the first functional column of the second conduction type and the second functional column of the second conduction type in the functional isolation region, and the width of the second functional column of the second conduction type in the first direction is less than the width of the first functional column of the second conduction type in the first direction, the functional active region is isolated. The isolation effect is better than that of only setting P / N columns in the functional isolation region before. After the semiconductor structure undergoes a high-temperature annealing process, the independence of the functional active region can still be guaranteed, and the isolation voltage is stable, the isolation electric field is smoother, and the peak electric field is effectively reduced. Therefore, it can ensure a stable isolation voltage under the condition that the voltage of the main semiconductor remains unchanged, increasing the design window, which can reach more than 200V.

[0014] 2. The arrangement of multiple first sub-epitaxial layers and multiple second epitaxial layers in the multi-epitaxial intelligent semiconductor device provided by the present invention enables the formation of first functional columns of a second conductivity type layer by layer within the first sub-epitaxial layer, and the formation of second functional columns of a second conductivity type layer by layer within the second sub-epitaxial layer. The connection of the first functional columns of the second conductivity type and the second functional columns of the second conductivity type can be achieved by high-temperature promotion. In production, it will not change the original production process too much. Only when growing the first sub-epitaxial layer and the second sub-epitaxial layer, it is necessary to inject ions of the second conductivity type, which is more convenient for forming the first functional columns of the second conductivity type and the second functional columns of the second conductivity type. Especially when the first functional columns of the second conductivity type and the second functional columns of the second conductivity type form a Y-shaped structure, compared with other preparation methods, it can not only obtain the advantages brought by the multi-epitaxial technology, but also form the Y-shaped structure more quickly, conveniently and stably, without multiple trench digging and filling. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0016] Figure 1 Schematic diagram of the prior art in the background art of the present invention; Figure 2 Schematic diagram of the structure of the multi-epitaxial intelligent semiconductor device in the present invention; Figure 3 is Figure 2 enlarged view of part A in; Figure 4 Front-end step diagram of the preparation method of the intelligent semiconductor device in the present invention; Figure 5 Back-end step diagram of the preparation method of the intelligent semiconductor device in the present invention.

[0017] Description of the reference numerals: 1. Substrate of the first conductivity type; 2. Epitaxial layer of the first conductivity type; 21. Sub-epitaxial layer; 211. First sub-epitaxial layer; 212. Second sub-epitaxial layer; 213. Third sub-epitaxial layer; 3. First functional pillar of the second conductivity type; 31. Region of the first functional pillar of the second conductivity type; 4. Second functional pillar of the second conductivity type; 41. Region of the second functional pillar of the second conductivity type; 5. Third functional pillar of the second conductivity type; 51. Region of the third functional pillar of the second conductivity type; 6. Fourth functional pillar of the second conductivity type; 61. Region of the fourth functional pillar of the second conductivity type; 7. Field oxide layer; 8. Main pillar of the second conductivity type; 81. Region of the main pillar of the second conductivity type; 9. Body region of the second conductivity type; 10. Source region of the first conductivity type; 11. Gate structure; 12. Gate oxide layer; 13. Insulating dielectric layer; 14. Front metal layer; 15. Back metal layer; 16. Main semiconductor; 17. Functional isolation region; 18. Functional active region. Detailed implementation manners

[0018] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the description of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0019] Unless otherwise clearly defined and limited, the terms "arranged", "installed", "connected", etc. shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific situations.

[0020] The orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the invention is usually placed during use. It is only for the convenience of description and simplification of the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0021] The terms "first", "second", "third", etc. are only used to distinguish elements with similar attributes, rather than indicating or implying relative importance or a specific order.

[0022] The term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion. In addition to the listed elements, it may also include other elements not specifically listed.

[0023] Embodiment The present invention provides a multi-layer epitaxial intelligent semiconductor device. The semiconductor device is set as a MOSFET device or an IGBT device. In this embodiment, the MOSFET device is taken as an example. The MOSFET device includes an N-type MOSFET device and a P-type MOSFET device. For the N-type MOSFET device, the first conduction type is N-type and the second conduction type is P-type; for the P-type MOSFET device, the first conduction type is P-type and the second conduction type is N-type. In this embodiment, the N-type MOSFET device is taken as an example.

[0024] Refer to Figure 2 and Figure 3 As shown, the multi-layer epitaxial intelligent semiconductor device includes a main semiconductor 16 and at least one functional semiconductor which are integrally arranged. In this embodiment, the functional semiconductor is set as a sampling semiconductor and / or a starting semiconductor. Further, in this embodiment, one sampling semiconductor and one starting semiconductor are provided.

[0025] Specifically, the functional semiconductor is arranged inside the main semiconductor 16 and surrounded by the main semiconductor 16. The functional semiconductor includes a functional isolation region 17 and a functional active region 18 arranged inside the functional isolation region 17 and surrounded by the functional isolation region 17. The functional active region 18, the functional isolation region 17 and the main semiconductor 16 share a first conduction type substrate 1 and a first conduction type epitaxial layer 2, and the first conduction type epitaxial layer 2 is arranged on the front surface of the first conduction type substrate 1.

[0026] The first conduction type epitaxial layer 2 includes a plurality of sub-epitaxial layers 21 stacked in sequence. The sub-epitaxial layer 21 includes a plurality of first sub-epitaxial layers 211 and a plurality of second sub-epitaxial layers 212. The second sub-epitaxial layer 212 is arranged on the front surface of the first sub-epitaxial layer 211, and the first sub-epitaxial layer 211 and the second sub-epitaxial layer 212 are stacked in sequence.

[0027] The functional isolation region 17 includes a first functional column 3 of a second conductivity type and a second functional column 4 of a second conductivity type. Among them, at least two first functional columns 3 of a second conductivity type are provided, which are arranged in the first sub-epitaxial layer 211 and extend from the lowermost first sub-epitaxial layer 211 into the uppermost first sub-epitaxial layer 211. The second functional column 4 of a second conductivity type is arranged corresponding to the first functional column 3 of a second conductivity type. A second functional column 4 of a second conductivity type is provided at each first functional column 3 of a second conductivity type. The second functional column 4 of a second conductivity type is arranged in the second sub-epitaxial layer 212 on the front surface of the first functional column 3 of a second conductivity type and extends from the lowermost second sub-epitaxial layer 212 into the uppermost second sub-epitaxial layer 212. The second functional column 4 of a second conductivity type is connected to the first functional column 3 of a second conductivity type to form an integral body. The width of the second functional column 4 of a second conductivity type in the first direction is smaller than the width of the first functional column 3 of a second conductivity type in the first direction; At this time, the functional active region 18 includes a third functional column 5 of a second conductivity type. At least two third functional columns 5 of a second conductivity type are provided, and they extend from the first sub-epitaxial layer 211 close to the first conductivity type substrate 1 towards the second sub-epitaxial layer 212 until they extend into the uppermost second sub-epitaxial layer 212. The width of the third functional column 5 of a second conductivity type in the first direction is larger than the width of the second functional column 4 of a second conductivity type in the first direction, and the width of the third functional column 5 of a second conductivity type in the first direction is the same as the width of the first functional column 3 of a second conductivity type in the first direction. And in Figure 1 the direction indicated by the arrow x is the first direction.

[0028] The traditional functional isolation region 17 is a P / N column with a single width. The charge balance depends on the precise control of the doping concentration. During the high-temperature annealing process, the influence of the lateral diffusion of doping ions is large, and it is easy to connect with the active region, resulting in the effective carrier concentration in the column region deviating from the design value, destroying the charge balance, and further reducing the isolation voltage. By providing a first functional column 3 of a second conductivity type and a second functional column 4 of a second conductivity type in the functional isolation region 17, and the width of the second functional column 4 of a second conductivity type in the first direction is smaller than the width of the first functional column 3 of a second conductivity type in the first direction, the functional active region 18 is isolated. Since the width of the second functional column 4 of a second conductivity type in the first direction is smaller than the width of the first functional column 3 of a second conductivity type in the first direction, the relative influence of the lateral distance during high-temperature annealing is smaller. In addition, the charge distribution is more refined, the charge imbalance degree is low, and the boundary with the main semiconductor 16 can still be maintained clear at high temperature, avoiding the carrier interdiffusion with the adjacent region and resulting in the connection with the main semiconductor 16. The isolation effect is better than the effect of only setting P / N columns in the functional isolation region 17 before, and the independence of the functional active region 18 can still be ensured after the semiconductor device undergoes the high-temperature annealing process; Meanwhile, by reducing the column width of the second functional pillar 4 of the second conductivity type, a secondary electric field step is formed on the side close to the active region, making the electric field distribution stepped. By discretizing the charge distribution, the electric field concentration effect of the traditional single-column structure is reduced, the peak electric field is lowered, and thus the isolation electric field becomes smoother, effectively reducing the peak electric field and avoiding local breakdown. Since the peak electric field is reduced, a stable isolation voltage can be ensured while the voltage of the main semiconductor 16 remains unchanged, increasing the design window to over 200V.

[0029] In addition, the arrangement of multiple first sub-epitaxial layers 211 and multiple second sub-epitaxial layers 212 enables the formation of the first functional pillar 3 of the second conductivity type layer by layer within the first sub-epitaxial layer 211 and the formation of the second functional pillar 4 of the second conductivity type layer by layer within the second sub-epitaxial layer 212. The connection of the first functional pillar 3 of the second conductivity type and the second functional pillar 4 of the second conductivity type can be achieved by high-temperature promotion without multiple trench etching and filling. In production, it is more convenient than the deep trench process to form the first functional pillar 3 of the second conductivity type and the second functional pillar 4 of the second conductivity type.

[0030] As a specific implementation manner, two second functional pillars 4 of the second conductivity type corresponding to each first functional pillar 3 of the second conductivity type are provided, and both ends facing the first functional pillar 3 of the second conductivity type are connected to the first functional pillar 3 of the second conductivity type. The two second functional pillars 4 of the second conductivity type are arranged in parallel. The width of the second functional pillar 4 of the second conductivity type in the first direction is set to be half of the width of the first functional pillar 3 of the second conductivity type in the first direction. The adjacent two second functional pillars 4 of the second conductivity type are separated by the middle second sub-epitaxial layer 212. The width ratio of the second functional pillar 4 of the second conductivity type to the second sub-epitaxial layer 212 therebetween is kept consistent with the width ratio of the first functional pillar 3 of the second conductivity type to the first sub-epitaxial layer 211 therebetween; By setting the number of the second functional columns 4 of the second conductivity type to two and setting the widths of the two second functional columns 4 of the second conductivity type to half of that of the first functional column 3 of the second conductivity type, the ratio of the width of the second functional column 4 of the second conductivity type to the width of the first conductive type epitaxial layer 2 therebetween is ensured to be the same as the ratio of the width of the first functional column 3 of the second conductivity type to the width of the first conductive type epitaxial layer 2 therebetween, avoiding the situation where only one second functional column 4 of the second conductivity type is provided on the front surface of the first functional column 3 of the second conductivity type and the width of the second functional column 4 of the second conductivity type is less than the width of the first functional column 3 of the second conductivity type at this time, which would cause the width of the first conductive type epitaxial layer 2 between the adjacent second functional columns 4 of the second conductivity type to become more than twice the width of the second functional column 4 of the second conductivity type. To ensure charge balance, it would be necessary to readjust the ion concentration in the first conductive type epitaxial layer 2 between the two second functional columns 4 of the second conductivity type here, which would invisibly increase the preparation steps, raise the preparation cost, and increase the preparation time. In this embodiment, two second functional columns 4 of the second conductivity type are provided at each first functional column 3 of the second conductivity type, and the size ratio is the same as that of the first conductive type epitaxial layer 2 between the first functional columns 3 of the second conductivity type below, directly ensuring charge balance up and down without the need to additionally adjust the ion concentration, reducing the preparation steps, the preparation cost, and the time.

[0031] In addition, when the number of the second functional columns 4 of the second conductivity type is set to two, the second functional columns 4 of the second conductivity type and the first functional columns 3 of the second conductivity type form a Y-shaped structure at this time. By preparing the Y-shaped structure through the method of multi-layer epitaxy, compared with other preparation methods, it can not only obtain the advantages brought by the multi-layer epitaxy technology, but also form the Y-shaped structure more quickly, conveniently, and stably. The preparation of the Y-shaped structure is further facilitated, and only the second conductivity type ions need to be implanted during multi-layer epitaxy.

[0032] As an alternative embodiment, the sub-epitaxial layer 21 further includes a plurality of third sub-epitaxial layers 213, and the plurality of third sub-epitaxial layers 213 are sequentially stacked on the front surface of the second sub-epitaxial layer 212. At each first functional pillar 3 of the second conductivity type, a fourth functional pillar 6 of the second conductivity type is correspondingly provided. The fourth functional pillar 6 of the second conductivity type is disposed within the third epitaxial layer and extends from the back surface to the front surface of the third epitaxial layer. One end of the fourth functional pillar 6 of the second conductivity type is connected to two corresponding second functional pillars 4 of the second conductivity type. The width of the fourth functional pillar 6 of the second conductivity type in the first direction is greater than the width of the second functional pillar 4 of the second conductivity type in the first direction. And in this embodiment, it can be further set that the width of the fourth functional pillar 6 of the second conductivity type is the same as or close to the width of the first functional pillar 3 of the second conductivity type. By providing the fourth functional pillar 6 of the second conductivity type, when other structures are provided on the front surface of the first conductivity type epitaxial layer 2, it is the same as the conventional setting, and there is no need to adjust the parameters or dimensions of other structures just because only the second functional pillar 4 of the second conductivity type is provided, making the production more convenient. Additionally, at this time, the third functional pillar 5 of the second conductivity type will extend into the third sub-epitaxial layer 213 until it extends into the uppermost third sub-epitaxial layer 213.

[0033] As a specific embodiment, the sub-epitaxial layer 21 is sequentially stacked with n layers from the front surface of the first conductivity type substrate 1 towards the second conductivity type body region 9, that is, in the direction from bottom to top. Among them, the thickness of the nth sub-epitaxial layer 21 is not greater than the thickness of the (n - 1)th sub-epitaxial layer 21, and the thickness of the nth sub-epitaxial layer 21 is less than the thickness of the first sub-epitaxial layer 21. In this embodiment, the sub-epitaxial layer 21 is provided with 7 - 13 layers. Further, in this embodiment, the sub-epitaxial layer 21 is provided with 8 layers. By gradually reducing the thickness of the plurality of sub-epitaxial layers 21 from bottom to top, a uniform electric field distribution is achieved, so that the electric field is more evenly distributed throughout the first conductivity type epitaxial layer 2, improving the breakdown voltage capability of the device, effectively controlling the electric field gradient of each sub-epitaxial layer 21, making the electric field change gradually between different layers, avoiding the possible sudden change of the electric field in a single sub-epitaxial layer 21, refining the current-carrying capacity, and achieving charge balance.

[0034] On the front surface of the first-conductivity-type epitaxial layer 2, a field oxide layer 7 is provided. The field oxide layer 7 is disposed in the region of the corresponding functional isolation region 17 on the first-conductivity-type epitaxial layer 2. In addition, the main semiconductor 16 includes second-conductivity-type main columns 8, a second-conductivity-type body region 9, a first-conductivity-type source region 10, and a gate structure 11. Among them, at least two second-conductivity-type main columns 8 are provided. The second-conductivity-type main columns 8 extend from the front surface of the first-conductivity-type epitaxial layer 2 toward the back surface of the first-conductivity-type epitaxial layer 2. The width of the second-conductivity-type main columns 8 in the first direction is the same as the width of the second-conductivity-type first functional columns 3 in the first direction. The second-conductivity-type body region 9 is disposed on the front surface of the first-conductivity-type epitaxial layer 2 and is located within the first-conductivity-type epitaxial layer 2. The first-conductivity-type source region 10 is disposed on the front surface of the second-conductivity-type body region 9 and is located within the second-conductivity-type body region 9. The gate structure 11 is disposed between two adjacent second-conductivity-type main columns 8 and is disposed on the front surface of the second-conductivity-type epitaxial layer. A gate oxide layer 12 is provided between the gate structure 11 and the first-conductivity-type epitaxial layer 2.

[0035] An insulating dielectric layer 13 is deposited on the front surface of the first-conductivity-type epitaxial layer 2, and the insulating dielectric layer 13 is etched to form a metal contact via. The metal contact via is opened corresponding to the second-conductivity-type body region 9. Metal is deposited on the surface of the insulating dielectric layer 13, and the metal contact via is filled to form a front metal layer 14. Metal is deposited on the back surface of the first-conductivity-type substrate 1 to form a back metal layer 15.

[0036] Embodiment 2 Refer to Figures 4 - 5 As shown, this embodiment provides a method for manufacturing an intelligent semiconductor device, including: S1, select a first-conductivity-type substrate 1, and grow a first-layer first sub-epitaxial layer 211 on the first-conductivity-type substrate 1. Among them, the first-conductivity-type substrate 1 selects an N-type silicon as the substrate, and the first sub-epitaxial layer 211 is grown by an epitaxial process; S2, through photolithographic masking, inject second-conductivity-type ions into the regions of the corresponding functional isolation region 17, functional active region 18, and main semiconductor 16 on the first sub-epitaxial layer 211, so as to form a second-conductivity-type first functional column region 31, a second-conductivity-type third functional column region 51, and a second-conductivity-type main column region 81; S3, continuously epitaxially grow multiple layers of the first sub-epitaxial layer 211 and inject second-conductivity-type ions into partial regions of the multiple layers of the first sub-epitaxial layer 211 to form multiple rows of second-conductivity-type first functional column regions 31, second-conductivity-type third functional column regions 51, and second-conductivity-type main column regions 81; S4. Continuously epitaxially grow multiple layers of a second sub-epitaxial layer 212 on the first sub-epitaxial layer 211, and implant ions of a second conduction type in partial regions of the multiple layers of the second sub-epitaxial layer 212 to form multiple rows of second-conduction-type second functional pillar regions 41, second-conduction-type third functional pillar regions 51, and second-conduction-type main pillar regions 81. S5. Continuously epitaxially grow multiple layers of a third sub-epitaxial layer 213 on the second sub-epitaxial layer 212, and implant ions of a second conduction type in partial regions of the multiple layers of the third sub-epitaxial layer 213 to form multiple rows of second-conduction-type fourth functional pillar regions 61, second-conduction-type third functional pillar regions 51, and second-conduction-type main pillar regions 81, where each row of the second-conduction-type third functional pillar regions 51 and the second-conduction-type main pillar regions 81 in S2, S3, and S4 are in the same row. S6. High-temperature drive to diffuse the second-conduction-type first functional pillar region 31, second-conduction-type second functional pillar region 41, second-conduction-type third functional pillar region 51, second-conduction-type fourth functional pillar region 61, and second-conduction-type main pillar region 81, so that each row of the second-conduction-type first functional pillar region 31, second-conduction-type second functional pillar region 41, second-conduction-type third functional pillar region 51, second-conduction-type fourth functional pillar region 61, and second-conduction-type main pillar region 81 are diffused and connected to form a second-conduction-type first functional pillar 3, second-conduction-type second functional pillar 4, second-conduction-type third functional pillar 5, second-conduction-type fourth functional pillar 6, and second-conduction-type main pillar 8, and the second-conduction-type first functional pillar 3 is connected to the corresponding two second-conduction-type second functional pillars 4 and one second-conduction-type fourth functional pillar 6.

[0037] S7. Grow a field oxide layer 7 on the front surface of the first-conduction-type epitaxial layer 2, and etch away the field oxide layer 7 in the regions of the main semiconductor 16 and the functional active region 18. S8. Grow a gate oxide layer 12 on the front surface of the first-conduction-type epitaxial layer 2 in the regions of the main semiconductor 16 and the functional active region 18, and etch away a part of it so that the gate oxide layer 12 at this time is located between two second-conduction-type third functional pillars 5 and between two second-conduction-type main pillars 8, and deposit polysilicon on the remaining part of the gate oxide layer 12 to form a gate structure 11. S9. There are gaps between the gate structure 11 and the second-conduction-type third functional pillar 5 and between the gate structure 11 and the second-conduction-type main pillar 8, and there is no restriction of the gate oxide layer 12 and the field oxide layer 7. Inject ions of a second conduction type on the front surface of the first-conduction-type epitaxial layer 2 without the gate structure 11 and the field oxide layer 7, and perform high-temperature drive to form a second-conduction-type body region 9. S10. Through photolithography masking, inject ions of a first conduction type in partial regions on the front surface of the second-conduction-type body region 9, and perform high-temperature drive to form two first-conduction-type source regions 10. S11. Deposit an insulating dielectric layer 13 on the front surface of the epitaxial layer 2 of the first conduction type, so that the insulating dielectric layer 13 wraps the gate structure 11 and the field oxide layer 7. Then, etch the insulating dielectric layer 13 to etch out a plurality of through holes in the insulating dielectric layer 13, thereby forming metal contact through holes. The metal contact through holes are located above the body region 9 of the second conduction type. And during etching, 0.3 mm to 0.4 mm more will be etched into the epitaxial layer 2 of the first conduction type, so as to ensure that the insulating dielectric layer 13 can be completely removed, exposing the metal contact points, and ensuring the stability and reliability of electrical connection.

[0038] Deposit metal on the front surface of the insulating dielectric layer 13 and fill the metal contact through holes to form a front metal layer 14, and deposit metal on the back surface of the first conduction type substrate 1 to form a back metal layer 15.

[0039] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A multi-layer epitaxial smart semiconductor device, characterized in that: The invention comprises an integrated main semiconductor and at least one functional semiconductor, wherein the functional semiconductor is arranged in the main semiconductor, and the functional semiconductor comprises a functional isolation region and a functional active region arranged inside the functional isolation region; The functional isolation region, the functional active region and the main semiconductor share a first conductive type substrate and a first conductive type epitaxial layer, and the first conductive type epitaxial layer is arranged on the front side of the first conductive type substrate; The functional isolation area includes: At least two first functional columns of the second conductivity type are provided and are arranged in the first conductivity type epitaxial layer; A second conductive type second functional column, arranged on the front side of each second conductive type first functional column and connected to the second conductive type first functional column, wherein the width of the second conductive type second functional column in the first direction is smaller than the width of the second conductive type first functional column in the first direction; The functional active area includes at least two third functional columns of the second conductivity type and arranged in the first conductivity type epitaxial layer, and the width of the third functional column of the second conductivity type along the first direction is greater than the width of the second functional column of the second conductivity type along the first direction; At least two second conductive type second functional pillars corresponding to each second conductive type first functional pillar are provided and are connected to the corresponding second conductive type first functional pillar, the two second conductive type second functional pillars are arranged in parallel, and two adjacent second conductive type second functional pillars are separated by the first conductive type epitaxial layer in the middle; The width of the second conductive type second functional column along the first direction is set to be half of the width of the second conductive type first functional column along the first direction.

2. The multi-layer epitaxial smart semiconductor device according to claim 1, characterized in that: The first conductive type epitaxial layer includes a plurality of sub-epitaxial layers stacked in sequence, the sub-epitaxial layers include a plurality of first sub-epitaxial layers and a plurality of second sub-epitaxial layers, the second sub-epitaxial layers are arranged on the front side of the first sub-epitaxial layers, and the first sub-epitaxial layers and the second sub-epitaxial layers are stacked in sequence; The first functional column of the second conductivity type is arranged in the first sub-epitaxial layer and extends toward the second sub-epitaxial layer, the second functional column of the second conductivity type is arranged in the second sub-epitaxial layer, and the third functional column of the second conductivity type extends from the first sub-epitaxial layer close to the first conductivity type substrate toward the second sub-epitaxial layer until it extends into the second sub-epitaxial layer.

3. The multi-layer epitaxial smart semiconductor device according to claim 2, characterized in that: The sub-epitaxial layer includes a plurality of third sub-epitaxial layers, and the plurality of third sub-epitaxial layers are sequentially stacked and arranged on the front side of the second sub-epitaxial layer; The functional isolation region further includes a fourth functional column of the second conductivity type, which is arranged in the third sub-epitaxial layer and extends along the stacking direction of the plurality of sub-epitaxial layers until it is connected to the corresponding second conductive type functional column; The width of the second conductive type fourth functional column along the first direction is greater than the width of the second conductive type second functional column along the first direction.

4. The multi-layer epitaxial smart semiconductor device according to claim 2, characterized in that: The sub-epitaxial layers are stacked in sequence to form N layers, wherein the thickness of the nth sub-epitaxial layer is not greater than the thickness of the n-1th sub-epitaxial layer, and the thickness of the nth sub-epitaxial layer is less than the thickness of the 1st sub-epitaxial layer.

5. The multi-layer epitaxial smart semiconductor device according to claim 1, characterized in that: A field oxide layer is disposed on the front surface of the first conductive type epitaxial layer, and the field oxide layer is disposed in a region of the first conductive type epitaxial layer corresponding to the functional isolation region.

6. The multi-layer epitaxial smart semiconductor device according to claim 1, characterized in that: The functional semiconductor is configured as a sampling semiconductor and / or a starting semiconductor.

7. The multi-layer epitaxial smart semiconductor device according to any one of claims 1 to 6, characterized in that: The main semiconductor comprises: At least two second conductive type main pillars are provided, extending from the front side to the back side of the first conductive type epitaxial layer; A second conductive type body region is disposed on the front surface of the first conductive type epitaxial layer and is located in the first conductive type epitaxial layer; A first conductive type source region, disposed on the front side of the second conductive type body region and located within the second conductive type body region; The gate structure is arranged between two adjacent second conductivity type main pillars and on the front side of the second conductivity type epitaxial layer.

8. A method for preparing a multi-layer epitaxial smart semiconductor device, characterized in that: include: Selecting a first conductive type substrate, and growing a first sub-epitaxial layer on the first conductive type substrate; By photolithography blocking, second conductivity type ions are implanted into the functional isolation region, the functional active region and a part of the main semiconductor region corresponding to the first sub-epitaxial layer to form a second conductivity type first functional column region, a second conductivity type third functional column region and a second conductivity type main column region; Continuously epitaxially growing multiple layers of the first sub-epitaxial layer, and continuously injecting second conductive type ions; Continuously epitaxially growing multiple layers of the second sub-epitaxial layer, and implanting second conductive type ions to form multiple rows of second conductive type second functional column regions, second conductive type third functional column regions, and second conductive type main column regions; Continuously epitaxially growing multiple layers of the third sub-epitaxial layer and implanting second conductive type ions into partial regions of the multiple layers of the third sub-epitaxial layer to form multiple rows of second conductive type fourth functional column regions, second conductive type third functional column regions, and second conductive type main column regions; High temperature is promoted to diffuse and connect to form a first functional column of the second conductivity type, a second functional column of the second conductivity type, a third functional column of the second conductivity type, a fourth functional column of the second conductivity type, and a second conductive type main column; Growing a field oxide layer on the front side of the first conductive type epitaxial layer, and etching away the field oxide layer in the main semiconductor and functional active area; Growing a gate oxide layer on the front side of the first conductivity type epitaxial layer at the main semiconductor and functional active area regions, and depositing polysilicon on the gate oxide layer to form a gate structure; Implanting second conductive type ions on the front side of the first conductive type epitaxial layer without the gate structure and the field oxide layer, and advancing at high temperature to form a second conductive type body region; By photolithography blocking, first conductive type ions are implanted into a partial area on the front side of the second conductive type body region, and are advanced at high temperature to form a first conductive type source region; An insulating dielectric layer is deposited on the front side of the first conductive type epitaxial layer, and metal is deposited on the front side of the insulating dielectric layer to form a front metal layer. Metal is deposited on the back side of the first conductive type substrate to form a back metal layer.

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