Semiconductor structure and preparation method thereof

Abstract

The invention discloses a semiconductor structure and a preparation method thereof. The preparation method comprises the following steps: providing a substrate with a groove structure; an insulating material is deposited in the groove structure to form a liner layer, the liner layer covers the inner wall of the groove structure, and the thickness of the liner layer is gradually reduced in the first direction extending from the groove opening of the groove structure to the groove bottom; pre-cleaning the surface of the liner layer to form a thinned liner layer of which the thickness is gradually increased along the first direction; and filling the trench structure with the thinned liner layer with a metal material to form a conductive structure. According to the method, the liner layer with the thick upper part and the thin lower part is formed, and the liner layer is etched in the surface pre-cleaning process, but cannot be etched to penetrate and expose the side wall of the groove structure, so that the shape of the groove structure is effectively controlled, and the accuracy is good; and meanwhile, the critical dimension between the conductive structure subsequently formed in the groove structure and the adjacent grid electrode can be effectively controlled, the risk of time-dependent breakdown failure is reduced, and the dielectric property and the reliability of the semiconductor structure are greatly improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly relates to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Time Dependence Dielectric Breakdown (TDDB) is a time-related dielectric breakdown. In the middle-of-line (MEOL) process of semiconductors, effective control of TDDB performance is crucial for the reliability of semiconductor structures. Among them, the distance between the conductive structure formed in the trench structure of the semiconductor structure and the gate is a very critical factor. If the distance between the conductive structure and the gate is too close, TDDB failure is more likely to occur. Therefore, optimizing the critical dimension and profile shape of the conductive structure is an important research direction for improving TDDB in cutting-edge technologies.

[0003] In related MEOL technologies, during the surface pre-cleaning of the trench structure, over-etching easily occurs, accidentally etching away the sidewalls of the trench opening, increasing the distance between the top opening of the trench structure and even the sidewalls in the middle, that is, increasing the width of the original trench structure, resulting in a smaller distance between the edge of the conductive structure formed in the trench structure in subsequent processes and the adjacent gate, and easily inducing TDDB failure. Summary of the Invention

[0004] To solve the problems of the prior art, embodiments of this application provide a semiconductor structure and a method for manufacturing the same. The technical solutions are as follows:

[0005] On the one hand, this application provides a method for manufacturing a semiconductor structure, including:

[0006] Providing a substrate having a trench structure; an electrode structure is formed below the trench structure;

[0007] Depositing an insulating material in the trench structure to form a liner layer, the liner layer covering the inner wall of the trench structure, and along a first direction extending from the trench opening of the trench structure to the trench bottom, the thickness of the liner layer gradually decreases; during the formation of the liner layer, etching treatment is performed on the insulating material deposited in the trench structure to reduce the thickness difference formed by the insulating material deposited on the sidewalls of the trench structure in the first direction;

[0008] Performing surface pre-cleaning on the liner layer to remove the part of the liner layer located at the bottom of the trench structure and thinning the part of the liner layer located on the sidewalls of the trench structure to form a thinned liner layer; the thickness of the thinned liner layer gradually increases along the first direction;

[0009] Fill the trench structure having the thinned cushion layer with a metallic material to form a conductive structure.

[0010] In some exemplary embodiments, forming the cushion layer by depositing an insulating material in the trench structure includes:

[0011] Deposit the insulating material in the trench structure to form an initial cushion layer;

[0012] Etch the initial cushion layer to reduce the thickness difference of the insulating material on the sidewalls of the trench structure along the first direction until the thickness difference between the insulating material on the sidewall of the trench opening and the insulating material on the sidewall of the trench bottom reaches a preset thickness difference, thereby obtaining the cushion layer.

[0013] In some exemplary embodiments, forming the cushion layer by depositing an insulating material in the trench structure includes:

[0014] Deposit the insulating material in the trench structure to form an initial cushion layer;

[0015] Etch the initial cushion layer to reduce the thickness difference of the insulating material on the sidewalls of the trench structure along the first direction;

[0016] Repeat the above deposition step and etching step until the thickness difference between the insulating material on the sidewall of the trench opening and the insulating material on the sidewall of the trench bottom reaches a preset thickness difference, thereby obtaining the cushion layer.

[0017] Further, the number of times of the deposition step and the etching step performed to form the cushion layer is 10 to 20 times respectively.

[0018] Further, during the process of forming the cushion layer, the deposition duration of a single deposition step is 15 s to 20 s, and the etching duration of a single etching step is 3 s to 5 s.

[0019] Further, the preset thickness difference is 1 nm to 2 nm.

[0020] Further, the insulating material includes at least one of silicon nitride, silicon oxynitride, and silicon carbide.

[0021] Further, during the process of forming the cushion layer in the trench structure, the ratio of the deposition rate of the insulating material to the etching rate of the insulating material is 1.8:1 to 2.5:1.

[0022] Further, during the process of forming the cushion layer in the trench structure, the ratio of the deposition rate of the insulating material to the depth of the trench structure is 0.10 to 0.04 min -1The ratio between the etching rate of the insulating material and the depth of the trench structure is 0.06 to 0.01 min -1 .

[0023] Furthermore, the preparation method satisfies at least one of the following characteristics:

[0024] The deposition temperature used during the formation of the liner layer within the trench structure is 300 to 400 °C;

[0025] The radio frequency power used during the formation of the liner layer within the trench structure is 200 to 400 W;

[0026] The deposition pressure used during the formation of the liner layer within the trench structure is 60 to 80 Pa;

[0027] The deposition rate used during the formation of the liner layer within the trench structure is 10 to 20 nm / min.

[0028] Furthermore, the thickness of the liner layer on the sidewalls of the trench structure is 6 nm to 9 nm.

[0029] Furthermore, the width difference between the inner diameter at the top and the inner diameter at the bottom of the inner cavity of the trench structure having the thinned liner layer is 2 to 4 nm.

[0030] Furthermore, filling the trench structure having the thinned liner layer with a metal material to form a conductive structure includes:

[0031] Forming a conductive isolation layer within the trench structure having the thinned liner layer;

[0032] Filling the trench structure having the conductive isolation layer with a metal material to form a metal filling structure, thereby obtaining the conductive structure.

[0033] On the other hand, the present application also provides a semiconductor structure, the semiconductor structure includes a substrate having a trench structure, and an electrode structure is provided below the trench structure;

[0034] The trench structure has a conductive structure, and the conductive structure is in contact with the bottom wall of the trench structure;

[0035] There is a thinned liner layer between the sidewall of the trench structure and the conductive structure, and the thickness of the thinned liner layer gradually increases in a first direction extending from the notch to the bottom of the trench structure.

[0036] In the present application, an insulating material is deposited in the trench structure of the substrate to form a liner layer. By etching the insulating material during the formation of the liner layer, the thickness difference in the first direction of the insulating material deposited on the sidewall of the trench structure is reduced, so that the thickness of the liner layer on the trench sidewall is precisely controllable, and a liner layer with a thick upper part and a thin lower part is formed, avoiding the situation that the liner layer is etched through during the subsequent surface pre-cleaning process to expose the sidewall of the trench structure, and even causing the sidewall of the trench structure to be etched and lost. The shape of the trench structure can be effectively controlled with good precision; at the same time, the shape of the trench structure is precisely controllable, which can further effectively control the shape precision of the conductive structure formed subsequently in the trench structure and the critical dimension between the conductive structure and the adjacent gate, reducing the risk of time-dependent dielectric breakdown failure and greatly improving the dielectric performance and reliability of the semiconductor structure; in addition, through the etching treatment, the deposition thickness of the insulating material can be thinned to a certain extent, which not only reduces the thickness difference of the liner layer in the first direction but also reduces the thickness of the formed liner layer, avoiding the adverse effect of the too thick liner layer on the dielectric performance of the semiconductor structure, and is beneficial to synergistically improving the structural reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0038] Figure 1 It is a cross-sectional view of a semiconductor structure provided by an embodiment of the present application;

[0039] Figure 2 It is a cross-sectional view of a substrate with a trench structure provided by an embodiment of the present application;

[0040] Figure 3 It is a schematic diagram of the deposition state of the insulating material when the contact angle between the insulating material and the trench structure is different;

[0041] Figure 4 It is a flowchart of a preparation method for forming a liner layer provided by an embodiment of the present application;

[0042] Figure 5 It is a flowchart of another preparation method for forming a liner layer provided by an embodiment of the present application;

[0043] Figure 6 It is a schematic flowchart of the deposition step and the etching step alternating with time in some embodiments of the present application;

[0044] Figure 7A cross-sectional view of a trench structure with a thinned cushion layer provided by an embodiment of the present application;

[0045] Figure 8 A cross-sectional view of a trench structure with an electrically insulating layer provided by an embodiment of the present application;

[0046] Figure 9 A cross-sectional view of a semiconductor structure with a conductive structure provided by an embodiment of the present application.

[0047] Among them, the reference numerals are: 100 - substrate, 110 - trench structure, 111 - notch, 112 - bottom of the trench, 120 - electrode structure, 130 - interlayer dielectric layer, 140 - epitaxial layer, 200 - cushion layer, 201 - initial cushion layer, 202 - thinned cushion layer, 300 - conductive structure, 310 - conductive isolation layer, 320 - metal filling structure, 400 - gate. Detailed implementation manners

[0048] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0049] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe specific objects or the order of precedence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or server including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0050] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although terms such as first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of this application, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part. And when discussing the second element, component, region, layer, or part, it does not indicate that there must necessarily be a first element, component, region, layer, or part in this application.

[0051] In the manufacturing process of semiconductor devices, operations such as grooving and filling are required for structures such as the substrate in the semiconductor structure to form semiconductor devices with target structures. Among them, when preparing steps such as surface cleaning and filling of the trench structure on the substrate, the etching degree is difficult to control, and it is easy to cause excessive corrosion of the sidewalls of the trench structure, resulting in a large change in the shape of the trench structure, thereby having an adverse impact on the semiconductor structure, and even causing the finally manufactured semiconductor device to fail, reducing the preparation yield and the lifespan of the semiconductor device.

[0052] In semiconductor devices, precise control of the shape of the trench structure can effectively improve the overall performance of the semiconductor device. Among them, control of the critical dimension between the source / drain contact and the gate can effectively reduce the breakdown risk during the operation of the semiconductor device, improve the TDDB performance of the gate oxide layer, and is beneficial to extending the service life of the semiconductor device; this critical dimension refers to the critical spacing between the source / drain contact and the gate that can stably operate under normal working voltage and is not easily broken down. When the spacing between the source / drain contact and the gate is less than this adjacent dimension, breakdown is more likely to occur, resulting in the TDDB failure of the gate oxide layer.

[0053] To solve the problems of difficult precise maintenance of the shape of the above trench structure and easy TDDB failure in the middle section process of semiconductors, this application provides a semiconductor structure and its preparation method, as Figure 1As shown in the figure, a semiconductor structure provided by an embodiment of the present application includes a substrate 100 having a trench structure 110, and an electrode structure 120 is provided below the trench structure 110; a conductive structure 300 is disposed in the trench structure 110, and the conductive structure 300 is in contact with the bottom wall of the trench structure 110; a thinning cushion layer 202 is provided between the side wall of the trench structure 110 and the conductive structure 300, and the thickness of the thinning cushion layer 202 gradually increases in a first direction extending from the notch 111 of the trench structure 110 to the bottom 112; wherein, the conductive structure 300 has a conductive isolation layer 310 and a metal filling structure 320, the conductive isolation layer 310 is located on the inner wall of the thinning cushion layer 202 and the bottom surface of the trench structure 110, and the metal filling structure 320 is located in the inner cavity of the conductive isolation layer 310; the shape profile of the trench structure 110 of the semiconductor structure is accurate and excellent, and the diameter of the inner cavity of the trench structure 110 is precise, so that the critical dimension between the conductive structure 300 and the adjacent gate 400 is also precisely controlled, and its TDDB performance is greatly improved.

[0054] The manufacturing method of the semiconductor structure provided by the embodiment of the present application includes providing a substrate 100 having a trench structure 110; forming a cushion layer 200 in the trench structure 110 by depositing an insulating material, the cushion layer 200 covers the inner wall of the trench structure 110, and along a first direction extending from the notch 111 of the trench structure 110 to the bottom 112, the thickness of the cushion layer 200 gradually decreases; performing a surface pre-cleaning on the cushion layer 200 to remove the part of the cushion layer 200 located on the bottom surface of the trench structure 110 and thinning the part of the cushion layer 200 located on the side wall of the trench structure 110 to form a thinning cushion layer 202; filling a metal material in the trench structure 110 having the thinning cushion layer 202 to form a conductive structure 300. During the process of forming the cushion layer 200, an etching treatment is performed on the deposited insulating material to reduce the thickness difference formed by the insulating material deposited on the side wall of the trench structure 110 in the first direction, so that the cushion layer 200 is resistant to etching during the subsequent surface pre-cleaning process, plays a blocking role, prevents the top and middle parts of the side wall of the trench structure 110 from being over-etched, and further maintains the accuracy and reliability of the shape of the trench structure 110, avoids the diffusion of the conductive structure 300 in the trench structure 110 during the process of filling the metal material, is beneficial to maintaining the spacing between the conductive structure 300 and the adjacent gate 400, that is, is beneficial to maintaining the reliability of the source / drain contact critical dimension, improves the TDDB performance, and enhances the performance and reliability of the semiconductor structure.

[0055] The following combines Figures 1-9 to describe in detail the manufacturing method of the semiconductor structure of the embodiment of the present application.

[0056] Refer to Figure 2, a substrate 100 with a trench structure 110 is provided; an electrode structure 120 is formed below the trench structure 110.

[0057] Among them, as Figure 1 shown, there may be multiple trench structures 110 on the substrate 100. The substrate 100 includes an insulating interlayer dielectric layer 130 (ILD) and an epitaxial layer 140 (EPI) located under the interlayer dielectric layer 130. The trench structure 110 is formed in the interlayer dielectric layer 130 and stops on the epitaxial layer 140, and is used to fill a metal material in the trench structure 110 to form a conductive structure 300 in subsequent processing steps, so that interlayer interconnection is realized through the conductive structure 300 and the electrode structure 120 below; at the same time, the interlayer dielectric layer 130 forms good electrical isolation, effectively reducing the parasitic capacitance between the conductive structure 300 and the epitaxial layer 140 or the substrate 100; in some exemplary embodiments, the dielectric material of the interlayer dielectric layer 130 is silicon oxide, which has good electrical insulation and is also easy to be etched to form the trench structure 110, which is beneficial to reducing the difficulty and processing cost of semiconductor processing.

[0058] In some exemplary embodiments, the electrode structure 120 may be an active region, and the conductive structure 300 is located on and in contact with the active region, so that the active region can perform multi-layer interconnection upward through the conductive structure 300; in some other exemplary embodiments, the electrode structure 120 may also be a metal material of the next layer, so that the conductive structure 300 can perform multi-layer interconnection downward through the metal material of the lower layer until it is connected and conducted with the active region to realize multi-layer interconnection.

[0059] Specifically, the trench structure 110 is formed by patterning and etching a photoresist and / or a hard mask formed above the interlayer dielectric layer 130; in some exemplary embodiments, the trench structure 110 is obtained by all in one etch (AIO). All in one etch refers to a process in which the three steps of via etching, photoresist removal, and trench etching are completed in the same step, so as to reduce the pattern defects generated during the formation of the trench structure 110 and greatly accelerate the processing efficiency of the semiconductor structure.

[0060] Next, a liner layer 200 is formed in the trench structure 110 by depositing an insulating material. The liner layer 200 covers the inner wall of the trench structure 110, and along a first direction extending from the trench opening 111 to the trench bottom 112 of the trench structure 110, the thickness of the liner layer 200 gradually decreases, that is, the liner layer 200 has a structure that is thicker at the top and thinner at the bottom. This makes it less likely for the top and middle parts of the liner layer 200 to be completely etched compared to the bottom during the subsequent surface pre-cleaning process, effectively blocking the damage of the surface pre-cleaning to the trench structure 110, preventing excessive corrosion of the top sidewalls of the trench structure 110 during the subsequent surface pre-cleaning process, and facilitating the maintenance of the accuracy and stability of the shape of the trench structure 110 during the semiconductor structure preparation process.

[0061] During the formation of the liner layer 200, the deposition rate of the insulating material is affected by the transport rate of the insulating material, that is, the deposition rate of the insulating material is affected by the depth of the trench structure 110 and the angle at the corners; as Figure 3 shown, at the intersection of the trench bottom 112 and the sidewall of the trench structure 110, the contact angle between it and the deposited insulating material is 90°, the surface of the substrate 100 is a plane, and the contact angle between the surface of the substrate 100 and the deposited insulating material is 180°. At the trench opening 111 of the trench structure 110, the contact angle between the trench opening 111 and the deposited insulating material is 270°; the larger the contact angle, the larger the contact area with the insulating material, and the easier it is for the insulating material to deposit. Then, the deposition rate of the insulating material at the trench opening 111 is greater than the deposition rate of the insulating material on the middle sidewall of the trench structure 110. Further, the deposition rate of the insulating material on the middle sidewall of the trench structure 110 is greater than the deposition rate of the insulating material at the trench bottom 112, so that on the sidewall of the trench structure 110, the thickness of the deposited insulating material gradually decreases along the first direction extending from the trench opening 111 to the trench bottom 112, forming an overhanging structure, which is convenient for resisting the etching of the liner layer 200 during the subsequent surface pre-cleaning process, preventing the liner layer 200 from being etched through and causing the outward expansion of the sidewalls of the trench structure 110, and facilitating the maintenance of the accuracy of the shape of the trench structure 110 during the entire processing process, with good reliability.

[0062] Specifically, the insulating material used in the process of forming the liner layer 200 includes at least one of silicon nitride, silicon oxynitride, and silicon carbide. This insulating material has a lower etching rate compared to silicon oxide and is more resistant to etching during the subsequent surface pre-cleaning process to avoid the liner layer 200 being etched through and losing its blocking effect during the subsequent surface pre-cleaning process; in some exemplary embodiments, the insulating material used to form the liner layer 200 in the trench structure 110 is silicon nitride, which is easy to obtain and has a low cost.

[0063] Specifically, in the process of forming the liner layer 200, the insulating material is deposited in the trench structure 110 by at least one of physical vapor deposition, atmospheric pressure chemical vapor deposition (APCVD), low-pressure chemical vapor deposition (LPCVD), and plasma-enhanced chemical vapor deposition (PECVD); in some exemplary embodiments, silicon nitride is deposited in the trench structure 110 by plasma-enhanced chemical vapor deposition. The raw materials of the insulating material used to deposit silicon nitride in the trench structure 110 during the process of forming the liner layer 200 include disilane and nitrogen. During the process of forming the liner layer 200, disilane reacts with nitrogen to generate silicon nitride, which is deposited in the trench structure 110 to form the liner layer 200; wherein, disilane is used as the silicon source for chemical vapor deposition, and under plasma enhancement, it can generate more reactive silicon radicals, which is beneficial to accelerating the deposition rate of silicon nitride, improving the processing efficiency, and the requirements for deposition temperature and deposition pressure are lower during the deposition of silicon nitride by disilane and nitrogen, making the deposition temperature and deposition pressure during the deposition process controllable, which is beneficial to reducing the processing difficulty.

[0064] In some exemplary embodiments, the gas flow ratio of disilane to nitrogen is 20 / 60 to 20 / 140; it can be understood that this gas flow ratio can be any point value within 20 / 60 to 20 / 140; exemplarily, this gas flow ratio can be 20 / 60, 20 / 70, 20 / 80, 20 / 90, 20 / 100, 20 / 120, 20 / 140, etc.; within this gas flow ratio range, the deposition rate of silicon nitride is precisely controllable, enabling silicon nitride to be stably and reliably deposited in the trench structure 110 to form the liner layer 200, and it is also beneficial to precisely control the shape, thickness, thickness difference in the first direction, etc. of the liner layer 200 during the entire process of forming the liner layer 200, with high accuracy.

[0065] It should be noted that during the formation process of the liner layer 200, the insulating material deposited in the trench structure 110 is also etched to reduce the thickness difference formed by the insulating material deposited on the sidewalls of the trench structure 110 in the first direction, so as to avoid excessive thickness difference of the overhang structure in the first direction, which may lead to a reduction in structural stability, and it is beneficial to maintain the manufacturing yield and structural reliability of the trench structure 110, the liner layer 200, and the entire semiconductor structure.

[0066] During the etching process, the etching rate of the insulating material is also affected by the depth of the trench structure 110 and the corner angle of the trench structure 110. On the sidewalls of the deeper trench structure 110, the etching rate of the insulating material is slower, such that the etching rate of the insulating material at the notch 111 of the trench structure 110 is greater than that of the insulating material at the bottom 112 of the trench. After etching for a period of time, the thickness difference of the overhanging structure can be reduced, that is, the thickness difference between the thickness of the insulating material at the notch 111 of the trench structure 110 and the thickness of the insulating material at the bottom 112 of the trench structure 110 can be reduced, such that the formed liner layer 200 can have good structural stability and can effectively block the excessive etching of the sidewalls of the trench structure 110 during subsequent surface pre-cleaning, greatly improving the accuracy, stability, and reliability of the shape of the trench structure 110, and also effectively improving the accuracy, stability, and reliability of the critical dimension between the subsequent formed conductive structure 300 and the adjacent gate 400.

[0067] The etching process can be carried out by methods such as dry etching or wet etching. Among them, the dry etching process can be reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method can also be used, or more than one etching method can also be used.

[0068] In some exemplary embodiments, the etching gas used for etching the insulating material during the formation of the liner layer 200 is a mixed gas of CF 4 、CH 3 F and O 2 This etching gas has a relatively high etching selectivity for silicon nitride insulating materials and can stably etch silicon nitride insulating materials to form a liner layer 200 having a preset thickness difference in the first direction. At the same time, etching damage to the interlayer dielectric layer 130 is avoided as much as possible, which is beneficial to maintaining the accuracy of the shape of the trench structure 110.

[0069] Specifically, in some exemplary embodiments, the liner layer 200 is obtained through one deposition step and one etching step, that is, the formation of the liner layer 200 by depositing the insulating material in the trench structure 110 includes:

[0070] Depositing the insulating material in the trench structure 110 to form an initial liner layer 201;

[0071] Etching the initial liner layer 201 to reduce the thickness difference of the insulating material on the sidewalls of the trench structure 110 in the first direction until the thickness difference between the insulating material on the sidewall of the notch 111 and the insulating material on the sidewall of the bottom 112 reaches a preset thickness difference, thereby obtaining the liner layer 200.

[0072] Wherein, as Figure 4As shown, an initial liner layer 201 is formed through a deposition step. A thicker overhang structure is formed on the top of the initial liner layer 201. The thickness of the top of the initial liner layer 201 is much greater than the thickness of the bottom of the initial liner layer 201, that is, the thickness difference of the initial liner layer 201 in the first direction is relatively large, forming a prototype of a shape thicker at the top and thinner at the bottom, so as to resist the excessive etching in the subsequent surface pre-cleaning process.

[0073] In some exemplary embodiments, the deposition duration of the step of forming the initial liner layer 201 is 3 min to 12 min; in this way, an insulating material with a certain thickness can be deposited on the sidewalls of the trench structure 110, and after subsequent etching treatment and surface pre-cleaning liquid, the sidewalls of the trench structure 110 are not easily exposed, and it is more difficult to cause the sidewalls of the trench structure 110 to be over-corroded, greatly improving the reliability of maintaining the precise shape of the trench structure 110, being beneficial to improving the preparation yield and improving the TDDB performance of the semiconductor structure; it can be understood that the deposition duration of the step of forming the initial liner layer 201 can be any point value within 3 min to 12 min, and no further enumeration is provided here.

[0074] After that, as Figure 4 shown, the thickness of the initial liner layer 201 is thinned through an etching process, and the thinning degree of the insulating material at the top of the initial liner layer 201 is greater than the thinning degree of the insulating material at the bottom of the initial liner layer 201, so as to narrow the thickness gap between the insulating material at the top and the insulating material at the bottom of the initial liner layer 201, that is, to reduce the thickness difference between the insulating material on the sidewall of the notch 111 and the insulating material on the sidewall of the trench bottom 112. Until this thickness difference reaches a preset difference, the liner layer 200 is obtained. The thickness of the top of the liner layer 200 is slightly greater than the thickness of the bottom of the liner layer 200, so as to play an effective blocking role in subsequent steps and prevent the trench structure 110 from undergoing unexpected outward expansion.

[0075] In some exemplary embodiments, the etching duration of the step of etching the initial liner layer 201 is 0.5 min to 2 min; in this way, the thickness of the insulating material on the sidewall of the notch 111 can still maintain a state slightly greater than the thickness of the insulating material on the sidewall of the trench bottom 112, and the thickness difference between the thickness of the liner layer 200 at the notch 111 and the thickness of the liner layer 200 at the trench bottom 112 can also reach the preset thickness difference, accurately and effectively protecting the sidewalls of the trench structure 110 and avoiding the outward expansion of the sidewalls of the trench structure 110 caused by the corrosion of the trench structure 110 in the subsequent surface pre-cleaning process.

[0076] Specifically, in some exemplary embodiments, forming the liner layer 200 in the trench structure 110 by depositing an insulating material includes:

[0077] Depositing the insulating material in the trench structure 110 to form an initial liner layer 201;

[0078] Etch the initial cushion layer 201 to reduce the thickness difference of the insulating material on the sidewall of the trench structure 110 in the first direction;

[0079] Repeat the above deposition step and etching step until the thickness difference between the insulating material on the sidewall of the notch 111 and the insulating material on the sidewall of the trench bottom 112 reaches a preset thickness difference, thereby obtaining the cushion layer 200.

[0080] Taking a single deposition step and a single etching step as one round of operation, the first round of operation and the second round of operation are taken as examples for illustration. As Figure 5 shown, in the initial deposition step, the initial cushion layer 201 is formed. After that, the thickness difference of the insulating material on the sidewall of the trench structure 110 is reduced through the initial etching step; at this time, the thickness difference has not reached the preset thickness difference. On the basis of the insulating material deposited on the trench sidewall, the second round of operation is carried out, that is, the next deposition step and etching step are carried out; in the second deposition step, the insulating material on the sidewall of the notch 111 is further thickened, and relative to the insulating material deposited in the first deposition step, the thickness difference of the insulating material on the sidewall of the trench structure 110 is further increased. After that, the thickness difference is reduced through the second etching step. However, the thickness of the insulating material formed after the second round of operation is increased relative to the thickness of the insulating material formed after the first round of operation, and the thickness difference of the insulating material formed after the second round of operation in the first direction is also increased relative to the thickness difference formed after the first round of operation. Therefore, the thickness and thickness difference of the insulating material are accumulated through multiple deposition steps and etching steps, and a cushion layer 200 with a specific thickness and a preset thickness difference is obtained. The alternating deposition step and etching step enable flexible and precise control of the deposition shape of the insulating material during the preparation process, and the forming accuracy of the cushion layer 200 is high.

[0081] Specifically, as Figure 6 shown, in some exemplary embodiments, during the process of forming the cushion layer 200, the deposition step and the etching step are carried out alternately. The deposition duration of a single deposition step is 15 s to 20 s, and the etching duration of a single etching step is 3 s to 5 s; within this duration range, the thickness difference of the insulating material formed on the sidewall of the trench structure 110 after a single deposition step and a single etching step is small, and an insulating material structure can be formed in which the thickness of the insulating material at the notch 111 is slightly greater than the thickness of the insulating material at the trench bottom 112. After repeatedly performing the above deposition step and etching step multiple times, the deposition duration and the etching duration are gradually accumulated, realizing the gradual accumulation of the insulating material until a cushion layer 200 with a preset thickness difference is formed. The cushion layer 200 has a certain thickness and can withstand etching damage during the subsequent surface pre-cleaning process, avoiding the cushion layer 200 from being etched through and damaging the trench structure 110.

[0082] Specifically, the number of deposition steps and etching steps performed to form the liner layer 200 is 10 to 20 times respectively; it can be understood that the number of deposition steps and etching steps performed to form the liner layer 200 can be any integer value between 10 and 20 times, which will not be enumerated here; in this way, a liner layer 200 of sufficient thickness can be formed on the side wall of the groove structure 110 to protect the side wall of the groove structure 110 and prevent the groove structure 110 from expanding outward during subsequent processing, and the change to the final structure of the semiconductor structure can be minimized to avoid adverse effects on the performance of the semiconductor structure; in some exemplary embodiments, the number of deposition steps and etching steps performed to form the liner layer 200 is 15 to 20 times respectively.

[0083] Specifically, in the process of forming the liner layer 200 in the groove structure 110, the ratio between the deposition rate of the insulating material and the etching rate of the insulating material is 1.8:1 to 2.5:1; it can be understood that the ratio can be any point value between 1.8:1 and 2.5:1 to stably form the liner layer 200 with a preset thickness difference in the groove structure 110 with good accuracy and high reliability; for example, in an exemplary embodiment, the ratio between the deposition rate of the insulating material and the etching rate is 2:1.

[0084] Specifically, in the process of forming the liner layer 200 in the trench structure 110, the deposition rate and etching rate of the insulating material are respectively related to the depth of the trench structure 110, wherein the deeper the sidewall of the trench structure 110, the slower the deposition rate of the insulating material, and the slower the etching rate of the insulating material; in some exemplary embodiments, in the process of forming the liner layer 200 in the trench structure 110, the ratio between the deposition rate of the insulating material and the depth of the trench structure 110 is 0.10 to 0.04 min -1 , so that the insulating material forms a shape of thick top and thin bottom in the trench structure 110, and at the same time, the ratio between the etching rate of the insulating material and the depth of the trench structure 110 is 0.06-0.01min -1 , making it easier for the insulating material to be etched away at the notch 111, and cooperating with the deposition step, gradually and accurately controlling the thickness difference between the thickness of the insulating material at the notch 111 and the thickness of the insulating material at the bottom 112 of the groove, so that the thickness of the insulating material at the notch 111 is always maintained slightly larger than its thickness at the bottom 112 of the groove, which is beneficial to improving the structural accuracy of the formed liner layer 200 and ensuring the reliability of the liner layer 200 in protecting the side wall of the groove structure 110 in subsequent steps.

[0085] Specifically, the deposition temperature used in the process of forming the liner layer 200 within the trench structure 110 is 300 - 400 °C; it can be understood that this deposition temperature can be any point value within 300 - 400 °C; exemplarily, this deposition temperature can be 300 °C, 330 °C, 350 °C, 360 °C, 380 °C, 400 °C, etc.; thus, it can enable the insulating material to be stably deposited in the trench structure 110, with good deposition reliability, and is also conducive to improving the performance of the liner layer 200, reducing the internal stress of the formed liner layer 200, making the structure dense, improving the etching resistance of the liner layer 200, so that the liner layer 200 can effectively protect the trench structure 110 and prevent the trench structure 110 from diffusing during subsequent processing. In addition, at this deposition temperature, it is also conducive to improving the insulation performance of the liner layer 200, reducing charge traps, enhancing the breakdown voltage resistance, improving the TDDB performance of the semiconductor structure in this middle process, and greatly improving the electrical performance of the finally formed semiconductor structure.

[0086] Specifically, the radio frequency power used in the process of forming the liner layer 200 within the trench structure 110 is 200 - 400 W; it can be understood that this radio frequency power can be any point value within 200 - 400 W, and will not be enumerated here; at this radio frequency power, the reaction gas can be fully ionized to provide the ions, neutral atomic groups, and plasma required for the deposition of the insulating material, so as to promote the deposition of the insulating material and improve the reliability of the deposition of the insulating material. At the same time, it can improve the uniformity and density of the internal structure of the liner layer 200, reduce the occurrence of holes in the liner layer 200, and also enhance the corrosion resistance of the liner layer 200.

[0087] Specifically, the deposition pressure used in the process of forming the liner layer 200 within the trench structure 110 is 60 - 80 Pa; it can be understood that this deposition pressure can be any point value within 60 - 80 Pa, and will not be enumerated here; thus, it can effectively adjust the deposition rate of the insulating material and improve the uniformity of the internal structure of the formed liner layer 200.

[0088] Specifically, the deposition rate used in the process of forming the liner layer 200 within the trench structure 110 is 10 - 20 nm / min; it can be understood that this deposition rate can be any point value within 10 - 20 nm / min; exemplarily, this deposition rate can be 10 nm / min, 12 nm / min, 15 nm / min, 18 nm / min, 20 nm / min, etc.; thus, on the one hand, it improves the processing efficiency, and on the other hand, it is convenient to control the shape of the liner layer 200, and improve the structural density, insulation, and etching resistance of the liner layer 200.

[0089] In addition, in the multiple deposition steps performed to form the liner layer 200, the specific set values of each deposition step (or etching step) can be the same parameter values, and the parameter values include parameters affecting the deposition or etching effect such as temperature, pressure, gas flow ratio, and duration, so that the preparation process is precise and orderly, and the shape of the formed liner layer 200 is within the expected shape range; the specific set values of a single deposition step in the multiple deposition steps (or a single etching step in the multiple etching steps) can also be selected as different parameter values to flexibly control the thickness of the insulating material on the sidewalls of the trench structure 110, form a liner layer 200 with a preset thickness difference, have good preparation flexibility and fault tolerance, and can also be flexibly applied to the preparation processes of various different semiconductor structures, meet the preparation requirements of various different semiconductor structures, and have good applicability.

[0090] By effectively controlling parameters such as deposition temperature, deposition pressure, RF power, deposition rate, deposition duration, etching rate, and etching duration during the formation of the liner layer 200, synergistically controlling the deposition process and etching process of the insulating material to form a liner layer 200 with a certain shape and a preset thickness difference, greatly improving the forming accuracy of the liner layer 200, which is beneficial to improving the reliability of the trench structure 110 with the liner layer 200 to maintain its own structural shape unchanged in subsequent processing steps, and further beneficial to improving the preparation yield and semiconductor structure performance.

[0091] Specifically, in some exemplary embodiments, the preset thickness difference is 1 nm to 2 nm; it can be understood that the preset thickness difference can be any point value within 1 nm to 2 nm; for example, the preset thickness difference can be 1 nm, 1.2 nm, 1.3 nm, 1.5 nm, 1.7 nm, 1.8 nm, 2.0 nm, etc.; in this way, more residues can be left at the top and middle of the thinned liner layer 202 after surface pre-cleaning, avoiding the situation of being completely etched through, making the shape of the trench structure 110 after surface pre-cleaning accurate, the cross-section excellent, and the spacing from the gate 400 large enough, and greatly improving the TDDB performance in the middle section process of the semiconductor.

[0092] In some exemplary embodiments, during the formation of the liner layer 200, after a single deposition step and a single etching step, the thickness difference of the insulating material on the sidewalls of the trench structure 110 from the trench opening 111 to the trench bottom 112 increases by 0.06 nm to 0.4 nm. Then, through the accumulation of multiple deposition steps and multiple etching steps, a liner layer 200 with a preset thickness difference of 1 nm to 2 nm can be finally formed.

[0093] Specifically, the thickness of the liner layer 200 on the sidewalls of the trench structure 110 is 6 nm to 9 nm, and the preset thickness difference is always maintained within the range of 1 nm to 2 nm; it can be understood that this thickness can be any point value within 6 nm to 9 nm, and will not be enumerated here; in this way, a stable and effective protection can be formed on the sidewalls of the trench structure 110, avoiding damage to the trench structure 110 caused by the liner layer 200 being etched through during the subsequent surface pre-cleaning process, so that the trench structure 110 can still maintain precise boundaries and excellent profiles after subsequent processing, and the TDDB performance in the middle process of semiconductor manufacturing is greatly improved; in some preferred embodiments, the thickness of the liner layer 200 on the sidewalls of the trench structure 110 is 7 nm to 8 nm.

[0094] Next, refer to Figure 7 , perform a surface pre-cleaning on the liner layer 200 to remove the part of the liner layer 200 located at the bottom of the trench structure 110 and thin the part of the liner layer 200 located on the sidewalls of the trench structure 110 to form a thinned liner layer 202; among them, the loss rate of the liner layer 200 during the surface pre-cleaning process is also related to the depth of the trench structure 110, so that the loss amount of the top of the liner layer 200 etched is greater than the loss amount of the bottom of the liner layer 200 etched, but the insulating material will not be completely lost. Finally, the thickness of the thinned liner layer 202 gradually increases in the first direction, forming a shape that is thinner at the top and thicker at the bottom, and can still play a certain role in protecting the sidewall profile of the trench structure 110; the liner layer 200 and the thinned liner layer 202 are insulated. While maintaining the accuracy of the shape of the trench structure 110, the thinned liner layer 202 can further increase the critical dimension between the subsequent formed conductive structure 300 and the adjacent gate 400, further improve the TDDB performance, and extend the life of the semiconductor structure.

[0095] This surface pre-cleaning can use the same etching process as the etching process used in the above process of forming the liner layer 200, or can use a plasma surface treatment process. On the one hand, it can thin the thickness of the liner layer 200 on the sidewalls of the trench structure 110 and remove the insulating material in the liner layer 200 located at the bottom of the trench structure 110 to expose the bottom of the trench structure 110, so that the subsequent formed conductive structure 300 filled with metal material can be in contact and conduct with the electrode structure 120 below the bottom of the trench structure 110 to facilitate current flow; on the other hand, it can also physically and chemically modify the insulating material in the liner layer 200, improve the surface adhesion of the formed thinned liner layer 202, facilitate the subsequent filling of metal material, and enhance the stability and reliability of the formed conductive structure 300.

[0096] Specifically, the width difference between the inner diameter at the top and the inner diameter at the bottom of the cavity of the trench structure 110 with the thinned liner layer 202 is 2 to 4 nm; it can be understood that this width difference can be any point value within 2 to 4 nm; for example, this width difference can be 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, etc.; in this way, the change in the profile of the trench structure 110 is small, greatly maintaining the accuracy of the cross-sectional profile of the trench structure 110, and also avoiding the outward expansion of the trench structure 110, greatly improving the critical dimension between the subsequent formed conductive structure 300 and the adjacent gate 400 in the trench structure 110, improving the TDDB performance in the middle section process of the semiconductor, and being beneficial to improving the final preparation yield and performance reliability of the semiconductor structure.

[0097] Finally, referring to Figure 8 and Figure 9 , a metal material is filled in the trench structure 110 with the thinned liner layer 202 to form a conductive structure 300, and is connected to the electrode structure 120 below the trench structure 110 through the exposed bottom surface in the trench structure 110; wherein, the metal material is used to form the conductive structure 300, and the metal material may include one or more of aluminum metal, copper metal, silver metal, tungsten metal, and cobalt metal to form metal contacts (source / drain contacts) in the trench structure 110 of the substrate 100 to transfer current or signals.

[0098] Specifically, in some exemplary embodiments, filling the trench structure 110 with the thinned liner layer 202 with a metal material to form the conductive structure 300 includes:

[0099] Forming a conductive isolation layer 310 in the trench structure 110 with the thinned liner layer 202;

[0100] Filling the trench structure 110 with the conductive isolation layer 310 with a metal material to form a metal filling structure 320, obtaining the conductive structure 300.

[0101] Wherein, as Figure 8 shown, the conductive isolation layer 310 is deposited on the inner wall of the thinned liner layer 202 and the bottom surface of the trench structure 110, as Figure 9As shown, the metal filling structure 320 is deposited in the inner cavity of the trench structure 110 having the conductive isolation layer 310 and the thinned cushion layer 202, which can further protect the sidewalls of the trench structure 110 and reduce the possible damage to the sidewalls of the trench structure 110 during the subsequent process of filling the metal material, so that the shortest distance between the edge of the finally formed conductive structure 300 and the adjacent gate 400 is greater than or equal to the critical dimension, thereby effectively improving the TDDB performance in the middle section process of the semiconductor and extending the service life of the semiconductor structure in the working state; at the same time, the bottom surface of the trench structure 110 is exposed, and a semiconductor material can be formed between the metal material of the conductive isolation layer 310 and the non-metal material of the interlayer dielectric layer 130 or the epitaxial layer 140 exposed on the bottom surface of the trench structure 110, thereby reducing the contact resistance between the conductive structure 300 and the electrode structure 120; in some exemplary embodiments, the material of the conductive isolation layer 310 includes at least one of TI and TIN, which can form a semiconductor amorphous silicide with the silicon oxide material, greatly reducing the contact resistance and improving the contact quality.

[0102] The embodiment of the present application also provides a semiconductor device, including any one of the semiconductor structures described in the embodiment of the present application.

[0103] The embodiment of the present application also provides an electronic device, which includes any one of the semiconductor devices described in the embodiment of the present application. The electronic device can be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, etc., or an intermediate product having the semiconductor device, such as: a device main board having the semiconductor device, etc.; the electronic device adopts the semiconductor device, and correspondingly improves the working performance of the electronic device.

[0104] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, comprising: providing a substrate having a trench structure; an electrode structure is formed below the trench structure; forming a liner layer in the trench structure by depositing an insulating material, the liner layer covering the inner wall of the trench structure, and along a first direction extending from the trench opening to the trench bottom, the thickness of the liner layer gradually decreases; during the formation of the liner layer, etching treatment is performed on the insulating material deposited in the trench structure to reduce the thickness difference formed by the insulating material deposited on the sidewall of the trench structure in the first direction; performing surface pre-cleaning on the liner layer to remove the part of the liner layer located at the bottom surface of the trench structure and thinning the part of the liner layer located at the sidewall of the trench structure to form a thinned liner layer; the thickness of the thinned liner layer gradually increases along the first direction; filling a metal material in the trench structure having the thinned liner layer to form a conductive structure.

2. The manufacturing method according to claim 1, characterized in that, the forming a liner layer in the trench structure by depositing an insulating material includes: depositing the insulating material in the trench structure to form an initial liner layer; etching the initial liner layer to reduce the thickness difference of the insulating material on the sidewall of the trench structure in the first direction until the thickness difference between the insulating material on the sidewall of the trench opening and the insulating material on the sidewall of the trench bottom reaches a preset thickness difference to obtain the liner layer.

3. The manufacturing method according to claim 1, characterized in that, the forming a liner layer in the trench structure by depositing an insulating material includes: depositing the insulating material in the trench structure to form an initial liner layer; etching the initial liner layer to reduce the thickness difference of the insulating material on the sidewall of the trench structure in the first direction; repeatedly performing the above deposition step and etching step until the thickness difference between the insulating material on the sidewall of the trench opening and the insulating material on the sidewall of the trench bottom reaches a preset thickness difference to obtain the liner layer.

4. The manufacturing method according to claim 3, characterized in that, the number of deposition steps and etching steps performed to form the liner layer are respectively 10 to 20 times.

5. The manufacturing method according to claim 3, characterized in that, during the formation of the liner layer, the deposition duration of a single deposition step is 15s to 20s, and the etching duration of a single etching step is 3s to 5s.

6. The manufacturing method according to any one of claims 2 - 5, characterized in that, the preset thickness difference is 1nm to 2nm.

7. The manufacturing method according to any one of claims 1 - 5, characterized in that, the insulating material includes at least one of silicon nitride, silicon oxynitride, and silicon carbide.

8. The manufacturing method according to any one of claims 1 - 5, characterized in that, during the formation of the liner layer in the trench structure, the ratio of the deposition rate of the insulating material to the etching rate of the insulating material is 1.8:1 to 2.5:

1.

9. The manufacturing method according to any one of claims 1 - 5, It is characterized in that During the process of forming the liner layer within the trench structure, the ratio between the deposition rate of the insulating material and the depth of the trench structure is 0.10 to 0.04 min -1 , and the ratio between the etching rate of the insulating material and the depth of the trench structure is 0.06 to 0.01 min -1 .

10. The preparation method according to any one of claims 1-5, It is characterized in that The preparation method satisfies at least one of the following characteristics: The deposition temperature used in the process of forming the liner layer in the trench structure is 300-400 °C; The radio frequency power used in the process of forming the liner layer in the trench structure is 200-400 W; The deposition pressure used in the process of forming the liner layer in the trench structure is 60-80 Pa; The deposition rate used in the process of forming the liner layer in the trench structure is 10-20 nm / min.

11. The preparation method according to any one of claims 1-5, It is characterized in that The thickness of the liner layer on the side wall of the trench structure is 6 nm-9 nm.

12. The preparation method according to any one of claims 1-5, It is characterized in that The width difference between the inner diameter at the top and the inner diameter at the bottom of the inner cavity of the trench structure having the thinned liner layer is 2-4 nm.

13. The preparation method according to any one of claims 1-5, It is characterized in that Filling the trench structure having the thinned liner layer with a metal material to form a conductive structure includes: Forming a conductive isolation layer in the trench structure having the thinned liner layer; Filling the trench structure having the conductive isolation layer with a metal material to form a metal filling structure to obtain the conductive structure.

14. A semiconductor structure, It is characterized in that The semiconductor structure includes a substrate having a trench structure, and an electrode structure is provided below the trench structure; A conductive structure is provided in the trench structure, and the conductive structure is in contact with the bottom wall of the trench structure; A thinned liner layer is provided between the side wall of the trench structure and the conductive structure, and the thickness of the thinned liner layer gradually increases in a first direction extending from the notch to the bottom of the trench structure.

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