A semiconductor structure and a method of fabricating the same

Abstract

The application discloses a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate with a trench structure, a liner layer formed by depositing an insulating material in the trench structure, the liner layer covering the inner wall of the trench structure and gradually decreasing in thickness along a first direction from the opening of the trench structure to the bottom of the trench structure, a thinned liner layer formed by surface pre-cleaning of the liner layer, and a conductive structure formed by filling a metal material in the trench structure with the thinned liner layer. The liner layer is formed to be thick at the top and thin at the bottom, and is etched during the surface pre-cleaning process but not etched through to expose the sidewall of the trench structure. The shape of the trench structure is effectively controlled and has good accuracy. The critical dimension between the conductive structure formed subsequently in the trench structure and the adjacent gate can be effectively controlled, the risk of breakdown failure over time is reduced, and the dielectric performance and reliability of the semiconductor structure are greatly improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] Time Dependence Dielectric Breakdown (TDDB) is a time-dependent dielectric breakdown, and effective control of TDDB performance is crucial to the reliability of a semiconductor structure in a middle-of-line (MEOL), wherein a spacing between a conductive structure formed in a trench structure of the semiconductor structure and a gate is a very critical factor, and if the spacing between the conductive structure and the gate is too close, TDDB is more likely to fail, therefore, optimization of a critical dimension and a profile shape of the conductive structure is an important research direction for improving TDDB in front-line technology.

[0003] In related MEOL technology, when performing surface pre-cleaning on the trench structure, over-etching is likely to occur, the sidewall of the trench structure notch is accidentally etched away, the spacing between the top notch of the trench structure and the sidewall of the middle part is increased, that is, the width of the original trench structure is increased, which causes the spacing between the edge of the conductive structure formed in the trench structure and the adjacent gate to be smaller in subsequent processes, and TDDB failure is likely to be induced. SUMMARY

[0004] In order to solve the problems in the prior art, the embodiments of the present application provide a semiconductor structure and a preparation method thereof. The technical solution is as follows:

[0005] In one aspect, the present application provides a preparation method of a semiconductor structure, comprising:

[0006] providing a substrate with a trench structure; an electrode structure is formed below the trench structure;

[0007] forming a liner layer in the trench structure by depositing an insulating material, the liner layer covers the inner wall of the trench structure, and the thickness of the liner layer gradually decreases along a first direction from the notch of the trench structure to the bottom of the trench structure; during the formation of the liner layer, the deposited insulating material in the trench structure is etched to reduce the thickness difference of the insulating material deposited on the sidewall of the trench structure in the first direction;

[0008] performing surface pre-cleaning on the liner layer to remove the part of the liner layer located on the bottom surface of the trench structure, and thinning the part of the liner layer located on the sidewall of the trench structure to form a thinned liner layer; the thickness of the thinned liner layer gradually increases along the first direction;

[0009] Filling a metal material in the trench structure with the thinned liner layer to form a conductive structure.

[0010] In some example embodiments, the forming the liner layer by depositing the insulating material in the trench structure comprises:

[0011] depositing the insulating material in the trench structure to form an initial liner layer;

[0012] etching the initial liner layer to reduce the thickness difference of the insulating material on the sidewalls of the trench structure along the first direction to a preset thickness difference between the insulating material on the sidewall of the notch and the insulating material on the sidewall of the groove bottom, to obtain the liner layer.

[0013] In some example embodiments, the forming the liner layer by depositing the insulating material in the trench structure comprises:

[0014] depositing the insulating material in the trench structure to form an initial liner layer;

[0015] etching the initial liner layer to reduce the thickness difference of the insulating material on the sidewalls of the trench structure along the first direction;

[0016] repeating the above-mentioned deposition step and etching step until the thickness difference between the insulating material on the sidewall of the notch and the insulating material on the sidewall of the groove bottom reaches the preset thickness difference, to obtain the liner layer.

[0017] Further, the deposition step and etching step performed in the process of forming the liner layer are performed for 10-20 times, respectively.

[0018] Further, in the process of forming the liner layer, the deposition time of a single deposition step is 15-20s, and the etching time of a single etching step is 3-5s.

[0019] Further, the preset thickness difference is 1-2nm.

[0020] Further, the insulating material comprises at least one of silicon nitride, silicon nitride, and silicon carbide.

[0021] Further, in the process of forming the liner layer in the trench structure, the ratio between the deposition rate of the insulating material and the etching rate of the insulating material is 1.8:1-2.5:1.

[0022] Further, in the process of forming the liner layer in the trench structure, the ratio between the deposition rate of the insulating material and the depth of the trench structure is 0.10-0.04min -1The ratio between the etching rate of the insulating material and the depth of the trench structure is 0.06-0.01 min -1 .

[0023] Further, the preparation method satisfies at least one of the following features:

[0024] The deposition temperature used in the process of forming the liner layer in the trench structure is 300-400℃;

[0025] The radio frequency power used in the process of forming the liner layer in the trench structure is 200-400W;

[0026] The deposition pressure used in the process of forming the liner layer in the trench structure is 60-80Pa;

[0027] The deposition rate used in the process of forming the liner layer in the trench structure is 10-20nm / min.

[0028] Further, the thickness of the liner layer on the sidewall of the trench structure is 6-9nm.

[0029] Further, the width difference between the top inner diameter and the bottom inner diameter of the inner cavity of the trench structure with the thinned liner layer is 2-4nm.

[0030] Further, the filling of the metal material in the trench structure with the thinned liner layer to form the conductive structure comprises:

[0031] forming a conductive isolation layer in the trench structure with the thinned liner layer;

[0032] filling the metal material in the trench structure with the conductive isolation layer to form a metal filling structure, to obtain the conductive structure.

[0033] In another aspect, the present application also provides a semiconductor structure, which comprises a substrate with a trench structure, and an electrode structure below the trench structure;

[0034] The trench structure has a conductive structure therein, which is in contact with the bottom wall of the trench structure;

[0035] The sidewall of the trench structure and the conductive structure have a thinned liner layer therebetween, which gradually increases in thickness along a first direction from the opening of the trench structure to the bottom of the trench structure.

[0036] The application deposits insulating material in the trench structure of the substrate to form a liner layer, and reduces the thickness difference of the insulating material deposited on the sidewall of the trench structure in the first direction by etching the insulating material during the formation of the liner layer, so that the thickness of the liner layer on the sidewall of the trench is accurately controllable, an upper-thin lower-thick liner layer is formed, the sidewall of the trench structure is not exposed by through etching during the subsequent surface pre-cleaning process, and even the sidewall of the trench structure is not etched and lost. The shape of the trench structure can be effectively controlled, and the accuracy is good. At the same time, the shape of the trench structure is accurately controllable, which can further effectively control the shape accuracy of the conductive structure subsequently formed in the trench structure and the critical dimension between the conductive structure and the adjacent gate, reduce the risk of time breakdown failure, and greatly improve the dielectric performance and reliability of the semiconductor structure. In addition, the deposition thickness of the insulating material can be thinned to a certain extent by etching, which not only reduces the thickness difference of the liner layer in the first direction, but also reduces the thickness of the formed liner layer, avoids the adverse effects of the over-thick liner layer on the dielectric performance of the semiconductor structure, and is beneficial to synergistically improve the structural reliability of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0038] Figure 1 A cross-sectional view of a semiconductor structure provided by an embodiment of the application;

[0039] Figure 2 A cross-sectional view of a substrate with a trench structure provided by an embodiment of the application;

[0040] Figure 3 A deposition state diagram of insulating material when the contact angle of insulating material and trench structure is different;

[0041] Figure 4 A flowchart of a preparation method for forming a liner layer provided by an embodiment of the application;

[0042] Figure 5 A flowchart of another preparation method for forming a liner layer provided by an embodiment of the application;

[0043] Figure 6 A flowchart of a deposition step and an etching step alternately with time in some embodiments of the application;

[0044] Figure 7A cross-sectional view of a trench structure with a thinned liner layer is provided for embodiments of the present application.

[0045] Figure 8 A cross-sectional view of a trench structure with an electrically insulating layer is provided for embodiments of the present application.

[0046] Figure 9 A cross-sectional view of a semiconductor structure with an electrically conductive structure is provided for embodiments of the present application.

[0047] Wherein, the reference signs are: 100 - substrate, 110 - trench structure, 111 - slot, 112 - slot bottom, 120 - electrode structure, 130 - interlayer dielectric layer, 140 - epitaxial layer, 200 - liner layer, 201 - initial liner layer, 202 - thinned liner layer, 300 - electrically conductive structure, 310 - electrically conductive isolation layer, 320 - metal filling structure, 400 - gate. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0049] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific object or a sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or server including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0050] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0051] In the manufacturing process of a semiconductor device, it is necessary to groove and fill a substrate structure in a semiconductor structure to form a semiconductor device with a target structure. However, in the surface cleaning and filling preparation steps of the trench structure on the substrate, the etching degree is difficult to control, which easily causes excessive corrosion of the sidewall of the trench structure, resulting in a large change in the shape of the trench structure, thereby adversely affecting the semiconductor structure, and even causing the failure of the finally prepared semiconductor device, reducing the preparation yield of the semiconductor device and the service life of the semiconductor device.

[0052] In a semiconductor device, accurate control of the shape of the trench structure can effectively improve the overall performance of the semiconductor device. The control of the critical dimension between the source / drain contact and the gate can effectively reduce the risk of breakdown during the operation of the semiconductor device, improve the TDDB performance of the gate oxide layer, and be beneficial to prolong the service life of the semiconductor device. The critical dimension refers to the critical spacing between the source / drain contact and the gate that stably works under normal working voltage without being easily broken down. When the spacing between the source / drain contact and the gate is less than the abutment dimension, the breakdown is more likely to occur, resulting in the TDDB failure of the gate oxide layer.

[0053] To solve the problems of the difficulty in accurately maintaining the shape of the trench structure and the TDDB failure in the middle stage of the semiconductor process, the present application provides a semiconductor structure and a preparation method thereof, such as Figure 1As shown, the semiconductor structure provided by the embodiment of the present application comprises a substrate 100 having a trench structure 110, and an electrode structure 120 below the trench structure 110; the trench structure 110 has a conductive structure 300 inside, the conductive structure 300 is in contact with the bottom wall of the trench structure 110; the sidewall of the trench structure 110 and the conductive structure 300 have a thinned liner layer 202 therebetween, the thickness of the thinned liner layer 202 gradually increases along a first direction extending from the opening 111 of the trench structure 110 to the bottom 112 of the trench structure 110; wherein the conductive structure 300 has a conductive isolation layer 310 and a metal filling structure 320, the conductive isolation layer 310 is located on the inner wall of the thinned liner layer 202 and the bottom surface of the trench structure 110, and the metal filling structure 320 is located in the inner cavity of the conductive isolation layer 310; the shape profile of the trench structure 110 of the semiconductor structure is accurate and excellent, the diameter of the inner cavity of the trench structure 110 is accurate, so that the critical dimension between the conductive structure 300 and the adjacent gate 400 is also accurately controlled, and the TDDB performance is greatly improved.

[0054] The preparation method of the semiconductor structure provided by the embodiment of the present application comprises the following steps: providing a substrate 100 having a trench structure 110; forming a liner layer 200 in the trench structure 110 by depositing an insulating material, the liner layer 200 covers the inner wall of the trench structure 110, and the thickness of the liner layer 200 gradually decreases along a first direction extending from the opening 111 of the trench structure 110 to the bottom 112 of the trench structure 110; performing surface pre-cleaning on the liner layer 200 to remove the part of the liner layer 200 located on the bottom surface of the trench structure 110, and thinning the part of the liner layer 200 located on the sidewall of the trench structure 110 to form a thinned liner layer 202; and filling a metal material in the trench structure 110 having the thinned liner layer 202 to form a conductive structure 300. In the process of forming the liner layer 200, the deposited insulating material is etched to reduce the thickness difference of the insulating material deposited on the sidewall of the trench structure 110 in the first direction, so that the liner layer 200 is resistant to etching in the subsequent surface pre-cleaning process, thereby playing a blocking role to prevent the top and middle parts of the sidewall of the trench structure 110 from being etched too much, and further maintaining the accuracy and reliability of the shape of the trench structure 110, avoiding the diffusion of the conductive structure 300 in the trench structure 110 during the filling of the metal material, and being beneficial to maintaining the spacing between the conductive structure 300 and the adjacent gate 400, i.e. being beneficial to maintaining the reliability of the source / drain contact critical dimension, improving the TDDB performance, and improving the performance and reliability of the semiconductor structure.

[0055] The following will be described in detail Figures 1-9 The preparation method of the semiconductor structure provided by the embodiment of the present application will be described in detail.

[0056] Reference will be made to Figure 2A substrate 100 having a trench structure 110 is provided; an electrode structure 120 is formed below the trench structure 110.

[0057] Among them, such as Figure 1 As shown, the substrate 100 may have multiple trench structures 110. The substrate 100 includes an insulating interlayer dielectric layer 130 (ILD) and an epitaxial layer 140 (EPI) located below the interlayer dielectric layer 130. The trench structure 110 is formed in the interlayer dielectric layer 130 and ends on the epitaxial layer 140. It is used to fill the trench structure 110 with metal material in subsequent processing steps to form a conductive structure 300, so that the conductive structure 300 can achieve interlayer interconnection with the electrode structure 120 below. At the same time, the interlayer dielectric layer 130 forms good electrical isolation, which effectively reduces the parasitic capacitance between the conductive structure 300 and the epitaxial layer 140 or the substrate 100. In some exemplary embodiments, the dielectric material of the interlayer dielectric layer 130 is silicon oxide, which has good electrical insulation and is easy to be etched to form the trench structure 110, which helps to reduce the difficulty and cost of semiconductor processing.

[0058] In some exemplary embodiments, the electrode structure 120 can be an active region, and the conductive structure 300 is located on and in contact with the active region, so that the active region can be interconnected upwards through the conductive structure 300 in multiple layers; in other exemplary embodiments, the electrode structure 120 can also be a metal material of the next layer, so that the conductive structure 300 can be interconnected downwards through the metal material of the next layer, until it is connected and conductive with the active region, thereby realizing multi-layer interconnection.

[0059] Specifically, the trench structure 110 is formed by patterning etching over a photoresist and / or hard mask formed above the interlayer dielectric layer 130. In some exemplary embodiments, the trench structure 110 is obtained by all-in-one etching (AIO), which is a process that completes the three steps of via etching, photoresist removal and trench etching in the same step, in order to reduce pattern defects generated during the formation of the trench structure 110 and greatly accelerate the processing efficiency of semiconductor structures.

[0060] Next, an insulating material is deposited within the trench structure 110 to form a pad layer 200. The pad layer 200 covers the inner wall of the trench structure 110, and along the first direction extending from the trench opening 111 to the trench bottom 112, the thickness of the pad layer 200 gradually decreases, that is, the pad layer 200 has a structure that is thicker at the top and thinner at the bottom. This makes it less likely for the top and middle parts of the pad layer 200 to be completely etched compared to the bottom during the subsequent surface pre-cleaning process. This can effectively prevent damage to the trench structure 110 during surface pre-cleaning and prevent excessive corrosion of the top sidewall of the trench structure 110 during the subsequent surface pre-cleaning process. This is beneficial to maintaining the accuracy and stability of the shape of the trench structure 110 during the semiconductor structure fabrication process.

[0061] During the formation of the liner layer 200, the deposition rate of the insulating material is affected by the transport rate of the insulating material, that is, the deposition rate of the insulating material is affected by the depth of the trench structure 110 and the angle at the corners; for example Figure 3 As shown, at the junction of the trench bottom 112 and the sidewall of the trench structure 110, the contact angle between the bottom 112 and the deposited insulating material is 90°. The surface of the substrate 100 is flat, and the contact angle between the surface of the substrate 100 and the deposited insulating material is 180°. At the trench opening 111 of the trench structure 110, the contact angle between the opening 111 and the deposited insulating material is 270°. The larger the contact angle, the larger the contact area with the insulating material, and the easier it is for the insulating material to deposit. Therefore, the deposition rate of the insulating material at the trench opening 111 is greater than that at the middle sidewall of the trench structure 110. Furthermore, the deposition rate of the insulating material on the middle sidewall of the trench structure 110 is greater than that on the bottom 112 of the trench. This results in the thickness of the deposited insulating material on the sidewall of the trench structure 110 gradually decreasing in the first direction from the opening 111 to the bottom 112, forming a hanging structure. This helps to resist the etching of the liner layer 200 during the subsequent surface pre-cleaning process, preventing the liner layer 200 from being etched through and causing the sidewall of the trench structure 110 to expand outward. This is beneficial for maintaining the accuracy of the shape of the trench structure 110 throughout the entire processing process, resulting in good reliability.

[0062] Specifically, the insulating material used in the formation of the pad layer 200 includes at least one of silicon nitride, silicon nitride, and silicon carbide. This insulating material has a lower etching rate than silicon oxide and is more resistant to etching in the subsequent surface pre-cleaning process, so as to prevent the pad layer 200 from being etched through and losing its blocking function in the subsequent surface pre-cleaning process. In some exemplary embodiments, the insulating material used to form the pad layer 200 in the trench structure 110 is silicon nitride, which is easy to obtain and has low cost.

[0063] Specifically, the deposition of the insulating material in the trench structure 110 in the process of forming the spacer layer 200 is realized by at least one of physical vapor deposition, atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), and plasma enhanced chemical vapor deposition (PECVD); in some exemplary embodiments, silicon nitride is deposited in the trench structure 110 by plasma enhanced chemical vapor deposition, the raw material of the insulating material deposited in the trench structure 110 in the process of forming the spacer layer 200 includes diiodosilane and nitrogen, and the diiodosilane reacts with the nitrogen to generate silicon nitride deposited in the trench structure 110 to form the spacer layer 200 in the process of forming the spacer layer 200; wherein the diiodosilane serves as a silicon source for chemical vapor deposition, and can generate more active silicon radicals under plasma enhancement, which is conducive to accelerating the deposition rate of silicon nitride and the processing efficiency, and the deposition temperature and deposition pressure in the process of depositing silicon nitride by diiodosilane and nitrogen are lower, so that the deposition temperature and deposition pressure in the deposition process are controllable, which is conducive to reducing the processing difficulty.

[0064] In some exemplary embodiments, the gas flow ratio of diiodosilane and nitrogen is 20 / 60-20 / 140; it can be understood that the gas flow ratio can be any point value in 20 / 60-20 / 140; for example, the gas flow ratio can be 20 / 60, 20 / 70, 20 / 80, 20 / 90, 20 / 100, 20 / 120, 20 / 140, etc.; within the gas flow ratio range, the deposition rate of silicon nitride is accurately controllable, so that silicon nitride can be stably and reliably deposited in the trench structure 110 to form the spacer layer 200, and it is also conducive to accurately controlling the shape, thickness, thickness difference in the first direction, etc. of the spacer layer 200 in the entire process of forming the spacer layer 200, and the accuracy is high.

[0065] It should be noted that, in the process of forming the spacer layer 200, the insulating material deposited in the trench structure 110 is also subjected to etching treatment to reduce the thickness difference of the insulating material deposited on the sidewall of the trench structure 110 in the first direction, so as to avoid that the thickness difference of the overhanging structure in the first direction is too large to reduce the structural stability, and to maintain the preparation yield and structural reliability of the trench structure 110, the spacer layer 200 and the entire semiconductor structure.

[0066] In the etching process, the etching rate of the insulating material is also affected by the depth of the trench structure 110 and the corner angle of the trench structure 110. The deeper the sidewall of the trench structure 110, the slower the etching rate of the insulating material on the sidewall, so that the etching rate of the insulating material in the notch 111 of the trench structure 110 is greater than that of the insulating material in the bottom 112 of the trench structure 110. After a period of etching, the thickness difference of the overhanging structure can be reduced, that is, the thickness difference between the insulating material thickness of the notch 111 of the trench structure 110 and the insulating material thickness of the bottom 112 of the trench structure 110 is reduced, so that the formed pad layer 200 can not only have good structural stability, but also effectively block the excessive etching of the sidewall of the trench structure 110 by subsequent surface pre-cleaning, greatly improving the accuracy, stability and reliability of the shape of the trench structure 110, and effectively improving the accuracy, stability and reliability of the critical dimension between the subsequently formed conductive structure 300 and the adjacent gate 400.

[0067] The etching process can be performed by dry etching or wet etching. The dry etching process can be reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method can be used, or more than one etching method can be used.

[0068] In some example embodiments, the etching gas used in the etching process of the insulating material in the process of forming the pad layer 200 is a mixed gas of CF4, CH3F and O2. The etching gas has a high etching selectivity for silicon nitride insulating material, can stably etch the silicon nitride insulating material, and can form a pad layer 200 with a preset thickness difference in the first direction, while avoiding etching damage to the interlayer dielectric layer 130 as much as possible, which is beneficial to maintaining the accuracy of the shape of the trench structure 110.

[0069] Specifically, in some example embodiments, the pad layer 200 is obtained by one deposition step and one etching step, that is, the forming of the pad layer 200 by depositing the insulating material in the trench structure 110 comprises:

[0070] depositing the insulating material in the trench structure 110 to form an initial pad layer 201;

[0071] etching the initial pad layer 201 to reduce the thickness difference of the insulating material on the sidewall of the trench structure 110 in the first direction, so that the thickness difference between the insulating material on the sidewall of the notch 111 and the insulating material on the sidewall of the bottom 112 reaches the preset thickness difference, and the pad layer 200 is obtained.

[0072] In some example embodiments, the pad layer 200 is obtained by one deposition step and one etching step, that is, the forming of the pad layer 200 by depositing the insulating material in the trench structure 110 comprises: Figure 4As shown, the initial liner layer 201 is formed by the deposition step, the top of the initial liner layer 201 forms a thicker overhanging structure, the top thickness of the initial liner layer 201 is much greater than the bottom thickness of the initial liner layer 201, that is, the thickness difference of the initial liner layer 201 in the first direction is large, forming an upper thick and lower thin shape to resist the excessive etching of the subsequent surface pre-cleaning process.

[0073] In some example embodiments, the deposition time of the initial liner layer 201 step is 3-12 minutes; in this way, a certain thickness of insulating material can be deposited on the sidewall of the trench structure 110, and the sidewall of the trench structure 110 is not easily exposed to the subsequent etching treatment and surface pre-cleaning solution, and the sidewall of the trench structure 110 is less likely to be excessively corroded, greatly improving the reliability of maintaining the shape accuracy of the trench structure 110, which is beneficial to improving the production yield and improving the TDDB performance of the semiconductor structure; it can be understood that the deposition time of the initial liner layer 201 step can be any point value in 3-12 minutes, which will not be enumerated here.

[0074] Then, as shown in Figure 4 The thickness of the initial liner layer 201 is thinned by etching treatment, and the thinning degree of the insulating material at the top of the initial liner layer 201 is greater than that of the insulating material at the bottom of the initial liner layer 201, so as to reduce the thickness difference between the insulating material on the sidewall of the notch 111 and the insulating material on the sidewall of the groove bottom 112, that is, to reduce the thickness difference between the insulating material on the sidewall of the notch 111 and the insulating material on the sidewall of the groove bottom 112, until the thickness difference reaches a preset difference, to obtain the liner layer 200, the thickness of the top of the liner layer 200 is slightly greater than the thickness of the bottom of the liner layer 200, so as to effectively prevent the trench structure 110 from expanding outwardly in the subsequent steps.

[0075] In some example embodiments, the etching time of the etching step of the initial liner layer 201 is 0.5-2 minutes; in this way, the thickness of the insulating material on the sidewall of the notch 111 can still be slightly greater than the thickness of the insulating material on the sidewall of the groove bottom 112, and the thickness difference between the thickness of the liner layer 200 at the notch 111 and the thickness of the liner layer 200 at the groove bottom 112 can also reach the preset thickness difference, which accurately and effectively protects the sidewall of the trench structure 110 and avoids the expansion of the sidewall of the trench structure 110 due to the corrosion of the trench structure 110 in the subsequent surface pre-cleaning process.

[0076] Specifically, in some example embodiments, the forming of the liner layer 200 by depositing the insulating material in the trench structure 110 comprises:

[0077] depositing the insulating material in the trench structure 110 to form an initial liner layer 201;

[0078] The initial liner layer 201 is etched to reduce the thickness difference of the insulating material on the sidewall of the trench structure 110 along the first direction;

[0079] Repeat the above deposition and etching steps until the thickness difference between the insulating material on the sidewall of the groove 111 and the insulating material on the sidewall of the groove bottom 112 reaches the preset thickness difference, and obtain the padding layer 200.

[0080] Taking a single deposition step and a single etching step as one operation cycle, the explanation will focus on the first and second operation cycles as examples. Figure 5 As shown, the initial deposition step forms an initial liner layer 201. Then, the thickness difference of the insulating material on the sidewall of the trench structure 110 is reduced through the initial etching step. At this time, the thickness difference has not yet reached the preset thickness difference. Based on the insulating material deposited on the sidewall of the trench, a second round of operation is performed, namely, the next deposition step and etching step. In the second deposition step, the insulating material on the sidewall of the trench opening 111 is further thickened, and the thickness difference of the insulating material on the sidewall of the trench structure 110 is further increased compared with the insulating material deposited in the first deposition step. Then, the thickness difference is reduced through the second etching step. However, the thickness of the insulating material formed after the second round of operation is increased compared with the thickness of the insulating material formed after the first round of operation, and the thickness difference of the insulating material formed after the second round of operation in the first direction is also increased compared with the thickness difference formed after the first round of operation. Thus, the thickness and thickness difference of the insulating material are accumulated through multiple deposition and etching steps to obtain a liner layer 200 with a specific thickness and a preset thickness difference. The alternation of deposition and etching steps makes the deposition shape of the insulating material flexible and precise during the preparation process, and the liner layer 200 has high forming accuracy.

[0081] Specifically, such as Figure 6 As shown, in some exemplary embodiments, during the formation of the pad layer 200, the deposition step and the etching step are performed alternately. The deposition time of a single deposition step is 15s to 20s, and the etching time of a single etching step is 3s to 5s. Within this time range, the thickness difference of the insulating material formed on the sidewall of the trench structure 110 after a single deposition step and a single etching step is small, which can form an insulating material structure in which the thickness of the insulating material at the trench opening 111 is slightly greater than the thickness of the insulating material at the trench bottom 112. After repeatedly performing the above deposition and etching steps, the deposition time and etching time gradually accumulate, realizing the gradual accumulation of insulating material until a pad layer 200 with a preset thickness difference is formed. The pad layer 200 has a certain thickness and can withstand etching damage during the subsequent surface pre-cleaning process, avoiding the pad layer 200 being etched through and damaging the trench structure 110.

[0082] Specifically, the number of deposition steps and etching steps performed in forming the liner layer 200 is 10-20, respectively; it can be understood that the number of deposition steps and etching steps performed in forming the liner layer 200 can be any integer value in 10-20, which is not enumerated here; in this way, a liner layer 200 with sufficient thickness can be formed on the sidewall of the trench structure 110 to protect the sidewall of the trench structure 110 from expanding in the subsequent processing process, and at the same time, the change to the final structure of the prepared semiconductor structure is minimized to avoid adversely affecting the performance of the semiconductor structure; in some exemplary embodiments, the number of deposition steps and etching steps performed in forming the liner layer 200 is 15-20, respectively.

[0083] Specifically, in the process of forming the liner layer 200 in the trench structure 110, the ratio between the deposition rate of the insulating material and the etching rate of the insulating material is 1.8:1-2.5:1; it can be understood that the ratio can be any point value in 1.8:1-2.5:1 to stably form the liner layer 200 with a preset thickness difference in the trench structure 110, with good accuracy and high reliability; for example, in an exemplary embodiment, the ratio between the deposition rate and the etching rate of the insulating material is 2:1.

[0084] Specifically, in the process of forming the liner layer 200 in the trench structure 110, the deposition rate and etching rate of the insulating material are related to the depth of the trench structure 110, respectively, wherein the deeper the sidewall in the trench structure 110, the slower the deposition rate of the insulating material, and the slower the etching rate of the insulating material being etched; in some exemplary embodiments, in the process of forming the liner layer 200 in the trench structure 110, the ratio between the deposition rate of the insulating material and the depth of the trench structure 110 is 0.10-0.04 min -1 so that the insulating material forms a shape of thick at the top and thin at the bottom in the trench structure 110, and at the same time, the ratio between the etching rate of the insulating material and the depth of the trench structure 110 is 0.06-0.01 min -1 so that the insulating material is more easily etched at the notch 111, and the thickness difference between the thickness of the insulating material at the notch 111 and the thickness of the insulating material at the bottom 112 is gradually and accurately controlled by the deposition step, so that the thickness of the insulating material at the notch 111 is always maintained in a shape slightly larger than the thickness of the insulating material at the bottom 112, which is beneficial to improve the structural accuracy of the formed liner layer 200 and ensure the reliability of the liner layer 200 in protecting the sidewall of the trench structure 110 in the subsequent steps.

[0085] Specifically, the deposition temperature used in the process of forming the liner layer 200 in the trench structure 110 is 300-400°C; it can be understood that the deposition temperature can be any point value in 300-400°C; for example, the deposition temperature can be 300°C, 330°C, 350°C, 360°C, 380°C, 400°C, etc.; in this way, the insulating material can be stably deposited in the trench structure 110, the deposition reliability is good, and it is also beneficial to improve the performance of the liner layer 200, reduce the internal stress of the formed liner layer 200, and improve the structure density, thereby improving the etching resistance of the liner layer 200, so that the liner layer 200 can effectively protect the trench structure 110 and avoid diffusion of the trench structure 110 in the subsequent processing process. In addition, at this deposition temperature, it is also beneficial to improve the insulation performance of the liner layer 200, reduce charge traps, improve the breakdown resistance, improve the TDDB performance of the semiconductor structure in the middle process, and greatly improve the electrical performance of the finally formed semiconductor structure.

[0086] Specifically, the radio frequency power used in the process of forming the liner layer 200 in the trench structure 110 is 200-400W; it can be understood that the radio frequency power can be any point value in 200-400W, which will not be enumerated here; at this radio frequency power, the reaction gas can be fully ionized to provide the required ions, neutral atomic groups and plasma for the deposition of the insulating material, so as to promote the deposition of the insulating material and improve the reliability of the deposition of the insulating material. At the same time, it can improve the uniformity and density of the internal structure of the liner layer 200, reduce the occurrence of holes in the liner layer 200, and also enhance the corrosion resistance of the liner layer 200.

[0087] Specifically, the deposition pressure used in the process of forming the liner layer 200 in the trench structure 110 is 60-80Pa; it can be understood that the deposition pressure can be any point value in 60-80Pa, which will not be enumerated here; in this way, the deposition rate of the insulating material can be effectively adjusted, and the uniformity of the internal structure of the formed liner layer 200 can be improved.

[0088] Specifically, the deposition rate used in the process of forming the liner layer 200 in the trench structure 110 is 10-20nm / min; it can be understood that the deposition rate can be any point value in 10-20nm / min; for example, the deposition rate can be 10nm / min, 12nm / min, 15nm / min, 18nm / min, 20nm / min, etc.; in this way, on the one hand, the processing efficiency is improved, and on the other hand, the shape of the liner layer 200 is facilitated to be controlled, and the structure density, insulation and etching resistance of the liner layer 200 are improved.

[0089] In addition, in the multiple deposition steps for forming the liner layer 200, the specific setting values of each deposition step (or etching step) can be the same parameter values, including temperature, pressure, gas flow ratio, and time length, and other parameter values affecting the deposition or etching effect, so that the preparation process is accurate and orderly, and the shape of the formed liner layer 200 is within the expected shape range; the specific setting values of each deposition step in the multiple deposition steps (or each etching step in the multiple etching steps) can also be selected as different parameter values, so as to flexibly control the thickness of the insulating material on the sidewall of the trench structure 110, form the liner layer 200 with a preset thickness difference, and have good preparation flexibility and fault tolerance. It can also be flexibly applied to the preparation process of various semiconductor structures, meet the preparation requirements of various semiconductor structures, and have good applicability.

[0090] By effectively controlling the deposition temperature, deposition pressure, radio frequency power, deposition rate, deposition time length, etching rate, and etching time length and other parameters in the process of forming the liner layer 200, the deposition process and etching process of the insulating material are cooperatively controlled to form the liner layer 200 with a certain shape and a preset thickness difference. This greatly improves the forming accuracy of the liner layer 200, is beneficial to improving the reliability of the trench structure 110 with the liner layer 200 in maintaining its structure shape unchanged in the subsequent processing process, and is further beneficial to improving the preparation yield and semiconductor structure performance.

[0091] Specifically, in some exemplary embodiments, the preset thickness difference is 1 nm to 2 nm. It can be understood that the preset thickness difference can be any point value in 1 nm to 2 nm. For example, the preset thickness difference can be 1 nm, 1.2 nm, 1.3 nm, 1.5 nm, 1.7 nm, 1.8 nm, 2.0 nm, etc. In this way, more residues can be left on the top and middle parts of the thinned liner layer 202 after surface pre-cleaning, avoiding the complete etching penetration. The shape of the trench structure 110 after surface pre-cleaning is accurate, the cross-section is excellent, the spacing between the gate 400 is large enough, and the TDDB performance in the middle stage of the semiconductor process is greatly improved.

[0092] In some exemplary embodiments, in the process of forming the liner layer 200, the thickness difference of the insulating material on the sidewall of the trench structure 110 from the slot opening 111 to the slot bottom 112 increases by 0.06 nm to 0.4 nm after each deposition step and each etching step. Through the accumulation of multiple deposition steps and multiple etching steps, a liner layer 200 with a preset thickness difference of 1 nm to 2 nm can be finally formed.

[0093] Specifically, the thickness of the pad layer 200 on the sidewall of the trench structure 110 is 6-9 nm, and the preset thickness difference is always kept in the range of 1-2 nm. Understandably, the thickness can be any value in the range of 6-9 nm, which will not be enumerated here. In this way, the sidewall of the trench structure 110 can be effectively protected, and the trench structure 110 will not be damaged due to the pad layer 200 being etched through in the subsequent surface pre-cleaning process. After the subsequent processing process, the trench structure 110 can still maintain accurate boundaries and excellent profiles, so that the TDDB performance in the middle stage of the semiconductor process is greatly improved. In some preferred embodiments, the thickness of the pad layer 200 on the sidewall of the trench structure 110 is 7-8 nm.

[0094] Next, referring to Figure 7 The pad layer 200 is subjected to surface pre-cleaning to remove the part of the pad layer 200 on the bottom surface of the trench structure 110 and thin the part of the pad layer 200 on the sidewall of the trench structure 110, forming a thinned pad layer 202. During the surface pre-cleaning process, the loss rate of the pad layer 200 is also related to the depth of the trench structure 110, so that the loss amount of the top of the pad layer 200 etched is greater than the loss amount of the bottom of the pad layer 200 etched, but the insulating material will not be completely lost. Finally, the thickness of the thinned pad layer 202 gradually increases in the first direction, forming an upper-thin lower-thick shape, which can still play a certain protective role in the profile of the sidewall of the trench structure 110. The pad layer 200 and the thinned pad layer 202 are insulating, which can maintain the accuracy of the shape of the trench structure 110, and further increase the critical dimension between the subsequently formed conductive structure 300 and the adjacent gate 400, further improve the TDDB performance, and prolong the service life of the semiconductor structure.

[0095] The surface pre-cleaning can adopt the same etching process as the etching process adopted in the process of forming the pad layer 200, or can adopt a plasma surface treatment process. On the one hand, it can thin the thickness of the pad layer 200 on the sidewall of the trench structure 110 and remove the insulating material in the pad layer 200 on the bottom surface of the trench structure 110 to expose the bottom surface of the trench structure 110, so that the subsequently filled metal material can form a conductive structure 300 that can contact and conduct with the electrode structure 120 below the bottom surface of the trench structure 110, facilitating current flow. On the other hand, the insulating material in the pad layer 200 can also be physically and chemically modified to improve the surface adhesion of the formed thinned pad layer 202, facilitate the subsequent filling of metal material, and improve the stability and reliability of the formed conductive structure 300.

[0096] Specifically, the width difference between the top inner diameter and the bottom inner diameter of the inner cavity of the trench structure 110 with the thinned liner layer 202 is 2-4 nm; it can be understood that the width difference can be any point value in 2-4 nm; for example, the width difference can be 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, etc.; in this way, the change of the profile of the trench structure 110 is small, which greatly maintains the accuracy of the profile of the trench structure 110, avoids the expansion of the trench structure 110, greatly improves the critical dimension between the conductive structure 300 subsequently formed in the trench structure 110 and the adjacent gate 400, improves the TDDB performance in the middle stage of the semiconductor process, and is beneficial to improve the final preparation yield and performance reliability of the semiconductor structure.

[0097] Finally, referring to Figure 8 and Figure 9 The trench structure 110 with the thinned liner layer 202 is filled with a metal material to form a conductive structure 300, which is connected to the electrode structure 120 below the trench structure 110 through the exposed bottom surface in the trench structure 110; wherein the metal material for forming the conductive structure 300 can include one or more of aluminum metal, copper metal, silver metal, tungsten metal, and cobalt metal to form a metal contact (source / drain contact) in the trench structure 110 of the substrate 100 to transmit current or signals.

[0098] Specifically, in some exemplary embodiments, the trench structure 110 with the thinned liner layer 202 is filled with a metal material to form a conductive structure 300, which includes:

[0099] forming a conductive isolation layer 310 in the trench structure 110 with the thinned liner layer 202;

[0100] filling the trench structure 110 with the conductive isolation layer 310 with a metal material to form a metal filling structure 320 to obtain the conductive structure 300.

[0101] wherein, as shown in Figure 8 The conductive isolation layer 310 is deposited on the inner wall of the thinned liner layer 202 and the bottom surface of the trench structure 110, as shown in Figure 9As shown, the metal filling structure 320 is deposited in the cavity of the trench structure 110 with the conductive isolation layer 310 and the thinned liner layer 202, which can further protect the sidewall of the trench structure 110 and reduce the damage to the sidewall of the trench structure 110 in the subsequent filling process of the metal material, so that the shortest distance between the edge of the conductive structure 300 and the adjacent gate 400 is greater than or equal to the critical dimension, which can effectively improve the TDDB performance in the middle process of the semiconductor and prolong the service life of the semiconductor structure in the working state. Meanwhile, the bottom surface of the trench structure 110 is exposed, and the metal material of the conductive isolation layer 310 and the non-metal material of the interlayer dielectric layer 130 or the epitaxial layer 140 exposed at the bottom surface of the trench structure 110 can form a semiconductor material, thereby reducing the contact resistance between the conductive structure 300 and the electrode structure 120. In some exemplary embodiments, the material of the conductive isolation layer 310 includes at least one of Ti and TIN, which can form a semiconductor amorphous silicide with the silicon oxide material, greatly reducing the contact resistance and improving the contact performance.

[0102] The embodiment of the present application further provides a semiconductor device, which comprises any one of the semiconductor structures provided by the embodiment of the present application.

[0103] The embodiment of the present application further provides an electronic device, which comprises any one of the semiconductor devices provided by the embodiment of the present application. The electronic device can be any electronic product or equipment such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, etc. The electronic device can also be an intermediate product with the semiconductor device, for example, a mainboard of an equipment with the semiconductor device. The electronic device adopts the semiconductor device, and accordingly the working performance of the electronic device is improved.

[0104] Although the present application is disclosed as above, the present application is not limited to this. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The application relates to a preparation method of a substrate with a trench structure. The application provides a substrate with a trench structure; An electrode structure is formed under the trench structure; An insulating material is deposited in the trench structure to form a liner layer, the liner layer covers the inner wall of the trench structure, and the thickness of the liner layer gradually decreases along a first direction from the trench mouth to the trench bottom; during the formation of the liner layer, etching treatment is performed on the insulating material deposited in the trench structure to reduce the thickness difference of the insulating material deposited on the side wall of the trench structure in the first direction; Surface pre-cleaning is performed on the liner layer to remove the part of the liner layer on the bottom surface of the trench structure and thin the part of the liner layer on the side wall of the trench structure, thereby forming a thinned liner layer; The thickness of the thinned liner layer gradually increases along the first direction; Metal material is filled in the trench structure with the thinned liner layer to form a conductive structure.

2. The production method according to claim 1, characterized by, The method comprises the following steps: The insulating material is deposited in the trench structure to form an initial liner layer; Etching is performed on the initial liner layer to reduce the thickness difference of the insulating material on the side wall of the trench structure in the first direction, and the thickness difference between the insulating material on the side wall of the trench mouth and the insulating material on the side wall of the trench bottom reaches a preset thickness difference, thereby obtaining the liner layer.

3. The method of claim 1, wherein, The method comprises the following steps: The insulating material is deposited in the trench structure to form an initial liner layer; Etching is performed on the initial liner layer to reduce the thickness difference of the insulating material on the side wall of the trench structure in the first direction; The deposition step and the etching step are repeatedly performed until the thickness difference between the insulating material on the side wall of the trench mouth and the insulating material on the side wall of the trench bottom reaches a preset thickness difference, thereby obtaining the liner layer.

4. The production method according to claim 3, characterized by, The number of times of the deposition step and the etching step performed in the formation of the liner layer is 10-20.

5. The preparation method according to claim 3, characterized in that, During the formation of the liner layer, the deposition time of a single deposition step is 15-20s, and the etching time of a single etching step is 3-5s.

6. The method of any one of claims 2-5, wherein, The preset thickness difference is 1-2nm.

7. The method of any one of claims 1-5, wherein, The insulating material comprises at least one of silicon nitride, silicon nitride and silicon carbide.

8. The method of any one of claims 1-5, wherein, During the formation of the liner layer in the trench structure, the ratio between the deposition rate of the insulating material and the etching rate of the insulating material is 1.8:1-2.5:

1.

9. The method of any one of claims 1-5, wherein, In the process of forming the liner layer in the trench structure, the ratio between the deposition rate of the insulating material and the depth of the trench structure is 0.10-0.04 min -1 , and the ratio between the etching rate of the insulating material and the depth of the trench structure is 0.06-0.01 min -1 .

10. The method of any one of claims 1-5, wherein, The preparation method satisfies at least one of the following characteristics: The deposition temperature adopted during the formation of the liner layer in the trench structure is 300-400 DEG C; The radio frequency power adopted during the formation of the liner layer in the trench structure is 200-400W; The deposition pressure adopted during the formation of the liner layer in the trench structure is 60-80Pa; The deposition rate adopted during the formation of the liner layer in the trench structure is 10-20nm / min.

11. The method of any one of claims 1-5, wherein, The thickness of the liner layer on the side wall of the trench structure is 6-9nm.

12. The method of any one of claims 1-5, wherein, The width difference between the top inner diameter and the bottom inner diameter of the inner cavity of the trench structure with the thinned liner layer is 2-4 nm.

13. The method of any one of claims 1-5, wherein, The filling of the metal material in the trench structure with the thinned liner layer to form the conductive structure comprises: forming a conductive isolation layer in the trench structure with the thinned liner layer; filling a metal material in the trench structure with the conductive isolation layer to form a metal filling structure, thereby obtaining the conductive structure.

14. A semiconductor structure, characterized by The semiconductor structure is prepared based on the preparation method of any one of claims 1-13, and comprises a substrate with a trench structure, and an electrode structure below the trench structure; The trench structure has a conductive structure therein, and the conductive structure is in contact with the bottom wall of the trench structure; The trench structure has a thinned liner layer between the sidewall of the trench structure and the conductive structure, and the thickness of the thinned liner layer gradually increases along a first direction extending from the trench opening to the trench bottom.

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