Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, and forming an interlayer dielectric layer on the substrate; forming a hard mask layer on the interlayer dielectric layer, wherein the etching selection ratio of the interlayer dielectric layer to the hard mask layer is greater than 9: 1; forming a patterned photoresist layer on the hard mask layer; etching the hard mask layer by taking the patterned photoresist layer as a mask so as to form a patterned hard mask layer which exposes part of the surface of the interlayer dielectric layer; etching the interlayer dielectric layer by taking the patterned hard mask layer as a mask so as to form a contact hole penetrating through the interlayer dielectric layer; and etching the substrate at the bottom of the contact hole to enable the contact hole to extend into the substrate. According to the technical scheme, the width of the contact hole can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and particularly to a semiconductor device and a manufacturing method thereof. Background Art

[0002] As the distance (pitch) between the centers of adjacent cells of a shield gate trench (SGT) device becomes smaller and smaller, the required contact hole width (CT CD) is also getting smaller. However, the current process cannot meet the requirement of a very small contact hole width.

[0003] Therefore, how to reduce the contact hole width is an urgent problem to be solved. Summary of the Invention

[0004] An object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which can reduce the contact hole width.

[0005] To achieve the above object, the present invention provides a manufacturing method of a semiconductor device, including:

[0006] Providing a substrate, on which an interlayer dielectric layer is formed;

[0007] Forming a hard mask layer on the interlayer dielectric layer, and the etching selectivity ratio between the interlayer dielectric layer and the hard mask layer is greater than 9:1;

[0008] Forming a patterned photoresist layer on the hard mask layer;

[0009] Etching the hard mask layer using the patterned photoresist layer as a mask to form a patterned hard mask layer exposing a partial surface of the interlayer dielectric layer;

[0010] Etching the interlayer dielectric layer using the patterned hard mask layer as a mask to form a contact hole penetrating through the interlayer dielectric layer;

[0011] Etching the substrate at the bottom of the contact hole to extend the contact hole into the substrate.

[0012] Optionally, during the process of etching the hard mask layer using the patterned photoresist layer as a mask, at least a partial thickness of the patterned photoresist layer is etched and removed.

[0013] Optionally, during the process of etching the interlayer dielectric layer using the patterned hard mask layer as a mask, the remaining thickness of the patterned photoresist layer and a partial thickness of the patterned hard mask layer are etched and removed.

[0014] Optionally, before etching the substrate at the bottom of the contact hole, the manufacturing method of the semiconductor device further includes:

[0015] Remove the patterned hard mask layer with the remaining thickness.

[0016] Optionally, the material of the hard mask layer is carbon.

[0017] Optionally, the material of the interlayer dielectric layer is at least one of silicon oxide, silicon oxynitride, borophosphosilicate glass, and phosphosilicate glass.

[0018] Optionally, the thickness of the patterned photoresist layer is 2000 Å to 2500 Å.

[0019] Optionally, the thickness of the hard mask layer is 1000 Å to 1500 Å.

[0020] Optionally, the width of the portion of the contact hole located in the substrate is less than or equal to 0.11 micrometers.

[0021] The present invention also provides a semiconductor device manufactured by using the manufacturing method of the semiconductor device.

[0022] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0023] 1. In the manufacturing method of the semiconductor device of the present invention, since it includes: providing a substrate on which an interlayer dielectric layer is formed; forming a hard mask layer on the interlayer dielectric layer, the etching selectivity between the interlayer dielectric layer and the hard mask layer is greater than 9:1; forming a patterned photoresist layer on the hard mask layer; etching the hard mask layer with the patterned photoresist layer as a mask to form a patterned hard mask layer exposing a partial surface of the interlayer dielectric layer; etching the interlayer dielectric layer with the patterned hard mask layer as a mask to form a contact hole penetrating the interlayer dielectric layer; etching the substrate at the bottom of the contact hole so that the contact hole extends into the substrate. As a result, the width of the contact hole can be reduced.

[0024] 2. In the semiconductor device of the present invention, since the semiconductor device is manufactured by using the manufacturing method of the semiconductor device, the width of the contact hole can be reduced. Description of the Drawings

[0025] Figure 1 is a flowchart of a manufacturing method of a semiconductor device according to an embodiment of the present invention;

[0026] Figures 2a to 2g is Figure 1 a schematic diagram of a device in the manufacturing method of the semiconductor device shown.

[0027] Among them, the attached Figures 1 to 2g reference numerals are described as follows:

[0028] 10 - Substrate; 11 - Interlayer dielectric layer; 12 - Patterned hard mask layer; 121 - Hard mask layer; 122 - Second opening; 13 - Patterned photoresist layer; 131 - First opening; 14 - Contact hole. Detailed implementation manners

[0029] To make the objectives, advantages and features of the present invention clearer, the following provides a further detailed description of the semiconductor device and its manufacturing method proposed by the present invention. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the objectives of the embodiments of the present invention.

[0030] An embodiment of the present invention provides a manufacturing method of a semiconductor device. Referring to Figure 1 , from Figure 1 , it can be seen that the manufacturing method of the semiconductor device includes:

[0031] Step S1: Provide a substrate, and an interlayer dielectric layer is formed on the substrate;

[0032] Step S2: Form a hard mask layer on the interlayer dielectric layer, and the etching selectivity between the interlayer dielectric layer and the hard mask layer is greater than 9:1;

[0033] Step S3: Form a patterned photoresist layer on the hard mask layer;

[0034] Step S4: Etch the hard mask layer using the patterned photoresist layer as a mask to form a patterned hard mask layer that exposes a part of the surface of the interlayer dielectric layer;

[0035] Step S5: Etch the interlayer dielectric layer using the patterned hard mask layer as a mask to form a contact hole that penetrates the interlayer dielectric layer;

[0036] Step S6: Etch the substrate at the bottom of the contact hole so that the contact hole extends into the substrate.

[0037] Next, referring to Figures 2a to 2g , a detailed description of the manufacturing method of the semiconductor device provided in this embodiment is given. Figures 2a to 2g It is also a longitudinal cross-sectional schematic diagram of the semiconductor device.

[0038] According to step S1, referring to Figure 2a , provide a substrate 10, and an interlayer dielectric layer 11 is formed on the substrate 10.

[0039] The substrate 10 may be a single-layer structure or may include a multi-layer structure composed of the same or different materials. The material of the substrate 10 may be at least one of semiconductor materials such as Si, SiGe, SiGeC, SiC, GaAs, InAs, and InP, and the present application does not limit this.

[0040] The interlayer dielectric layer 11 may be formed on the substrate 10 by a deposition process.

[0041] The material of the interlayer dielectric layer 11 is at least one of insulating materials such as silicon oxide, silicon oxynitride, borophosphosilicate glass, and phosphosilicate glass.

[0042] The interlayer dielectric layer 11 may be a single-layer structure, or the interlayer dielectric layer 11 may be a stacked structure of at least two layers of the same or different materials.

[0043] In one embodiment, the thickness of the interlayer dielectric layer 11 is 7000 angstroms to 9000 angstroms.

[0044] According to step S2, refer to Figure 2b , a hard mask layer 121 is formed on the interlayer dielectric layer 11, and the etching selectivity between the interlayer dielectric layer 11 and the hard mask layer 121 is greater than 9:1.

[0045] Preferably, the material of the hard mask layer 121 is carbon, that is, the hard mask layer 121 is a carbon film.

[0046] In one embodiment, the thickness of the hard mask layer 121 is 1000 angstroms to 1500 angstroms.

[0047] The hard mask layer 121 may be formed on the interlayer dielectric layer 11 by a deposition process.

[0048] According to step S3, refer to Figure 2c , a patterned photoresist layer 13 is formed on the hard mask layer 121.

[0049] Among them, a photoresist layer may be first formed on the hard mask layer 121, and then, an exposure and development process is performed so that the photoresist layer is formed into a patterned photoresist layer 13, and the patterned photoresist layer 13 has a first opening 131 exposing a partial surface of the hard mask layer 121.

[0050] In one embodiment, the thickness of the patterned photoresist layer 13 is 2000 angstroms to 2500 angstroms.

[0051] According to step S4, refer to Figure 2d, using the patterned photoresist layer 13 as a mask to etch the hard mask layer 121 to form a patterned hard mask layer 12 that exposes a partial surface of the interlayer dielectric layer 11.

[0052] The patterned hard mask layer 12 has a second opening 122 that exposes a partial surface of the interlayer dielectric layer 11. The second opening 122 communicates with the first opening 131, and the second opening 122 is located at the bottom of the first opening 131.

[0053] During the process of etching the hard mask layer 121 using the patterned photoresist layer 13 as a mask to form the patterned hard mask layer 12, at least a partial thickness of the patterned photoresist layer 13 is etched away. That is, during the process of etching the hard mask layer 121 exposed by the first opening 131 using a dry etching process, the patterned photoresist layer 13 around the first opening 131 is also etched, resulting in a reduction in the thickness of the patterned photoresist layer 13.

[0054] When the hard mask layer 121 exposed by the first opening 131 is etched through, that is, after the second opening 122 is formed, the patterned photoresist layer 13 can be etched away only partially or the entire patterned photoresist layer 13 can be etched away.

[0055] According to step S5, refer to Figure 2e , using the patterned hard mask layer 12 as a mask to etch the interlayer dielectric layer 11 to form a contact hole 14 that penetrates the interlayer dielectric layer 11.

[0056] When forming the patterned hard mask layer 12, if a partial thickness of the patterned photoresist layer 13 remains, then during the process of etching the interlayer dielectric layer 11 using the patterned hard mask layer 12 as a mask to form the contact hole 14, the remaining thickness of the patterned photoresist layer 13 and a partial thickness of the patterned hard mask layer 12 are etched away. That is, during the process of etching the interlayer dielectric layer 11 exposed by the second opening 122 using a dry etching process, the patterned photoresist layer 13 around the first opening 131 and the patterned hard mask layer 12 around the second opening 122 are also etched, resulting in the complete removal of the patterned photoresist layer 13 and a reduction in the thickness of the patterned hard mask layer 12.

[0057] When forming the patterned hard mask layer 12, if the patterned photoresist layer 13 is also completely removed, during the process of etching the interlayer dielectric layer 11 using the patterned hard mask layer 12 as a mask to form the contact hole 14, a part of the thickness of the patterned hard mask layer 12 is etched away. That is, during the process of etching the interlayer dielectric layer 11 exposed by the second opening 122 using a dry etching process, the patterned hard mask layer 12 around the second opening 122 is also etched, resulting in a reduction in the thickness of the patterned hard mask layer 12.

[0058] Refer to Figure 2f , after forming the contact hole 14 that penetrates the interlayer dielectric layer 11 and before etching the substrate 10 at the bottom of the contact hole 14 subsequently, the manufacturing method of the semiconductor device further includes: removing the remaining thickness of the patterned hard mask layer 12 to avoid the patterned hard mask layer 12 being etched during the subsequent process of etching the substrate 10 at the bottom of the contact hole 14, thereby avoiding by-products generated from etching the patterned hard mask layer 12 from contaminating the substrate 10.

[0059] In one embodiment, step S4 and step S5 can be completed in the same chamber using the same or different etching gases.

[0060] According to step S6, refer to Figure 2g , etch the substrate 10 at the bottom of the contact hole 14 so that the contact hole 14 extends into the substrate 10.

[0061] Among them, a dry etching process can be used to etch the substrate 10 at the bottom of the contact hole 14. At this time, the interlayer dielectric layer 11 serves as a mask for etching the substrate 10.

[0062] In one embodiment, the longitudinal cross-sectional shape of the contact hole 14 is an inverted trapezoid.

[0063] The manufacturing method of the semiconductor device further includes: filling a metal material into the contact hole 14 to form a contact plug.

[0064] The manufacturing method of the semiconductor device can be used for fabricating semiconductor devices such as shield gate trench (SGT) devices that require the contact plug to extend into the substrate 10.

[0065] In the existing process, a patterned photoresist layer is directly used as a mask to etch the interlayer dielectric layer. However, during the process of etching the interlayer dielectric layer, the patterned photoresist layer will also be etched and consumed, and the etching selectivity between the interlayer dielectric layer and the patterned photoresist layer is very small (for example, 2:1). And the thickness of the interlayer dielectric layer has requirements (that is, it needs to be thick enough), which makes the patterned photoresist layer also need to be thick enough. Otherwise, if the thickness of the patterned photoresist layer is too thin, it will cause the interlayer dielectric layer not to be etched through while the patterned photoresist layer has been etched and consumed, that is, the thickness of the patterned photoresist layer is not enough to act as a shield for etching the interlayer dielectric layer. However, if the patterned photoresist layer is too thick, it will cause that when exposing and developing the photoresist layer to form a patterned photoresist layer, the exposed positions of the photoresist layer cannot be fully exposed and the width of the exposed positions cannot be made small. As a result, the width of the contact holes formed in the interlayer dielectric layer after etching the interlayer dielectric layer using the patterned photoresist layer as a mask cannot be made small, and the width of the part of the contact holes formed by subsequent etching of the substrate within the substrate cannot be made small either. For example, the minimum width of the part of the contact holes made by the existing process within the substrate can only reach 0.16 microns.

[0066] In the present invention, by forming the hard mask layer 121 between the patterned photoresist layer 13 and the interlayer dielectric layer 11, and first etching the hard mask layer 121 using the patterned photoresist layer 13 as a mask to form a patterned hard mask layer 12 exposing a part of the surface of the interlayer dielectric layer 11, and then etching the interlayer dielectric layer 11 using the patterned hard mask layer 12 as a mask to form contact holes 14 penetrating the interlayer dielectric layer 11, and the etching selectivity between the interlayer dielectric layer 11 and the hard mask layer 121 is greater than 9:1, and the etching selectivity between the interlayer dielectric layer 11 and the hard mask layer 121 is much greater than the etching selectivity between the interlayer dielectric layer 11 and the patterned photoresist layer 13. So that when the thickness of the interlayer dielectric layer 11 remains unchanged (that is, the thickness of the interlayer dielectric layer 11 is thick enough), when etching through the interlayer dielectric layer 11, the patterned hard mask layer 12 is not completely etched and consumed, and the patterned hard mask layer 12 can still retain a part of its thickness, that is, the thickness of the patterned hard mask layer 12 (that is, the thickness of the hard mask layer 121) is enough to act as a shield for etching the interlayer dielectric layer 11, and at the same time, the thickness of the patterned hard mask layer 12 (that is, the thickness of the hard mask layer 121) can be made thinner.

[0067] Moreover, since the patterned photoresist layer 13 is also etched and consumed by at least a part of its thickness during the process of etching the hard mask layer 121 using the patterned photoresist layer 13 as a mask to form the patterned hard mask layer 12, when the thickness of the patterned hard mask layer 12 (i.e., the thickness of the hard mask layer 121) is made thinner, the thickness of the patterned photoresist layer 13 can be made thinner, that is, the thickness of the photoresist layer for exposure and development can be made thinner. Furthermore, the width of the first opening 131 in the patterned photoresist layer 13 formed after exposing and developing the photoresist layer can be made smaller, the width of the second opening 122 in the patterned hard mask layer 12 can be made smaller, so that the widths of the contact hole 14 in the interlayer dielectric layer 11 and the inner part of the substrate 10 can both be made smaller to meet the requirements of small pitch (i.e., the distance between the centers of adjacent units of the device) devices.

[0068] In one embodiment, the width of the part of the contact hole 14 located in the substrate 10 may be less than or equal to 0.11 micrometers.

[0069] In summary, the present invention provides a method for manufacturing a semiconductor device, including: providing a substrate with an interlayer dielectric layer formed thereon; forming a hard mask layer on the interlayer dielectric layer, where the etching selectivity between the interlayer dielectric layer and the hard mask layer is greater than 9:1; forming a patterned photoresist layer on the hard mask layer; etching the hard mask layer using the patterned photoresist layer as a mask to form a patterned hard mask layer exposing a part of the surface of the interlayer dielectric layer; etching the interlayer dielectric layer using the patterned hard mask layer as a mask to form a contact hole penetrating the interlayer dielectric layer; etching the substrate at the bottom of the contact hole so that the contact hole extends into the substrate. The method for manufacturing a semiconductor device provided by the present invention can reduce the width of the contact hole.

[0070] An embodiment of the present invention provides a semiconductor device manufactured using the method for manufacturing a semiconductor device described above.

[0071] The method for manufacturing the semiconductor device described above is as described above and will not be elaborated here.

[0072] Since the semiconductor device is manufactured using the method for manufacturing a semiconductor device described above, the width of the contact hole can be reduced.

[0073] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the protection scope of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, on which an interlayer dielectric layer is formed; forming a hard mask layer on the interlayer dielectric layer, wherein an etching selectivity ratio between the interlayer dielectric layer and the hard mask layer is greater than 9:1; forming a patterned photoresist layer on the hard mask layer; Etching the hard mask layer using the patterned photoresist layer as a mask to form a patterned hard mask layer exposing a portion of the surface of the interlayer dielectric layer; Etching the interlayer dielectric layer using the patterned hard mask layer as a mask to form a contact hole penetrating the interlayer dielectric layer; The substrate at the bottom of the contact hole is etched so that the contact hole extends into the substrate.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: In the process of etching the hard mask layer using the patterned photoresist layer as a mask, at least a portion of the thickness of the patterned photoresist layer is etched away.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: In the process of etching the interlayer dielectric layer using the patterned hard mask layer as a mask, the remaining thickness of the patterned photoresist layer and a portion of the thickness of the patterned hard mask layer are removed by etching.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: Before etching the substrate at the bottom of the contact hole, the method for manufacturing the semiconductor device further includes: The remaining thickness of the patterned hard mask layer is removed.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the hard mask layer is carbon.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the interlayer dielectric layer is at least one of silicon oxide, silicon oxynitride, borophosphosilicate glass and phosphosilicate glass.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The thickness of the patterned photoresist layer is 2000 angstroms to 2500 angstroms.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The thickness of the hard mask layer is 1000 angstroms to 1500 angstroms.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: A width of a portion of the contact hole located in the substrate is less than or equal to 0.11 micrometers.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9.

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