Package structure

Abstract

The invention discloses a packaging structure for packaging a semiconductor device. The semiconductor device comprises a first surface and a second surface which are opposite to each other, a plurality of electrodes of the semiconductor device are exposed on the first surface and the second surface, the packaging structure comprises a first substrate, the semiconductor device and a second substrate which are stacked, the first substrate comprises a first metal layer, the first metal layer is directly connected with the first surface, and the second substrate comprises a second metal layer; and the second substrate comprises a second metal layer which is directly connected with the second surface so as to be electrically connected with one part of the plurality of electrodes, and the second substrate comprises a second metal layer which is directly connected with the second surface so as to be electrically connected with the other part of the plurality of electrodes. Different electrodes on the semiconductor device can be directly connected with corresponding substrates, so that wireless connection of the semiconductor device is realized, the problems of large packaging volume, poor signal transmission quality, low reliability and the like caused by bonding wire connection are avoided, and improvement of the performance and the service life of the packaging structure are facilitated.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a packaging structure for packaging semiconductor devices. Background Art

[0002] With the continuous development of semiconductor technology, the integration of semiconductor devices has been increasing day by day, the functions have become more powerful, and the applications in electronic devices have become more and more extensive. However, semiconductor devices themselves are usually relatively small and fragile, and their internal circuits need to be reliably electrically connected to external circuits in order to work properly and play their roles.

[0003] Currently, wire bonding is an important and commonly used technical means to realize the connection between semiconductor devices and external circuits. Through wire bonding, the electrodes on the semiconductor device chip can be connected to the external pins of the package, thereby establishing a signal transmission channel between the chip and the external circuit.

[0004] However, the existing wire bonding technology has some problems that need to be solved urgently. On the one hand, as the operating frequency of semiconductor devices continues to increase, the parasitic parameters such as parasitic inductance and capacitance of wire bonds have a more significant impact on signal transmission, which may lead to problems such as signal delay and distortion, affecting the high-frequency performance of semiconductor devices. On the other hand, in some application scenarios with extremely high reliability requirements, such as aerospace and automotive electronics, wire bonds may break or fall off during long-term use due to factors such as mechanical stress and thermal stress, reducing the reliability and service life of semiconductor devices. In addition, the layout of wire bonds requires a certain amount of space. As semiconductor devices develop towards miniaturization and high density, how to compress the connection space is also one of the current challenges. Summary of the Invention

[0005] In view of the above problems, the purpose of the present application is to provide a packaging structure that can achieve wireless connection of semiconductor devices.

[0006] According to one aspect of the present application, there is provided a packaging structure for packaging a semiconductor device, wherein the semiconductor device includes opposite first and second surfaces, and a plurality of electrodes of the semiconductor device are exposed on the first and second surfaces. The packaging structure includes: a first substrate, the semiconductor device, and a second substrate stacked in sequence. The first substrate includes a first metal layer, and the first metal layer is directly connected to the first surface to be electrically connected to a part of the plurality of electrodes. The second substrate includes a second metal layer, and the second metal layer is directly connected to the second surface to be electrically connected to another part of the plurality of electrodes.

[0007] Optionally, the first metal layer and / or the second metal layer includes a plurality of electrically insulated sub-metal layers. Each metal layer and / or sub-metal layer is connected to a corresponding electrode among the plurality of electrodes and receives an electrical signal through a corresponding signal terminal. Wherein, there is a groove on the metal layer and / or the sub-metal layer connected to the signal terminal. In the stacking direction of the first substrate, the semiconductor device, and the second substrate, the signal terminal is at least partially embedded in the corresponding groove.

[0008] Optionally, in the stacking direction, 1 / 3h ≤ d1 ≤ 1 / 2h, where d1 is the embedding depth of the signal terminal, and h is the thickness of the metal layer or sub-metal layer connected to the signal terminal.

[0009] Optionally, in a plane perpendicular to the stacking direction, the distance between the groove and the semiconductor device is greater than or equal to a preset distance.

[0010] Optionally, in the direction of the preset distance, 1 / 2w ≤ d2 ≤ 2 / 3w, where d2 is the preset distance, and w is the width of the metal layer or sub-metal layer connected to the signal terminal.

[0011] Optionally, the connection method between the signal terminal and each metal layer and / or sub-metal layer includes ultrasonic welding.

[0012] Optionally, the plurality of electrodes includes a first electrode exposed on the first surface, a second electrode, and a third electrode exposed on the second surface. The first metal layer is welded to the first electrode, and the welding point includes a ball grid array. The second metal layer is welded to the second electrode and the third electrode, and the welding points include a ball grid array and columnar bumps.

[0013] Optionally, the second metal layer includes an electrically insulated first sub-metal layer and a second sub-metal layer. The first sub-metal layer is connected to the second electrode, and the welding point is the ball grid array. The second sub-metal layer is connected to the third electrode, and the welding point is the columnar bump.

[0014] Optionally, the material for welding the first metal layer to the first electrode is selected from at least one of gold, silver, and copper; and / or the material for welding the second metal layer to the second electrode and the third electrode is selected from at least one of gold, silver, and copper.

[0015] Optionally, the first substrate and the second substrate are ceramic insulating substrates. The first substrate further includes: a third metal layer, and a first ceramic layer located between the first metal layer and the third metal layer; the second substrate further includes: a fourth metal layer, and a second ceramic layer located between the second metal layer and the fourth metal layer; the third metal layer and / or the fourth metal layer is connected to a heat dissipation structure.

[0016] According to the packaging structure provided by the present application, a stacked first substrate, a semiconductor device, and a second substrate are provided, enabling different electrodes on the semiconductor device to be directly connected to the corresponding substrates, thereby achieving wireless connection of the semiconductor device, avoiding problems such as large packaging volume, poor signal transmission quality, and low reliability caused by bonding wire connection, and facilitating the improvement of the performance and service life of the packaging structure.

[0017] Furthermore, by embedding the signal terminal in the metal layer, the deformation of the signal terminal can be reduced, which is beneficial to improving the mechanical strength of the packaging structure, thereby further enhancing the service life of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Through the following description of the embodiments of the present invention with reference to the accompanying drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0019] Figure 1 A schematic structural diagram showing the second surface of the semiconductor device;

[0020] Figure 2 Showing along Figure 1 A schematic cross-sectional view of the semiconductor device taken along line A-A' in

[0021] Figure 3 A schematic structural diagram showing the packaging structure in the disclosed embodiment of the present application;

[0022] Figure 4 Showing Figure 3 An enlarged schematic diagram of the signal terminal connection part in DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] The various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are denoted by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0024] At the same time, certain terms are used in this specification and the claims to refer to particular components. Those of ordinary skill in the art should understand that manufacturers may use different names to refer to the same component. This specification and the claims do not use the difference in names as a way to distinguish components.

[0025] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuits. When an element or circuit is said to be "connected to" another element or when an element or circuit is said to be "connected between" two nodes, it can be directly coupled or connected to the other element or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. In contrast, when an element is said to be "directly coupled to" or "directly connected to" another element, it means there are no intermediate elements between the two.

[0026] In addition, it should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the said element.

[0027] The packaging structure provided by this application is used to package semiconductor devices, especially for packaging power semiconductor devices such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or IGBT (Insulated Gate Bipolar Transistor).

[0028] The semiconductor device includes opposite first and second surfaces, and a plurality of electrodes of the semiconductor device are exposed on the first and second surfaces. The packaging structure includes a first substrate, a semiconductor device, and a second substrate stacked. Among them, the first substrate includes a first metal layer, and the first metal layer is directly connected to the first surface of the semiconductor device to be electrically connected to a part of the plurality of electrodes of the semiconductor device. The second substrate includes a second metal layer, and the second metal layer is directly connected to the second surface of the semiconductor device and is electrically connected to another part of the plurality of electrodes of the semiconductor device.

[0029] It should be understood that, based on the different structures of semiconductor devices, the first metal layer and / or the second metal layer may each include a plurality of sub-metal layers that are electrically insulated from each other. Each metal layer and / or sub-metal layer is connected to a corresponding electrode among the plurality of electrodes and receives an electrical signal through a corresponding signal terminal, thereby avoiding signal interference between the electrodes.

[0030] For power semiconductor devices, generally, among the plurality of electrodes, there is a first electrode exposed on the first surface, and a second electrode and a third electrode exposed on the second surface. Exemplarily, for a MOSFET, the first electrode is the drain, the second electrode is the source, and the third electrode is the gate; for an IGBT, the first electrode is the collector, the second electrode is the emitter, and the third electrode is the gate. Correspondingly, in the power semiconductor device, at least the second metal layer includes a plurality of sub-metal layers that are electrically connected to the second electrode and the third electrode respectively.

[0031] To facilitate the understanding of the semiconductor package structure disclosed in this application, the following takes a MOSFET device as an example for a detailed introduction.

[0032] Figure 1 A schematic structural diagram of the second surface is shown. Figure 2 Shows along Figure 1 A schematic cross-sectional view of the semiconductor device taken along the line A-A' in

[0033] Refer to Figure 1 and Figure 2 , the semiconductor device 110 includes opposite first surface 10 and second surface 20. Among them, the first electrode, that is, the drain 113, is exposed on the first surface 10; the second electrode and the third electrode, that is, the source 111 and the gate 112, are exposed on the second surface 20. It should be understood that, based on the internal structure of the semiconductor device, each electrode may include a plurality of sub-electrodes exposed in different regions of the corresponding surface. Exemplarily, in the semiconductor structure shown in Figure 1 and Figure 2 , the source 111 includes three sub-electrodes 111a, 111b, and 111c.

[0034] Figure 3 Shows a schematic structural diagram of the package structure in the disclosed embodiment of this application. Refer to Figure 3 , the package structure 100 includes a first substrate 120, a semiconductor device 110, and a second substrate 130 that are stacked. Among them, to facilitate a more intuitive understanding of the relative positional relationship between the various parts, Figure 3 The A end and the A' end of the semiconductor device in Figure 1 and Figure 2The relative positions of the A end and the A' end shown in the figure are the same, and the direction indicated by the arrow is the direction from the first surface 10 to the second surface 20 of the semiconductor device 110, that is, the stacking direction of the first substrate 120, the semiconductor device 110, and the second substrate 130.

[0035] The first substrate 120 includes a first metal layer 121. The first metal layer 121 is directly connected to the first surface 10 of the semiconductor device 110 and is electrically connected to the first electrode exposed on the first surface 10. Specifically, the first metal layer 121 is connected to the first surface 10 by welding, and the solder joints are taken as an example of a ball grid array BGA (Ball Grid Array).

[0036] The second substrate 130 includes a second metal layer 131. The second metal layer 131 is directly connected to the second surface 20 of the semiconductor device 110 and is electrically connected to the second electrode and the third electrode exposed on the second surface 20. Among them, the second metal layer 131 includes a plurality of sub-metal layers that are electrically insulated from each other and are respectively electrically connected to the second electrode and the third electrode.

[0037] As Figure 3 In the illustrated embodiment, the second metal layer 131 includes a first sub-metal layer 131a and a second sub-metal layer 131b. The first sub-metal layer 131a is electrically connected to the second electrode, and the second sub-metal layer 131b is electrically connected to the third electrode. The second metal layer 131 can also be connected to the second surface 20 by welding. For example, as Figure 3 shown, the solder joint between the second electrode and the first sub-metal layer 131a is a ball grid array BGA, and the solder joint between the third electrode and the second metal layer 131b is a columnar bump Bump.

[0038] It should be understood that this application does not impose too many restrictions on the connection structure, connection method, or connection material between the first metal layer 121 and the first surface 10, and the connection structure, connection method, or connection material between the second metal layer 122 and the second surface 20. For example, in the case of welding, the welding material can be selected from at least one of gold, silver, and copper. That is to say, the welding material between the first metal layer 121 and the first electrode on the first surface 10 can be selected from at least one of gold, silver, and copper; and / or the material for welding the second metal layer 131 to the second electrode and the third electrode on the second surface 20 is selected from at least one of gold, silver, and copper.

[0039] In some embodiments, other types of solder joints can also be selected in combination with the contact area between each electrode and the corresponding metal layer / sub-metal layer.

[0040] In addition, in some other embodiments, for the connection between the first surface 10 and the first metal layer 121, and the connection between the second surface 20 and the second metal layer 131, other connection structures and methods in the prior art can be selected.

[0041] Further, in a preferred embodiment, as Figure 3 shown, both the first substrate 120 and the second substrate 130 are ceramic substrates, such as direct bonding copper ceramic substrates (DBC) or active metal brazed ceramic substrates (AMB).

[0042] The first substrate 120 further includes a third metal layer 122 and a first ceramic layer 123. The first ceramic layer 123 is located between the third metal layer 122 and the first metal layer 121 to electrically insulate the first metal layer 121 and the third metal layer 122. The second substrate 130 further includes a fourth metal layer 133 and a second ceramic layer 132. The second ceramic layer 132 is located between the second metal layer 131 and the fourth metal layer 133 to electrically insulate the second metal layer 131 and the fourth metal layer 133.

[0043] Further, in some embodiments, the third metal layer 122 and / or the fourth metal layer 133 can also be connected to a heat dissipation structure to dissipate heat from the semiconductor device 110 through the double-sided heat dissipation structure, improving the heat dissipation capacity of the packaging structure 100.

[0044] Further, in the packaging structure 100, each sub-metal layer in the first metal layer 121 and / or the second metal layer 131 receives an electrical signal through a corresponding signal terminal 140. The signal terminal 140 can be connected to the corresponding metal layer and / or sub-metal layer by, for example, ultrasonic welding. To improve the mechanical strength, in the embodiments of the present application, the first metal layer 121 and / or the second metal layer 131 has grooves to allow the signal terminal 140 to be embedded in the grooves in the above-mentioned stacking direction.

[0045] In Figure 3 only the signal terminal 140 on the second sub-metal layer 131b is shown as an example. As Figure 3 shown, one end of the signal terminal 140 is embedded in the groove on the second sub-metal layer 131b, and the other end receives the electrical signal provided by the outside. In some embodiments, these grooves are obtained, for example, by etching. The structural strength of the signal terminal 140 can be improved through embedded installation.

[0046] In some embodiments, by defining the groove depth, that is, the depth d1 of the signal terminal 140 embedded in the corresponding metal layer or sub-metal layer, both the connection strength between the signal terminal 140 and the corresponding metal layer and / or sub-metal layer can be ensured, and it can be ensured that the signal terminal 140 does not squeeze the semiconductor device 110 and / or the substrate on the other side.

[0047] In a preferred embodiment, in the above-mentioned stacking direction, that is, the embedding direction of the signal terminal 140, the limitation of the embedding depth d1 is, for example, 1 / 3h ≤ d1 ≤ 1 / 2h, where d1 is the groove depth, that is, the embedding depth of the signal terminal, and h is the thickness of the metal layer or sub-metal layer connected to the signal terminal 140.

[0048] To facilitate a better understanding of the above limitation on the groove depth d1. Figure 4 It shows Figure 3 an enlarged view of the connection position of the signal terminal 140 in Figure 3 and 4 , taking the example that the signal terminal 140 is connected to the second sub-metal layer 131b, then in the above-mentioned preferred embodiment, 1 / 3h ≤ d1 ≤ 1 / 2h exists. Wherein, as Figure 4 shown, d1 is the groove depth, that is, the depth of the signal terminal 140 embedded in the second sub-metal layer 131b, and h is the thickness of the second sub-metal layer 131b. Thus, on the basis of ensuring the connection strength of the signal terminal 140, the extrusion of the signal terminal 140 on the semiconductor device 110 and the first substrate 120 can be avoided.

[0049] Furthermore, the connection position of the signal terminal 140 can be specified by limiting the groove position on the corresponding metal layer and / or sub-metal layer, so as to avoid the influence on the semiconductor device 110 when the signal terminal vibrates. Exemplarily, the above limitation on the groove position can be specifically embodied as shown in Figure 3 , in a plane perpendicular to the stacking direction, that is, the mounting plane of the signal terminal 140, the distance between the groove for mounting the signal terminal 140 and the semiconductor device 110 is at least a preset distance d2. At this preset distance d2, the projections of the signal terminal 140 and the semiconductor device 110 or the first metal layer 121 in the stacking direction do not overlap. That is to say, referring to Figure 3 , at this preset distance d2, the semiconductor device 110 or the first metal layer 121 is not located above the signal terminal 140. Thus, even if the signal terminal 140 is displaced or vibrates during operation, it will not cause extrusion on the first substrate 120 and / or the semiconductor structure 110, which is beneficial to improving the reliability of the packaging structure.

[0050] It should be noted that since this application does not specifically limit the installation direction of the signal terminal 140, the preset distance d2 should be understood as: the projection of the straight-line distance between the signal terminal 140 and the semiconductor device 110 in the direction from end A to end A' in the figure. The direction of the preset distance d2 is also the direction from end A to end A' in the figure.

[0051] More specifically, in some embodiments, in the direction of the preset distance, the limitation of the groove position is, for example, 1 / 2w ≤ d2 ≤ 2 / 3w, where d2 is the preset distance between the groove and the semiconductor device 110, and w is the width of the metal layer or sub-metal layer connected to the signal terminal 140. By way of example, in combination with Figure 3 and 4 , in the example where the signal terminal 140 is connected to the second sub-metal layer 131b, d2 is the preset distance between the groove and the semiconductor device 110, that is, the preset distance between the signal terminal 140 and the semiconductor device 110; w is the width of the second sub-metal layer 131b in the direction of the preset distance d2.

[0052] According to the packaging structure provided by the present application, a stacked first substrate, a semiconductor device, and a second substrate are provided, so that different electrodes on the semiconductor device can be directly connected to the corresponding substrates, thereby realizing wireless connection of the semiconductor device, avoiding problems such as large packaging volume, poor signal transmission quality, and low reliability caused by wire bonding, and being beneficial to improving the performance and service life of the packaging structure.

[0053] Furthermore, by embedding the signal terminal in the metal layer, the deformation of the signal terminal can be reduced, which is beneficial to improving the mechanical strength of the packaging structure, thereby further improving the service life of the packaging structure.

[0054] As described above in accordance with the embodiments of the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to only the specific embodiments. Obviously, according to the above description, many modifications and variations can be made. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The protection scope of the present application should be determined by the scope defined by the claims of the present application.

Claims

1. A packaging structure for packaging a semiconductor device, wherein: The semiconductor device includes a first surface and a second surface opposite to each other, a plurality of electrodes of the semiconductor device being exposed to the first surface and the second surface, Wherein, the packaging structure includes: A first substrate, the semiconductor device and a second substrate are stacked. The first substrate includes a first metal layer, the first metal layer is directly connected to the first surface so as to be electrically connected to a portion of the plurality of electrodes. The second substrate includes a second metal layer, and the second metal layer is directly connected to the second surface to be electrically connected to another part of the plurality of electrodes.

2. The packaging structure according to claim 1, wherein: The first metal layer and / or the second metal layer includes a plurality of sub-metal layers electrically insulated from each other, each metal layer and / or sub-metal layer is connected to a corresponding electrode among the plurality of electrodes and receives an electrical signal through a corresponding signal terminal. The metal layer and / or the sub-metal layer connected to the signal terminal has a groove, and in the stacking direction of the first substrate, the semiconductor device and the second substrate, the signal terminal is at least partially embedded in the corresponding groove.

3. The packaging structure according to claim 2, wherein: In the stacking direction, 1 / 3h≤d1≤1 / 2h, d1 is the embedding depth of the signal terminal, and h is the thickness of the metal layer or sub-metal layer connected to the signal terminal.

4. The packaging structure according to claim 2, wherein: On a plane perpendicular to the stacking direction, a distance between the groove and the semiconductor device is greater than / equal to a preset distance.

5. The packaging structure according to claim 4, wherein: In the direction of the preset distance, 1 / 2w≤d2≤2 / 3w, d2 is the preset distance, and w is the width of the metal layer or sub-metal layer connected to the signal end.

6. The packaging structure according to claim 2, wherein: The method for connecting the signal terminal with each of the metal layers and / or the sub-metal layers includes ultrasonic welding.

7. The packaging structure according to claim 1, wherein: The plurality of electrodes include a first electrode exposed to the first surface and a second electrode and a third electrode exposed to the second surface, The first metal layer is connected to the first electrode by welding, and the welding point includes a ball grid array. The second metal layer is connected to the second electrode and the third electrode by welding, and the welding points include a ball grid array and a columnar bump.

8. The packaging structure according to claim 7, wherein: The second metal layer includes a first sub-metal layer and a second sub-metal layer which are electrically insulated from each other. The first sub-metal layer is connected to the second electrode, and the welding point is the ball grid array. The second sub-metal layer is connected to the third electrode, and the welding point is the columnar bump.

9. The packaging structure according to claim 7, wherein: The material of welding the first metal layer to the first electrode is selected from at least one of gold, silver and copper; and / or The material used for welding the second metal layer to the second electrode and the third electrode is selected from at least one of gold, silver and copper.

10. The packaging structure according to claim 1, wherein: The first substrate and the second substrate are ceramic insulating substrates, The first substrate further includes: a third metal layer, and a first ceramic layer located between the first metal layer and the third metal layer; The second substrate further includes: a fourth metal layer, and a second ceramic layer located between the second metal layer and the fourth metal layer; The third metal layer and / or the fourth metal layer are connected to the heat dissipation structure.

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