Packaging structure and preparation method thereof
By adopting large array planar packaging structure and conductive column electrical elicitation method in gene sequencing technology, the problems of small flux and low efficiency of sequencing chips in the prior art are solved, and high accuracy and low cost analysis of biochemical substances are achieved.
Patent Information
- Application Number
- CN202311682750.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-07
- Publication Date
- 2025-06-10
AI Technical Summary
Among the existing gene sequencing technologies, the sequencing chip has a small throughput, which limits the sequencing accuracy and application scenarios, and has low sequencing efficiency and high labor costs.
Using a large array planar packaging structure, multiple chips for biochemical substance analysis are integrated into the same packaging layer, and the electrical extraction of the chip is achieved by forming through holes in the packaging layer and forming conductive columns in the through holes.
Significantly increase the flux of biochemical substance analysis, improve the accuracy of biochemical substance analysis, reduce labor costs, and reduce the risk of line corrosion and chip failure.
Smart Images
Figure CN120127085A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of biochemical substance analysis, and particularly to a packaging structure and a preparation method thereof. Background Art
[0002] Currently, gene sequencing usually adopts small-throughput targeted sequencing, and a sequencing chip is connected to a circuit board through a traditional soldering method to form a complete device. However, the current sequencing chip has a small throughput, which limits the sequencing accuracy and application scenarios. At the same time, the sequencing efficiency is low and the labor cost is high. Summary of the Invention
[0003] To solve at least one of the above defects, it is necessary to propose a packaging structure, which is a large-array planar packaging structure and can include multiple chips for biochemical substance analysis.
[0004] In addition, this application also provides a preparation method of the foregoing packaging structure.
[0005] In a first aspect, an embodiment of this application provides a packaging structure, which includes: multiple chips, a packaging layer, conductive posts, and a redistribution layer. Each chip has a biological function layer on its surface, and the chip is used for biochemical substance analysis; the packaging layer covers each chip, and all the biological function layers are exposed from the same side of the packaging layer. Through holes are formed through the packaging layer, and the through holes are located around the chips; the conductive posts are located in the through holes, and the conductive posts are electrically connected to the chips; and the redistribution layer is located on the surface of the packaging layer away from the biological function layer, and the redistribution layer is electrically connected to the conductive posts.
[0006] In some possible embodiments, the multiple chips are arranged in an array.
[0007] In some possible embodiments, the chip further includes pins located outside the biological function layer. The conductive posts are electrically connected to the pins through connecting portions, and the packaging structure further includes a protective layer covering the surface of the connecting portions.
[0008] In some possible embodiments, an insulating layer is provided on the surface of the redistribution layer facing away from the packaging layer, and a conductive portion is provided on the insulating layer, and the conductive portion is electrically connected to the redistribution layer.
[0009] In some possible embodiments, a single conductive post is electrically connected to a single chip, and the conductive posts connecting different chips are independent of each other.
[0010] In a second aspect, an embodiment of this application provides a preparation method of a packaging structure, and the preparation method includes:
[0011] A plurality of chips are disposed on a substrate. A biofunctional layer is provided on the surface of the chips, and the biofunctional layer is disposed close to the substrate. The chips are used for biochemical substance analysis;
[0012] An encapsulation layer is formed on the surface of the substrate where the chips are disposed, and the encapsulation layer covers each of the chips;
[0013] The substrate is removed to expose the biofunctional layer;
[0014] A through hole is formed through the encapsulation layer, and the through hole is located around the chips;
[0015] A conductive pillar is formed in the through hole to electrically connect the conductive pillar to the chips; and
[0016] A redistribution layer is formed on the surface of the encapsulation layer facing away from the biofunctional layer, and the redistribution layer is electrically connected to the conductive pillar, thereby obtaining the encapsulation structure.
[0017] In some possible embodiments, the step of disposing a plurality of chips on a substrate includes:
[0018] A temporary bonding layer is provided on the surface of the substrate; and
[0019] The surface of the chips where the biofunctional layer is provided is attached to the temporary bonding layer.
[0020] In some possible embodiments, the step of removing the substrate includes:
[0021] The substrate and the temporary bonding layer are removed by heating.
[0022] In some possible embodiments, the chips further include pins located outside the biofunctional layer. The step of forming a conductive pillar in the through hole to electrically connect the conductive pillar to the chips includes:
[0023] A dielectric layer is formed on the surface of the encapsulation layer close to the biofunctional layer, and the dielectric layer extends to the surface of the biofunctional layer;
[0024] The dielectric layer is patterned to expose the through hole and the pins;
[0025] The conductive pillar is formed in the through hole, and a connection portion is formed on the surface of the encapsulation layer. The connection portion electrically connects the conductive pillar and the pins; and
[0026] The dielectric layer is removed.
[0027] In some possible embodiments, before the step of removing the dielectric layer, the preparation method further includes:
[0028] A protective layer is formed on the surface of the encapsulation layer, and the protective layer covers the connection part and the pins.
[0029] In some possible embodiments, after the step of forming the redistribution layer on the surface of the encapsulation layer away from the biofunctional layer, the manufacturing method further includes:
[0030] forming an insulating layer on the surface of the redistribution layer; and
[0031] forming a conductive part on the surface of the insulating layer, and the conductive part is electrically connected to the redistribution layer.
[0032] The encapsulation structure and its manufacturing method provided by the embodiments of the present application integrate multiple chips (such as sequencing chips) for biochemical substance analysis in the same encapsulation layer to form a large-array planar encapsulation structure, which can significantly increase the throughput of biochemical substance analysis, improve the accuracy of biochemical substance analysis, and reduce labor costs; by forming vias in the encapsulation layer and forming conductive posts in the vias, the electrical lead-out of the chips is realized. Therefore, the electrical lead-out lines of the chips are not exposed outside, and the risks of reagent corrosion of the lines, short circuits of the lines, and chip failure can be effectively reduced; the electrical lead-out method of the chips does not use glue, and can also reduce the influence of glue on the biochemical performance of the chips and improve the accuracy of biochemical substance analysis; in addition, multiple chips in the encapsulation structure can be independently controlled, and the failure of a few chips will not affect the use of the entire large array. Description of the Drawings
[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0034] Figure 1 It is a schematic structural diagram of an encapsulation structure according to an embodiment of the present application.
[0035] Figure 2 It is a schematic flowchart of a manufacturing method of an encapsulation structure according to an embodiment of the present application.
[0036] Figure 3 It is a schematic structural diagram of a wafer according to an embodiment of the present application.
[0037] Figure 4 For Figure 3 the structure schematic diagram of the chip obtained by dicing the wafer in
[0038] Figure 5 For Figure 4Schematic diagram of the structure for forming a packaging layer on the substrate shown.
[0039] Figure 6 For removing Figure 5 Schematic diagram of the structure of the substrate in
[0040] Figure 7 For removing Figure 6 Schematic diagram of the structure of the temporary bonding layer in
[0041] Figure 8 For forming Figure 7 Schematic diagram of the structure for opening a through hole in the packaging layer shown.
[0042] Figure 9 For forming Figure 8 Schematic diagram of the structure for forming a dielectric layer on the surface of the packaging layer shown and patterning the dielectric layer.
[0043] Figure 10 For forming Figure 9 Schematic diagram of the structure for forming a conductive pillar in the through hole shown and forming a connection part on the conductive pillar.
[0044] Description of main component symbols
[0045]
[0046]
[0047] The following specific embodiments will further illustrate the present application in conjunction with the above-mentioned drawings. Specific embodiments
[0048] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.
[0049] It should be noted that when a component is referred to as "fixed to" or "installed on" another component, it can be directly on the other component or there may also be an intermediate component. When a component is considered to be "disposed on" another component, it can be directly disposed on the other component or there may be an intermediate component at the same time. The term "and / or" used herein includes all and any combinations of one or more of the related listed items.
[0050] Please refer to Figure 1As shown in the figure, an embodiment of the present application provides a packaging structure 100, and the packaging structure 100 includes: a plurality of chips 1, a packaging layer 2, conductive pillars 3, and a redistribution layer 4. A biofunctional layer 11 is provided on the surface of each chip 1, and the chip 1 is used for biochemical substance analysis (such as gene sequencing, and the chip 1 can be a sequencing chip). The packaging layer 2 covers each chip 1, and all the biofunctional layers 11 are exposed from the same side of the packaging layer 2. A through hole 21 is formed through the packaging layer 2, and the through hole 21 is located around the chip 1. The conductive pillar 3 is located in the through hole 21, and the conductive pillar 3 is electrically connected to the chip 1. The redistribution layer 4 is located on the surface of the packaging layer 2 away from the biofunctional layer 11, and the redistribution layer 4 is electrically connected to the conductive pillar 3, thereby realizing the electrical lead-out of the chip 1. It can be understood that during the process of electrically connecting the conductive pillar 3 and the chip 1, a single conductive pillar 3 is electrically connected to a single chip 1, that is, a single chip is electrically connected to a single conductive pillar 3 located around the chip 1, and the conductive pillars 3 connecting different chips 1 are independent of each other, that is, the chips 1 are electrically insulated from each other, so that the plurality of chips 1 will not interfere with each other, and thus independent control of the plurality of chips 1 can be realized.
[0051] Define the side of the chip 1 with the biofunctional layer 11 as the front side 14, then the side opposite to the front side 14 is the back side 15. The plurality of chips 1 are packaged through the packaging layer 2, and the front side 14 of the chip 1 is exposed to facilitate loading a sample into the biofunctional layer 11. Specifically, the chip 1 for biochemical substance analysis, such as a sequencing chip, mainly includes the biofunctional layer 11 and a sensor layer 12 located below the biofunctional layer 11. The biofunctional layer 11 is used to fix the sample to be detected, and exposing the biofunctional layer 11 from the packaging layer 2 facilitates loading the sample to be detected. The sensor layer 12 is configured to identify the signal generated after the sample to be detected reacts with the corresponding reagent. For example, the sensor layer 12 may include one or more image sensors, and may also include other sensors.
[0052] In some embodiments, the biofunctional layer 11 may include a plurality of microstructures (not shown in the figure) recessed toward the sensor layer 12, and the microstructures can be used to fix the sample to be detected. It can be understood that the biofunctional layer 11 may further include a flow channel cavity (not shown in the figure), and the flow channel cavity has a plurality of array sites near the bottom surface of the sensor layer 12, and the array sites are used to fix the sample to be detected.
[0053] In some embodiments, multiple chips 1 can be arranged in an array to facilitate sample addition to each chip 1. The multiple chips 1 are encapsulated within an encapsulation layer 2, thereby forming a large-array planar encapsulation structure 100, which can significantly improve the throughput of biochemical substance analysis (such as sequencing throughput), enhance the accuracy of biochemical substance analysis, reduce labor costs at the same time, and be applicable to more application scenarios.
[0054] The chip 1 further includes pins 13 located outside the biological functional layer 11, and the conductive posts 3 are electrically connected to the pins 13 through a connecting portion 5. That is, pins 13 are provided on the peripheral edge of the front surface of the chip 1, which facilitates the electrical connection between the conductive posts 3 and the chip 1 during the formation of the conductive posts 3.
[0055] The encapsulation structure 100 further includes a protective layer 6 covering the surface of the connecting portion 5. By locally adding the protective layer 6, it can protect the connecting portion 5 and avoid risks such as corrosion of the connecting portion 5 by reagents and short circuits during use. It can be understood that if the connecting portion 5 does not completely cover the pins 13 during the electrical connection process, the protective layer 6 can also cover the pins 13 to prevent the pins 13 from being corroded by reagents and causing risks such as short circuits.
[0056] The material of the conductive posts 3 can be a metal (such as copper) or a conductive paste. The conductive posts 3 can be formed in the through holes 21 by electroplating a metal, or the conductive posts 3 can be formed in the through holes 21 by filling a conductive paste and curing it.
[0057] The redistribution layer 4 can include one layer of circuit 41 or multiple layers of circuits 41. When multiple layers of circuits 41 are included, an insulating layer is provided between adjacent circuits 41. An insulating layer 7 is provided on the surface of the redistribution layer 4 facing away from the encapsulation layer 2 (i.e., an insulating layer 7 is formed on the outer surface of the redistribution layer 4). A conductive portion 8 is provided on the insulating layer 7, and the conductive portion 8 is electrically connected to the redistribution layer 4. Further, the conductive portion 8 can be electrically connected to a main board, thereby realizing the electrical lead-out of the redistribution layer 4.
[0058] In some embodiments, the conductive portion 8 can be a solder ball.
[0059] The packaging structure 100 provided by the embodiment of the present application integrates multiple chips 1 for biochemical substance analysis (such as sequencing chips) in the same packaging layer 2 to form a large-array planar packaging structure 100, which can significantly increase the throughput of biochemical substance analysis, improve the accuracy of biochemical substance analysis, and reduce labor costs. By forming through holes 21 in the packaging layer 2 and forming conductive posts 3 in the through holes 21, the electrical lead-out of the chip 1 is realized. Therefore, the electrical lead-out lines of the chip 1 are not exposed, which can effectively reduce the risks of line corrosion by reagents, short circuits, and chip failure. The electrical lead-out method of the chip 1 does not require the use of glue, and can also reduce the impact of glue on the biochemical performance of the chip 1, improving the accuracy of biochemical substance analysis. The line connections of multiple chips 1 in the packaging structure 100 do not affect each other, and the failure of a few chips 1 does not affect the use of the entire large array. In addition, multiple chips 1 in the packaging structure 100 can be independently controlled to meet different reaction process requirements.
[0060] Please refer to Figure 2 As shown, the embodiment of the present application also provides a preparation method for the foregoing packaging structure, including the following steps:
[0061] Step S1, a plurality of chips are disposed on a substrate. A biofunctional layer is provided on the surface of the chip, and the biofunctional layer is disposed close to the substrate. The chip is used for biochemical substance analysis.
[0062] Step S2, a packaging layer is formed on the surface of the substrate where the chip is disposed, and the packaging layer covers each chip.
[0063] Step S3, the substrate is removed to expose the biofunctional layer.
[0064] Step S4, through holes are formed through the packaging layer, and the through holes are located around the chips.
[0065] Step S5, conductive posts are formed in the through holes to electrically connect the conductive posts to the chips.
[0066] Step S6, a redistribution layer is formed on the surface of the packaging layer facing away from the biofunctional layer, and the redistribution layer is electrically connected to the conductive posts, thereby obtaining the packaging structure.
[0067] Next, in conjunction with Figure 1 、 Figures 3 to 10 The preparation method of the packaging structure 100 of the embodiment of the present application will be described in detail. The preparation method specifically includes the following steps:
[0068] Step 1, as Figure 3 shown, a wafer 10 is provided. A plurality of chips 1 are provided on the wafer 10, and the wafer 10 is diced to separate the plurality of chips 1.
[0069] Among them, the specific structure of chip 1 has been described above and will not be elaborated here.
[0070] Step 2, as Figure 4 shown, a plurality of chips 1 are respectively disposed on a substrate 20.
[0071] Among them, a temporary bonding layer 30 is provided on the surface of the substrate 20, and the back surface 15 of the chip 1 is facing upward and the front surface 14 is facing downward and mounted on the temporary bonding layer 30.
[0072] In some embodiments, the temporary bonding layer 30 may be a release adhesive that can be peeled off and removed by a specific method (such as heating).
[0073] Step 3, as Figure 5 shown, an encapsulation layer 2 is formed on the surface of the substrate 20, and the encapsulation layer 2 covers each chip 1.
[0074] Specifically, a plurality of chips 1 are encapsulated by using a molding material, and the molding material can be cured to form the encapsulation layer 2.
[0075] In some embodiments, the molding material may be resins such as ABS resin, epoxy resin, polyphenylene oxide (PPO), polyimide (PI), polyethylene terephthalate (PET), and polyethylene naphthalate (PEN).
[0076] Step 4, as Figure 6 and Figure 7 shown, the substrate 20 and the temporary bonding layer 30 are removed to expose the biological functional layer 11.
[0077] Specifically, the substrate 20 and the temporary bonding layer 30 can be removed by heating, and the heating method can be hot plate heating or laser heating, etc.
[0078] It can be understood that in order to avoid the influence of the temporary bonding layer 30 on the biological functional layer 11, after removing the temporary bonding layer 30, a cleaning step can be performed on the exposed biological functional layer 11. The biological functional layer 11 can also be protected by forming a removable protective structure on the surface of the biological functional layer 11 in advance, and the protective structure can be removed during use.
[0079] Step 5, as Figure 8 shown, a through hole 21 is formed through the encapsulation layer 2, and the through hole 21 is located around the chip 1.
[0080] Specifically, vias 21 can be formed on the encapsulation layer 2 through processes such as mechanical punching, etching, or laser ablation.
[0081] Step 6, as Figure 9 shown, a dielectric layer 40 is formed on the surface of the encapsulation layer 2 close to the biofunctional layer 11, and the dielectric layer 40 extends to the surface of the biofunctional layer 11.
[0082] Among them, extending the dielectric layer 40 to the biofunctional layer 11 can play a protective role to prevent the biofunctional layer 11 from being damaged during subsequent patterning and electroplating processes.
[0083] Step 7, as Figure 9 shown, the dielectric layer 40 is patterned to expose the vias 21 and the pins 13 of the chip 1.
[0084] Specifically, an opening 50 is formed at the position of the dielectric layer 40 corresponding to the vias 21, so that the vias 21 and the pins 13 of the chip 1 are exposed by the opening 50.
[0085] Among them, the method of patterning the dielectric layer 40 may include steps such as film coating, exposure and development, and etching.
[0086] Step 8, as Figure 10 shown, conductive posts 3 are formed in the vias 21, and a connection part 5 is formed on the surface of the encapsulation layer 2. The connection part 5 is electrically connected to the conductive posts 3 and the pins 13.
[0087] Among them, the conductive posts 3 can be formed in the vias 21 by physical vapor deposition, chemical vapor deposition, electroplating, etc. It can be understood that the conductive posts 3 can also be formed by filling the vias 21 with conductive paste.
[0088] In some embodiments, before forming the conductive posts 3, a seed layer can also be formed on the inner wall of the vias 21 to improve the bonding force between the conductive posts 3 and the encapsulation layer 2.
[0089] Step 9, as Figure 10 shown, a protective layer 6 is formed in the opening 50, and the protective layer 6 covers the connection part 5.
[0090] Forming the protective layer 6 in the opening 50 can cover the connection part 5, thereby reducing the risk of the connection part 5 being corroded by reagents. It can be understood that the protective layer 6 can also cover the exposed pins 13.
[0091] Step 10, as Figure 1 shown, the dielectric layer 40 is removed.
[0092] After removing the dielectric layer 40, the biofunctional layer 11 can be exposed. In addition, if the biofunctional layer 11 needs to be cleaned, it can be done at this step or after completing the production of the entire encapsulation structure.
[0093] Step 11, as Figure 1 shown, a redistribution layer 4 is formed on the surface of the encapsulation layer 2 facing away from the biological function layer 11, and the redistribution layer 4 is electrically connected to the conductive posts 3.
[0094] Among them, as described above, the redistribution layer 4 may include a single layer of circuit 41 or may include multiple layers of circuits 41. The specific circuit formation method may adopt methods such as electroplating and etching.
[0095] Step 12, as Figure 1 shown, an insulating layer 7 is formed on the surface of the redistribution layer 4.
[0096] Step 13, as Figure 1 shown, a conductive part 8 is formed on the surface of the insulating layer 7, and the conductive part 8 is electrically connected to the redistribution layer 4, thereby obtaining the encapsulation structure 100.
[0097] Among them, the conductive part 8 may be a solder ball, and electrical connection with a structure such as a main board can be achieved through the conductive part 8.
[0098] The preparation method of the encapsulation structure provided by the embodiment of the present application encapsulates multiple chips 1 in the encapsulation layer 2 by adding temporary bonding and removing the bonding, and can expose the biological function layer 11 to realize biochemical substance analysis, achieving large-array planar packaging, effectively improving the throughput and accuracy of biochemical substance analysis. Moreover, by forming through holes 21 in the encapsulation layer 2 and placing the conductive posts 3 for electrically leading out the chips 1 in the through holes 21, corrosion of the conductive posts 3 by reagents and short circuits can be avoided, reducing the risk of chip 1 failure; the electrical lead-out method of the chips 1 does not use glue, which can also reduce the influence of glue on the biochemical performance of the chips 1 and improve the accuracy of biochemical substance analysis. In addition, the preparation process of the encapsulation structure 100 is simple, improving the yield of the encapsulation structure 100 and reducing the labor cost.
[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and not to limit them. Although the present application has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present application can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present application.
Claims
1. An encapsulation structure, characterized in that, it includes: a plurality of chips, each chip having a biofunctional layer on its surface, and the chips are used for biochemical substance analysis; an encapsulation layer covering each chip, and all the biofunctional layers are exposed from the same side of the encapsulation layer, and through holes are formed through the encapsulation layer, and the through holes are located around the chips; conductive posts located in the through holes, and the conductive posts are electrically connected to the chips; and a redistribution layer located on the surface of the encapsulation layer away from the biofunctional layer, and the redistribution layer is electrically connected to the conductive posts.
2. The encapsulation structure according to claim 1, characterized in that, the plurality of chips are arranged in an array.
3. The encapsulation structure according to claim 1, characterized in that, the chip further includes pins located outside the biofunctional layer, the conductive posts are electrically connected to the pins through connection parts, and the encapsulation structure further includes a protective layer covering the surface of the connection parts.
4. The encapsulation structure according to claim 1, characterized in that, an insulating layer is provided on the surface of the redistribution layer facing away from the encapsulation layer, and a conductive part is provided on the insulating layer, and the conductive part is electrically connected to the redistribution layer.
5. The encapsulation structure according to claim 1, characterized in that, a single conductive post is electrically connected to a single chip, and the conductive posts connecting different chips are independent of each other.
6. A method for manufacturing an encapsulation structure, characterized in that, it includes: placing a plurality of chips on a substrate, the chips having a biofunctional layer on their surfaces, and the biofunctional layer is disposed close to the substrate, and the chips are used for biochemical substance analysis; forming an encapsulation layer on the surface of the substrate where the chips are disposed, and the encapsulation layer covers each chip; removing the substrate to expose the biofunctional layer; forming through holes through the encapsulation layer, and the through holes are located around the chips; forming conductive posts in the through holes to electrically connect the conductive posts to the chips; and forming a redistribution layer on the surface of the encapsulation layer facing away from the biofunctional layer, and the redistribution layer is electrically connected to the conductive posts, thereby obtaining the encapsulation structure.
7. The method for manufacturing an encapsulation structure according to claim 6, characterized in that, the step of placing a plurality of chips on a substrate includes: providing a temporary bonding layer on the surface of the substrate; and attaching the surface of the chip provided with the biofunctional layer to the temporary bonding layer.
8. The method for manufacturing an encapsulation structure according to claim 7, characterized in that, the step of removing the substrate includes: removing the substrate and the temporary bonding layer by heating.
9. The method for manufacturing an encapsulation structure according to claim 6, characterized in that, the chip further includes pins located outside the biofunctional layer, and the step of forming conductive posts in the through holes to electrically connect the conductive posts to the chips includes: forming a dielectric layer on the surface of the encapsulation layer close to the biofunctional layer, and the dielectric layer extends to the surface of the biofunctional layer; patterning the dielectric layer to expose the through holes and the pins; Form the conductive pillar within the through hole, and form a connection part on the surface of the encapsulation layer, where the connection part is electrically connected to the conductive pillar and the pin; and Remove the dielectric layer.
10. The method for manufacturing the encapsulation structure according to claim 9, characterized in that before the step of removing the dielectric layer, the manufacturing method further includes: Form a protective layer on the surface of the encapsulation layer, where the protective layer covers the connection part and the pin.
11. The method for manufacturing the encapsulation structure according to claim 6, characterized in that after the step of forming the redistribution layer on the surface of the encapsulation layer away from the biofunctional layer, the manufacturing method further includes: Form an insulating layer on the surface of the redistribution layer; and Form a conductive part on the surface of the insulating layer, where the conductive part is electrically connected to the redistribution layer.