Semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof. The semiconductor element comprises a first wafer, a second wafer, a dielectric layer and a first metal structure. The first wafer includes a first substrate and a first interconnect layer disposed on the first substrate. The second wafer includes a second substrate and a second interconnection layer. The second substrate comprises a buried oxide layer and a semiconductor layer arranged on the buried oxide layer, the second interconnection layer is arranged on the semiconductor layer, and the second interconnection layer is connected with the first interconnection layer. The dielectric layer is disposed on the buried oxide layer. The first metal structure is arranged in the dielectric layer in a penetrating mode, one end of the first metal structure is in contact with the embedded oxide layer, and the embedded oxide layer is grounded through the first metal structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and particularly to a bonded semiconductor element and a manufacturing method thereof. Background Art

[0002] A three-dimensional integrated circuit (3D IC) refers to the transformation of a traditional two-dimensional chip into a three-dimensional stacked chip by using wafer level bonding and through silicon via (TSV) technology. Since 3D IC can effectively utilize space and shorten the circuit transmission distance, providing a very low resistance connection, it has gradually become the mainstream technology for components such as power converters, low-noise amplifiers, radio frequency (RF) or millimeter wave (MMW). Therefore, how to improve the properties of 3D IC, such as the electrical performance of 3D IC, has become the goal that related industries continue to strive for. Summary of the Invention

[0003] According to an embodiment of the present invention, a semiconductor element is provided, including a first wafer, a second wafer, a dielectric layer, and a first metal structure. The first wafer includes a first substrate and a first interconnect layer disposed on the first substrate. The second wafer includes a second substrate and a second interconnect layer. The second substrate includes a buried oxide layer and a semiconductor layer disposed on the buried oxide layer, and the second interconnect layer is disposed on the semiconductor layer, wherein the second interconnect layer is bonded to the first interconnect layer. The dielectric layer is disposed on the buried oxide layer. The first metal structure is disposed through the dielectric layer, wherein one end of the first metal structure contacts the buried oxide layer, and the buried oxide layer is grounded through the first metal structure.

[0004] According to another embodiment of the present invention, a method for manufacturing a semiconductor element is provided, including the following steps: providing a first wafer, wherein the first wafer includes a first substrate and a first interconnect layer disposed on the first substrate; providing a second wafer, wherein the second wafer includes a second substrate and a second interconnect layer, the second substrate includes a buried oxide layer and a semiconductor layer disposed on the buried oxide layer, and the second interconnect layer is disposed on the semiconductor layer; bonding the second interconnect layer to the first interconnect layer; forming a dielectric layer on the buried oxide layer; and forming a first metal structure through the dielectric layer, wherein one end of the first metal structure contacts the buried oxide layer, and the buried oxide layer is grounded through the first metal structure.

[0005] Compared with the prior art, the semiconductor device of the present invention includes a first metal structure. One end of the first metal structure is in contact with the buried oxide layer, enabling the buried oxide layer to be grounded through the first metal structure, which is beneficial for forming a charge release path and can transfer the charges accumulated in the buried oxide layer during the manufacturing process to the outside, thus being beneficial for improving the electrical performance of the semiconductor device. The semiconductor device may further include a diode. The diode is in direct contact with the buried oxide layer, enabling the buried oxide layer to be grounded through the diode, providing another charge release path for the charges accumulated in the buried oxide layer to be transferred to the outside, and further improving the electrical performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 and Figure 7 are schematic cross-sectional views of the steps for manufacturing a semiconductor device according to an embodiment of the present invention.

[0007] SYMBOLS AND DESCRIPTIONS

[0008] 1: Semiconductor device

[0009] 10: First wafer

[0010] 20: Second wafer

[0011] 30: Dielectric layer

[0012] 50: Protective layer

[0013] 62: First metal structure

[0014] 61, 63, 67, 167, 169, 267: Contact holes

[0015] 64: Second metal structure

[0016] 66: Third metal structure

[0017] 68: Fourth metal structure

[0018] 70: Diode

[0019] 80: Shallow trench isolation structure

[0020] 110: First substrate

[0021] 112, 212: Buried oxide layer

[0022] 114, 214, 216: Semiconductor layer

[0023] 120, 220: Dielectric layer

[0024] 130: First Interconnection Layer

[0025] 132, 232: Inter-Metal Dielectric Layer

[0026] 134, 234: Metal Interconnect

[0027] 140: High Capture Layer

[0028] 150: Support Substrate

[0029] 160: First Transistor

[0030] 162, 262: Gate Structure

[0031] 163, 263: Spacer

[0032] 164, 264: Well Region

[0033] 166, 266: Source / Drain Region

[0034] 168, 268: Contact Plug

[0035] 210: Second Substrate

[0036] 230: Second Interconnection Layer

[0037] 2341: Metal Layer

[0038] 260: Second Transistor

[0039] 410: First Metal Pad

[0040] 420: Second Metal Pad

[0041] 510: First Protective Layer

[0042] 520: Second Protective Layer

[0043] 530: Hole

[0044] 621, 622, 641, 642, 661, 662: End

[0045] 710: N-Type Doped Region

[0046] 720: P-Type Doped Region

[0047] S1: Bonding Surface Detailed Implementation Manner

[0048] The foregoing and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the accompanying drawings. In order to make the content of the present invention clearer and easier to understand, the following drawings may be simplified schematic diagrams, and the elements therein may not be drawn to scale. Moreover, the number and size of the elements in the drawings are only for illustration and do not limit the present invention. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front, back, bottom, top, etc., are only with reference to the directions of the drawings. Therefore, the directional terms used are for illustration and do not limit the present invention. In addition, in the following embodiments, the same or similar elements will be denoted by the same or similar reference numerals.

[0049] In the following description of "the first feature is formed on or above the second feature", it may mean that "the first feature is in direct contact with the second feature", or it may mean that "there are other features between the first feature and the second feature", so that the first feature and the second feature are not in direct contact.

[0050] The present invention uses terms such as first, second, etc. to describe elements, regions, layers, and / or sections, but it should be understood that these terms are only used to distinguish one element, region, layer, and / or section from another element, region, layer, and / or section, and they do not inherently imply and represent that the element has any previous ordinal number, nor does it represent the arrangement order of one element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, region, layer, and / or section discussed below may also be referred to by the terms of the second element, region, layer, and / or section. Such terms in the claims may not be the same as those in the specification, and may be replaced by first, second, third... in accordance with the order of the element declarations in the claims.

[0051] Please refer to Figures 1 to 7 , which is a schematic cross-sectional view of the steps of manufacturing a semiconductor device according to an embodiment of the present invention. Figure 1 In, first, a first wafer 10 is provided. The first wafer 10 includes a first substrate 110 and a first interconnect layer 130. The first interconnect layer 130 is disposed on the first substrate 110.

[0052] For example, the first wafer 10 can be fabricated in the following manner. First, a first substrate 110 can be provided. The first substrate 110 is, for example, a silicon-on-insulator (SOI) substrate, which mainly includes a semiconductor layer (not shown in the figure, hereinafter also referred to as the bottom semiconductor layer for ease of description), a buried oxide layer 112 disposed on the bottom semiconductor layer, and another semiconductor layer 114 (also referred to as the top semiconductor layer) disposed on the buried oxide layer 112. The materials of the aforementioned bottom semiconductor layer (not shown in the figure) and the semiconductor layer 114 can be the same or different, and can independently include silicon, germanium, silicon germanide, or a combination thereof. The material of the buried oxide layer 112 can include silicon dioxide, but is not limited thereto.

[0053] Next, a portion of the semiconductor layer 114 can be removed to form a shallow trench isolation (STI) structure 80 surrounding each active region (not separately labeled). The active regions surrounded by the shallow trench isolation structure 80 can be used to dispose active devices, such as the first transistor 160.

[0054] Next, the first transistor 160 is formed in the first substrate 110. In this embodiment, the first transistor 160 is taken as an example of an n-type metal oxide semiconductor (NMOS) transistor for illustration, but the present invention is not limited thereto. The first transistor 160 includes a well region 164 disposed in the semiconductor layer 114 surrounded by the shallow trench isolation structure 80, a gate structure 162 disposed on the semiconductor layer 114 surrounded by the shallow trench isolation structure 80 and above the well region 164, spacer walls 163 disposed on the sidewalls of the gate structure 162, and two source / drain regions 166 disposed in the semiconductor layer 114 on both sides of the spacer walls 163. The conductivity types of the two source / drain regions 166 are the same and different from the conductivity type of the well region 164. Here, taking the first transistor 160 as an NMOS transistor as an example, the well region 164 is a P-type well region, which can be doped with a P-type dopant, such as boron, indium, etc., and the conductivity type of the two source / drain regions 166 is N-type, which can be doped with an N-type dopant, such as arsenic, phosphorus, etc.

[0055] The gate structure 162 may include, from bottom to top, a gate dielectric layer (not shown in the figure) and a gate material layer (not shown in the figure). The material of the gate dielectric layer may include silicon dioxide, silicon nitride, or a high dielectric constant (high-k) material. The material of the gate material layer may include a conductive material, such as doped polysilicon, doped amorphous silicon, a metal, or a metal compound. However, the present invention is not limited thereto, and the gate structure 162 may include other material layers according to actual needs. For example, one or more work function metal layers and / or barrier layers may be selectively disposed between the gate dielectric layer and the gate material layer. The spacer 163 may be a single material layer or a stacked material layer, and the material of the spacer 163 may include an oxide and / or a nitride, such as silicon dioxide, silicon nitride, silicon oxynitride, or silicon carbonitride.

[0056] Next, a dielectric layer 120 is formed on the first substrate 110 to cover the first transistor 160. A contact etch stop layer (CESL) (not shown in the figure) may be selectively formed on the first substrate 110 to cover the first transistor 160 before forming the dielectric layer 120. The material of the dielectric layer 120 may include, for example, an oxide such as silicon dioxide, borophosphosilicate glass (BPSG), tetraethoxysilane (TEOS), spin-on glass (SOG), undoped silicate glass (USG), or fluorinated silicate glass (FSG). The material of the contact etch stop layer may include, for example, silicon nitride, but is not limited thereto.

[0057] Next, semiconductor manufacturing processes such as photolithography and etching may be used to remove part of the dielectric layer 120 and part of the contact etch stop layer to form a plurality of contact holes 167 exposing the gate structure 162 and the two source / drain regions 166 of the first transistor 160. Then, a contact plug manufacturing process is performed. For example, a conductive layer (not shown in the figure) may be first formed in the contact holes 167, and then a planarization manufacturing process, such as a chemical mechanical polishing (CMP) manufacturing process, is used to remove part of the conductive layer to form a plurality of contact plugs 168 in the dielectric layer 120 electrically connecting the gate structure 162 and the two source / drain regions 166, wherein the upper surface of the contact plugs 168 may be flush with the upper surface of the dielectric layer 120.

[0058] Next, using another semiconductor manufacturing process such as photolithography and etching, part of the dielectric layer 120, part of the contact hole etch stop layer, part of the semiconductor layer 114 (or the shallow trench isolation structure 80 disposed in the semiconductor layer 114), and part of the buried oxide layer 112 are removed to form a contact hole 169. Then, another contact plug manufacturing process is performed. For example, a conductive layer (not shown in the figure) can be first formed to fill the contact hole 169, and then a planarization manufacturing process, such as a chemical mechanical polishing manufacturing process, is used to remove part of the conductive layer to form a third metal structure 66 passing through the dielectric layer 120 and the semiconductor layer 114 (or the shallow trench isolation structure 80 disposed in the semiconductor layer 114) and the buried oxide layer 112 of the first substrate 110. That is, the third metal structure 66 is a through-silicon via.

[0059] The materials of the conductive layers for forming the contact plug 168 and the third metal structure 66 described above can be the same or different, and can each independently include a barrier layer (not shown in the figure) and a metal layer (not shown in the figure). The material of the barrier layer can include titanium, tantalum, titanium nitride, tantalum nitride, nitrogen, or a combination thereof. The material of the metal layer can include aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, or a combination thereof, but is not limited thereto.

[0060] After that, a metal interconnect manufacturing process can be performed to form a first interconnect layer 130 on the dielectric layer 120. For example, a stop layer (not shown in the figure) and an intermetal dielectric layer 132 can be sequentially formed on the surface of the dielectric layer 120. One or more photolithography and etching manufacturing processes are performed to remove part of the intermetal dielectric layer 132 and part of the stop layer to form contact holes (not shown in the figure). Then, a conductive material is filled into each contact hole and a planarization manufacturing process such as chemical mechanical polishing is used to form a metal interconnect 134 connecting the underlying contact plug 168 and the third metal structure 66. Subsequently, the above manufacturing process can be repeated and multiple sets of the first interconnect layer 130 composed of the intermetal dielectric layer 132 and the metal interconnect 134 can be formed on the dielectric layer 120 according to the manufacturing process requirements to complete the back-end-of-the-line (BEOL) manufacturing process. The material of the metal interconnect 134 can be the same as that of the third metal structure 66, which will not be elaborated here. Then, the bottom semiconductor layer of the first substrate 110 can be completely removed by chemical mechanical polishing to expose the bottom of the third metal structure 66.

[0061] It is worth noting that the first wafer 10 of the present invention can selectively form a trap rich layer 140 and a supporting substrate 150 on the back side of the first substrate 110. For example, the trap rich layer 140 can be first formed on a supporting substrate 150, and then an oxide layer (not shown) for bonding with the buried oxide layer 112 can be formed on the trap rich layer 140. Then the first substrate 110 is thinned to remove the bottom semiconductor layer of the first substrate 110. Then the thinned first substrate 110 is bonded to the supporting substrate 150 having the trap rich layer 140. The supporting substrate 150 can be, for example, a high-resistance silicon substrate with a very low doping amount. The trap rich layer 140 can be, for example, formed by depositing a high-resistance material on the supporting substrate 150, and the high-resistance material can be a polycrystalline semiconductor material or an amorphous semiconductor material, such as polycrystalline silicon or amorphous silicon. Alternatively, the trap rich layer 140 can be formed by bombarding and destroying the surface of the supporting substrate 150 with high-energy particles using an ion implantation process. The oxide layer may be a surface oxide layer (superficial oxide layer), and the material of the oxide layer may be the same as that of the buried oxide layer 112 to provide better interface performance (interface performance), but is not limited thereto. By providing a high capture layer 140, it is beneficial to reduce nonlinear parasitic capacitance (nonlinear parasitic capacitance) and parasitic surface conduction (parasitic surface conduction), which is beneficial to reduce noise. At this point, the production of the first wafer 10 can be completed. In addition, in other embodiments, the present invention can also directly select an SOI substrate with a high capture layer 140 as the first substrate 110, and then sequentially manufacture the aforementioned first transistor 160, the third metal structure 66, the metal interconnect 134 and other structures thereon.

[0062] Then, if Figure 2 As shown, a second wafer 20 is provided. The second wafer 20 includes a second substrate 210 and a second interconnection layer 230, and the second interconnection layer 230 is disposed on the semiconductor layer 214 of the second substrate 210. For example, the second wafer 20 can be manufactured in the following manner. First, a second substrate 210 can be provided. The second substrate 210 is, for example, a silicon-coated insulating substrate, which mainly includes a semiconductor layer 216 (also referred to as a bottom semiconductor layer), a buried oxide layer 212 disposed on the semiconductor layer 216, and another semiconductor layer 214 (also referred to as a top semiconductor layer) disposed on the buried oxide layer 212. For details about the second substrate 210, reference can be made to the relevant description of the first substrate 110, which will not be repeated here.

[0063] Next, a part of the semiconductor layer 214 can be removed to form a shallow trench isolation structure 80 surrounding each active region (not otherwise labeled), and the active regions surrounded by the shallow trench isolation structure 80 can be used to dispose active elements, such as the second transistor 260.

[0064] Next, the second transistor 260 and the diode 70 are formed in the second substrate 210. In this embodiment, the second transistor 260 is taken as an example of an NMOS transistor for illustration, but the present invention is not limited thereto. The second transistor 260 includes a well region 264 disposed in the semiconductor layer 214 surrounded by the shallow trench isolation structure 80, a gate structure 262 disposed on the semiconductor layer 214 surrounded by the shallow trench isolation structure 80 and above the well region 264, spacer walls 263 disposed on the sidewalls of the gate structure 262, and two source / drain regions 266 disposed in the semiconductor layer 214 on both sides of the spacer walls 263. Details of the second transistor 260 can refer to the related description of the first transistor 160 and will not be elaborated herein. The diode 70 includes an N-type doped region 710 and a P-type doped region 720, and the doping concentration of the P-type doped region 720 can be higher than that of the N-type doped region 710. The N-type doped region 710 can be doped with an N-type dopant, such as arsenic, phosphorus, etc., and the P-type doped region 720 can be doped with a P-type dopant, such as boron, indium, etc.

[0065] Next, a dielectric layer 220 is formed on the second substrate 210 to cover the second transistor 260. A contact hole etch stop layer (not shown) can be selectively formed on the second substrate 210 to cover the second transistor 260 before forming the dielectric layer 220. Next, part of the dielectric layer 220 and part of the contact hole etch stop layer can be removed by semiconductor manufacturing processes such as photolithography and etching to form a plurality of contact holes 267 exposing the gate structure 262 of the second transistor 260, the two source / drain regions 266, and the P-type doped region 720 of the diode 70. Next, a contact plug manufacturing process is performed to form a plurality of contact plugs 268 in the dielectric layer 220 to electrically connect the gate structure 262, the two source / drain regions 266, and the P-type doped region 720 of the diode 70, wherein the upper surface of the contact plug 268 can be flush with the upper surface of the dielectric layer 220. Details of the dielectric layer 220 and the contact plug 268 can refer to the related description of the dielectric layer 120 and the contact plug 168 and will not be elaborated herein.

[0066] Afterwards, a metal interconnection manufacturing process may be performed to form a second interconnection layer 230 on the dielectric layer 220. For example, a stop layer (not shown) and an intermetallic dielectric layer 232 may be sequentially formed on the surface of the dielectric layer 220, and one or more photolithography and etching processes may be performed to remove a portion of the intermetallic dielectric layer 232 and a portion of the stop layer to form contact holes (not shown), and then a conductive material is filled into each contact hole and a planarization process such as chemical mechanical polishing is performed to form a metal interconnection 234 to connect the contact plug 268 below and the first metal structure 62 formed subsequently (see Figure 5 ), the second metal structure 64 (see Figure 5 ) and the fourth metal structure 68 (see Figure 5 ). For details about the inter-metal dielectric layer 232 and the metal interconnect 234, reference may be made to the related descriptions of the inter-metal dielectric layer 132 and the metal interconnect 134, which will not be described in detail herein. At this point, the manufacturing of the second wafer 20 is completed.

[0067] Then, if Figure 3 As shown, the second wafer 20 is flipped over to face its back side upwards, and then a bonding process is performed, such as hybrid bonding technology, to make the metal interconnects 134, 234 embedded in the intermetallic dielectric layers 132, 232 face each other and contact each other, and then a heat treatment is performed to bond the second interconnect layer 230 of the second wafer 20 and the first interconnect layer 130 of the first wafer 10 by utilizing atomic diffusion of the metal in the solid state. Figure 4 As shown, a thinning process is performed, such as chemical mechanical polishing to completely remove the semiconductor layer 216 of the second substrate 210. However, during the process of removing the semiconductor layer 216, charges (not shown) may be generated and accumulated in the buried oxide layer 212. The charges accumulated in the buried oxide layer 212 may affect the electrical performance of the second transistor 260, for example, may cause the breakdown voltage of the second transistor 260 to decrease.

[0068] Then, if Figure 5As shown, a dielectric layer 30 is formed on the buried oxide layer 212 of the second substrate 210. The material of the dielectric layer 30 may include, for example, silicon nitride, but is not limited thereto. Then, contact holes 61, 63, and 67 are sequentially formed using semiconductor manufacturing processes such as photolithography and etching. Next, a contact plug manufacturing process is performed. For example, a conductive layer (not shown in the figure) may be first formed to fill the contact holes 61, 63, and 67, and then a planarization manufacturing process, such as chemical mechanical polishing, is used to remove a part of the conductive layer to form a first metal structure 62 penetrating the dielectric layer 30, and a second metal structure 64 and a fourth metal structure 68 penetrating the dielectric layer 30, the buried oxide layer 212 of the second substrate 210, the semiconductor layer 214, and the dielectric layer 220. That is, the second metal structure 64 and the fourth metal structure 68 are through-silicon vias. Details of the first metal structure 62, the second metal structure 64, and the fourth metal structure 68 can be referred to the related description of the third metal structure 66, and will not be elaborated here.

[0069] Next, as Figure 6 shown, a first metal pad 410 and a second metal pad 420 are formed on the dielectric layer 30 and used as bonding pads for external output / input of the entire three-dimensional integrated circuit (3D IC). For example, a metal material layer (not shown in the figure) may be first formed on the dielectric layer 30, and then a part of the metal material layer is removed using semiconductor manufacturing processes such as photolithography and etching to form the first metal pad 410 and the second metal pad 420 arranged separately. The materials of the first metal pad 410 and the second metal pad 420 may include conductive metal materials, such as aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, or a combination thereof, but are not limited thereto.

[0070] Next, as Figure 7As shown, a protective layer 50 is formed on the dielectric layer 30, the first metal pad 410 and the second metal pad 420, wherein the protective layer 50 partially covers the first metal pad 410 and the second metal pad 420. Here, the protective layer 50 includes a first protective layer 510 and a second protective layer 520 from bottom to top. For example, a first protective material layer (not shown) and a second protective material layer (not shown) may be formed on the dielectric layer 30, the first metal pad 410 and the second metal pad 420 first, and then a part of the first protective material layer and the second protective material layer may be removed by photolithography, etching or other manufacturing processes to form two holes 530, thereby completing the manufacturing of the first protective layer 510 and the second protective layer 520, and the two holes 530 of the protective layer 50 expose the first metal pad 410 and the second metal pad 420 respectively. The materials of the first protective layer 510 and the second protective layer 520 may include dielectric materials, and the dielectric materials of the first protective layer 510 and the second protective layer 520 may each independently include nitride, plasma enhanced oxide, or a combination thereof. According to one embodiment, the dielectric material of the first protective layer 510 includes plasma enhanced oxide, and the dielectric material of the second protective layer 520 includes nitride. However, the present invention is not limited thereto, and the number of layers and materials of the protective layer 50 may be adjusted according to actual needs. At this point, the manufacturing of the semiconductor device 1 can be completed.

[0071] Please refer to Figure 7 , which is a schematic cross-sectional view of a semiconductor device 1 according to an embodiment of the present invention. The semiconductor device 1 includes a first wafer 10, a second wafer 20, a dielectric layer 30, and a first metal structure 62, and optionally includes a first metal pad 410, a second metal pad 420, a protective layer 50, a second metal structure 64, and a fourth metal structure 68. The first wafer 10 and the second wafer 20 are bonded via a bonding surface S1, the dielectric layer 30 is disposed on the second wafer 20, the first metal pad 410 and the second metal pad 420 are disposed on the dielectric layer 30, and the protective layer 50 is disposed on the dielectric layer 30, the first metal pad 410, and the second metal pad 420, and the protective layer 50 partially covers the first metal pad 410 and the second metal pad 420.

[0072] The first wafer 10 includes a first substrate 110 and a first interconnect layer 130 disposed on the first substrate 110. The second wafer 20 includes a second substrate 210 and a second interconnect layer 230. The second substrate 210 includes a buried oxide layer 212 and a semiconductor layer 214 disposed on the buried oxide layer 212, and the second interconnect layer 230 is disposed on the semiconductor layer 214, wherein the second interconnect layer 230 is bonded to the first interconnect layer 130. A dielectric layer 30 is disposed on the buried oxide layer 212. A first metal structure 62 is disposed through the dielectric layer 30, wherein one end 621 of the first metal structure 62 contacts the buried oxide layer 212, and the buried oxide layer 212 is grounded through the first metal structure 62. Here, one end 621 of the first metal structure 62 contacts the buried oxide layer 212, and the other end 622 is connected to the first metal pad 410, that is, the buried oxide layer 212 can be grounded through the first metal structure 62 and the first metal pad 410.

[0073] As described above, charge may accumulate in the buried oxide layer 212 during the process of removing the semiconductor layer 216. The present invention can form at least one charge release path through the first metal structure 62 and the first metal pad 410 to transfer the charge accumulated in the buried oxide layer 212 to the outside, which is beneficial to improving the electrical performance of the second transistor 260. For example, the breakdown voltage drop of the second transistor 260 can be avoided.

[0074] Specifically, the first wafer 10 may include, from bottom to top, a support substrate 150, a high capture layer 140, a first substrate 110, a dielectric layer 120, and a first interconnect layer 130, and may further include a first transistor 160 and a third metal structure 66. The first substrate 110 includes a buried oxide layer 112 and a semiconductor layer 114. The semiconductor layer 114 is disposed on the buried oxide layer 112. The first interconnect layer 130 is disposed on the semiconductor layer 114 of the first substrate 110. Here, the first interconnect layer 130 is disposed on the semiconductor layer 114 through the dielectric layer 120. The high capture layer 140 is disposed on the buried oxide layer 112 of the first substrate 110. The first transistor 160 is disposed in the semiconductor layer 114. The first transistor 160 includes a well region 164 and two source / drain regions 166 disposed in the semiconductor layer 114, a gate structure 162 disposed on the semiconductor layer 114, and spacer walls 163 disposed on the sidewalls of the gate structure 162. The gate structure 162 and the two source / drain regions 166 are electrically connected to a metal interconnect 134 in the first interconnect layer 130 through a contact plug 168. The third metal structure 66 penetrates through the dielectric layer 120, the semiconductor layer 114, and the buried oxide layer 112 of the first substrate 110. One end 661 of the third metal structure 66 contacts the high capture layer 140, and the other end 662 of the third metal structure 66 is electrically connected to a second metal pad 420. Here, the other end 662 of the third metal structure 66 is electrically connected to the second metal pad 420 through the metal interconnect 134 in the first interconnect layer 130, the metal interconnect 234 in the second interconnect layer 230, and a fourth metal structure 68.

[0075] The second wafer 20 may include, from top to bottom, a second substrate 210, a dielectric layer 220, and a second interconnect layer 230, and may further include a second transistor 260 and a diode 70. The second substrate 210 includes a buried oxide layer 212 and a semiconductor layer 214. The semiconductor layer 214 is disposed on the buried oxide layer 212. The second interconnect layer 230 is disposed on the semiconductor layer 214 of the second substrate 210. Here, the second interconnect layer 230 is disposed on the semiconductor layer 214 through the dielectric layer 220. The second transistor 260 and the diode 70 are disposed in the semiconductor layer 214. The second transistor 260 includes a well region 264 and two source / drain regions 266 disposed in the semiconductor layer 214, a gate structure 262 disposed on the semiconductor layer 214, and spacer walls 263 disposed on the sidewalls of the gate structure 262. The diode 70 includes an N-type doped region 710 and a P-type doped region 720 disposed in the semiconductor layer 214, and the diode 70 is in direct contact with the buried oxide layer 212. The gate structure 262, the two source / drain regions 266, and the P-type doped region 720 are electrically connected to a metal interconnect 234 in the second interconnect layer 230 through a contact plug 268.

[0076] The second interconnect layer 230 includes a metal layer 2341, which is a part of the metal interconnects 234 in the second interconnect layer 230 and is closest to the second substrate 210. One of the two source / drain regions 266 (here, the source / drain region 266 on the right side) is electrically connected to the first metal pad 410 through a contact plug 268, the metal layer 2341, and a second metal structure 64. One end 641 of the second metal structure 64 is connected to the metal layer 2341, and the other end 642 of the second metal structure 64 is connected to the first metal pad 410. The diode 70 is electrically connected to the first metal pad 410. Here, the diode 70 is electrically connected to the first metal pad 410 through the contact plug 268, the metal layer 2341, and the second metal structure 64. Thus, the diode 70, the contact plug 268, the metal layer 2341, the second metal structure 64, and the first metal pad 410 can form a charge release path, and the charge accumulated in the buried oxide layer 212 can be transmitted to the outside, which is beneficial to maintaining the electrical performance of the second transistor 260. For example, the breakdown voltage drop of the second transistor 260 can be avoided. Further, the diode 70 can use the existing conduction path of the second transistor 260 (i.e., the metal layer 2341, the second metal structure 64, and the first metal pad 410) to transmit the charge accumulated in the buried oxide layer 212 to the outside, without the need to fabricate an additional new conduction path, which is beneficial to streamlining the manufacturing process.

[0077] Compared with the prior art, the semiconductor device of the present invention includes a first metal structure. One end of the first metal structure is in contact with the buried oxide layer, enabling the buried oxide layer to be grounded through the first metal structure, which is beneficial to forming a charge release path and transmitting the charge accumulated in the buried oxide layer during the manufacturing process to the outside, and is beneficial to improving the electrical performance of the semiconductor device. The semiconductor device may further include a diode. The diode is in direct contact with the buried oxide layer, enabling the buried oxide layer to be grounded through the diode, providing another charge release path for the charge accumulated in the buried oxide layer to be transmitted to the outside, and further improving the electrical performance of the semiconductor device.

[0078] The above are only the preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims

1. A semiconductor device, comprising: A first wafer, comprising: A first substrate; and A first interconnect layer disposed on the first substrate; A second wafer, comprising: A second substrate, comprising a buried oxide layer and a semiconductor layer disposed on the buried oxide layer ； And A second interconnect layer, disposed on the semiconductor layer, wherein the second interconnect layer is bonded to the first interconnect layer; A dielectric layer, disposed on the buried oxide layer; And A first metal structure, penetrating through and disposed in the dielectric layer, wherein one end of the first metal structure is in contact with the buried oxide layer, and the buried oxide layer is grounded through the first metal structure.

2. The semiconductor device according to claim 1, further comprising: A first metal pad, disposed on the dielectric layer; and A protective layer, disposed on the dielectric layer and the first metal pad, wherein the protective layer partially covers the first metal pad, and the other end of the first metal structure is connected to the first metal pad.

3. The semiconductor device according to claim 2, wherein the second wafer further comprises a diode disposed in the semiconductor layer, and the diode is electrically connected to the first metal pad.

4. The semiconductor device according to claim 3, wherein the second interconnect layer comprises a metal layer, and the semiconductor device further comprises a second metal structure penetrating through and disposed in the second substrate and the dielectric layer, one end of the second metal structure is connected to the metal layer, the other end of the second metal structure is connected to the first metal pad, and the diode is electrically connected to the first metal pad through the metal layer and the second metal structure.

5. The semiconductor device according to claim 4, wherein the second wafer further comprises a transistor disposed in the semiconductor layer, the transistor comprises two source / drain regions, and one of the two source / drain regions is electrically connected to the first metal pad through the metal layer and the second metal structure.

6. The semiconductor device according to claim 1, wherein the protective layer comprises a dielectric material.

7. The semiconductor device according to claim 6, wherein the dielectric material comprises nitride, plasma enhanced oxide, or a combination thereof.

8. The semiconductor device according to claim 1, wherein the first substrate comprises a buried oxide layer and a semiconductor layer disposed on the buried oxide layer, and the first interconnect layer is disposed on the semiconductor layer of the first substrate.

9. The semiconductor device according to claim 8, wherein the first wafer further comprises a high capture layer disposed on the buried oxide layer of the first substrate.

10. The semiconductor device according to claim 9, further comprising: A second metal pad, disposed on the dielectric layer, wherein the protective layer partially covers the second metal pad; and A third metal structure penetrating through and disposed in the buried oxide layer and the semiconductor layer of the first substrate, wherein one end of the third metal structure is in contact with the high capture layer, and the other end of the third metal structure is electrically connected to the second metal pad.

11. A method of manufacturing a semiconductor device, comprising: Providing a first wafer, wherein the first wafer comprises a first substrate and a first interconnect layer disposed on the first substrate; Provide a second wafer, wherein the second wafer includes a second substrate and a second interconnect layer, the second substrate includes a buried oxide layer and a semiconductor layer disposed on the buried oxide layer, and the second interconnect layer is disposed on the semiconductor layer; Bond the second interconnect layer to the first interconnect layer; Form a dielectric layer on the buried oxide layer; And Form a first metal structure penetrating through the dielectric layer, wherein one end of the first metal structure contacts the buried oxide layer, and the buried oxide layer is grounded through the first metal structure.

12. The method according to claim 11, further comprising: Form a first metal pad on the dielectric layer; and Form a protective layer on the dielectric layer and the first metal pad, wherein the protective layer partially covers the first metal pad, and the other end of the first metal structure is connected to the first metal pad.

13. The method according to claim 12, wherein the second wafer further includes a diode disposed in the semiconductor layer, and the diode is electrically connected to the first metal pad.

14. The method according to claim 13, wherein the second interconnect layer includes a metal layer, and before forming the first metal pad, the method further comprises: Form a second metal structure penetrating through the second substrate and the dielectric layer, wherein one end of the second metal structure is connected to the metal layer, the other end of the second metal structure is connected to the first metal pad, and the diode is electrically connected to the first metal pad through the metal layer and the second metal structure.

15. The method according to claim 14, wherein the second wafer further includes a transistor disposed in the semiconductor layer, the transistor includes two source / drain regions, and one of the two source / drain regions is electrically connected to the first metal pad through the metal layer and the second metal structure.

16. The method according to claim 11, wherein the protective layer includes a dielectric material.

17. The method according to claim 16, wherein the dielectric material includes nitride, plasma enhanced oxide, or a combination thereof.

18. The method according to claim 11, wherein the first substrate includes a buried oxide layer and a semiconductor layer disposed on the buried oxide layer, and the first interconnect layer is disposed on the semiconductor layer of the first substrate.

19. The method according to claim 18, wherein the first wafer further includes: A high capture layer disposed on the buried oxide layer of the first substrate.

20. The method according to claim 19, further comprising: Form a second metal pad on the dielectric layer, wherein the protective layer partially covers the second metal pad; and Form a third metal structure penetrating through the buried oxide layer and the semiconductor layer of the first substrate, wherein one end of the third metal structure contacts the high capture layer, and the other end of the third metal structure is electrically connected to the second metal pad.

Images