Semiconductor structure

Abstract

The embodiment of the invention provides a semiconductor structure, and the structure comprises heterojunction bipolar transistors which are arranged in parallel and are located on a substrate; the landing structure is located at the edge of the heterojunction bipolar transistor on the substrate; a wiring over the heterojunction bipolar transistor and connected to the landing structure; the insulating layer is positioned on the landing structure and is provided with a guide hole; and a bump over a top surface of the insulating layer and connected to the wiring through the via, a sidewall of the landing structure having a recess in a top view.

Description

Technical Field

[0001] This application relates to the field of semiconductors, specifically to a semiconductor structure, particularly to a bump structure of a heterojunction bipolar transistor. Background Art

[0002] A heterojunction bipolar transistor (HBT) is a bipolar junction transistor of two different materials with different band gaps. Heterojunction bipolar transistors are widely used in the industry due to many advantages, including low base resistance, high cut-off frequency, high efficiency, more design flexibility, and low cost.

[0003] In the packaging process of heterojunction bipolar transistors, the formation of the bump structure may affect the reliability. In addition, the semiconductor structure may occupy too much space.

[0004] Although existing heterojunction bipolar transistors are sufficient for their original purposes, they are not satisfactory in all aspects and need to be improved, especially in the packaging process of heterojunction bipolar transistors. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor structure, including: heterojunction bipolar transistors, arranged in parallel and located on a substrate; landing structures, located at the edges of the heterojunction bipolar transistors on the substrate; wirings, located above the heterojunction bipolar transistors and connected to the landing structures; insulating layers, located above the landing structures and having vias; bumps, located above the top surfaces of the insulating layers and connected to the wirings through the vias. In a top view, the side walls of the landing structures have recesses.

[0006] Embodiments of the present invention also provide a semiconductor structure, including: heterojunction bipolar transistors, located on a substrate; wirings, located above the heterojunction bipolar transistors; landing structures, located beside the heterojunction bipolar transistors on the substrate; bumps, located above the wirings and the landing structures; insulating layers, covering the side walls and part of the top surfaces of the landing structures. In a top view, the landing structures have curved surfaces.

[0007] Embodiments of the present invention further provide a semiconductor structure, including: heterojunction bipolar transistors, located on a substrate; a first dielectric layer, located above the heterojunction bipolar transistors and the substrate; landing structures, located above the first dielectric layer; insulating layers, located between the heterojunction bipolar transistors on the substrate and the landing structures; wirings, located above the heterojunction bipolar transistors; and bumps, located above the wirings and the landing structures. The bottom surfaces of the landing structures are lower than the bottom surfaces of the wirings. Brief Description of the Drawings

[0008] The embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that various feature components are not drawn to scale and are only used for illustration. In fact, the dimensions of the components may be enlarged or reduced to clearly show the technical features of the embodiments of the present invention.

[0009] Figure 1 FIG. is a top view of a semiconductor structure according to some embodiments.

[0010] Figure 1A FIG. is a cross-sectional view of a semiconductor structure according to some embodiments.

[0011] Figure 2 FIG. is an enlarged top view of a semiconductor structure according to some embodiments.

[0012] Figure 2A FIG. is an enlarged cross-sectional view of a semiconductor structure according to some embodiments.

[0013] Figure 3 FIG. is an enlarged top view of a semiconductor structure according to some embodiments.

[0014] Figure 4 FIG. is an enlarged top view of a semiconductor structure according to some embodiments.

[0015] Figure 5 FIG. is an enlarged top view of a semiconductor structure according to some embodiments.

[0016] Figure 6 FIG. is an enlarged top view of a semiconductor structure according to some embodiments.

[0017] Figure 7 FIG. is an enlarged top view of a semiconductor structure according to some embodiments.

[0018] Figure 8 FIG. is an enlarged top view of a semiconductor structure according to some embodiments.

[0019] Figure 9 FIG. is an enlarged top view of a semiconductor structure according to some embodiments.

[0020] Figure 10 FIG. is an enlarged top view of a semiconductor structure according to some embodiments.

[0021] Figure 11 FIG. is an enlarged top view of a semiconductor structure according to some embodiments.

[0022] Figure 12 FIG. is an enlarged top view of a semiconductor structure according to some embodiments.

[0023] Figure 13Shows an enlarged cross-sectional view of a semiconductor structure according to some embodiments.

[0024] Figure 14 Shows an enlarged cross-sectional view of a semiconductor structure according to some embodiments.

[0025] Figure 15 Shows an enlarged cross-sectional view of a semiconductor structure according to some embodiments.

[0026] [Symbol Explanation]

[0027] 10a, 10b, 10c, 10d, 10e, 10f, 10g, 10h, 10i, 10j, 10k, 10l: Semiconductor structure

[0028] 100: Heterojunction bipolar transistor

[0029] 102: Substrate

[0030] 104a: First dielectric layer

[0031] 104b: Second dielectric layer

[0032] 105: Opening

[0033] 106: Insulating layer

[0034] 106a: First insulating layer

[0035] 106b: Second insulating layer

[0036] 108: Conductive layer

[0037] 108a: First conductive layer

[0038] 108b: Second conductive layer

[0039] 110: Landing structure

[0040] 110s: Sidewall

[0041] 110i: Inner width

[0042] 110o: Outer width

[0043] 110e: Extension structure

[0044] 111: Wiring

[0045] 112: Bump

[0046] 112a: Connection part

[0047] 112as: Sidewall

[0048] A - A’: Line

[0049] D: Distance

[0050] Da: Distance

[0051] Db: Distance Detailed Implementation Manner

[0052] The following disclosure provides many different embodiments or examples for implementing different features of the present case. The following disclosure describes specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not used for limitation. For example, if an embodiment of the present invention describes that a first feature component is formed on or above a second feature component, it means that it may include an embodiment in which the above-mentioned first feature component and the above-mentioned second feature component are in direct contact, and it may also include an embodiment in which additional feature components are formed between the above-mentioned first feature component and the above-mentioned second feature component, so that the above-mentioned first feature component and the second feature component may not be in direct contact. In addition, repeated reference numerals or labels may be used in different embodiments. These repetitions are only for simply and clearly describing the embodiments of the present invention and do not represent a specific relationship between the different embodiments and / or structures discussed.

[0053] In addition, spatially relative terms may be used, such as "below", "beneath", "lower", "above", "higher", and similar terms. These spatially relative terms are for facilitating the description of the relationship between one or some elements or feature components and another or some other elements or feature components in the drawings. These spatially relative terms include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted according to the orientation after turning.

[0054] Herein, the terms "about", "approximately", "substantially" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or 3%, or 2%, or 1%, or 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, even without specifically stating "about", "approximately", "substantially", the meanings of "about", "approximately", "substantially" can still be implied.

[0055] Although the steps in some of the described embodiments are carried out in a specific order, these steps can also be carried out in other logical orders. In different embodiments, some of the described steps can be replaced or omitted, and some other operations can also be carried out before, during, and / or after the steps described in the embodiments of the present invention. Other features can be added to the semiconductor structures in the embodiments of the present invention. In different embodiments, some features can be replaced or omitted.

[0056] A semiconductor device structure may include various active devices. For example, a semiconductor device structure may include a heterojunction bipolar transistor, and a semiconductor device structure may also include a high electron mobility transistor, other suitable devices, and combinations thereof.

[0057] Embodiments of the present invention provide a heterojunction bipolar transistor. By forming a landing structure having a recess and / or a curved surface in a top view at an edge of the heterojunction bipolar transistor, reliability can be improved and device area can be minimized.

[0058] According to some embodiments, Figure 1 A top view of a semiconductor structure 10a is shown. Figure 1A FIG. 10 is a cross-sectional view of a semiconductor structure 10a according to some embodiments. Figure 1A Shown along Figure 1 a cross-section taken along line A-A'.

[0059] According to some embodiments, as Figure 1 and Figure 1A shown, a heterojunction bipolar transistor 100 is formed over a substrate 102. The substrate 102 may be a semiconductor substrate. In addition, the substrate 102 may include a III-V semiconductor, such as GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, or combinations thereof. In some embodiments, the substrate 102 includes undoped GaAs.

[0060] Each heterojunction bipolar transistor 100 includes a collector layer formed on the substrate 102, a base layer formed on the collector layer, and an emitter layer (not shown) formed on the base layer.

[0061] The collector layer may include a III-V semiconductor having a first conductivity type. The collector layer may include a III-V semiconductor such as GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, GaSb, InGaP, InGaAsP, or combinations thereof. In some embodiments, the collector layer is an n-type GaAs layer. The collector layer may be formed using molecular beam epitaxy, metalorganic chemical vapor deposition, chemical vapor deposition, hydride vapor phase epitaxy, another suitable method, or combinations thereof.

[0062] The base layer includes a group III-V semiconductor having a second conductivity type. The base layer may include group III-V semiconductors such as GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, GaSb, or a combination of the foregoing. In some embodiments, the base layer may be a p-type GaAs layer highly doped with C, Mg, Zn, Ca, Be, Sr, Ba, and Ra. The base layer may be formed using molecular beam epitaxy, metalorganic chemical vapor deposition, chemical vapor deposition, hydride vapor phase epitaxy, another suitable method, or a combination of the foregoing.

[0063] The emitter layer includes a group III-V semiconductor having a first conductivity type. The emitter layer may include group III-V semiconductors such as GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, or a combination of the foregoing. The emitter layer may be an n-type InGaP layer. The emitter layer may be an AlGaAs layer having a wide bandgap. In some embodiments, the emitter layer is an n-type AlGaAs layer. The emitter layer may be a multilayer structure. The material of the emitter layer and the material of the base layer are different materials having different bandgaps. Thus, a heterojunction can be formed at the interface between the emitter layer and the base layer. The emitter layer may be formed using molecular beam epitaxy, metalorganic chemical vapor deposition, chemical vapor deposition, hydride vapor phase epitaxy, another suitable method, or a combination of the foregoing.

[0064] Next, according to some embodiments, as Figure 1A shown, a first dielectric layer 104a is conformally formed over the heterojunction bipolar transistor 100 and the substrate 102. The first dielectric layer 104a may include Si 3 N 4 、SiO 2 、SiO x N y 、one or more other suitable dielectric materials, or a combination of the foregoing. The first dielectric layer 104a may be formed using low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, evaporation, or other suitable methods.

[0065] Next, according to some embodiments, as Figure 1A shown, a first conductive layer 108a is formed over the first dielectric layer 104a. The first conductive layer 108a may include Ti, Al, Au, Pd, Pt, Cu, W, other suitable metals, alloys thereof, or a combination of the foregoing. The first conductive layer 108a may be formed using electroplating, sputtering, resistance heating evaporation, physical vapor deposition, chemical vapor deposition, atomic layer deposition, other suitable methods, or a combination of the foregoing.

[0066] Next, according to some embodiments, as Figure 1AAs shown, a second dielectric layer 104b is formed over the first conductive layer 108a. The processes and materials used to form the second dielectric layer 104b may be the same as or similar to those used to form the first dielectric layer 104a. For the sake of brevity, the details of these processes are not repeated herein.

[0067] It should be noted that the first dielectric layer 104a and the second dielectric layer 104b may be selectively formed. It may be a single dielectric layer or a double dielectric layer.

[0068] Next, an opening is formed to expose the heterojunction bipolar transistor 100. Thereafter, according to some embodiments, such as Figure 1A As shown, a first insulating layer 106a is formed in the opening to cover the heterojunction bipolar transistor 100. In some embodiments, the first insulating layer 106a is formed between the heterojunction bipolar transistors 100. The first insulating layer 106a may include polybenzoxazole (PBO), benzocyclobutene (BCB), polyimide (PI), other polymers or insulating materials, or a combination of the above. The first insulating layer 106a may be formed using metal-organic chemical vapor deposition, chemical vapor deposition, spin coating, another suitable method, or a combination of the above.

[0069] Next, according to some embodiments, such as Figure 1A As shown, an opening 105 is formed in the first insulating layer 106a and the first dielectric layer 104a over the heterojunction bipolar transistor 100. According to some embodiments, such as Figure 1A As shown, a second conductive layer 108b is formed in the opening 105 over the heterojunction bipolar transistor 100 and over the second dielectric layer 104b. In some embodiments, the heterojunction bipolar transistor 100 is electrically connected to the second conductive layer 108b. The process used to form the second conductive layer 108b may be the same as or similar to the process used to form the first conductive layer 108a. For the sake of brevity, the details of these processes are not repeated herein.

[0070] In some embodiments, the second conductive layer 108b and the first conductive layer 108a formed at the edges of the heterojunction bipolar transistor 100 on the substrate 102 are referred to as the landing structure 110. The second conductive layer 108b formed over the heterojunction bipolar transistor 100 may be referred to as the wiring 111. The first conductive layer 108a and the second conductive layer 108b may be referred to as the conductive layer 108. In some embodiments, the first conductive layer 108a and the second conductive layer 108b are separated by the second dielectric layer 104b, but this is not limiting. In some embodiments, the wiring 111 is formed over the heterojunction bipolar transistor 100 and connected to the landing structure 110.

[0071] According to some embodiments, such asFigure 1A As shown, since the second conductive layer 108b is made of the same material, the boundary between the second conductive layer 108b of the wiring 111 and the second conductive layer 108b of the landing structure 110 is shown as a dashed line.

[0072] It should be noted that although the widths of the first conductive layer 108a and the second conductive layer 108b of the landing structure 110 are generally the same, the widths of the first conductive layer 108a and the second conductive layer 108b are not limited thereto. For example, the first conductive layer 108a and the second conductive layer 108b of the landing structure 110 may have different widths.

[0073] In some embodiments, the landing structure 110 is formed on the first dielectric layer 104a and is in direct contact with the first dielectric layer 104a. In some embodiments, the landing structure 110 is laterally spaced from the heterojunction bipolar transistor 100. In some embodiments, the first insulating layer 106a is formed between the heterojunction bipolar transistor 100 and the landing structure 110 on the substrate 102. In some embodiments, the shortest distance between the bottom surface of the landing structure 110 and the substrate 102 is less than the height of the heterojunction bipolar transistor 100. In some embodiments, the bottom surface of the landing structure 110 is lower than the bottom surface of the wiring 111.

[0074] Next, a second insulating layer 106b is formed to surround the landing structure 110 and partially cover the landing structure 110. The process and materials used to form the second insulating layer 106b may be the same as or similar to the process and materials used to form the first insulating layer 106a. For the sake of brevity, the details of these processes are not repeated herein.

[0075] According to some embodiments, as Figure 1A shown, since the second insulating layer 106b and the first insulating layer 106a are made of the same material, the boundary between the second insulating layer 106b and the first insulating layer 106a is shown as a dashed line. The second insulating layer 106b and the first insulating layer 106a may be referred to as the insulating layer 106, or there may be only a single insulating layer 106. In some embodiments, the insulating layer 106 covers the sidewalls and a part of the top surface of the landing structure 110.

[0076] Next, according to some embodiments, as Figure 1A shown, vias may be formed in the second insulating layer 106b on the heterojunction bipolar transistor 100. According to some embodiments, as Figure 1AAs shown, the bump 112 can be formed on the heterojunction bipolar transistor 100 and in the vias above the first insulating layer 106a. In some embodiments, the bump 112 is formed on the wiring 111 and the landing structure 110. Then, the bump 112 is patterned to expose a part of the insulating layer 106. The bump 112 formed in the via on the heterojunction bipolar transistor 100 can be referred to as the connection part 112a. In some embodiments, the bump 112 is formed on the top surface of the insulating layer 106 and is connected to the wiring 111 through the connection part 112a.

[0077] The bump 112 can include Cu, Ti, Al, Au, Pd, Pt, W, other suitable metals, their alloys, or a combination of the above. The bump 112 can be formed using electroplating, sputtering, resistance heating evaporation, physical vapor deposition, chemical vapor deposition, atomic layer deposition, other suitable methods, or a combination of the above. According to some embodiments, as Figure 1A shown, since the bump 112 and the connection part 112a are made of the same material, the boundary of the connection part 112a is shown as a dotted line.

[0078] According to some embodiments, the distance D between the edge of the heterojunction bipolar transistor 100 and the bump 112 is greater than 12 μm. If the distance D is too small, the reliability may deteriorate.

[0079] In some embodiments, the bump 112 extends a distance Db from the sidewall 112as of the connection part 112a, and the sidewall 110s of the landing structure 110 extends a distance Da from the sidewall 112as of the connection part 112a. In some embodiments, the distance Da is greater than or approximately equal to the distance Db. In some embodiments, as Figure 1 shown, in the top view, the edge of the bump 112 is within the landing structure 110. The reliability can be improved.

[0080] According to some embodiments, as Figure 1A shown, the insulating layer 106 is further formed between the landing structure 110 and the bump 112. In some embodiments, a part of the top surface of the insulating layer 106 is covered by the bump 112. In some embodiments, the insulating layer 106 is extended to cover the sidewall 110s of the landing structure 110. In some embodiments, by not exposing the landing structure 110 covered by the bump 112 and the insulating layer 106, the chemicals used in subsequent processes may not damage the landing structure 110.

[0081] However, according to some embodiments, as Figure 1 shown, since the landing structure 110 is only formed at the edge of the heterojunction bipolar transistor 100, in other cross-sectional views, the insulating layer 106 (the first insulating layer 106a) may extend from the sidewall of the heterojunction bipolar transistor 100 to the edge of the substrate 102.

[0082] In some embodiments, bump 112 is in direct contact with wiring 111 and landing structure 110. In some embodiments, the bottom surface of bump 112 on wiring 111 is higher than the bottom surface of bump 112 on landing structure 110. In some embodiments, the top surface of wiring 111 is higher than the top surface of landing structure 110.

[0083] By forming landing structure 110 in insulating layer 106 at the edge of heterojunction bipolar transistor 100, the reliability of heterojunction bipolar transistor 100 can be improved.

[0084] Many variations and / or modifications can be made to the embodiments of the present invention. Figure 2 FIG. is an enlarged top view showing semiconductor structure 10b according to some embodiments. Some processes or elements are the same as or similar to those in the above embodiments, so these processes and elements will not be repeated here. Different from the above embodiments, according to some other embodiments, as Figure 2 shown, in the top view, landing structure 110 has recesses and / or curved surfaces.

[0085] In some embodiments, landing structure 110 has a concave surface on the side close to heterojunction bipolar transistor 100. In some embodiments, in the top view, one of the heterojunction bipolar transistors 100 is formed in the recess of landing structure 110.

[0086] A patterning process can be used to define the shape of landing structure 110. Landing structure 110 having recesses and / or curved surfaces can minimize the area of landing structure 110, which can improve space availability. In addition, the recess can minimize the space and more heterojunction bipolar transistors 100 can be placed.

[0087] In some embodiments, as Figure 2 shown, landing structure 110 has an inner width 110i and an outer width 110o. In some embodiments, as Figure 2 and Figure 2A shown, the inner width 110i is less than the outer width 110o. In some embodiments, the distance Db that bump 112 extends beyond the edge of connecting portion 112a is within the range of the inner width 110i of landing structure 110. In some embodiments, the distance Da that landing structure 110 extends beyond the edge of connecting portion 112a is within the range of the outer width 110o of landing structure 110.

[0088] By forming landing structure 110 in insulating layer 106 at the edge of heterojunction bipolar transistor 100, the reliability of heterojunction bipolar transistor 100 can be improved. In the top view, the sidewall 110s of landing structure 110 has recesses and / or curved surfaces.

[0089] Many variations and / or modifications can be made to the embodiments of the present invention.Figures 3 to 7 An enlarged top view of semiconductor structures 10c - 10g is shown according to some embodiments. Some processes or elements are the same as or similar to those in the above embodiments, so these processes and elements will not be repeated here. Different from the above embodiments, according to some other embodiments, as Figures 3 to 7 shown, in the top view, the shape of the landing structure 110 is different.

[0090] In some embodiments, the landing structure 110 has an inner wall facing the heterojunction bipolar transistor 100 and an outer wall on the opposite side.

[0091] For example, according to some embodiments, as Figure 3 shown, in the top view, the landing structure 110 of the semiconductor structure 10c has a straight outer wall and an angled inner wall. According to some embodiments, as Figure 4 shown, in the top view, the landing structure 110 of the semiconductor structure 10d has a straight outer wall and a curved inner wall. According to some embodiments, as Figure 5 shown, both the outer wall and the inner wall of the landing structure 110 of the semiconductor structure 10e have angles. According to some embodiments, as Figure 6 shown, both the outer wall and the inner wall of the landing structure 110 of the semiconductor structure 10f have curved surfaces. According to some embodiments, as Figure 7 shown, in the top view, the landing structure 110 of the semiconductor structure 10g has a straight inner wall and a curved outer wall.

[0092] The shape of the landing structure 110 can be defined by a patterning process, depending on the design and process requirements. Different shapes of the landing structure 110 can provide design and process flexibility.

[0093] By forming the landing structure 110 in the insulating layer 106 at the edge of the heterojunction bipolar transistor 100, the reliability of the heterojunction bipolar transistor 100 can be improved. In the top view, the sidewall 110s of the landing structure 110 can have different shapes, which can provide more design and process flexibility.

[0094] Many variations and / or modifications can be made to the embodiments of the present invention. Figures 8 to 12 An enlarged top view of semiconductor structures 10h - 10l is shown according to some embodiments. Some processes or elements are the same as or similar to those in the above embodiments, so these processes and elements will not be repeated here. Different from the above embodiments, according to some other embodiments, as Figures 8 to 12 shown, in the top view, the shape of the landing structure 110 is asymmetric.

[0095] According to some embodiments, as Figures 8 to 12As shown, the landing structure 110 of the semiconductor structure 10h-10l has an extending structure 110e extending towards the heterojunction bipolar transistor 100. In some embodiments, the landing structure 110 has an inner wall facing the heterojunction bipolar transistor 100 and an outer wall on the opposite side.

[0096] According to some embodiments, as Figure 8 shown, in a top view, the landing structure 110 of the semiconductor structure 10h has an asymmetric straight inner wall and a curved outer wall. According to some embodiments, as Figure 9 shown, in a top view, the landing structure 110 of the semiconductor structure 10i has a straight outer wall and an asymmetric inner wall with a bevel angle. According to some embodiments, as Figure 10 shown, in a top view, the landing structure 110 of the semiconductor structure 10j has a straight outer wall and a curved asymmetric inner wall. According to some embodiments, as Figure 11 shown, the outer wall and the asymmetric inner wall of the landing structure 110 of the semiconductor structure 10k both have bevel angles. According to some embodiments, as Figure 12 shown, the outer wall and the asymmetric inner wall of the landing structure 110 of the semiconductor structure 10l both have curved surfaces.

[0097] The asymmetric shape of the landing structure 110 can be defined by a patterning process, depending on the design and process requirements. Landing structures 110 with different asymmetric shapes can provide design and process flexibility.

[0098] By forming the landing structure 110 in the insulating layer 106 at the edge of the heterojunction bipolar transistor 100, the reliability of the heterojunction bipolar transistor 100 can be improved. In a top view, the side walls 110s of the landing structure 110 can have different asymmetric shapes, which can provide more design and process flexibility.

[0099] Many variations and / or modifications can be made to the embodiments of the present invention. Figures 13 to 15 Shown is an enlarged cross-sectional view of semiconductor structures 10m-10o according to some embodiments. Some processes or elements are the same as or similar to those in the above embodiments, so these processes and elements will not be repeated here. Different from the above embodiments, according to some other embodiments, as Figures 13 to 15 shown, there can be various arrangements of the dielectric layers 104a and 104b and the conductive layers 108a and 108b.

[0100] Figures 13 to 15 Shown is an enlarged cross-sectional view of the landing structure 110 according to some embodiments.

[0101] For example, according to some embodiments, as Figure 13As shown, a conductive layer 108 of the semiconductor structure 10m is formed on the first dielectric layer 104a. In some embodiments, the conductive layer 108 is in direct contact with the first dielectric layer 104a. The conductive layer 108 is connected to the connecting portion 112a of the bump 112. In some embodiments, the second dielectric layer 104b covers at least a part of the sidewalls and a part of the top surface of the conductive layer 108. In some embodiments, the second dielectric layer 104b is formed on the first dielectric layer 104a, and the landing structure 110 is in direct contact with the second dielectric layer 104b.

[0102] In some embodiments, as Figure 14 As shown, a first conductive layer 108a of the semiconductor structure 10n is formed on the substrate 102 and is covered by the first dielectric layer 104a. The first dielectric layer 104a can be formed between the conductive layers 108a and 108b. The first conductive layer 108a is in direct contact with the substrate 102 and the first dielectric layer 104a. In some embodiments, the first dielectric layer 104a covers the sidewalls and the top surface of the first conductive layer 108a. A second conductive layer 108b is formed on the first dielectric layer 104a and is connected to the connecting portion 112a of the bump 112. In some embodiments, the second dielectric layer 104b covers a part of the sidewalls and the top surface of the second conductive layer 108b. In some embodiments, the landing structure 110 includes multiple conductive layers 108a and 108b and multiple dielectric layers 104a and 104b formed between and on the conductive layers 108a and 108b.

[0103] In some embodiments, as Figure 15 As shown, a conductive layer 108 of the semiconductor structure 10o is formed on the substrate 102 and is covered by the second dielectric layer 104b. The conductive layer 108 is in direct contact with the substrate 102, the first dielectric layer 104a, and the second dielectric layer 104b. The conductive layer 108 is connected to the connecting portion 112a of the bump 112. In some embodiments, the first dielectric layer 104a and the second dielectric layer 104b cover the sidewalls of the conductive layer 108. In some embodiments, the landing structure 110 is in direct contact with the substrate 102.

[0104] By forming the landing structure 110 in the insulating layer 106 at the edge of the heterojunction bipolar transistor 100, the reliability of the heterojunction bipolar transistor 100 can be improved. The landing structure 110 having a concave portion and / or a curved surface can further minimize the area of the landing structure 110, which can improve the space availability. The conductive layer 108 and the dielectric layers 104a and 104b may have different arrangements depending on the process requirements.

[0105] As described above, in the embodiments of the present invention, a landing structure is formed on the substrate at the edge of the heterojunction bipolar transistor. The reliability can be improved. In the top view, by adjusting the shape of the landing structure, the area can be saved, and more flexibility in the process and design can be provided.

[0106] It should be noted that although some benefits and effects are described in the above embodiments, not all embodiments need to achieve all the benefits and effects.

[0107] The foregoing text outlines the characteristic components of many embodiments, enabling those skilled in the art to better understand the embodiments of the present invention from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not depart from the inventive spirit and scope of the embodiments of the present invention. Various changes, substitutions, or modifications can be made to the embodiments of the present invention without departing from the inventive spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims. Additionally, although the present invention has been disclosed above in several preferred embodiments, it is not intended to limit the present invention, and not all advantages have been detailed herein.

Claims

1. A semiconductor structure, characterized in that: include: A plurality of heterojunction bipolar transistors are arranged in parallel and located on a substrate; a landing structure located at an edge of the heterojunction bipolar transistor on the substrate; a wiring line located on the heterojunction bipolar transistor and connected to the landing structure; an insulating layer, located on the landing structure and having a guide hole; and a bump, located on the top surface of the insulating layer and connected to the wiring through the guide hole, In a top view, a side wall of the landing structure has a recess.

2. The semiconductor structure according to claim 1, characterized in that: The insulating layer extends to cover a side wall of the landing structure.

3. The semiconductor structure according to claim 1, characterized in that: Also includes: A first dielectric layer is located on the substrate and covers the heterojunction bipolar transistor.

4. The semiconductor structure according to claim 3, characterized in that: The landing structure is located on the first dielectric layer and contacts the first dielectric layer.

5. The semiconductor structure according to claim 1, characterized in that: The landing structure includes a plurality of metal layers and a plurality of dielectric layers between the metal layers.

6. The semiconductor structure according to claim 5, characterized in that: The dielectric layer covers a portion of a side wall of the metal layer.

7. The semiconductor structure according to claim 1, characterized in that: In the top view, one of the heterojunction bipolar transistors is located in the recess.

8. A semiconductor structure, characterized in that: include: A plurality of heterojunction bipolar transistors are disposed on a substrate; a wiring located on the heterojunction bipolar transistor; a landing structure located next to the heterojunction bipolar transistor on the substrate; a bump, located on the wiring and the landing structure; as well as an insulating layer covering a side wall and a portion of the top surface of the landing structure, In the top view, the landing structure has a curved surface.

9. The semiconductor structure according to claim 8, characterized in that: The landing structure is laterally spaced from the heterojunction bipolar transistor.

10. The semiconductor structure according to claim 8, characterized in that The insulating layer includes polybenzoxazole.

11. The semiconductor structure according to claim 8, characterized in that: A shortest distance between a bottom surface of the landing structure and the substrate is smaller than a height of the heterojunction bipolar transistor.

12. The semiconductor structure according to claim 8, characterized in that The heterojunction bipolar transistor comprises: a collector layer, located on the substrate; a base layer, located on the collector layer; and An emitter layer is located on the base layer.

13. The semiconductor structure according to claim 8, characterized in that The bump is in direct contact with the wiring and the landing structure, A bottom surface of the bump on the wiring is higher than the bottom surface of the bump on the landing structure.

14. A semiconductor structure, characterized in that: include: a plurality of heterojunction bipolar transistors disposed on the substrate; a first dielectric layer, located on the heterojunction bipolar transistor and the substrate; a landing structure located on the first dielectric layer; an insulating layer located between the heterojunction bipolar transistor and the landing structure on the substrate; a wiring located on the heterojunction bipolar transistor; as well as a bump, located on the wiring and the landing structure, A bottom surface of the landing structure is lower than a bottom surface of the wiring.

15. The semiconductor structure according to claim 14, characterized in that: A portion of a top surface of the insulating layer is covered by the bump.

16. The semiconductor structure according to claim 14, characterized in that Also includes: a second dielectric layer, located on the first dielectric layer, The landing structure is in direct contact with the second dielectric layer.

17. The semiconductor structure according to claim 14, characterized in that The landing structure includes multiple metal layers.

18. The semiconductor structure according to claim 14, characterized in that The landing structure is in direct contact with the substrate.

19. The semiconductor structure according to claim 14, characterized in that The landing structure is in direct contact with the first dielectric layer.

20. The semiconductor structure according to claim 14, wherein: The insulating layer is further located between the landing structure and the bump.

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