Slot configuration die-to-package balun coupler

Abstract

Disclosed is a packaged semiconductor device, comprising: a semiconductor die comprising an MMIC, the MMIC having a differential output; a package substrate including a first metal layer, a second metal layer, and a third metal layer, and electrically connected to the semiconductor die through a plurality of pillars between the semiconductor die and the first metal layer, where the first metal layer and the third metal layer include a ground plane, the second metal layer between the first metal layer and the second metal layer comprises a single-ended strip line; wherein the differential output is galvanically connected to the first metal layer through a pair of struts aligned along a first axis; wherein the packaged semiconductor device comprises a balun coupler between the differential output and the single-ended stripline aligned along a second axis; wherein the balun coupler comprises an opening in the first metal layer, the opening comprising two arms extending in a first direction parallel to the second axis.

Description

Technical Field

[0001] The present disclosure relates to a packaged millimeter or microwave frequency semiconductor device having a signal coupler between a semiconductor die and a package substrate. Background Art

[0002] A high-performance millimeter-wave (“mm-wave”) or microwave interface is crucial for maximizing the performance of a monolithic microwave integrated circuit (MMIC). A cost-effective and performance-driven packaging technology for connecting MMIC I / O to a PCB can be achieved by using a ball grid array-based (BGA) packaging structure. Examples of such packages are an embedded wafer-level ball grid array (eWLB), a flip chip chip-scale package (FCCSP), and a flip chip ball grid array (FCBGA).

[0003] A current-carrying connection from a silicon die (MMIC) to a PCB board is then obtained, and the current-carrying connection includes two intermediate transitions: First is the die-to-package transition, which connects the die to the package laminated metal and dielectric layers, or connects the die to a metallization layer on top of the dielectric layer. A differential implementation of the silicon circuitry is generally preferred because this reduces the sensitivity of the active circuitry to external (common-mode) signals present, for example, on PCB traces. And thus, the transition from the die to the package will also be differential. The second transition is the package-to-PCB interface, which connects the package to the PCB using a (solder ball) ball grid array. This interface can be designed to be differential or single-ended. Generally, on a PCB, it is usually preferred to use single-ended signals, such as for a single-ended antenna feed, and since the routing of a single-ended transmission line can be more easily achieved than that of a balanced differential transmission line.

[0004] In all such implementations where all mm-wave interfaces are differential at the die-to-package and package-to-PCB interfaces, an additional function of converting a balanced signal to a single-ended (unbalanced) signal must be added on the PCB. This is commonly referred to as the BALUN function.

[0005] Recent efforts to reduce PCB interconnect losses have given rise to the in-package emitter concept, particularly in the field of millimeter-wave automotive radar. In this concept, an mm-wave signal is directly emitted from the package into a low-loss air-filled waveguide using, for example, a patch antenna; this can avoid using PCB interconnects.

[0006] As mentioned, a mm-wave interface with differential is typically required. However, most PCB antenna solutions for automotive radar are based on patch arrays fed by striplines with a characteristic impedance of approximately 50Ω. To optimize the PCB footprint, it is preferred that the package-ball connections be single-ended, thus requiring an on-die or in-package integrated BALUN. On-die BALUNs typically have high losses because the metal thickness in traditional CMOS processes is limited to a maximum of 1 - 2um, while the relatively expensive "ultra-thick metal (UTM)" process can be extended to 3 - 4um.

[0007] To reduce the area occupancy of the on-die BALUN and at the same time reduce mm-wave losses, the thick metal on the package, which can be obtained on packages such as FCCSP / FCBGA, for example, can be utilized, such as by implementing a BALUN structure based on in-package microstrip. However, this low-loss BALUN implementation typically requires a minimum half-wavelength ("λ / 2") additional length to transform the differential signal into the grounded coplanar waveguide mode (GCPW), and also typically requires a ball pitch of at least 1.5mm between the adjacent receive (RX) channel and transmit (TX) channel.

[0008] Another limitation of using a microstrip-based balun is the challenge of providing a tunable impedance range to the die. This limitation is specified by the design rules of the packaging technology that limit the achievable impedance range on the package (such as line width, gap, and stack height). SUMMARY OF THE INVENTION

[0009] According to a first aspect of the present disclosure, there is provided a packaged semiconductor device comprising: a semiconductor die including a monolithic microwave integrated circuit (MMIC), wherein the MMIC has differential outputs; a packaging substrate including at least a first metal layer, a second metal layer, and a third metal layer, and electrically connected to the semiconductor die through a plurality of pillars between the semiconductor die and the first metal layer, wherein the first metal layer and the third metal layer include ground planes, and the second metal layer therebetween includes a single-ended stripline; wherein the differential outputs are electrically connected to the first metal layer through a pair of pillars aligned along a first axis; wherein the packaged semiconductor device includes a balun coupler between the differential outputs and the single-ended stripline aligned along a second axis; wherein the balun coupler includes an opening in the first metal layer, the opening including two arms extending in a first direction parallel to the second axis. Providing a balun integrated from the die to the package and the coupler can be used to save space and can provide good electrostatic discharge (ESD) protection because the ground and signal pins can be electrically connected by shorting on a generally thick ground plane. In the case of an ESD event, the active components are protected due to this short. Additionally, the configuration can provide a high common-mode rejection ratio of up to 25 - 30 dB. Further, this arrangement allows for several degrees of freedom, which can be useful, for example, to be able to match a certain range of impedances.

[0010] In one or more embodiments, the first axis is parallel to the second axis.

[0011] In one or more embodiments, the opening has an "H" configuration, the "H" configuration including two elongated arms and a bridge section therebetween. The H configuration has a high degree of symmetry, which can be beneficial in allowing a lower voltage standing wave ratio (VSWR), particularly below two, over a wide bandwidth. The high degree of symmetry can also be particularly effective in canceling electric fields on different arms of, for example, an "H". In turn, this can result in very little radiation and effective low-loss coupling.

[0012] In one or more embodiments, a pair of pillars is located between the two elongated arms and one pillar is provided on each side of the bridge section. The pillars can be symmetrically arranged on each side of the bridge section, that is, the pillars can be equidistant from the bridge section and can be at an intermediate position between the two elongated arms; this can enhance the symmetry of the device, thereby improving the cancellation of fields and unwanted radiation.

[0013] In one or more embodiments, the packaged semiconductor device further includes at least two ground bumps between the elongated arm and each side of the pair of pillars. This can improve the shielding of signals.

[0014] In one or more embodiments, the packaging substrate further includes a fourth metal layer.

[0015] In one or more embodiments, a first axis is orthogonally aligned with a second axis. This can result in an apparatus in which an incoming differential signal and an outgoing single-ended signal propagate in the same direction.

[0016] In one or more such embodiments, the two arms are a first arm and a second arm, where the opening additionally includes a third arm and a fourth arm extending in a direction orthogonal to the first arm and the second arm. This can result in an incomplete loop of the opening. Each of the pair of parallel arms can have an electric field in an opposite direction, and this can cause cancellation or partial cancellation of the fields.

[0017] In one or more embodiments, the opening forms an incomplete loop in which a third arm connects the first arm and the second arm, and a fourth arm is connected to the second arm. In one or more such embodiments, a pair of struts is located on either side of the third arm such that one of the pair of struts is inside the incomplete loop and the other of the pair of struts is outside the incomplete loop.

[0018] According to another aspect of the present disclosure, the packaged semiconductor device can additionally include or be mounted on a printed circuit board that is electrically connected to the package substrate through a ball grid array.

[0019] In one or more embodiments, the MMIC includes a transmitter circuit for a radar device. The radar device can be an automotive radar device. However, the present disclosure is not limited to radar devices.

[0020] The MMIC can include multiple transmitter circuits for an automotive radar device. The packaged semiconductor device can operate in the 77 GHz frequency range.

[0021] According to a second aspect, there is provided a packaged semiconductor device including: a semiconductor die including a monolithic microwave integrated circuit MMIC, where the MMIC has a differential output; and a package substrate including a balun coupler and a strip transmission line formed in a second metal layer between a first metal layer and a third metal layer that are electrically connected to the semiconductor die through a plurality of pillars, where the first metal layer and the third metal layer each include a reference plane; where the differential output is electrically connected to the first metal layer through a pair of pillars aligned along a first axis among the plurality of pillars; where the strip transmission line is aligned along a second axis; and where the balun coupler includes an opening in the first metal layer, the opening including two arms extending in a first direction parallel to the second axis.

[0022] These and other aspects of the invention will be apparent from the embodiments described below and will be elucidated with reference to the embodiments described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The embodiments will be described by way of example with reference to the drawings, in which:

[0024] Figure 1A A cross-section of a packaged semiconductor device 100 according to an embodiment of the present disclosure is schematically shown;

[0025] Figure 1B Shown Figure 1A A schematic partial plan view of the packaged semiconductor device;

[0026] Figure 2A A cross-section of a packaged semiconductor device 100 according to other embodiments of the present disclosure is schematically shown;

[0027] Figure 2B Shown Figure 2A A schematic partial plan view of the packaged semiconductor device;

[0028] Figure 3 Shown is a metal layer (e.g., the first metal layer 122 on the first main surface of the package substrate) having a conventional "straight slot";

[0029] Figure 4 Shown is a metal layer having an "H" configuration slot according to an embodiment of the present disclosure;

[0030] Figure 5A Shown is a packaged semiconductor device according to one or more embodiments;

[0031] Figure 5B Shown Figure 5A A model-based simulation of the device;

[0032] Figure 6A A cross-section of a packaged semiconductor device 100 according to other embodiments of the present disclosure is schematically shown;

[0033] Figure 6B Shown Figure 6A A model-based simulation of the device;

[0034] Figure 7A A side view of a packaged semiconductor device mounted on a PCB by means of solder balls is schematically shown;

[0035] Figure 7B Is Figure 7A A plan view of the device; and

[0036] Figure 7C Is Figure 7A And Figure 7B A perspective view of the device.

[0037] It should be noted that the figures are diagrammatic and not drawn to scale. For clarity and convenience in the drawings, the relative dimensions and proportions of the various parts of these figures have been shown by being enlarged or reduced in size. The same reference numerals are generally used to refer to corresponding or similar features in modified and different embodiments. Detailed Description

[0038] Figure 1A A cross-section of a packaged semiconductor device 100 according to an embodiment of the present disclosure is schematically shown. The packaged semiconductor device 100 includes a semiconductor die 110 and a package substrate 120. The semiconductor die 110 includes MMICs thereon and therein, which are not shown in the schematic diagram. The package substrate 120 can be described as a multi-layer laminated substrate. The package substrate includes at least three metal layers. A first metal layer 122 is located on a first major or top surface of the package substrate, a second metal layer 124 is buried within the package substrate, and a third metal layer 126 is located on a second major or bottom surface of the package substrate 120. The first metal layer 122 and the third metal layer 126 form a ground plane for transmitting millimeter-wave signals; the second metal layer is patterned to form one or more strip transmission lines; the one or more strip transmission lines may include additional metal therebetween. Those skilled in the art will understand that a strip transmission line is a variant of a microstrip transmission line, where the primary conductor or transmission line is located between two reference or ground planes separated by a dielectric (whereas in a conventional microstrip transmission line, the primary conductor or transmission line is typically located on a surface and separated from a single reference or ground plane by a dielectric), and a strip line can generally be referred to as a microstrip or microstrip transmission line. An opening or slot 130 is included in the first metal layer, which will be discussed in more detail below. The opening is substantially completely surrounded by metal and can thus be considered "finite". The metal layers are separated by dielectric layers formed of an insulating material 128 including a low-loss dielectric, as is familiar to those skilled in the art. The package substrate 120 supports functions including signal power distribution, heat dissipation, and protection. In some applications, such as in an FCCSP arrangement, the semiconductor die 110 is connected to the package substrate 120 by a matrix of solder balls or pillars, which may alternatively be described as "bumps", or "C4 (controlled collapse chip connections)", typically formed of copper. Figure 1A Two example groups of pillars are shown. The first group includes a pair of pillars that are a first pillar 142 and a second pillar 144. The pillars are connected to MMIC circuits in the semiconductor die 110 by metal tracks or traces 152a, 154a that carry high-frequency signals, i.e., millimeter-wave or microwave signals. Figure 1BA pair of signal tracks 152a and 154a are shown, between which a differential or balanced millimeter-wave signal is carried to contact pads 152 and 154 connected to respective posts 142 and 144. A second group of posts 146 is also shown. These posts may generally be referred to as ground posts and are connected to a grounded metal region 156 on the semiconductor die. The posts may be arranged in a regular or irregular array, as will be illustrated in more detail below. Generally, there may be more ground posts than differential signal posts, but only two ground posts are shown in Figure 1A for illustrative purposes.

[0039] As Figure 1A shown, a current connection may be provided between the first metal layer 122 and the second metal layer including the strip transmission line 124, and the current connection is generally provided by a vertical shorting via formed of a metal such as copper, for example. Figure 1A An example shown in

[0040] Figure 1B includes one such via 162 located at the end of the strip transmission line. Figure 1A A schematic partial plan view of a packaged semiconductor device is shown. Specifically, the semiconductor die 110 and the MMIC circuit thereon are not shown, except for the differential metal tracks or traces 152a and 154b, which will carry differential signals S+ and S- to contact pads 152 and 154 in use, the contact pads being connected for differential signal posts 142 and 144 and to a pair of contact pad linings 156 for ground posts 146. Figure 1B The first metal layer 122 is shown, which has an opening or slot 130. The opening or slot includes two arms 132 and 134 extending in a first direction parallel to the axis between the differential signal posts 142 and 144. In Figure 1A and Figure 1B the embodiment depicted, the opening slot 130 has the geometric form of an "H", where the two arms are elongated and are connected by a bridge region 136. Also in Figure 1B the strip transmission line 124 is shown. In the illustrated embodiment, the strip transmission line is parallel to the elongated arms of the "H" configuration of the opening or slot 130. It should be noted that in the schematic diagram, the dielectric is hidden here Figure 1B (and Figure 2B ), so the strip line 172 is visible through the slot. As can be seen from Figure 1B and Figure 1AAs can be seen, the arrangement of the slots in the first metal layer at the surface of the encapsulation substrate 120 acts as a balun, in that it converts the differential, i.e., balanced signal on lines or traces 152a and 154a into a single-ended, i.e., unbalanced signal on the strip transmission line 124. The slots thus act as a balun coupler, in that they both couple the signal from the semiconductor die 110 to the encapsulation substrate 120 and convert the signal from differential to single-ended.

[0041] Figure 1A and Figure 1B The embodiment depicted in includes a current coupling to the strip transmission line through appropriately positioned vias 162. Figure 2A and Figure 2B shows an alternative embodiment according to the present disclosure, in which the coupling is non-current. Figure 2A and Figure 2B are generally similar to Figure 1A and Figure 1B respectively, and depict an encapsulated semiconductor device 200 including a semiconductor die 110 having signal contact pads 152 and 154 connected to signal traces 152a and 154a, and a ground pad 156. The signal contact pads 152 and 154 and the ground pad 156 are connected to an encapsulation substrate 220 by means of metal posts 142 and 144 and 146 respectively. The encapsulation substrate 220 includes a first metal layer 222 on its first major surface, a second metal layer 224 including a strip transmission line within its body, and a third metal layer 226 on its second major surface. In this embodiment, the opening or slot 230 takes the geometric form of an "H" having a first elongated arm 232 and a second elongated arm 234 connected by a bridge section 236. However, in this embodiment, there are no vias 162 in the first metal layer connected to the strip transmission line 224. That is, there is no current connection between the first metal layer and the second metal layer forming a closed circuit coupling. Instead, the ends of the transmission line extend away from the slot by a distance of approximately "one-quarter wavelength", i.e., λ / 4, to form an open stub 224a, as would be familiar to one skilled in the art.

[0042] Now turning to Figure 3, which shows a metal layer (e.g., the first metal layer 122 on the first major surface of the package substrate), in which there is a conventional "straight slot" 330 fed by feed points 352 and 354, such as pillars 142 and 144. The slot has a length l between approximately one-half λ and λ, where λ is the wavelength of the signal, i.e., λ / 2 < l < λ. The width of the slot is small compared to the wavelength, typically w < λ / 20, and is thus typically about 50 μm. Due to the nature of the in-phase electric field (E-field) distribution 340, the conventional straight slot can be used as an antenna in many applications, which is depicted as the envelope of the individual field vectors 342, 344, etc. on the left and right arms of the slot, as Figure 3 shown. Specifically, the conventional straight slot is an effective antenna for radiating signals (as shown into and out of the paper and also up and down along the ground plane, as shown).

[0043] Now turning to Figure 4 , which shows a metal layer having an "H" configuration slot 430 according to an embodiment of the present disclosure. The slot 430 includes a first elongated arm 432 having a left branch 432a and a right branch 432b, and a second elongated arm 434 having a left branch 434a and a right branch 434b. The elongated arms are connected by a bridge section 436. The feed points 452 and 454 are positioned adjacent to or near either side of the bridge section 436 and thereon. The elongated arms are separated by a relatively small distance l ∼ λ 0 / 10 compared to the wavelength of the signal, and the length of each of the elongated arms is at least one-quarter of the target wavelength λ0, i.e., l > λ 0 / 4. The E-field lines bend to follow the slot geometry (i.e., they point from the positive feed point 452 to the negative feed point 454), such that the two sides (left and right) are excited out of phase by 180°, thereby suppressing or even canceling any radiation from each arm. Since there is a 180° phase difference between the top slot section and the bottom slot section, radiation is further suppressed. This can result in a higher isolation and lower loss between adjacent channels, which may or may not be composed of the slot geometry.

[0044] Figure 5A shows a packaged semiconductor device 500 according to one or more embodiments. The device 500 is similar to the devices shown in Figure 2A and Figure 2B above, and includes a semiconductor die 110 and a package substrate 520. The package substrate is arranged with a quarter-λ stub to provide an open-circuit non-current coupling into the strip transmission line 224 in the package substrate 520. The first metal layer 222 and the third metal layer 226 are electrically coupled together via a so-called "via fence". The via fence is a plurality of vias that directly couple the first metal layer 222 and the third metal layer 226. For clarity, in Figure 5AOnly a single via hole 552 is shown. The via fence may be arranged with vias that generally surround the end portion and specifically the beginning of the strip transmission line.

[0045] Figure 5B A model-based simulation of the electromagnetic (EM) insertion loss is shown at 560, and the return loss at the die (in the form of graph 562) and at the stripline (in the form of graph 564) at a reference plane near the transition is shown. Figure 5B is plotted for frequencies in the frequency range of 70 to 90 GHz. Refer to Figure 2B , the slot dimensions for the simulation are for l 1 in the range of 100 - 250 μm, for l 2 in the range of 1000 - 1500 μm, for w1 and w2 in the range of 50 - 75 μ, the stripline width is in the range of 50 - 75 μm, and the open stub length is in the range of 250 - 300 μm. As is obvious from Figure 5B and the impedance values mentioned above, in addition to performing a compact die-to-package transition and a balun function, the transition also allows for impedance transformation at the die-to-package interface.

[0046] Figure 1B The geometric configuration of the slot depicted in includes a high degree of symmetry and is thus particularly effective in providing low-loss coupling and avoiding parasitic radiation into adjacent channels. However, other geometric configurations of the slot are also possible. Figure 6A shows one such geometric configuration. Similar to Figure 2A , this Figure 6A depicts a partial plan view of a packaged semiconductor device, where a first metal layer 622 on the top surface of the package substrate includes an opening or slot 630. Two feed points 652 and 654 provide differential feeding to the opening or slot 630. The opening or slot 630 includes two arms 632 and 634 that extend in a first direction parallel to the axis joining the two feed points 652 and 654. In the illustrated embodiment, the opening or slot 630 includes two additional arms 636 and 638 that are generally orthogonal to the arms 632 and 634. The arms are arranged to form a continuously connected slot, where the angles between arm 636 and 634, between arm 634 and 638, and between arm 638 and 632 are generally right angles. The feed points are located on either side of one of the arms, in this case arm 636. A strip transmission line 624 is shown, and in this embodiment, it extends in a direction orthogonal to the axis joining the feed points. Since the differential signals on the semiconductor die are typically routed to the feed points in a direction orthogonal to the axis joining the feed points, this embodiment results in a single-ended or unbalanced transmission line in the package substrate that is aligned - that is, it has an axis parallel to the direction of the tracks supplying the signal to the feed points. This is in contrast to Figure 1Band Figure 2B in contrast to the embodiment shown in, where the strip transmission line is parallel to the axis of the bonding feed point and thus generally orthogonal to the direction of the track supplying the signal to the feed point. In other words, in the embodiments shown in Figure 1B and Figure 2B the signal undergoes a 90° or right-angle turn within the balun coupler, while in the embodiment shown in Figure 6A the signal continues to travel in generally the same direction, as the signal is coupled from its differential form in the semiconductor die to its single-ended form in the strip transmission line in the package substrate.

[0047] Generally, the total length of the opening or slot may be one-half λ, that is, half of the wavelength of the coupled signal. The phase difference between the signals in a pair of opposing arms 634 and 632 is thus typically less than 90°, and can be seen from the electric field lines 632a, 632b,... and 634a, 634b. The fields in the two arms tend to cancel each other out to suppress radiation. Similarly, the phase difference between the signals in a pair of opposing arms 636 and 638 is typically less than 90°, and the electric fields in the two arms tend to cancel each other out to suppress radiation. Of course, those skilled in the art will understand that due to the lower symmetry of the embodiments with respect to Figure 1B and Figure 2B compared to the embodiments shown herein in Figure 6A the radiation suppression and cancellation in the opposing arms is generally more effective and complete in the "H" configuration compared to the embodiments shown in Figure 6A .

[0048] Figure 6B Shown at 660 is a model-based simulation of the electromagnetic (EM) insertion loss for the configuration shown in Figure 6A and shows the return loss at the die (in the form of graph 662) and at the stripline (in the form of graph 664) at the reference plane near the transition, Figure 6B plotted for frequencies in the frequency range from 70 to 90 GHz. Comparing this Figure 6B with the graph of Figure 5B it should be understood that, compared to the "H" configuration, it is evident that the embodiment shown in Figure 6A results in an increase in insertion loss as the frequency moves away from the design frequency and a higher return loss. On the other hand, being able to route the single-ended strip transmission line in the same direction as the differential signal can result in a more compact device design for some applications.

[0049] Figure 7AA side view of a packaged semiconductor device 100 mounted on a circuit board or PCB 730 is schematically shown by means of solder balls 710. The packaged semiconductor device 100 includes a semiconductor die 110 and a package substrate 220. The semiconductor die 110 is electrically connected to the package substrate 220 by means of pillars such as solder pillars, the pillars including a ground pillar 146 and a pair of differential signal pillars 142 and 144. As described above, the pillars 142 and 144 are positioned on either side of a bridge section 236 of an opening or slot 230, the opening or slot having two elongated arms 232 and 234 in a first metal layer 222 at a first or top surface of the package substrate 220. Also as described above, the package substrate 220 includes a third metal layer 226 on its second major or bottom surface. The slot acts as a balun transformer coupler for a stripline included in a second metal layer 224 within the package substrate 220. Figure 7A Also shown is a fourth metal layer 728 also within the package substrate 220, the fourth metal layer being connected to portions of the second metal layer that do not form the stripline by a plurality of conductive vias 554. (It should be noted that, counting from the top of the substrate, the fourth metal layer may alternatively be referred to as M3, and the third metal layer be referred to as M4). Those skilled in the art will appreciate that the non-signal portions of the second metal as well as the other metal layers will generally all be grounded to assist in isolation. Additionally, although only four metal layers are shown in this figure, the substrate may include more metal layers interleaved between and / or around low-loss dielectrics.

[0050] Figure 7B A plan view of the device 100 mounted on the circuit board 730 is schematically shown. Figure 7A As with the configuration of the opening or slot in the first metal layer 222 that forms the balun transformer coupler, a “fence” of ground vias 552 around the stripline 224 is evident in this view. It can be seen that the conductive vias 554 connecting portions of the second metal layer and the fourth metal layer other than the stripline are also arranged in a fence configuration, the fence acting as an outer shield for a coaxial cable. Providing such via fences and connecting the vias mimics a waveguide at much higher cut-off frequencies, which helps to limit any losses due to radiation in the substrate. Figure 7B Also shown is a coaxial connector 560 within the package, the coaxial connector being used to route signals from the stripline in the second metal layer through the fourth metal layer (728) to the third metal layer 226 (at the bottom of the package). The signals are transmitted to the PCB by means of signal balls (not visible), the signal balls being below the coaxial cable and surrounded and grounded by the solder balls 710 and thus providing additional shielding.

[0051] Figure 7C Shown Figure 7A and Figure 7BA perspective view of the apparatus 100 and the circuit board 730 as shown. Differential signal lines on the die are shown as 752. The vias 552 and 554 forming the fence are more clearly visible. It is also more apparent that the strip transmission line 224 is separated from other metal regions 724 within the same metal layer by the gap 726.

[0052] Other variations and modifications will be apparent to those skilled in the art upon reading this disclosure. Such variations and modifications may involve equivalents and other features that are known in the field of MMIC couplers and may be used as alternatives or supplements to the features described herein.

[0053] Although the appended claims are directed to specific combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any combination of novel features or any generalization of such novel features that are explicitly or implicitly disclosed herein, regardless of whether such novel features relate to the same invention as that currently claimed in any claim or whether such novel features mitigate any or all of the technical problems mitigated by the present invention.

[0054] It should be noted that the above one or more embodiments have been described with reference to different subject matters. Specifically, some embodiments may have been described with reference to method-type claims, while other embodiments may have been described with reference to apparatus-type claims. However, those skilled in the art will appreciate from the above that, unless otherwise stated, any combination of features related to different subject matters, specifically combinations of features of method-type claims and features of apparatus-type claims, is also considered to be disclosed with this document, in addition to any combination of features belonging to one type of subject matter.

[0055] Features described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, the various features described in the context of a single embodiment may also be provided separately or in any suitable sub-combination.

[0056] For completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, the term "a" or "an" does not exclude a plurality, a single processor or other unit may fulfill the functions of several components recited in the claims [delete if not relevant], and the reference numerals in the claims should not be construed as limiting the scope of the claims. Additionally, the word "may" is used in a permissive sense (i.e., meaning having the possibility of...) rather than a mandatory sense (i.e., meaning must). Similarly, the words "include", "including" and "includes" mean including but not limited to.

Claims

1. A packaged semiconductor device, characterized in that: include: a semiconductor die comprising a monolithic microwave integrated circuit (MMIC), wherein the MMIC has a differential output; a package substrate comprising at least a first metal layer, a second metal layer, and a third metal layer and electrically connected to the semiconductor die through a plurality of pillars between the semiconductor die and the first metal layer, wherein the first metal layer and the third metal layer comprise a ground plane and the second metal layer therebetween comprises a single-ended stripline; wherein the differential output is galvanically connected to the first metal layer through a pair of pillars among the plurality of pillars aligned along a first axis; wherein the packaged semiconductor device comprises a balun coupler between the differential output and the single-ended stripline aligned along a second axis; and The balun coupler comprises an opening in the first metal layer, the opening comprising two arms extending in a first direction parallel to the second axis.

2. The packaged semiconductor device according to claim 1, It is characterized in that The first axis is parallel to the second axis.

3. The packaged semiconductor device according to claim 2, It is characterized in that The opening has an "H" configuration including the two long arms and a bridge section therebetween.

4. The packaged semiconductor device according to claim 3, It is characterized in that The pair of struts are located between the two elongated arms with one strut on either side of the bridge section.

5. The packaged semiconductor device according to claim 4, wherein: Further included are at least two grounding posts between the elongated arms and on either side of the pair of posts.

6. The packaged semiconductor device according to claim 1, It is characterized in that The first axis is aligned orthogonally with the second axis.

7. The packaged semiconductor device according to claim 6, wherein: The two arms are a first arm and a second arm, Wherein the opening further comprises a third arm and a fourth arm extending in a direction orthogonal to the first arm and the second arm.

8. The packaged semiconductor device according to claim 7, It is characterized in that The opening forms an incomplete loop in which the third arm connects the first arm and the second arm, and the fourth arm connects to the second arm.

9. The packaged semiconductor device according to claim 8, It is characterized in that A pair of tabs are located on either side of the third arm such that one of the pair of posts is within the incomplete loop and the other of the pair of posts is outside the incomplete loop.

10. A packaged semiconductor device, characterized in that: include: a semiconductor die comprising a monolithic microwave integrated circuit (MMIC), wherein the MMIC has a differential output; as well as a package substrate including a balun coupler, and a stripline transmission line formed in a second metal layer between a first metal layer and a third metal layer electrically connected to the semiconductor die through a plurality of pillars, wherein the first metal layer and the third metal layer each include a reference plane; wherein the differential output is galvanically connected to the first metal layer through a pair of pillars among the plurality of pillars aligned along a first axis; wherein the strip transmission line is aligned along a second axis; And wherein the balun coupler comprises an opening in the first metal layer, the opening comprising two arms extending in a first direction parallel to the second axis.

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