Apparatuses, systems, and methods for facilitating phase shifters

Abstract

The disclosure relates to devices, systems, and methods for facilitating phase shifters. Aspects of the present disclosure are directed to phase shifters, including active 90-degree phase shifters. A phase shifter of the present disclosure may include a coupler that generates a first signal at a first coupler output and a second signal at a second coupler output based on an input signal; a first plurality of transistors, the first plurality of transistors coupled to the first coupler output; and a second plurality of transistors, the second plurality of transistors coupled to the second coupler output. The first plurality of transistors and the second plurality of transistors may form a multiplexer that implements a nominal 90-degree phase shift in the output signal according to a selection via a control signal. Other aspects and embodiments are disclosed.

Description

Technical Field

[0001] The present disclosure relates to devices, systems, and methods for facilitating phase shifters. Background Art

[0002] Phase shifters are components / devices that can be used in many practical applications. For example, a phase shifter can be used as part of an analog beamformer (ABF) system, network, or application. In many cases, a phase shifter can include fixed phase steps or increments, such as 90 degrees or 180 degrees.

[0003] Conventionally, an active vector modulator (VM) can be used to implement a phase shifter. However, in practice, a VM has an inherently high noise figure (NF) and low linearity. Additionally, a VM requires a high-resolution digital-to-analog converter (DAC) for obtaining accurate phase step control.

[0004] In some cases, an ABF is implemented using a distributed passive switched LC phase shifter. However, such an arrangement is prone to having insertion loss. Additionally, such an arrangement requires a silicon-on-insulator (SOI) switching device with a low figure of merit (FOM) to reduce the insertion loss, where the FOM can be expressed as the product of resistance and capacitance (e.g., R on *C off ). Given the current trend towards higher frequencies in the signaling being used, these problems are even more pronounced. Additionally, an amplifier can be used to compensate for the loss caused by the passive shifter. However, the introduction of such an amplifier results in additional complexity, power dissipation, and chip area (e.g., utilization). Summary of the Invention

[0005] According to a first aspect of the present invention, there is provided a circuit comprising:

[0006] a coupler having a first coupler output and a second coupler output, wherein the coupler generates a first signal at the first coupler output and a second signal at the second coupler output in accordance with an input signal;

[0007] a first plurality of transistors coupled to the first coupler output; and

[0008] a second plurality of transistors coupled to the second coupler output, the first plurality of transistors and the second plurality of transistors forming a multiplexer that implements a nominal 90-degree phase shift in an output signal based on a selection via a control signal received at a control signal input.

[0009] In one or more embodiments, the circuit further comprises:

[0010] A transistor, the transistor being coupled to a first transistor of the first plurality of transistors and a first transistor of the second plurality of transistors.

[0011] In one or more embodiments, the circuit further comprises:

[0012] A first bias circuit, the first bias circuit supplying a first bias voltage to the first transistor of the first plurality of transistors and supplying a second bias voltage to the first transistor of the second plurality of transistors.

[0013] In one or more embodiments, the circuit further comprises:

[0014] A second bias circuit, the second bias circuit supplying a third bias voltage to the transistor.

[0015] In one or more embodiments, the circuit further comprises:

[0016] A first input matching network, the first input matching network being disposed between the output of the first coupler and a second transistor of the first plurality of transistors; and

[0017] A second input matching network, the second input matching network being disposed between the output of the second coupler and a second transistor of the second plurality of transistors.

[0018] In one or more embodiments, the circuit further comprises:

[0019] A second bias circuit, the second bias circuit supplying a third bias voltage to the second transistor of the first plurality of transistors and supplying a fourth bias voltage to the second transistor of the second plurality of transistors.

[0020] In one or more embodiments, the nominal 90-degree phase shift corresponds to a phase shift of 90 degrees plus or minus 3 degrees.

[0021] In one or more embodiments, the circuit further comprises:

[0022] A first switch, the first switch being coupled to the output of the first coupler and the first plurality of transistors; and

[0023] A second switch, the second switch being coupled to the output of the second coupler and the second plurality of transistors.

[0024] In one or more embodiments, the second switch is coupled to the control signal input.

[0025] In one or more embodiments, the circuit further comprises:

[0026] An inverter that generates an inverted control signal at an inverter output based on the control signal,

[0027] wherein the first switch is coupled to the inverter output.

[0028] In one or more embodiments, each transistor of the first plurality of transistors and the second plurality of transistors is an NPN transistor.

[0029] In one or more embodiments, the emitter of the first transistor of the first plurality of transistors is connected to the collector of the second transistor of the first plurality of transistors.

[0030] In one or more embodiments, the emitter of the first transistor of the second plurality of transistors is connected to the collector of the second transistor of the second plurality of transistors.

[0031] According to a second aspect of the present invention, there is provided a system including:

[0032] A phase inversion variable gain amplifier (PI-VGA) that provides a phase shift of 0 to 180 degrees;

[0033] A 0 to 90 degree phase shifter implemented via passive components; and

[0034] An active 90 degree phase shifter.

[0035] In one or more embodiments, the system further includes:

[0036] A power splitter that distributes an input signal.

[0037] In one or more embodiments, the system further includes:

[0038] A power amplifier (PA).

[0039] In one or more embodiments, the system further includes:

[0040] An antenna that transmits an output signal,

[0041] wherein the output signal is based on the input signal, and wherein the input signal is processed at least via the power splitter, the PI-VGA, the 0 to 90 degree phase shifter, the active 90 degree phase shifter, and the PA when generating the output signal.

[0042] According to a third aspect of the present invention, there is provided a method including:

[0043] Obtaining an input signal;

[0044] Generate an in-phase signal component and a quadrature signal component via a coupler and based on the input signal; and

[0045] Generate an output signal that provides a nominal 90-degree phase shift according to a selection via a control signal via an active circuit and based on the in-phase signal component and the quadrature signal component.

[0046] In one or more embodiments, the active circuit includes a plurality of transistors arranged in at least a double-stack configuration.

[0047] In one or more embodiments, the at least double-stack configuration includes a triple-stack configuration.

[0048] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Reference will now be made to the drawings, which are not necessarily drawn to scale, and in which:

[0050] Figure 1 A block diagram of a system according to an aspect of the present disclosure is shown.

[0051] Figure 2 A circuit for implementing a phase shifter according to an aspect of the present disclosure is shown.

[0052] Figure 3 A circuit for implementing Figure 2 a part of the circuit is shown.

[0053] Figure 4 A circuit for implementing Figure 2 a part of the circuit is shown.

[0054] Figures 5A - 5C A circuit for implementing a phase shifter according to an aspect of the present disclosure is shown.

[0055] Figure 6 A flowchart of an exemplary method according to an aspect of the present disclosure is shown. DETAILED DESCRIPTION

[0056] The present disclosure particularly describes illustrative embodiments of a phase shifter. The phase shifter of the present disclosure may include a phase-invariant, active, nominal 90-degree phase shifter. The phase shifter of the present disclosure may be implemented using components, devices, circuits, etc., as described in further detail hereinafter.

[0057] One or more of the exemplary embodiments may include, in whole or in part: a coupler that generates a first signal at a first coupler output and a second signal at a second coupler output in accordance with an input signal; a first plurality of transistors coupled to the first coupler output; and a second plurality of transistors coupled to the second coupler output, the first plurality of transistors and the second plurality of transistors forming a multiplexer that implements a nominal 90-degree phase shift in an output signal based on a selection via a control signal. One or more of the exemplary embodiments may include, in whole or in part: obtaining an input signal; generating an in-phase signal component and a quadrature signal component via the coupler and based on the input signal; and generating an output signal that provides a nominal 90-degree phase shift based on a selection via a control signal via an active circuit and based on the in-phase signal component and the quadrature signal component. The output signal may provide a nominal 90-degree phase shift based on a selection via a control signal. Other embodiments are described in further detail below.

[0058] By way of introduction, aspects of the present disclosure may facilitate a transmit / transmitter (TX) configuration that may be used as part of one or more practical applications, e.g., as part of an integrated circuit (IC) that supports an analog beamformer (ABF). In some embodiments, an active circuit may be used to implement a major or coarse phase shift (e.g., between 0 and 180 degrees or 0 and 90 degrees in terms of phase shift / step size), which may reduce (e.g., eliminate) insertion loss and reduce the amount of chip / IC area utilized / required. A passive circuit may be utilized to facilitate small / fine amounts of phase shift, potentially obviating the need for a high-resolution digital-to-analog converter (DAC).

[0059] In accordance with aspects of the present disclosure, a phase shifter may include a radio frequency (RF) in-phase (I) and quadrature (Q) signal generation circuit. In some embodiments, a signal selection circuit that may implement the functionality of a multiplexer (MUX) may be provided, and the signal selection circuit may be characterized by precise and robust phase shift control of an output signal at a low power dissipation level. A biasing circuit that may be used in conjunction with the MUX may produce low switching times between different operating modes, which in turn may enable fast and accurate phase shift operation.

[0060] Referring Figure 1 , a block diagram of a system 100 incorporating a 2-channel TX line that may potentially be used as part of an ABF IC is shown. Specifically, a first channel in the channels is labeled TX channel 1, and a second channel in the channels is labeled TX channel 2. The use of two channels is illustrative, that is, in some embodiments, a different count of channels may be used. Various components that may be used as part of Figure 1 TX channel 1 as shown are described below, and it should be understood that corresponding examples of those components may be utilized in conjunction with TX channel 2.

[0061] As part of system 100, node 108 may correspond to the input of a 2-channel TX line. For example, input 108 may correspond to a location where an input signal is obtained or provided. Component 101 may correspond to a power splitter. The power splitter 101 may be implemented in one or more forms, e.g., via a Wilkinson power splitter or another suitable type of power splitter. Component 102 may correspond to a phase-inverting variable gain amplifier (PI-VGA) that may provide / support beam gain control and a phase shift, e.g., from 0 to 180 degrees. In some embodiments, component 102 may be implemented via a Gilbert cell or another suitable circuit. Component 103 may correspond to a 0 to 90-degree phase shifter and may support small step sizes or increments (e.g., 5.625, 11.25,..., 84.375-degree steps). Component 103 may be implemented using passive components, e.g., including a passive reflective type phase shifter (RTPS) or a passive delay line-based phase shifter. Component 104 may correspond to an active 90-degree phase shifter. Various embodiments for implementing component 104 are described in further detail below. Component 105 may correspond to a single-stage or multi-stage power amplifier. Component 106 may correspond to an antenna that may be used to transmit an output signal.

[0062] Figure 1 The serial coupling order or arrangement of each of the components shown is illustrative, i.e., other orders / arrangements may be utilized without departing from the scope and spirit of the present disclosure. For example, the order or sequence of coupling components 102, 103, and 104 is exemplary; the serial coupling order of the components (e.g., the order of 103, 102, and 104) represents another possible order in the direction from component 100 towards antenna 106. Additionally, it should be noted that each of the components (e.g., component 104) may be utilized in applications other than TX. For example, aspects of system 100 may be utilized in conjunction with a receive / receiver (RX) line, an IQ modulator, etc.

[0063] Now referring to Figure 2 , a circuit 200 corresponding to an active 90-degree phase shifter in accordance with aspects of the present disclosure is shown. In some embodiments, circuit 200 may be used to implement Figure 1 the function of phase shifter 104.

[0064] The circuit 200 includes a directional coupler 201, a common-base buffer / transistor Q1, an IQ signal selector (including cascode pairs Q2 / Q4 and Q3 / Q5), and a control circuit. The directional coupler 201 has an input terminal (e.g., terminal 1), first and second coupler output terminals (e.g., terminals 2 and 3), and an isolation terminal (e.g., terminal 4) that can be impedance-coupled to ground. The first output terminal is coupled to a first node (Vb_ce_I) (i.e., to the first input of the IQ signal selector) via a first input matching network (IMN) 212, and the second output terminal is coupled to a second node (Vb_ce_Q) (i.e., to the second input of the IQ signal selector) via a second IMN 214.

[0065] As part of the circuit 200, the directional coupler 201 can be utilized. The coupler 201 can act as an RFIQ signal generator by splitting an input signal (RFin) received at the coupler input into two signals and providing those two signals to first and second paths or branches coupled to the first and second coupler outputs, where the phase difference between the signals provided to the two paths or branches is 90 degrees. For example, these two signal paths / branches are represented as RF_I and RF_Q in Figure 2 and can include portions that are the I-branch and Q-branch, respectively, as further detailed below. The circuit 200 can be used to generate an output signal (RFout) that can correspond to the selection of one of the two paths. As part of generating the output signal RFout, the selection of which of the two paths to utilize can be based on a control / selection signal labeled PS_ctrl in Figure 2 More specifically, the control circuit includes a control signal input (PS_ctrl), an inverter 202 (having an inverter input and an inverter output), and first and second impedances. The control input is coupled to the inverter input, and the inverter output is coupled to the control terminal (e.g., base terminal) of a first control transistor M1 via a first impedance. The control input is also coupled to a second control transistor M2 via a second impedance. The transistors M1 and M2 can be, for example, field-effect transistors (or other types of transistors) having a first current conduction terminal coupled to the first or second input node (Vb_ce_I or Vb_ce_Q) and a second current conduction terminal coupled to ground via a DC blocking capacitor.

[0066] As used herein, a reference to a transistor being "on" means that a control signal at the control terminal (e.g., base terminal) of the transistor causes the transistor to be in a low impedance state (i.e., allows current flow between the emitter and collector terminals). Conversely, a reference to a transistor being "off" means that a control signal at the control terminal of the transistor causes the transistor to be in a high impedance state (i.e., blocks current flow between the emitter and collector terminals).

[0067] Figure 2 The transistors Q2, Q3, Q4, and Q5 shown can act as an IQ signal selector (e.g., can act as a 2-to-1 MUX that selects between the input signals RF_I and RF_Q). The transistors Q2 and Q4 are coupled in a cascode relationship, where the collector of transistor Q2 is coupled to the output node (Ve_cb2), the emitter of transistor Q2 is coupled to the collector of transistor Q4, and the emitter of transistor Q4 is coupled to ground. The base of transistor Q4 is coupled to the first input node (Vb_ce_I) and to the collector / emitter bias circuit 220, and the base of transistor Q2 is coupled to the first collector / base bias circuit 210. Similarly, the transistors Q3 and Q5 are coupled in a cascode relationship, where the collector of transistor Q3 is coupled to the output node (Ve_cb2), the emitter of transistor Q3 is coupled to the collector of transistor Q5, and the emitter of transistor Q5 is coupled to ground. The base of transistor Q5 is coupled to the second input node (Vb_ce_Q) and to the collector / emitter bias circuit 220, and the base of transistor Q3 is coupled to the first collector / base bias circuit 210. The emitter of transistor Q1 is coupled to the collectors of transistors Q2 and Q3 (or the output node (Ve_cb2)), and the emitter of transistor Q1 is coupled to the RF output (RFout) via OMN 216. The base of transistor Q1 is coupled to the second collector / base bias circuit 230.

[0068] In a first operating mode of circuit 200 corresponding to selecting the I branch, the transistors Q2 and Q4 can be turned on, where the voltage at node Vb_ce_I is approximately equal to the turn-on voltage of the base-emitter of transistor Q4 (approximately 0.8V) (hereinafter denoted as Vbe), and node Vb_cb1_I is approximately twice that amount (e.g., 1.6V). In this first operating mode, the transistor / switch M1 can be turned off (via the control signal PS_ctrl, with the aid of inverter 202). In the first operating mode, the Q branch transistors Q3 and Q5 can be turned off, where the voltages at nodes Vb_ce_Q and Vb_cb1_Q are equal and approximately at 0V. In the first operating mode, the transistor / switch M2 can be turned on (via the control signal PS_ctrl).

[0069] A second operating mode of circuit 200 can correspond to selecting the Q branch. The second operating mode can represent the mirror image of the first operating mode described above. Those skilled in the art will understand how to exercise the various signals / nodes to achieve the second operating mode, and thus, for the sake of brevity, a complete description is omitted herein. Briefly, in the second operating mode, the I branch transistors Q2 and Q4 can be turned off, the transistor / switch M1 can be turned on, the Q branch transistors Q3 and Q5 can be turned on, and the transistor / switch M2 can be turned off.

[0070] Regardless of which of the I-branch or Q-branch is selected, transistor Q1 can always be turned on (where the voltage value at node Vb_cb2 is approximately three times the value of Vbe, or approximately 2.4V, the cb2 biasing circuit 230 can be configured to provide the voltage Vb_cb2, and can correspond to a fixed DC power supply, etc.; in this regard, it should be noted that the values used are exemplary and can vary depending on the type or technology of the transistors or switches used in a given embodiment). The switching between the two branches can generate signals with a 90-degree phase difference at the output RFout. Thus, circuit 200 can be used to implement an active 90-degree phase shifter.

[0071] The switch or MUX topology provided by circuit 200 can provide high-quality isolation between the I-branch and the Q-branch. In this way, precise and robust phase control can be obtained at the output RFout. For example, as part of the first operating mode described above (when transistors Q2 and Q4 are turned on and transistors Q3 and Q5 are turned off), the leakage of the I-branch signal to the Q-branch components (e.g., from node Ve_cb2 to node Vb_ce_Q) can be (substantially) prevented. Additionally, the common-base buffer / transistor Q1 can provide a low-ohm load impedance for turning on the cascode transistor pair Q2 and Q4, while the turned-off transistor pair Q3 and Q5 has a high output impedance, which is further used to prevent the leakage of the I-branch signal into the Q-branch. Similar remarks apply to the second operating mode (corresponding to the selection of the Q-branch).

[0072] As those skilled in the art will appreciate based on a review of the present disclosure, switches / transistors M1 and M2 can be used to implement a constant input impedance, for example, for transistors Q4 and Q5 between the on and off states, such that the directional coupler 201 can have a (substantially) constant load impedance between the first output and the second output (labeled 2 and 3) of the coupler 201 between the first operating mode and the second operating mode (or in other words, when implementing different phase shifts / settings). In addition, it should be understood that since switches M1 and M2 can be utilized / applied to compensate for the change in input impedance, they do not need to provide a good / high-quality short / cut-off state. Therefore, the FOM of switches M1 and M2 is not important, thus achieving flexibility in selecting the parameters of switches M1 and M2.

[0073] Even without using switches M1 and M2, aspects of circuit 200 can be utilized to implement an active phase shifter. The trade-off when omitting switches M1 and M2 is that the phase shift actually achieved may not be 90 degrees, but may be approximately 92 or 93 degrees (providing a variation of roughly plus or minus 2%). More generally, a range of the form 90 degrees plus or minus X can be achieved, where X is a certain value (e.g., X is 1 degree, 2 degrees, 3 degrees, etc.). In this regard, a nominal 90-degree phase shift can be achieved using the phase shifter of the present disclosure, where the term nominal in this context expresses the concept that the phase shift can be approximate but may not exactly equal 90 degrees.

[0074] Circuit 200 can include a first input matching network (IMN) 212 and a second IMN 214 associated with the I-branch and the Q-branch, respectively. Circuit 200 can include an output matching network (OMN) 216 at the output (RFout). As those skilled in the art will understand and appreciate, IMNs 212 and 214 and OMN 216 can be used to provide impedance matching, which can reduce the likelihood or degree of signal reflection, etc.

[0075] Now referring to Figure 3 , circuit 300 is shown. Circuit 300 can be used to implement or carry out Figure 2 the cb1 bias circuit 210 shown in

[0076] Now referring to Figure 4 , circuit 400 is shown. Circuit 400 can be used to implement or carry out Figure 2The CE bias circuit 220 shown in. The circuit 400 (in combination with the circuit 200) is very similar to the circuit 300 described above and can be used to achieve nanosecond time delay and fast beam steering capabilities (e.g., switching or steering in about 5 nanoseconds).

[0077] Figure 4 The switches / transistors M401 and M402 shown in can be used to pull down the bias voltages Vb_ce_I and Vb_ce_Q. The switches / transistors M401 and M402 can be complementary in nature (e.g., one of the switches / transistors M401 and M402 can be turned on while the other of the switches / transistors M401 and M402 can be turned off, as generally represented by the operation of the control signals PS_ctrl and the inverter 412 [where the inverter 412 can correspond to the inverter 202 or the inverter 312 in a given embodiment]) such that the voltages Vb_ce_I and Vb_ce_Q will be opposite in magnitude / polarity (to facilitate turning on one of the transistors Q4 and Q5 and turning off the other of the transistors Q4 and Q5 in the manner described above with respect to Figure 2 the circuit 200).

[0078] As part of the circuit 400, the transistor Q401 can provide current and increase the bias voltage Vb_ce_I in one operating mode, and the transistor Q402 can absorb current and pull down the bias voltage Vb_ce_I (to about 0V) in another operating mode. Similar remarks apply to the bias voltage Vb_ce_Q of the transistors Q403 and Q404.

[0079] The current mirror transistors M404, M405, M406, and M407 can share the same / common gate connection at the node 411. With this configuration, charge can mainly travel between the transistors M404 and M406, and thus, when switching between the I-branch and the Q-branch, the voltage at the node 411 can remain (substantially) constant, as described above.

[0080] After just describing the circuit 200 (and selecting some of the components of the circuit 200 with the aid of the descriptions of the circuit 300 and the circuit 400 above), it should be understood that there can be variations of the circuit 200 that can be utilized in a given embodiment. For example, and with reference to Figure 5A 、 5B and 5C, the circuits 500a, 500b, and 500c are shown that can correspond to variants of the circuit 200. In Figures 5A - 5C and with respect to Figure 2 , for simplicity of illustration, some markings of the components are omitted (e.g., those skilled in the art will understand that the components shown in Figures 5A - 5C are the same as those shown in Figure 2the corresponding relationships between the components shown in). Further, in terms of the representation or symbols, the switches / transistors M1 and M2 (and the associated components coupled thereto, such as resistors or capacitors) are simplified in Figures 5A - 5C relative to Figure 2 those shown in. The differences between each of the circuits 500a, 500b, and 500c and the circuit 200 are described in detail below.

[0081] Relative to the circuit 200, the circuit 500a may omit the top stack cb2 stage (including the transistor Q1 and the cb2 bias circuit 230). Relative to the circuit 200, the circuit 500b may omit the middle stack cb1 stage (including the transistors Q2 and Q3 and the cb1 bias circuit 210). Relative to the circuit 200, the circuit 500c may omit the bottom stack ce stage (including the transistors Q4 and Q5 and the ce bias circuit 220).

[0082] Thus, Figures 5A - 5C the configurations shown in relative to the circuits 500a, 500b, and 500c may utilize a dual-stack configuration (compared to the circuit 200 that utilizes a triple-stack configuration) by omitting the stages / stacks in each of the circuits 500a, 500b, and 500c as described above. The circuits 500a, 500b, and 500c may be particularly useful or applicable for low-voltage (transistor / switch) environments or technologies (e.g., 1.5V, 1.8V, etc.), while the circuit 200 may be more suitable for use with higher-value voltage environments or technologies (e.g., 3.3V or greater). With fewer stacks, the circuits 500a, 500b, and 500c may provide less isolation and provide less robust control of the output phase shift relative to the circuit 200.

[0083] Although the various circuits 200, 300, 400, 500a, 500b, and 500c depicted in the figures demonstrate various switches or transistors using a specific type or technology (e.g., NPN transistors in the case of Q1, Q2, Q3, Q4, and Q5), Figure 2 in the case of the circuit 200 of, including, for example, M1, M2, Q1, Q2, Q3, Q4, and Q5), it should be understood that other types or technologies (e.g., MOS, HBT, HEMT, etc.) may be used without departing from the scope and spirit of the present disclosure. In this regard, the specific form or type of the switches or transistors shown as part of the circuits 200, 300, 400, 500a, 500b, and 500c are considered illustrative or exemplary (and not restrictive). Similarly, any values such as voltages or currents are illustrative / exemplary, and different values may be utilized / provided without departing from the scope and spirit of the present disclosure.

[0084] The various devices, components, signals, etc. of the present disclosure may be coupled to each other, as demonstrated in the accompanying drawings. In this context, coupling may refer to a direct connection or an indirect connection. An indirect connection between a first entity or signal and a second entity or signal may include at least one intervening entity or signal.

[0085] Reference is now made to Figure 6 , which shows a flowchart of an exemplary method 600 according to various aspects described herein. Method 600 may be utilized (e.g., implemented or executed) to achieve the functionality of a phase shifter. Method 600 is described below with respect to operations associated with the various blocks shown in Figure 6 . It should be understood and appreciated that in some embodiments, aspects of some of the operations / blocks shown may be optional. Additionally, in some embodiments, additional operations / blocks not shown may be included. Further, the order or sequence of the operations / blocks may be different from the order or sequence explicitly shown.

[0086] In block 602, an input signal may be obtained. By way of example and with simple reference to (e.g.) Figure 2 , the input signal of block 602 may correspond to the signal at RF in. As part of block 602, the signal may be obtained from the source or distributor of the signal (as potentially subject to modification, processing, conditioning, etc.). In some embodiments, block 602 may include generating the input signal in a first scenario (e.g., via a signal generator).

[0087] In block 606, the input signal (from block 602) may be processed to generate a first signal and a second signal. By way of example, the first signal of block 606 may correspond to the in-phase (I) signal component, and the second signal of block 606 may correspond to the quadrature (Q) signal component. With simple reference to, for example, Figure 2 , the processing (e.g., distribution) of the input signal in block 606 may be facilitated via coupler 201.

[0088] In block 610, a control or selection signal may be generated. The parameters of the control / selection signal of block 610 (which, in some embodiments, may correspond to the control signal PS_ctrl mentioned above), such as timing or frequency parameters, may be selected based on an identifier of a particular environment / recognition or the actual application at hand using the phase shifter. By way of example, it may be the case that in a first actual application involving a TX line or an RX line, a first frequency should be used, while in a second actual application involving an IQ modulator, a second frequency should be used, the second frequency being the same as or different from the first frequency.

[0089] In block 614, an output signal may be generated based on the control signal of block 610. By way of example, block 614 may include generating the output signal via the control signal via a MUX (e.g., in the context of Figure 2 ), the signal at RF out).Figure 2 In the context of, a MUX formed by transistors Q2, Q3, Q4, and Q5, etc. selects one of two signals or paths (corresponding to the first and second signals of block 606).

[0090] Aspects of the present disclosure may be implemented via one or more processing systems. Each processing system may include one or more processors. Aspects of the present disclosure may be implemented using transient and / or non-transitory computer-readable media or machines. For example, aspects of the present disclosure may include a computer-readable medium (or memory) storing executable instructions thereon; the instructions, when executed (by a processing system, for example), may facilitate the execution of one or more operations, such as one or more of the operations described herein.

[0091] As set forth herein, aspects of the present disclosure represent a substantial improvement over the technologies associated with practical applications. For demonstration, and as set forth above, aspects of the present disclosure may facilitate fast switching relative to phase shifters while also providing a high level of signal isolation. Additionally, due to some devices or components (e.g., switches or transistors) being selectively turned off, power dissipation may be reduced (e.g., minimized). At least for these reasons, those skilled in the art will understand that aspects of the present disclosure are not directed to abstract concepts. Instead, and as demonstrated herein, aspects of the present disclosure relate to and cover significantly more than any single abstract concept.

[0092] The description of the embodiments described herein is intended to provide a general understanding of the structures of the various embodiments, and it is not intended to serve as a complete description of all elements and features of the devices and systems that may utilize the structures described herein. Many other embodiments will be apparent to those skilled in the art upon review of the above description. Other embodiments may be utilized and other embodiments may be derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of the present disclosure. The figures are only representative and may not be drawn to scale. Certain scales of the figures may be enlarged and other scales may be minimized. Accordingly, the specification and the drawings are to be regarded as illustrative rather than restrictive.

[0093] Although specific embodiments have been shown and described herein, it should be understood that any arrangement that is expected to achieve the same purpose may replace the shown specific embodiments. The present disclosure is intended to cover any and all adaptations or variations of the various embodiments. The present disclosure covers combinations of the above embodiments and other embodiments not specifically described herein.

[0094] For example, one or more features from one or more embodiments may be combined with one or more features of one or more other embodiments. In one or more embodiments, a feature that is positively recited may also be negatively recited and excluded from the embodiment, with or without replacement by another structural and / or functional feature. The steps or functions described with respect to the embodiments of the present disclosure may be performed in any order. The steps or functions described with respect to the embodiments of the present disclosure may be performed alone, in combination with other steps or functions of the present disclosure, or in accordance with other embodiments or other steps not described in the present disclosure. Additionally, more or fewer than all of the features described with respect to the embodiments may be used.

[0095] In one or more exemplary embodiments, all of the steps or functions described with respect to the exemplary processes or methods may also be performed. Additionally, unless explicitly stated otherwise, the use of numerical terms such as first, second, third, etc. to describe devices, components, steps, or functions is not intended to describe an order or a function. Unless explicitly stated otherwise, the use of the terms first, second, third, etc. is generally for the purpose of distinguishing devices, components, steps, or functions. Further, one or more of the devices or components described with respect to the exemplary embodiments may facilitate one or more functions, where the facilitation (e.g., facilitating access or facilitating establishing a connection) may include reducing each step required to perform the function, or may include performing all of the steps required to perform the function.

[0096] When providing the abstract of the present disclosure, it should be understood that the abstract will not be used to interpret or limit the scope or meaning of the claims. Additionally, in the foregoing detailed description, various features may be grouped together in a single embodiment for the purpose of streamlining the present disclosure. The methods of this disclosure should not be construed as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. In fact, as reflected in the appended claims, the subject matter of the present invention lies in less than all of the features of a single disclosed embodiment. Accordingly, the following claims are hereby incorporated into the detailed description, where each claim stands on its own as a separately claimed subject matter.

Claims

1. A circuit, characterized in that: include: a coupler having a first coupler output and a second coupler output, wherein the coupler generates a first signal at the first coupler output and a second signal at the second coupler output in dependence on an input signal; a first plurality of transistors coupled to the first coupler output; as well as A second plurality of transistors are coupled to the second coupler output, the first plurality of transistors and the second plurality of transistors forming a multiplexer that implements a nominal 90 degree phase shift in the output signal based on selection via a control signal received at a control signal input.

2. The circuit according to claim 1, characterized in that Further including: A transistor is coupled to a first transistor of the first plurality of transistors and a first transistor of the second plurality of transistors.

3. The circuit according to claim 2, characterized in that Further including: A first bias circuit supplies a first bias voltage to the first transistor of the first plurality of transistors and supplies a second bias voltage to the first transistor of the second plurality of transistors.

4. The circuit according to claim 3, characterized in that Further including: A second bias circuit supplies a third bias voltage to the transistor.

5. The circuit according to claim 3, characterized in that Further including: a first input matching network disposed between the first coupler output and a second transistor of the first plurality of transistors; as well as A second input matching network is disposed between the second coupler output and a second transistor of the second plurality of transistors.

6. The circuit according to claim 5, characterized in that Further including: A second bias circuit supplies a third bias voltage to the second transistor of the first plurality of transistors and supplies a fourth bias voltage to the second transistor of the second plurality of transistors.

7. The circuit according to claim 1, characterized in that The nominal 90 degree phase shift corresponds to a phase shift of 90 degrees plus or minus 3 degrees.

8. The circuit according to claim 1, characterized in that Further including: a first switch coupled to the first coupler output and the first plurality of transistors; as well as A second switch is coupled to the second coupler output and the second plurality of transistors.

9. A system, characterized in that: include: a phase inversion variable gain amplifier (PI-VGA) providing a 0 to 180 degree phase shift; a 0 to 90 degree phase shifter implemented via passive components; as well as Active 90 degree phase shifter.

10. A method, characterized in that include: Get input signal; generating an in-phase signal component and a quadrature signal component via a coupler and based on the input signal; as well as An output signal providing a nominal 90 degree phase shift according to selection made via a control signal is generated via active circuitry and based on the in-phase signal component and the quadrature signal component.

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