Relaxation oscillator clock circuit

Abstract

The invention discloses a relaxation oscillator clock circuit, which is characterized in that by adding another voltage-current conversion circuit and a resistor string, a resistor proportionality coefficient is constructed in a period expression of a relaxation oscillator circuit which uses a current mirror to charge and discharge a capacitor to generate a period signal, and the resistor proportionality coefficient is used for replacing the resistance value of a resistor to realize temperature calibration. A temperature calibration range containing negative-to-positive temperature coefficients can be generated under the condition that the process does not need to contain positive temperature coefficient resistors and negative temperature coefficient resistors at the same time and only need to contain two resistors with different temperature coefficients (can be proportional combination of the resistors with the positive temperature coefficient or the negative temperature coefficient at the same time); positive and negative temperature calibration of the clock circuit is realized, the process applicability of the relaxation oscillator clock circuit is remarkably improved, and the development cost and the development period of a chip are reduced.

Description

Technical Field

[0001] The present invention relates to the design technology of chip analog integrated circuits, and particularly to a relaxation oscillator clock circuit. Background Art

[0002] The relaxation oscillator clock circuit structure that uses a current mirror to charge and discharge a capacitor to generate a periodic signal is widely used in various chips as a high-precision clock without a PLL. As a clock, the temperature coefficient of its output frequency is often determined by resistors, and different types of resistors with positive and negative temperature coefficients provided by the foundry need to be combined, which makes it impossible to achieve temperature coefficient calibration in some processes that cannot provide such resistors, greatly limiting the process adaptability of this structure.

[0003] The basic structure of a common relaxation oscillator clock circuit is as Figure 1 shown. It includes a reference module that generates a reference voltage or current, a resistor-capacitor charge and discharge module that uses the reference current to charge and discharge the capacitor and generate a sawtooth wave, a square wave signal generation module that uses a comparator (possibly including an integrator) to detect the voltage of the sawtooth wave and generate a square wave, and a switch control logic circuit that uses the output of the square wave signal generation module to control the switching of the charging and discharging of the capacitor. The charging current of the capacitor in this structure is generally generated by a reference voltage from the reference module and a resistor, and its output clock frequency is determined by the product of the resistor and the capacitor. In general processes, capacitors often do not have significant temperature correlation, while resistors made of different materials have various different temperature characteristics, so the adjustment of the temperature coefficient of the output frequency is often designed in the resistor module.

[0004] For Figure 1 the specific circuit structure of the resistor-capacitor charge and discharge module in Figure 2As shown, this circuit structure requires a well-matched set of current mirrors. On the side of the matched current, the reference current I10 flows through the adjustable resistor string R. The reference current I10 and the voltage division of the adjustable resistor string R act together to generate the internal reference voltage V0. If the reference module outputs a reference current to the current mirror here, the internal reference voltage V0 is generated by multiplying the internal reference current I10 by the adjustable resistor string R or the voltage division part of the adjustable resistor string R; if the reference module outputs a reference voltage, then a voltage-current conversion module is needed here to generate the reference current I10 by acting the reference voltage on the adjustable resistor string R. At this time, the internal reference voltage V0 is equivalent to the resistor voltage division of the reference voltage. Neither method will affect the current charging and discharging process described later, and the final output frequency is f = K / (4RC), where K is the proportional relationship of the current mirror (I1 / I10). The internal reference voltage V0 here will be used as the reference voltage of the internal square wave signal generation module (comparator or integrator); the charging current I1 on the other side of the matched current is used to charge the capacitor array, and when it charges the capacitor array, a sawtooth voltage signal VC is generated on the capacitor. Based on the internal reference voltage V0 and the sawtooth voltage signal VC generated by this structure, a square wave signal generation module (comparator or integrator, with different specific structures depending on different RC circuit principles) generates a switch control signal to control the periodic charging and discharging of the capacitor array, thereby generating a periodic clock signal.

[0005] Figure 1 , Figure 2 In the structure shown, due to various non-ideal characteristics of the actual circuit, mismatches of operational amplifiers and current mirrors, delays in switches and logic controls, etc., the temperature characteristics of the factors affecting the output frequency may be positive temperature characteristics or negative temperature characteristics. Therefore, when calibrating the clock frequency with respect to temperature, the adjustable temperature coefficient range of the adjustable resistor string R must include an interval from negative to positive, which means that the process used for this circuit must be able to provide at least one resistor with a positive temperature coefficient and at least one resistor with a negative temperature coefficient. By combining the two resistors in series and parallel and adjusting the ratio of this combination, an equivalent resistor with a temperature coefficient of the total resistance that can vary between positive and negative within a certain range can be generated. The adjustable temperature coefficient range can only be between the temperature coefficients of the two resistors. For example, when the required range of the adjustable resistor string R is [-400ppm, 400ppm], at least one resistor with a temperature coefficient less than -400ppm (absolute value greater than 400ppm but with a negative temperature correlation) and a resistor with a temperature coefficient greater than 400ppm are required. That is to say, Figure 1 , Figure 2 the structure shown cannot generate a calibration range of the temperature coefficient that exceeds the temperature coefficient of the resistors provided by the process. Therefore, when the resistors provided by the process cannot simultaneously include a positive temperature coefficient resistor and a negative temperature coefficient resistor with good linearity, Figure 1, Figure 2 The shown structure cannot meet the temperature calibration requirements.

[0006] For the relaxation oscillator disclosed in Chinese Patent Document CN104868881A, its output frequency is f = K / (4RC). If positive and negative temperature coefficient calibration is to be performed on R, a combination of a positive temperature coefficient resistor and a negative temperature coefficient resistor must be used.

[0007] For the temperature compensated relaxation oscillator circuit disclosed in Chinese Patent Document CN101599761A, it is clearly stated in the description of the temperature coefficient calibration method that a parallel combination of a positive temperature coefficient resistor and a negative temperature coefficient resistor is required.

[0008] For the relaxation oscillator disclosed in Chinese Patent Document CN202111498650, it is clearly stated in the description of the temperature coefficient calibration method that a series combination of a positive temperature coefficient resistor and a negative temperature coefficient resistor is required. Summary of the Invention

[0009] The technical problem to be solved by the present invention is to provide a relaxation oscillator clock circuit, which can generate a temperature calibration range with a temperature coefficient from negative to positive and achieve positive and negative temperature calibration of the clock circuit without the need for a process that simultaneously includes positive and negative temperature coefficient resistors, but only requires two resistors with different temperature coefficients (which can be a proportional combination of positive or negative temperature coefficient resistors). This significantly improves the process applicability of the relaxation oscillator clock circuit and reduces the development cost and development cycle of the chip.

[0010] To solve the above technical problem, the relaxation oscillator clock circuit provided by the present invention includes a main voltage-current conversion circuit, a slave voltage-current conversion circuit, a sawtooth wave generation module, a square wave generation module, and a switch control logic circuit;

[0011] The main voltage-current conversion circuit includes a first operational amplifier OP1, a first MOS transistor M1, and a resistor string R1;

[0012] One end of the source-drain of the first MOS transistor M1 is connected to the working voltage AVCC, and the other end is connected to an input terminal of the first operational amplifier OP1 and one end of the resistor string R1;

[0013] The gate terminal of the first MOS transistor M1 is connected to the output terminal of the first operational amplifier OP1;

[0014] The other input terminal of the first operational amplifier OP1 is connected to an external reference voltage Vref;

[0015] The other end of the resistor string R1 is grounded;

[0016] An internal reference voltage V0 is output from a voltage division point of the resistor string R1;

[0017] The voltage-to-current conversion circuit includes a second operational amplifier OP2, a second MOS transistor M2, a third MOS transistor M3, and a variable resistor R2;

[0018] One end of the source-drain of the second MOS transistor M2 is connected to the operating voltage AVCC, and the other end is connected to an input terminal of the second operational amplifier OP2 and one end of the variable resistor R2;

[0019] The gate terminal of the second MOS transistor M2 and the gate terminal of the third MOS transistor M3 are connected to the output terminal of the second operational amplifier OP2;

[0020] The other input terminal of the second operational amplifier OP2 is connected to an external reference voltage Vref;

[0021] The other end of the variable resistor R2 is grounded;

[0022] One end of the source-drain of the third MOS transistor M3 is connected to the operating voltage AVCC, and the other end is used as the output terminal of the charging current I2;

[0023] The input terminal of the sawtooth wave generation module is connected to the output terminal of the charging current I2;

[0024] The sawtooth wave generation module includes a capacitor array C and a charge-discharge control switch, and uses the charging current I2 to charge and discharge the capacitor array C to output a sawtooth voltage signal VC;

[0025] One input terminal of the square wave generation module is connected to the sawtooth voltage signal VC output by the sawtooth wave generation module, and the other input terminal is connected to an internal reference voltage V0, and outputs a square wave signal according to the internal reference voltage V0 and the sawtooth voltage signal VC;

[0026] The switch control logic circuit uses the square wave signal output by the square wave generation module as a periodic clock signal to control the on-off of the charge-discharge control switch in the sawtooth wave generation module, and charges and discharges the capacitor array C to generate a sawtooth voltage signal VC.

[0027] Preferably, the square wave generation module is a comparator.

[0028] Preferably, the square wave generation module is a combined circuit of an integrator and a comparator.

[0029] Preferably, the charge-discharge control switch includes a first control switch K1 and a second control switch K2;

[0030] The first control switch K1 is connected in series between the input terminal of the sawtooth wave generation module and one end of the capacitor array C;

[0031] The other end of the capacitor array C is grounded;

[0032] The second control switch K2 is connected in parallel between both ends of the capacitor array C;

[0033] When the first control switch K1 is turned on and the second control switch K2 is turned off, the capacitor array C is charged;

[0034] When the first control switch K1 is turned off and the second control switch K2 is turned on, the capacitor array C discharges;

[0035] One end of the capacitor array C serves as the output terminal of the sawtooth voltage signal VC.

[0036] Preferably, the first MOS transistor M1, the second MOS transistor M2, and the third MOS transistor M3 are all PMOS transistors;

[0037] The source terminal of the first MOS transistor M1 is connected to the operating voltage AVCC, and the drain terminal is connected to one input terminal of the first operational amplifier OP1 and one end of the resistor string R1;

[0038] The source terminal of the second MOS transistor M2 is connected to the operating voltage AVCC, and the drain terminal is connected to one input terminal of the second operational amplifier OP2 and one end of the adjustable resistor R2;

[0039] The source terminal of the third MOS transistor M3 is connected to the operating voltage AVCC, and the drain terminal serves as the output terminal of the charging current I2.

[0040] In the relaxation oscillator clock circuit of the present invention, by adding another voltage-current conversion circuit and a resistor string, a resistance ratio coefficient is constructed in the period expression of the relaxation oscillator circuit that uses a current mirror to charge and discharge a capacitor to generate a periodic signal, and the resistance value is replaced to achieve temperature calibration. Without the need for a process that simultaneously includes positive temperature coefficient and negative temperature coefficient resistors, but only requires two resistors with different temperature coefficients (which can be a proportional combination of positive or negative temperature coefficient resistors), a temperature calibration range including a temperature coefficient from negative to positive can be generated, realizing positive and negative temperature calibration of the clock circuit; at the same time, the newly added error sources of the structures of the two voltage-current conversion circuits are less, and basically have no impact on the accuracy of the relaxation oscillator, significantly improving the process applicability of the relaxation oscillator clock circuit, and reducing the development cost and development cycle of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the present invention, the drawings required for the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0042] Figure 1 is the basic structure of a common relaxation oscillator clock circuit;

[0043] Figure 2It is a common circuit structure of the resistor-capacitor charge and discharge module in the relaxation oscillator clock circuit;

[0044] Figure 3 It is an embodiment of the relaxation oscillator clock circuit of the present invention. Specific embodiments

[0045] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0046] The "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0047] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments may be combined with each other.

[0048] Embodiment 1

[0049] A relaxation oscillator clock circuit is as Figure 3 shown, which includes a main voltage-current conversion circuit Main V2I, a slave voltage-current conversion circuit Sub V2I, a sawtooth wave generation module, a square wave generation module and a switch control logic circuit;

[0050] The main voltage-current conversion circuit includes a first operational amplifier OP1, a first MOS transistor M1 and a resistor string R1;

[0051] One end of the source and drain of the first MOS transistor M1 is connected to the working voltage AVCC, and the other end is connected to an input terminal of the first operational amplifier OP1 and one end of the resistor string R1;

[0052] The gate terminal of the first MOS transistor M1 is connected to the output terminal of the first operational amplifier OP1;

[0053] The other input terminal of the first operational amplifier OP1 is connected to an external reference voltage Vref;

[0054] The other end of the resistor string R1 is grounded;

[0055] An internal reference voltage V0 is output from a voltage dividing point of the resistor string R1;

[0056] The voltage-current conversion circuit includes a second operational amplifier OP2, a second MOS transistor M2, a third MOS transistor M3, and a variable resistor R2;

[0057] One end of the source-drain of the second MOS transistor M2 is connected to the operating voltage AVCC, and the other end is connected to an input terminal of the second operational amplifier OP2 and one end of the variable resistor R2;

[0058] The gate terminal of the second MOS transistor M2 and the gate terminal of the third MOS transistor M3 are connected to the output terminal of the second operational amplifier OP2;

[0059] Another input terminal of the second operational amplifier OP2 is connected to an external reference voltage Vref;

[0060] The other end of the variable resistor R2 is grounded;

[0061] One end of the source-drain of the third MOS transistor M3 is connected to the operating voltage AVCC, and the other end is used as an output terminal of the charging current I2;

[0062] The input terminal of the sawtooth wave generating module is connected to the output terminal of the charging current I2;

[0063] The sawtooth wave generating module includes a capacitor array C and a charge-discharge control switch, and charges and discharges the capacitor array C with the charging current I2 to output a sawtooth voltage signal VC;

[0064] One input terminal of the square wave generating module is connected to the sawtooth voltage signal VC output by the sawtooth wave generating module, and another input terminal is connected to the internal reference voltage V0, and a square wave signal is output according to the internal reference voltage V0 and the sawtooth voltage signal VC;

[0065] The switch control logic circuit uses the square wave signal output by the square wave generating module as a periodic clock signal to control the on-off of the charge-discharge control switch in the sawtooth wave generating module, charges and discharges the capacitor array C, and generates a sawtooth voltage signal VC.

[0066] Preferably, the square wave generating module is a comparator or a combination circuit of an integrator and a comparator (the specific structure is different according to different RC circuit principles).

[0067] For the relaxation oscillator clock circuit of Embodiment 1, an external reference voltage Vref generates a first reference current I10 on a resistor string R1 through a main voltage-to-current conversion circuit Main V2I. At the same time, an internal reference voltage V0 required is generated by resistor voltage division on the resistor string R1 as the reference voltage for the square wave generation module. The external reference voltage Vref is also used as the reference voltage for a sub voltage-to-current conversion circuit Sub V2I, generating a second reference current I20 on an adjustable resistor R2. The second reference current I20 then generates a charging current I2 through a current mirror with a ratio of K to charge a capacitor array C, generating a sawtooth voltage signal VC on the capacitor array C.

[0068] The internal reference voltage V0 and the sawtooth voltage signal VC then pass through a square wave generation module to generate a square wave signal. The switch control logic circuit uses the square wave signal output by the square wave generation module as a periodic clock signal to control the on / off of the charge / discharge control switch in the sawtooth wave generation module, charging and discharging the capacitor array C to generate the sawtooth voltage signal VC.

[0069] From Figure 3 the following relationships can be obtained from the circuit:

[0070] V ref = I 10 * R 1 ; V ref = I 20 * R 2 ; I 2 = I 20 * K; - Equation 1;

[0071] Assume that the relaxation oscillator to which this circuit is applied needs to compare the sawtooth voltage signal VC on the capacitor with M times V0 (for generality, the value of M is determined according to the specific RC circuit structure). Each time the comparator output flips, the switch control logic circuit controls the on / off of the charge / discharge control switch in the sawtooth wave generation module to discharge the capacitor array C. There is a complete charging process of the capacitor array C between every two flips, and every two charging processes of the capacitor array C constitute a period T of the relaxation oscillator.

[0072] T = 2 * M * V 0 / I 1 * C - Equation 2;

[0073] Substituting Equation 1 into Equation 2 gives:

[0074]

[0075] As can be seen from Equation 3, compared with the reference existing patent design, the expression of the period T (the reciprocal of the output frequency f) has added the resistance ratio R2 / R1. Without loss of generality, assume that M and K have no significant temperature correlation, and the capacitor array C also has no significant temperature correlation. Then the temperature coefficient of the clock period is determined by the temperature coefficient of the resistor R ref and the resistance ratio R2 / R1. Then, compared with the reference existing patent design, the clock frequency can be temperature-calibrated here by adjusting the resistance ratio R2 / R1. The key is that different from adjusting the temperature coefficient of R in the existing patent design, when adjusting the resistance ratio R2 / R1, it is not necessary for the resistor string R1 and the adjustable resistor R2 to include two types of resistors with different positive and negative temperature coefficients, but only two resistors with different temperature coefficient magnitudes are required.

[0076] Let The temperature coefficient of β relative to itself is That is, the difference between the temperature coefficients of the adjustable resistor R2 and the resistor string R1. In this relationship, if it is required that β has an adjustable range from a negative temperature coefficient to a positive temperature coefficient centered on 0, it is not necessary for the temperature coefficients of the resistor string R1 and the adjustable resistor R2 to be different in sign. For example, when the range of β is [-400ppm, 400ppm], it can be set that Let be adjustable in the range [0, 800ppm], and the required range of β can be obtained. And the resistors used in this way are all positive temperature coefficients, and negative temperature coefficient resistors are not required. Similarly, the same effect can also be achieved by using two types of resistors with the same negative temperature coefficient, which will not be elaborated here. It can be seen that the relaxation oscillator clock circuit based on current charging and discharging of capacitors in Embodiment 1 realizes the broadening of process adaptability.

[0077] At the same time, compared with the Figure 2 common structure of this relaxation oscillator clock circuit, the error contribution to the output frequency only increases the mismatch of the operational amplifier and the mismatch of the resistance ratio. These two mismatches can be eliminated by common frequency calibration except for their temperature drift. And their temperature drift characteristics generally have very little influence on the frequency in a reasonable circuit design. Therefore, the relaxation oscillator clock circuit in Embodiment 1 is very suitable for the temperature calibration design of high-precision relaxation oscillator clock circuits.

[0078] The relaxation oscillator clock circuit of Embodiment 1 constructs a resistance ratio coefficient in the period expression of the relaxation oscillator circuit that uses a current mirror to charge and discharge a capacitor to generate a periodic signal, and replaces the resistance value of the resistor to achieve temperature calibration. Without the need for a process that simultaneously includes positive temperature coefficient and negative temperature coefficient resistors, but only requires two resistors with different temperature coefficients (which can be a proportional combination of positive or negative temperature coefficient resistors), a temperature calibration range that includes a temperature coefficient from negative to positive can be generated, realizing positive and negative temperature calibration of the clock circuit. At the same time, the newly added error sources of the structures of the two voltage-current conversion circuits are few, and basically have no impact on the accuracy of the relaxation oscillator, significantly improving the process applicability of the relaxation oscillator clock circuit and reducing the development cost and development cycle of the chip.

[0079] Embodiment 2

[0080] Based on the relaxation oscillator clock circuit of Embodiment 1, the first MOS transistor M1, the second MOS transistor M2, and the third MOS transistor M3 are all PMOS transistors;

[0081] The source terminal of the first MOS transistor M1 is connected to the working voltage AVCC, and the drain terminal is connected to an input terminal of the first operational amplifier OP1 and one end of the resistor string R1;

[0082] The source terminal of the second MOS transistor M2 is connected to the working voltage AVCC, and the drain terminal is connected to an input terminal of the second operational amplifier OP2 and one end of the adjustable resistor R2;

[0083] The source terminal of the third MOS transistor M3 is connected to the working voltage AVCC, and the drain terminal is used as the output terminal of the charging current I2.

[0084] Embodiment 3

[0085] Based on the relaxation oscillator clock circuit of Embodiment 1, the charge and discharge control switch includes a first control switch K1 and a second control switch K2;

[0086] The first control switch K1 is connected in series between the input terminal of the sawtooth wave generation module and one end of the capacitor array C;

[0087] The other end of the capacitor array C is grounded;

[0088] The second control switch K2 is connected in parallel between both ends of the capacitor array C;

[0089] When the first control switch K1 is turned on and the second control switch K2 is turned off, the capacitor array C is charged;

[0090] When the first control switch K1 is turned off and the second control switch K2 is turned on, the capacitor array C discharges;

[0091] One end of the capacitor array C serves as the output terminal of the sawtooth voltage signal VC.

[0092] The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A relaxation oscillator clock circuit, characterized in that, it includes a main voltage-current conversion circuit, a slave voltage-current conversion circuit, a sawtooth wave generation module, a square wave generation module and a switch control logic circuit; The main voltage-current conversion circuit includes a first operational amplifier (OP1), a first MOS transistor (M1) and a resistor string (R1); One end of the source-drain of the first MOS transistor (M1) is connected to the working voltage (AVCC), and the other end is connected to an input terminal of the first operational amplifier (OP1) and one end of the resistor string (R1); The gate terminal of the first MOS transistor (M1) is connected to the output terminal of the first operational amplifier (OP1); The other input terminal of the first operational amplifier (OP1) is connected to an external reference voltage (Vref); The other end of the resistor string (R1) is grounded; An internal reference voltage (V0) is output from a voltage dividing point of the resistor string (R1); The slave voltage-current conversion circuit includes a second operational amplifier (OP2), a second MOS transistor (M2), a third MOS transistor (M3) and a variable resistor (R2); One end of the source-drain of the second MOS transistor (M2) is connected to the working voltage (AVCC), and the other end is connected to an input terminal of the second operational amplifier (OP2) and one end of the variable resistor (R2); The gate terminal of the second MOS transistor (M2) and the gate terminal of the third MOS transistor (M3) are connected to the output terminal of the second operational amplifier (OP2); The other input terminal of the second operational amplifier (OP2) is connected to an external reference voltage (Vref); The other end of the variable resistor (R2) is grounded; One end of the source-drain of the third MOS transistor (M3) is connected to the working voltage (AVCC), and the other end is used as the output terminal of the charging current (I2); The sawtooth wave generation module has its input terminal connected to the output terminal of the charging current (I2); The sawtooth wave generation module includes a capacitor array (C) and a charge-discharge control switch, and uses the charging current (I2) to charge and discharge the capacitor array (C) to output a sawtooth voltage signal (VC); The square wave generation module has one input terminal connected to the sawtooth voltage signal (VC) output by the sawtooth wave generation module, and the other input terminal connected to the internal reference voltage (V0), and outputs a square wave signal according to the internal reference voltage (V0) and the sawtooth voltage signal (VC); The switch control logic circuit uses the square wave signal output by the square wave generation module as a periodic clock signal to control the on-off of the charge-discharge control switch in the sawtooth wave generation module, charge and discharge the capacitor array (C), and generate a sawtooth voltage signal (VC).

2. The relaxation oscillator clock circuit according to claim 1, characterized in that, the square wave generation module is a comparator.

3. The relaxation oscillator clock circuit according to claim 1, characterized in that, the square wave generation module is a combined circuit of an integrator and a comparator.

4. The relaxation oscillator clock circuit according to claim 1, characterized in that, the charge-discharge control switch includes a first control switch (K1) and a second control switch (K2); The first control switch (K1) is connected in series between the input terminal of the sawtooth wave generation module and one end of the capacitor array (C); The other end of the capacitor array (C) is grounded; The second control switch (K2) is connected in parallel between both ends of the capacitor array (C); When the first control switch (K1) is turned on and the second control switch (K2) is turned off, the capacitor array (C) is charged; When the first control switch (K1) is turned off and the second control switch (K2) is turned on, the capacitor array (C) discharges; One end of the capacitor array (C) serves as the output terminal of the sawtooth voltage signal (VC).

5. The relaxation oscillator clock circuit according to claim 1, characterized in that, the first MOS transistor (M1), the second MOS transistor (M2) and the third MOS transistor (M3) are all PMOS transistors; The source terminal of the first MOS transistor (M1) is connected to the working voltage (AVCC), and the drain terminal is connected to one input terminal of the first operational amplifier (OP1) and one end of the resistor string (R1); The source terminal of the second MOS transistor (M2) is connected to the working voltage (AVCC), and the drain terminal is connected to one input terminal of the second operational amplifier (OP2) and one end of the adjustable resistor (R2); The source terminal of the third MOS transistor (M3) is connected to the working voltage (AVCC), and the drain terminal serves as the output terminal of the charging current (I2).

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